BIT1612 - NewHaven Display

BIT1612
10-Bit Digital Video Decoder
with
OSD and T-CON
Version: A0
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Preliminary
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Content
1 General Description ................................................................................................................................... 1
2 Features..................................................................................................................................................... 1
General:................................................................................................................................................... 1
Input: ...................................................................................................................................................... 1
Output:..................................................................................................................................................... 2
Interface:.................................................................................................................................................. 2
OSD: ...................................................................................................................................................... 2
Power Management: ............................................................................................................................... 2
Package:.................................................................................................................................................. 2
3 Order Information....................................................................................................................................... 3
4 Block Diagram............................................................................................................................................ 3
5 Pin Definition.............................................................................................................................................. 4
6 Functional Description ............................................................................................................................... 8
6.1
Version Control.............................................................................................................................. 8
6.2
Interrupt Function .......................................................................................................................... 8
6.3
Double Buffer ...............................................................................................................................11
6.4
Pad Type Setup........................................................................................................................... 12
6.5
GPO (General Purpose Output) Function................................................................................... 13
6.6
System Enable and Reset........................................................................................................... 13
6.7
Clock Domain Systems ............................................................................................................... 14
6.8
Panel Timing Setup ..................................................................................................................... 16
6.9
Output Data Path ........................................................................................................................ 17
6.10 Special Output Setup .................................................................................................................. 18
6.11 Special Timing Adjustment .......................................................................................................... 19
6.11.1
Synchronization Timing................................................................................................ 19
6.11.2
Two-Fields Synchronization Timing ............................................................................. 19
6.12 TCON Function ........................................................................................................................... 20
6.13 TCON Clock Mode ...................................................................................................................... 22
6.14 Display Layer .............................................................................................................................. 22
6.15 Background 2 .............................................................................................................................. 23
6.16 Background 1 and Test Pattern Setup ........................................................................................ 23
6.17 Auto Blank Screen ...................................................................................................................... 24
6.18 Input Image Window Setup ......................................................................................................... 25
6.19 Input Data Path Setup................................................................................................................. 25
6.20 Input Format................................................................................................................................ 27
6.20.1
ITU656 ......................................................................................................................... 27
i
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.20.2
ITU656-Like ................................................................................................................. 27
6.20.3
ITU601 ......................................................................................................................... 27
6.20.4
RGB888 ....................................................................................................................... 27
6.20.5
Serial-RGB................................................................................................................... 27
6.20.6
YUV444........................................................................................................................ 27
6.20.7
RGB565 ....................................................................................................................... 28
6.21 Input Mode Selection .................................................................................................................. 29
6.22 Auto Switch ................................................................................................................................. 31
6.23 Display Window Setup ................................................................................................................ 31
6.24 Scaling Engine ............................................................................................................................ 32
6.24.1
Horizontal Scaling Down Engine ................................................................................. 32
6.24.2
Horizontal Scaling UP Engine...................................................................................... 33
6.24.3
Vertical Scaling Engine ................................................................................................ 34
6.25 Timing Adjustment....................................................................................................................... 35
6.26 Image Enhancement ................................................................................................................... 36
6.26.1
Post-Processing Brightness and Contrast................................................................... 36
6.26.2
Pre-Processing Brightness/Contrast Adjustment ........................................................ 37
6.26.3
Sharpness Process...................................................................................................... 37
6.26.4
Saturation and Kill Color Process................................................................................ 37
6.26.5
Chroma Transient Improvement (CTI)......................................................................... 38
6.26.6
Color Space Conversion .............................................................................................. 38
6.26.7
LUT Gamma Correction............................................................................................... 38
6.26.8
Dither ........................................................................................................................... 38
6.26.9
DAC Correction............................................................................................................ 39
6.26.10 Clamp and Linear Mapping.......................................................................................... 39
6.27 PWM Function............................................................................................................................. 40
6.28 Video Decoder............................................................................................................................. 41
6.28.1
Video Decoder Feature................................................................................................ 41
6.28.2
Video Decoder Architectures ....................................................................................... 42
6.28.3
Video Decoder Adjustment .......................................................................................... 42
6.28.4
Synchronization Process ............................................................................................. 44
6.28.5
VBI Data Slicer............................................................................................................. 45
6.28.6
Source Detection ......................................................................................................... 45
6.28.7
Luminance Process ..................................................................................................... 46
6.28.8
Chroma Process .......................................................................................................... 47
6.28.9
Comb Filter Process .................................................................................................... 48
6.28.10 AGC and ACC Process................................................................................................ 50
6.28.11 AFE and PLL Control ................................................................................................... 53
ii
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.28.12 Input Path Selection..................................................................................................... 54
6.28.13 Standard Setting and Detection................................................................................... 55
6.29 Video Decoder Status Register ................................................................................................... 56
6.30 Serial RGB Output ...................................................................................................................... 58
6.31 BIT1690 Interface........................................................................................................................ 58
6.32 OSD Function.............................................................................................................................. 59
6.32.1
OSD Windows Function............................................................................................... 59
6.32.2
OSD Memory Mapping ................................................................................................ 60
6.32.3
OSD Windows Attributes ............................................................................................. 63
6.32.4
OSD Windows Overlap Selection................................................................................ 67
6.32.5
External OSD Interface................................................................................................ 68
6.32.6
OSD User Programmable RAM Selection................................................................... 68
6.32.7
OSD Clock Control ...................................................................................................... 69
6.32.8
OSD Built-In Fixed Font............................................................................................... 69
6.33 Timer ........................................................................................................................................... 70
6.34 IR Decoder Function ................................................................................................................... 71
6.35 GPI and KEY Function ................................................................................................................ 72
6.36 PLL and OSC Pads ..................................................................................................................... 72
6.37 Auto Detection............................................................................................................................. 73
7 User Interface .......................................................................................................................................... 76
7.1
Options Pins................................................................................................................................ 76
7.2
Master Mode – Script MCU......................................................................................................... 79
7.3
7.2.1
Architecture.................................................................................................................. 79
7.2.2
Instruction Set.............................................................................................................. 81
7.2.3
Start and Interrupt ........................................................................................................ 84
7.2.4
Serial EEPROM and ROM Space Mapping................................................................. 84
7.2.5
Serial EEPROM Write Protection and Power Monitor ................................................. 85
7.2.6
Watch Dog Timer ......................................................................................................... 85
7.2.7
Second TWSI for Multi-Processor Communication ..................................................... 86
7.2.8
TWSI Write/Read ......................................................................................................... 86
7.2.9
SPI Interface ................................................................................................................ 86
7.2.10
Debug Mode ................................................................................................................ 86
Slave Mode ................................................................................................................................. 87
7.3.1
BiTEKbus Protocol....................................................................................................... 87
7.3.2
TWSI Protocol.............................................................................................................. 88
8 Timing Diagram........................................................................................................................................ 91
8.1
Hardware Reset .......................................................................................................................... 91
8.2
Clock and Interrupt...................................................................................................................... 91
iii
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
8.3
Input Signal ................................................................................................................................. 91
8.4
Output Signal .............................................................................................................................. 92
9 Electrical Characteristic ........................................................................................................................... 93
9.1
Absolute Maximum Rating .......................................................................................................... 93
9.2
Recommend Operating Condition............................................................................................... 93
9.3
DC Electrical Characters............................................................................................................. 93
10 Soldering Information............................................................................................................................... 94
10.1 Reflow Soldering ......................................................................................................................... 94
10.2 Wave Soldering ........................................................................................................................... 94
10.3 Manual Soldering ........................................................................................................................ 94
11 Package Information................................................................................................................................ 95
Index.............................................................................................................................................................. 96
iv
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Table
Table 5-1 BIT1612 Pin Definition.................................................................................................................. 4
Table 5-2 PAD Type Definition...................................................................................................................... 7
Table 6-1 Version Control Register............................................................................................................... 8
Table 6-2 Interrupt Source and Flags ........................................................................................................... 8
Table 6-3 Interrupt Controller Register ......................................................................................................... 9
Table 6-4 Video Decoder Lock Source for Interrupt Selection ..................................................................... 9
Table 6-5 Double Buffer Register ................................................................................................................11
Table 6-6 Output Tri-State Control Register ............................................................................................... 12
Table 6-7 Pad Pull Up or Down Control Register ....................................................................................... 12
Table 6-8 General Purpose Output Register .............................................................................................. 13
Table 6-9 General Purpose Output Pads Setup Table ............................................................................... 13
Table 6-10 Clock Domain System Register................................................................................................ 14
Table 6-11 Panel Timing Setup Register .................................................................................................... 16
Table 6-12 Output Data Path Register ....................................................................................................... 17
Table 6-13 Special Output Setup................................................................................................................ 18
Table 6-14 Special Timing Adjust Register ................................................................................................. 19
Table 6-15 TCON Function Register .......................................................................................................... 20
Table 6-16 TCON Clock Mode Register ..................................................................................................... 22
Table 6-17 Background 2 Register ............................................................................................................. 23
Table 6-18 Background and Test Pattern Register..................................................................................... 23
Table 6-19 Blank Screen Register.............................................................................................................. 24
Table 6-20 Input Crop Register .................................................................................................................. 25
Table 6-21 Input Data Path Register .......................................................................................................... 25
Table 6-22 Input Mode Selection Register ................................................................................................. 29
Table 6-23 Auto Switch Register ................................................................................................................ 31
Table 6-24 Display Windows Register........................................................................................................ 31
Table 6-25 Horizontal Scale Down Register............................................................................................... 32
Table 6-26 Horizontal Scale UP Register ................................................................................................... 33
Table 6-27 Vertical Scale-Down Register ................................................................................................... 34
Table 6-28 Timing Adjust Register.............................................................................................................. 35
Table 6-29 Color Adjustment Register........................................................................................................ 36
Table 6-30 Color Adjustment Register........................................................................................................ 37
Table 6-31 Sharpness and Smoothness Process Register........................................................................ 37
Table 6-32 UV Domain Register................................................................................................................. 37
Table 6-33 Chroma Transient Improvement Register ................................................................................ 38
Table 6-34 Color Space Converter Register............................................................................................... 38
v
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Table 6-35 LUT Gamma Register............................................................................................................... 38
Table 6-36 Dither Register.......................................................................................................................... 38
Table 6-37 DAC Correction Register .......................................................................................................... 39
Table 6-38 Clamp and Linear Mapping Register........................................................................................ 39
Table 6-39 PWM Function Register............................................................................................................ 40
Table 6-40 Color Adjustment Register........................................................................................................ 42
Table 6-41 Sharpness and Smoothness Process Register........................................................................ 42
Table 6-42 UV Domain Register................................................................................................................. 43
Table 6-43 Chroma Transient Improvement Register ................................................................................ 43
Table 6-44 Synchronization Process Register............................................................................................ 44
Table 6-45 VBI Data Slicer Process Register............................................................................................. 45
Table 6-46 Source Detection Process Register ......................................................................................... 45
Table 6-47 Luminance Process Register.................................................................................................... 46
Table 6-48 Chroma Process Register ........................................................................................................ 47
Table 6-49 Comb Filter Process Register................................................................................................... 48
Table 6-50 AGC Control Register............................................................................................................... 50
Table 6-51 ADC Control Register ............................................................................................................... 53
Table 6-52 Analog Input Path Register....................................................................................................... 54
Table 6-53 Analog Input Selection.............................................................................................................. 54
Table 6-54 Standard Setting and Detection Register ................................................................................. 55
Table 6-55 Video Decoder Status Register ................................................................................................ 56
Table 6-56 Serial RGB Output Register ..................................................................................................... 58
Table 6-57 BIT1690 Interface Register....................................................................................................... 58
Table 6-58 OSD Windows Register............................................................................................................ 59
Table 6-59 OSD Memory Mapping Table ................................................................................................... 63
Table 6-60 OSD Windows Attribute Register.............................................................................................. 63
Table 6-61 OSD Windows Overlap Selection............................................................................................. 67
Table 6-62 External OSD Register ............................................................................................................. 68
Table 6-63 User Programmable RAM Selection ........................................................................................ 68
Table 6-64 OSD Clock Setting Register ..................................................................................................... 69
Table 6-65 Timer Register .......................................................................................................................... 70
Table 6-66 IR Pulse Detection Register ..................................................................................................... 71
Table 6-67 GPI and KEY Register.............................................................................................................. 72
Table 6-68 PLL Register ............................................................................................................................. 72
Table 6-69 Auto Detection Register............................................................................................................ 74
Table 7-1 Options Pins Setup..................................................................................................................... 76
Table 7-2 TWSI Speed................................................................................................................................ 79
Table 7-3 Register and Address Index ....................................................................................................... 79
vi
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Table 7-4 Instruction Set............................................................................................................................. 81
Table 7-5 Instruction Format....................................................................................................................... 83
Table 7-6 Start and Interrupt ....................................................................................................................... 84
Table 7-7 BiTEKbus Slave Address............................................................................................................ 87
Table 7-8 TWSI Protocol Device Address .................................................................................................. 88
vii
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Figure
Figure 4-1 BIT1612 Architecture .................................................................................................................. 3
Figure 5-1 Pin Configuration ........................................................................................................................ 4
Figure 6-1 Interrupt Function Block ............................................................................................................ 10
Figure 6-2 Double Buffer Function ..............................................................................................................11
Figure 6-3 Hardware Reset Waveform....................................................................................................... 13
Figure 6-4 Panel Timing Setup................................................................................................................... 16
Figure 6-5 Output Data Path Selection ...................................................................................................... 18
Figure 6-6 Synchronization Timing............................................................................................................. 19
Figure 6-7 Two-Fields Synchronization Timing .......................................................................................... 19
Figure 6-8 Display Layer ............................................................................................................................ 22
Figure 6-9 Free Run and Background........................................................................................................ 24
Figure 6-10 Input Window Setup................................................................................................................ 25
Figure 6-11 Input Data Path Setup ............................................................................................................. 26
Figure 6-12 ITU656/656-Like (27MHz)....................................................................................................... 27
Figure 6-13 ITU601 (13.5MHz) .................................................................................................................. 27
Figure 6-14 RGB 8:8:8 (Max. 100MHz)...................................................................................................... 27
Figure 6-15 Serial-RGB (Max. 40MHz) ...................................................................................................... 27
Figure 6-16 YUV 4:4:4 (Max.100MHz) ....................................................................................................... 28
Figure 6-17 RGB 565 8:8:8 (Max. 100MHz)............................................................................................... 28
Figure 6-18 RGB 5:6:5 Setup..................................................................................................................... 28
Figure 6-19 Input Mode Selection .............................................................................................................. 30
Figure 6-20 Display Window Setup ............................................................................................................ 31
Figure 6-21 Scaling Function ..................................................................................................................... 32
Figure 6-22 Timing Adjustment VREF Information..................................................................................... 36
Figure 6-23 Image Enhancement............................................................................................................... 36
Figure 6-24 Linear Mapping ....................................................................................................................... 39
Figure 6-25 DAC Clamp ............................................................................................................................. 39
Figure 6-26 PWM Function ........................................................................................................................ 41
Figure 6-27 Video Decoder Block Diagram................................................................................................ 42
Figure 6-28 Synchronization Process ........................................................................................................ 44
Figure 6-29 Luminance Process Block....................................................................................................... 46
Figure 6-30 Chroma Process Function Block ............................................................................................ 47
Figure 6-31 AGC and Clamp Pulse............................................................................................................ 50
Figure 6-32 AGC Control Selection............................................................................................................ 50
Figure 6-33 Input Path................................................................................................................................ 54
Figure 6-34 Field Type Selection................................................................................................................ 55
viii
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Figure 6-35 Color Standard Selection ........................................................................................................ 55
Figure 6-36 UPS051................................................................................................................................... 58
Figure 6-37 UPS052................................................................................................................................... 58
Figure 6-38 BIT1690 Interface ................................................................................................................... 59
Figure 6-39 OSD Windows Setup .............................................................................................................. 60
Figure 6-40 OSD Memory Mapping ........................................................................................................... 61
Figure 6-41 Palette RAM Example............................................................................................................. 62
Figure 6-42 OSD User Programmable Font RAM...................................................................................... 62
Figure 6-43 OSD Color Font RAM ............................................................................................................. 63
Figure 6-44 OSD Windows Attribute .......................................................................................................... 66
Figure 6-45 OSD Windows Overlap ........................................................................................................... 67
Figure 6-46 Fixed Font ............................................................................................................................... 69
Figure 6-47 Timer Mode 0 (Circulation) ..................................................................................................... 70
Figure 6-48 Timer Mode 1 (One-Shot) ....................................................................................................... 70
Figure 6-49 Long Key Process................................................................................................................... 72
Figure 6-50 PLL Frequency Formula.......................................................................................................... 73
Figure 7-1 Slave Mode ............................................................................................................................... 76
Figure 7-2 Master Mode with Single 24C16 ............................................................................................... 77
Figure 7-3 Master Mode with Single 24C32 ............................................................................................... 77
Figure 7-4 Master Mode with Dual EEPROM............................................................................................. 78
Figure 7-5 BIT1612 Script Controller Addressing Space............................................................................ 85
Figure 7-6 Bitek Serial Interface Bus – Extension Mode............................................................................ 87
Figure 7-7 TWSI Slave Mapping Address .................................................................................................. 89
Figure 7-8 TWSI Read/Write Mode ............................................................................................................ 90
ix
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
1 General Description
BIT1612 是結合 T-CON 與 OSD 的一個高性能單晶片數字式視訊解碼器。視訊解碼器解譯普遍使用的
NTSC/PAL/SECAM 影像內容。投向 BIT1612 的信號包括類比視訊 CVBS 和 Y/C、數字式 CCIR601/656 和數字式
RGB 格式。類比/數字轉換器的自動增益控制 (AGC) 功能加強了處理微弱和失真信號的能力。卓越的 2D 梳型濾波
器和先進的 CTI 和 Skin-Tone 處理使顯示顏色更加清楚,圖像更加自然。可編程序的時序控制 (TCON) 讓 BIT1612
系統 (解析度可達 800xRGBx600) 可使用大多數普及的 LCD 屏。可編程序的亮度、對比和色飽和度以及內含的伽瑪
校正讓用戶自由地調整顯示的顏色。嵌入式 OSD 使系統設計師非常容易開發出簡單易用使用者介面。先進的顯示格
式控制器能非常順利地轉換 4:3 顯示成 16:9。BIT1612 可以用在一臺傳統手持式 LCD 顯示器。以其卓越的影像處理
表現,使用在車用 TV/導航系統和便攜式的 AV 系統也是適當的。
2 Features
General:
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
No external memory required
Two 10-bit video CMOS Analog-to-Digital Converters (ADCs) in differential CMOS style for best
S/N-performance
Fully programmable static gain or automatic gain control (AGC) the selected CVBS or Y/C channel : 0~12db
(Analog) and 0~18db (Digital)
Automatic Clamp Control (ACC) for CVBS, Y and C
On-chip clock generator
L-lock system clock frequencies
Digital PLL for synchronization and clock generation from all standards and non-standard video sources e.g.
consumer grade VTR
Requires only one crystal (24.576 MHz) for all standards
Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC
standards
Accepts NTSC (J, M, 4.43), PAL (60, B, D, G, H, I, M, N), and SECAM (B, D, G, K, K1, L) video signal
User programmable luminance peaking or aperture correction
Adaptive 3/5-line comb filter for two dimensional chrominance/luminance separation
PAL delay line for correcting PAL phase errors
Multi-standard VBI-data slicer including closed caption
MV copy protection detection
YUV to RGB color space converting
Fully programmable zoom-out arbitrary ratio in both horizontal and vertical
Anamorphic zoom for 4:3 video input to 16:9 display converting
Embedded brightness, contrast, sharpness and gamma correction
Embedded Skin-Tone and CTI
Embedded programmable OSD for user Interface
Embedded programmable TCON (Timing-Control) generator for LCD interface
Embedded 3 PWM (Pulse Width Modulation) generators for general purpose control
Embedded IR remote control decoder
Input:
y
y
y
y
y
y
y
y
y
y
3 analog inputs, internal analog source selectors, e.g. CVBS x 3 or Y/C x 1 or (Y/C x 1 and CVBS x 1) or
YPbPr (480i or 576i)
3 of 8-bit digital video input ports (R,G,B)
HSYNC/VSYNC Input x 1
Clock Input x 2
24-bit RGB/YUV input up to 85MHz
16-bit RGB (RGB 5:6:5) input
8-bit Serial RGB Data format
ITU-R BT.601(16-bit) (CCIR 601)
ITU-R BT.656(8-bit) (CCIR 656)
Built-in YUV to RGB color space converter
1
BIT1612
y
y
10-Bit Digital Video Decoder with OSD and T-CON
Programmable RGB input port order and pin order
5V tolerance input pads support 5V/3.3V interface
Output:
y
y
y
y
y
y
y
y
4x8 Bits digital output ports (R,G,B,T)
Programmable RGB output port order and pin order
Maximum output pixel frequency 85MHz@ digital output
Support inverse and frequency adjustment for LCD panel clock
Support programmable H/V sync. for LCD panel
Support programmable TCON for LCD panel
Support Delta and Stripe types LCD panel
Free-run Synchronization mode if sync signal disappeared
Interface:
y
y
y
Support Two-wire BiTEKBus interface
Support Two-Wire Serial Interface (TWSI) Bus interface
Support 24Cxx serial EEPROM Script controller
OSD:
y
y
y
y
y
y
y
y
Built-in OSD generator with 128 ROM fonts, 512 mix color
3 windows support overlay function
48 user download fonts
9 sizes of zooming font (1/2, x1, x2, x3, x4, x5, x6, x7, x8)
Flashing font attribute
Fringe font attribute
Transparent overlay for OSD windows
Support external OSD interface
Power Management:
y
y
y
1.8V power source for core,
3.3V power source for output pads
Power Consumption less than 300 mW
Package:
y
LQFP 128 pins
2
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
3 Order Information
BIT1612-LQ
LQFP Type Package
Part Number
Beyond Innovation Technology Co., Ltd.
4 Block Diagram
External OSD Interface
Built-in
OSD
TCON
Video Decoder
Output
Process
Input
Process
Pre-Image
Enhancement
Programmable
Horizontal
Scale Down
Programmable
Vertical Scale
UP/Down
Programmable
Horizontal
Scale UP
Control Register Sets
Interface
PLL
Script Macro Controller
BiTEKBUS / TWSI
Interface
EEPROM
Interface
Programmable Interface
Figure 4-1 BIT1612 Architecture
3
Misc. Function
IR Decoder
Interrupt
PWM
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
33 VSS18
34
35 BOUT0
BOUT1
36
BOUT2
37
BOUT3
38
BOUT4
39
BOUT5
40
BOUT6
41
BOUT7
42
VDD33
43
OCLK
44
SRGB_D0
45
SRGB_D1
46
SRGB_D2
47 SRGB_D3
48 SRGB_D4
49 SRGB_D5
50 SRGB_D6
51 SRGB_D7
52 SRGB_D8
53 GND33
54 SRGB_CK
55 SRGB_CS
56 SRGB_DIO
57 TOUT0
58 TOUT1
59 VDD33
60 TOUT2
61 TOUT3
62 TOUT4
63 VDD18
64 PLL_VDD
AVDD
AGND
YCMY
AIN12
AIN11
AVDD
AGND
BIN7
BIN6
BIN5
BIN4
BIN3
BIN2
BIN1
BIN0
IR
ICLK2
VDD33
OSCO
OSCI
VDD18
OP1
OP0
OP2
OP3
OP4
OP5
SRST
ICLK1
TEST
VSS18
PLL_VSS
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
5 Pin Definition
Figure 5-1 Pin Configuration
Table 5-1 BIT1612 Pin Definition
Pin Name
Pin #
Pin Type
IBEXT
1
AIO
VREFP
2
AIO
VCM
3
AIO
VREFN
4
AIO
AGND
5
AG33
VBG
6
AIO
VCMC
AIN2
AVDD
AGND
7
8
9
10
AI
AI
AP33
AG33
Function Description
Monitor Internal Bias Current Generation or
External Bypass for Use with Some Test Mode
Output for Decoupling or Bypass of
Positive Internal Reference Voltage
Output for Decoupling or Bypass
Common Mode Voltage
Output for Decoupling or Bypass of
Negative Internal Reference Voltage
Analog Ground and Reference Generators
Output for Decoupling or Bypass of
Band-Gap Voltage
Chroma Channel PGA Negative Reference Input
ADC 2 Input (Y / CVBS)
AFE ADC Power (3.3V)
AFE ADC GND (3.3V)
4
Pad Type
BIT1612
ROUT0
ROUT1
VDD33
ROUT2
ROUT3
ROUT4
ROUT5
GND33
ROUT6
ROUT7
VDD18
GOUT0
GOUT1
VDD33
GOUT2
GOUT3
GOUT4
VSS18
GOUT5
GOUT6
GOUT7
GND33
VSS18
BOUT0
BOUT1
BOUT2
BOUT3
BOUT4
BOUT5
BOUT6
BOUT7
VDD33
OCLK
SRGB_D0
SRGB_D1
SRGB_D2
SRGB_D3
SRGB_D4
SRGB_D5
SRGB_D6
SRGB_D7
SRGB_D8
GND33
SRGB_CLK
SRGB_CS
SRGB_DIO
TOUT0
TOUT1
VDD33
TOUT2
TOUT3
TOUT4
VDD18
PLLAVDD
PLLAVSS
10-Bit Digital Video Decoder with OSD and T-CON
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
O
O
P33
O
O
O
O
G33
O
O
P18
O
O
P33
O
O
O
G18
O
O
O
G33
G18
O
O
O
O
O
O
O
O
P33
O
O
O
O
O
O
O
O
O
O
G33
O
O
IO
I/O
I/O
P33
I/O
I/O
I/O
P18
AP18
AG18
ROUT[1] / ~VCOM / Raw Data[0] / GPO[0]
ROUT[2] / ~Q2H / Raw Data[1] / GPO[1]
IO Power (3.3V)
ROUT[3] / STV2 / Raw Data[2]
ROUT[4] / STV1 / Raw Data[3]
ROUT[5] / CKV / Raw Data[4]
ROUT[6] / FRP / Raw Data[5]
IO GND (3.3V)
ROUT[7] / LD / Raw Data[6]
ROUT[8] / VCOM / Raw Data[7]
Core Power (1.8V)
GOUT[1] / ~STV / Raw Data[8] / GPO[2]
GOUT[2] / ~STH / Raw Data[9] / GPO[3]
IO Power (3.3V)
GOUT[3] / OEH / Raw Data[10]
GOUT[4] / STH2 / Raw Data[11]
GOUT[5] / STH1 / Raw Data[12]
Core GND (1.8V)
GOUT[6] / Raw Data[13] / CPH1
GOUT[7] / Raw Data[14] / CPH2
GOUT[8] / Raw Data[15] / CPH3
IO GND (3.3V)
Core GND (1.8V)
BOUT[1] / UD / Raw Data[16] / GPO[4]
BOUT[2] / RL / Raw Data[17] / GPO[5]
BOUT[3] / VCOM_SEL / Raw Data[18]
BOUT[4] / Raw Data[19] / SPI_CS
BOUT[5] / Raw Data[20] / SPI_DO
BOUT[6] / ~OEH / Raw Data[21] / SPI_CK
BOUT[7] / ~CKV / Raw Data[22]
BOUT[8] / ~LD / Raw Data[23]
IO Power (3.3V)
Clock Output
Serial RGB[0] / GPO[0]
Serial RGB[1] / GPO[1]
Serial RGB[2] / GPO[2]
Serial RGB[3] / GPO[3]
Serial RGB[4] / GPO[4]
Serial RGB[5] / GPO[5]
Serial RGB[6] / PWM2
Serial RGB[7] / PWM3
Serial RGB[8] / SPI_CK
IO Power (3.3V)
DAC CLOCK
BIT1690_INF.CS / SPI_CS
BIT1690_INF.DIO / SPI_DO
KEY[0] / STH2 / Raw Data[24]
KEY[1] / STH1 / Raw Data[25]
IO Power (3.3V)
KEY[2] / STV2 / Raw Data[26]
KEY[3] / STV1 / Raw Data[27]
KEY[4] / VCOM_SEL / Raw Data[28]
Core Power (1.8V)
PLL Power (1.8V) – Panel Clock PLL
PLL GND (1.8V) – Panel Clock PLL
5
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT8
POT16
POT4
POT4
POT4
POT4
POT4
POT4
POT4
POT4
POT4
POT4
POT4
PB4
PBCU8
PBCU8
PBCU8
PBCU8
PBCU8
BIT1612
TOUT5
TOUT6
GND33
TOUT7
RTS3
RTS2
RTS1
VDD33
PWM1
PWM2
RIN0
RIN1
RIN2
RIN3
VSS18
RIN4
RIN5
RIN6
RIN7
GIN0
GIN1
GIN2
GIN3
VDD18
GIN4
GIN5
GIN6
GIN7
HSYNC
VSYNC
PLLAVDD
PLLAVSS
VSS18
TEST
ICLK1
SRST
OP5
OP4
OP3
OP2
OP0
OP1
VDD18
OSCI
OSCO
VDD33
ICLK2
IR
BIN0
BIN1
BIN2
BIN3
BIN4
BIN5
BIN6
10-Bit Digital Video Decoder with OSD and T-CON
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
I/O
I/O
G33
I/O
O
O
O
P33
O
O
I
I
I
I
G18
I
I
I
I
I
I
I
I
P18
IO
IO
IO
I
I
I
AP18
AG18
G18
I
I
I
I
I
IO
IO
IO
IO
G18
I
O
P33
I
I
I
I
I
I
I
I
I
KEY[5] / CKV / Raw Data[29]
KEY[6] / LD / Raw Data[30]
IO GND (3.3V)
KEY[7] / OEH / Raw Data[31]
Multi – Function Output
Multi – Function Output
Multi – Function Output
IO Power (3.3V)
PWM1 / GPO[6]
PWM2 / GPO[7]
RIN[1] / KEY[0]
RIN[2] / KEY[1]
RIN[3] / KEY[2]
RIN[4] / KEY[3]
Core GND (1.8V)
RIN[5] / KEY[4]
RIN[6] / KEY[5]
RIN[7] / KEY[6]
RIN[8] / KEY[7]
GIN[0] / EXT_OSD_R
GIN[1] / EXT_OSD_G
GIN[2] / EXT_OSD_B
GIN[3] / EXT_OSD_Blank
Core Power (1.8V)
GIN[4] / EXT_OSD_HS
GIN[5] / EXT_OSD_VS
GIN[6] / EXT_OSD_CLK
GIN[7] / VPG_In
HSYNC Input / KEY[1]
VSYNC Input / KEY[0]
PLL Power (1.8V) – AFE PLL
PLL GND (1.8V) – AFE PLL
Core GND (1.8V)
Test Mode
Clock 1 Input
System Reset, Low Active
Option[5]
Option[4]
SDA2 / Slave Address[1]
SCL2 / Slave Address[0]
SDA (Master and Slave)
SCL (Master and Slave)
Core Power (1.8V)
Oscillator Input
Oscillator Output
IO Power (3.3V)
Clock 2 Input
Infrared Decoder Input
BIN[0] / KEY_IN[0]
BIN[1] / KEY_IN[1]
BIN[2] / KEY_IN[2]
BIN[3] / KEY_IN[3]
BIN[4] / KEY_IN[4]
BIN[5] / KEY_IN[5]
BIN[6] / KEY_IN[6]
6
PBCU8
PBCU8
PBCU8
POT8
POT8
POT8
POT16
POT16
PICD
PICD
PICD
PICD
PICD
PICD
PICD
PICD
PICD
PICD
PICD
PICD
PBCD4
PBCD4
PBCD4
PICD
PICD
PICD
PID
PIS
PIU
PIU
PID
PB4
PB4
PB4
PB4
PIS
PICU
PICU
PICU
PICU
PICU
PICU
PICU
PICU
BIT1612
BIN7
AGND
AVDD
AIN11
AIN12
VCMY
AGND
AVDD
10-Bit Digital Video Decoder with OSD and T-CON
121
122
123
124
125
126
127
128
I
AG33
AP33
AI
AI
AI
AG33
AP33
BIN[7] / KEY_IN[7]
PICU
AFE GND (3.3V)
AFE Power (3.3V)
ADC 1 Channel 1 ( Pb / CVBS )
ADC 1 Channel 2 ( Pr / CVBS)
Luma Composite Channel PGA Negative Reference Input
AFE Band Gap GND (3.3V)
AFE Band Gap Power (3.3V)
Table 5-2 PAD Type Definition
Pad Type
POT4
POT8
POT16
PICD
PB4
PIU
PID
PIS
PBCU4
PBCU4
PBCD4
Function
Controllable Tri-state and 4mA Output Pad Type
Controllable Tri-state and 8mA Output Pad Type
Controllable Tri-state and 16mA Output Pad Type
Controllable Pull-Down Input Pad Type
No Pull-Up and Pull-Down Input and 4mA Output Bidirectional Pad Type
Pull-Up Input Pad Type
Pull-Down Input Pad Type
Schmitt Trigger Input Pad Type
Controllable Pull-Up Input and 4mA Output Bidirectional Pad Type
Controllable Pull-Up Input and 8mA Output Bidirectional Pad Type
Controllable Pull-Down Input and 4mA Output Bidirectional Pad Type
7
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6 Functional Description
6.1 Version Control
BIT1612 內部提供硬體版本資訊及軟體版本資訊,兩組 Register 作為版本控管使用,相關 Register 請參考下
表。
Table 6-1 Version Control Register
Mnemonic
Address R/W
Bits
R_HW_VER
0x000
R
8
R_SW_VER
0x001
RW
8
Description
[1:0] Product version
[4:2] Product Number
[7:5] Product Group
Software Version Control
Default
0xAC
0x00
6.2 Interrupt Function
BIT1612 Interrupt Function提供INT Pin (共有Pin 72、 Pin 71 和Pin 70,R_RTSx_SEL = 0x0B) 作為Interrupt
Trigger Output (請參考“6.10
Special Output Setup”小節的說明),經由Register可設定為Edge or Level trigger
output。當Level Trigger時並可設定為High or Low Active,若為Edge Trigger時則可設定為Falling or Rising Active
。其Interrupt架構採用三層架構 (FLAG、ACK and MASK),架構請參考Figure 6-1。BIT1612 提供 8 個Interrupt
Flags 和 12 個 Interrupt Sources請參考下表 Table 6-2,相關Registers設定請參考 Table 6-3 和 Table 6-4。
Table 6-2 Interrupt Source and Flags
Interrupt Source
Bit
R_HASSIG_FLAG
0
R_NOSIG_FLAG
1
R_MODE_FLAG
2
R_VSYNC_FLAG
3
R_ERROR1_FLAG
4
R_ERROR2_FLAG
5
R_MVCC_FLAG
6
R_IRKEY_FLAG
7
Function
Active when Input HSYNC Has Some
R_INTSIGIN_SEL (0x0FB[5]) = 0
Changes in 2047 XCLKs
Active when Video Decoder Lock
Selected Source (HLCK & SYNC_RDY
R_INTSIGIN_SEL (0x0FB[5]) = 1
& STD_RDY & AGC1_RDY &
AGC2_RDY) (see Table 6-4)
Active when Input HSYNC Has No
R_INTSIGIN_SEL (0x0FB[5]) = 0
Change in 2047 XCLKs
Active when Video Decoder Un-Lock
Selected Source (HLCK & SYNC_RDY
R_INTSIGIN_SEL (0x0FB[5]) = 1
& STD_RDY & AGC1_RDY &
AGC2_RDY) (see Table 6-4)
Active when Input VSYNC Variation
R_INTMODECHG_SEL (0x0FB[6]) = 0
Larger than 8 HSYNCs
Active when Video Decoder FIDT
R_INTMODECHG_SEL (0x0FB[6]) = 1
(50Hz/60Hz) Changes
Active when Selected VSYNC Falling Edge Occurs
R_INTVS_POL (0x005[4]) = 0
VSYNC Normal
R_INTVS_POL (0x005[4]) = 1
VSYNC Invert
R_INT_ERRSEL (0x006[4]) = 0
Active when Timer 0 Overflow
Active when Line Buffer Error Type 1
R_INT_ERRSEL (0x006[4]) = 1
Occurs
R_INT_ERRSEL (0x006[4]) = 0 Active when Timer 1 Overflow
VP
Active when Line Buffer Error Type 2
R_INT_ERRSEL (0x006[4]) = 1
Occurs
VD From SRC2 (AIN2) or SRC12 (AIN12) or SRC11 (AIN11) (see Table 6-4)
MV or CC Detection (see Table 6-4)
Active when IR Remote Control Detection is Ready or
Active when GPI (General Purpose Input) Status Changes
8
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Table 6-3 Interrupt Controller Register
Mnemonic
Address
R/W Bits
R_INT_FLAG
0x002[7:0]
R
8
R_INT_MASK
0x003[7:0]
RW
8
R_INT_ACK
0x004[7:0]
RW
8
R_INT_TYPE
0x005[0]
RW
1
R_POL_INT
0x005[1]
RW
1
R_INTSIGIN_SEL
0x0FB[5]
RW
1
R_INTMODECHG_SEL 0x0FB[6]
RW
1
R_INT_VSSE
0x005[3:2]
RW
2
R_INTVS_POL
0x005[4]
RW
1
R_VP_ERR2_EN
0x006[3]
RW
1
R_INT_ERRSEL
0x006[4]
RW
1
R_ERROR_TYPE
0x006[5]
RW
1
R_IHSPS_SEL
0x04D[7]
RW
1
Description
Interrupt Flag
0: Nothing
1: Interrupt Event Occurs
Interrupt MASK (see Figure 6-1)
0: Interrupt Mask Off (Enable Interrupt)
1: Interrupt Mask On (Disable Interrupt)
Interrupt ACK (see Figure 6-1)
0: Clear Interrupt Flag and Disable Interrupt
1: Enable Interrupt
Interrupt TYPE
0: Level Type
1: Edge Type
Interrupt Polarity
0: High Level Active (Level Type)
0: Rising Edge Active (Edge Type)
1: Low Level Active (Level Type)
1: Falling Edge Active (Edge Type)
Interrupt Vector[0] and Vector[1]
Source Selection
0: From VP
1: From VD
Interrupt Vector[2] Source Selection
0: From VP
1: From VD
Interrupt Vector[3] Source Selection
00: VSYNC from Input VSYNC Source
01: VSYNC from Output VSYNC Source
10: VSYNC from VD VSYNC Source
11: VSYNC Source Active when TWSI
Detection Occurs.
Interrupt Vector[3] Polarity Selection
0: Normal
1: Invert
Interrupt Vector[5] VP Error Source Enable
0: Disable
1: Enable
Interrupt Vector[4] and Vector[5]
Source Selection
0: From Timer Overflow
1: From Line Buffer Error
Line Buffer Error Detection Selection
0: ODD Field
1: EVEN Field
IHS Pulse Width Selection
0: Type 0
1: Type 1
Default
-
0x00
0x00
0
0
0
0
00
0
0
0
0
0
Table 6-4 Video Decoder Lock Source for Interrupt Selection
Mnemonic
Address
R_INTHLCK_EN
0x0FB[0]
R/W Bits
RW
Description
HLCK Detection Enable
1 0: Disable
1: Enable
9
Default
0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_INTSYNCRDY_EN
0x0FB[1]
RW
R_INTSTDRDY_EN
0x0FB[2]
RW
R_INTAGC1_EN
0x0FB[3]
RW
R_INTAGC2_EN
0x0FB[4]
RW
R_INTSRC2_EN
0x006[0]
RW
R_INTSRC12_EN
0x006[1]
RW
R_INTSRC11_EN
0x006[2]
RW
R_INTMV_EN
0x006[6]
RW
R_INTCC_EN
0x006[7]
RW
Sync Ready Detection Enable
1 0: Disable
1: Enable
Standard Ready Detection Enable
1 0: Disable
1: Enable
AGC1 Ready Detection Enable
1 0: Disable
1: Enable
AGC2 Ready Detection Enable
1 0: Disable
1: Enable
SRC2 (AIN2) Detection Enable
1 0: Disable
1: Enable
SRC12 (AIN12) Detection Enable
1 0: Disable
1: Enable
SRC11 (AIN11) Detection Enable
1 0: Disable
1: Enable
MV Detection Enable
1 0: Disable
1: Enable
CC Detection Enable
1 0: Disable
1: Enable
0
0
0
0
0
0
0
0
0
R_INT_FLAG
R_INT_ACK
R_INT_MASK
FF
Interrupt
Control
Interrupt
Source
Figure 6-1 Interrupt Function Block
10
INT
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.3 Double Buffer
BIT1612 在Scaling Factor (0x05F~0x061,0x067) 和Display Windows Setup (0x052~0x057) 提供Double
Buffer Register,提供給使用者針對這些Registers可以做Parallel Update,其相關架構請參考 Figure 6-2,相關
Registers設定請參考 Table 6-5。
Double Buffer Regs
Register Table
DI
DO
DI
DO
0
1
VSYNC
R_LOAD_EN
(0x00C[5])
MUX
LOAD
R_LOAD_TYPE (0x00C[6])
Figure 6-2 Double Buffer Function
Table 6-5 Double Buffer Register
Mnemonic
Address
R/W Bits
R_LOAD_EN
0x00C[5]
RW
R_LOAD_TYPE
0x00C[6]
RW
Description
Double Buffer Load Enable
1 0: Nothing
1: Load
Double Buffer Register Update Type
1 0: Immediately
1: Control by R_LOAD_EN
11
Default
1
0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.4 Pad Type Setup
BIT1612 輸出的 PAD 可設定為 Tri-State 輸出,而輸入的 PAD 尚可控制其內建之 Pull-Up or Pull-Down 電阻
導通或關閉,相關 Registers 設定請參考下表。
Table 6-6 Output Tri-State Control Register
Mnemonic
R_ROUT_TRI
R_GOUT_TRI
R_BOUT_TRI
R_TOUT_TRI
R_OCLK_TRI
R_PWM1_TRI
R_PWM2_TRI
Address
0x007[0]
0x007[1]
0x007[2]
0x007[3]
0x007[4]
0x007[5]
0x007[6]
R/W
RW
RW
RW
RW
RW
RW
RW
Bits
1
1
1
1
1
1
1
R_SRGB_TRI
0x007[7]
RW
1
Description
ROUT Port Tri-State Enable
GOUT Port Tri-State Enable
BOUT Port Tri-State Enable
TOUT Port Tri-State Enable
OCLK (43) Pin Tri-State Enable
PWM1 (74) Pin Tri-State Enable
PWM2 (75) Pin Tri-State Enable
SRGB Port Tri-State Enable
1 Î Tri-State, 0 ÎNormal
Default
1
1
1
1
1
1
1
0
Table 6-7 Pad Pull Up or Down Control Register
Mnemonic
R_BIN_REN
R_TOUT_REN
R_RIN_REN
R_GIN_REN
R_GIN1_REN
Address
0x0FD[7:0]
0x0FE[7:0]
0x0FF[0]
0x0FF[1]
0x0FF[2]
R/W
RW
RW
RW
RW
RW
Bits
8
8
1
1
1
R_SYNC_REN
0x0FF[3]
RW
1
R_IR_REN
0x0FF[4]
RW
1
Description
BIN[7:0] Port Pull-Down Resistance On/Off
TOUT[7:0] Port Pull-Up Resistance On/Off
RIN[7:0] Port Pull-Down Resistance On/Off
GIN[7] Pin Pull-Down Resistance On/Off
GIN[6:0] Port Pull-Down Resistance On/Off
HSYNC/VSYNC Pins Pull-Down Resistance
On/Off
IR (Pin 113) Pin Pull-Down Resistance On/Off
1 Î Off, 0 ÎOn
12
Default
0x00
0xFF
0
0
0
0
0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.5 GPO (General Purpose Output) Function
BIT1612 內部提供 8 個GPO Register control輸出、其可分別規劃為High Level、Low Level、Tri-State和Status
四種狀態。其相關Registers設定請參考 Table 6-8 和 Table 6-9。
Table 6-8 General Purpose Output Register
Mnemonic
Address
R/W Bits
R_GPO_SEL
0x008[7:0]
RW
R_GPO_TYPE
0x009[7:0]
RW
R_GPO_REG
0x00A[7:0]
RW
Description
GPO Port Enable
8 0: Disable
1: Enable
GPO Port Type
8 0: Normal
1: Tri-State
GPO Port Value
8 0: Low Level
1: High Level
Default
0x00
0xFF
0x00
Table 6-9 General Purpose Output Pads Setup Table
GPO Pin Name/ No.
GPO[0]
GPO[1]
GPO[2]
GPO[3]
GPO[4]
GPO[5]
GPO[6]
GPO[7]
GPO[0]
GPO[1]
GPO[2]
GPO[3]
GPO[4]
GPO[5]
Output Pin
SRGB_D0(44)
SRGB_D1(45)
SRGB_D2(46)
SRGB_D3(47)
SRGB_D4(48)
SRGB_D5(49)
PWM1(74)
PWM2(75)
ROUT[0](11)
ROUT[1](12)
GOUT[0](22)
GOUT[1](23)
BOUT[0](34)
BOUT[1](35)
Register Recommended Setting
R_GPO_OUT (0x13C[5]) = 1
R_GPO_OUT (0x13C[5]) = 1
R_GPO_OUT (0x13C[5]) = 1
R_GPO_OUT (0x13C[5]) = 1
R_GPO_OUT (0x13C[5]) = 1
R_GPO_OUT (0x13C[5]) = 1
R_GPO_SEL[6] = 1
R_GPO_SEL[7] = 1
R_GPO_SEL[0] = 1
R_GPO_SEL[1] = 1
R_GPO_SEL[2] = 1
R_GPO_SEL[3] = 1
R_GPO_SEL[4] = 1
R_GPO_SEL[5] = 1
6.6 System Enable and Reset
BIT1612 可以從外部SRST PIN (Pin 101) 輸入一個大於 16 個XCLK Cycles的Low訊號,BIT1612 將被強制
Reset 回到Power On 時的狀態。相關波形請參考 Figure 6-3。
Reset Pulse must be longer than 16 XCLK cycles
RESET
PIN
Figure 6-3 Hardware Reset Waveform
13
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.7 Clock Domain Systems
BIT1612 內部存在五個 Clock Domain:
1. PCLK Domain: Source Clock
2. LCLK Domain: Output Clock
3. XCLK Domain: System Clock
4. MCLK Domain: Image Clock
5. TCLK Domain: Panel Clock
相關Registers設定請參考 Table 6-10。
注意事項:XCLK Domain 頻率必須比 LCLK Domain 低。
Table 6-10 Clock Domain System Register
Mnemonic
Address
R/W Bits
R_XCLK_SEL
0x00B[6:4] RW
3
R_TCLK_SEL
0x00C[2:0] RW
3
R_TCLK_POL
0x00C[3]
RW
1
R_TCLK_EN
0x00C[4]
RW
1
R_LCLK_SEL
0x00D[5:4] RW
2
R_LCLK_POL
0x00D[6]
RW
1
R_LCLK_EN
0x00D[7]
RW
1
R_MCLK_SEL
0x00E[1:0] RW
2
R_MCLK_POL
0x00E[2]
RW
1
R_MCLK_EN
0x00E[3]
RW
1
R_PCLK_SEL
0x00E[5:4] RW
2
R_PCLK_POL
0x00E[6]
RW
1
R_PCLK_EN
0x00E[7]
RW
1
Description
XCLK Domain Clock Source Selection
XCLK = OSCCLK / (2^R_XCLK_SEL)
TCLK Domain Clock Source Selection
000: PLLCLK
001: OSCCLK
010: ICLK1
011: ICLK2
1xx: VDCLK
TCLK Domain Polarity
0: Normal.
1: Invert.
TCLK Domain Enable
0: Disable.
1: Enable.
LCLK Domain Clock Source Selection
00: Normal Clock (Freq. equals to LCLK)
01: Phase 1 Clock (Freq. equals to LCLK/3)
10: Phase 2 Clock (Freq. equals to LCLK/3)
11: Phase 3 Clock (Freq. equals to LCLK/3)
LCLK Domain Polarity
0: Normal
1: Invert
LCLK Domain Enable
0: Disable
1: Enable
MCLK Domain Clock Source Selection
MCLK = PCLK / (R_MCLK_MODE+1)
MCLK Domain Polarity
0: Normal
1: Invert
MCLK Domain Enable
0: Disable
1: Enable
PCLK Domain Clock Source Selection
00: ICLK1
01: ICLK2
1x: VDCLK
PCLK Domain Polarity
0: Normal
1: Invert
PCLK Domain Enable
0: Disable
14
Default
000
001
0
1
10
0
1
01
1
1
00
1
1
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_DACCLK_EN
0x00B[2]
RW
1
R_DACCLK_POL
0x00B[3]
RW
1
R_LCLK_4X
0x00B[7]
RW
1
R_LINEBUF_CKEN 0x00D[1]
RW
1
R_REGS_CKEN
0x00D[2]
RW
1
R_VDCLK_SEL
0x00D[3]
RW
1
R_AFEBUF_SEL
0x00F[6]
RW
1
R_AFEBUF_POL
0x00F[7]
RW
1
R_AFECLK_SEL
0x00F[4]
RW
1
R_AFECLK_POL
0x00F[5]
RW
1
R_AFECLK_EN
0x00F[3]
RW
1
R_DVPCLK_SEL
0x00F[1]
RW
1
R_DVPCLK_POL
0x00F[2]
RW
1
R_DVPCLK_EN
0x00F[0]
RW
1
R_CLK27_POL
0x0EF[0]
RW
1
R_CLK27_EN
0x0EF[1]
RW
1
R_LN5CLK_POL
0x0F7[4]
RW
1
R_LN4CLK_POL
0x0F7[3]
RW
1
1: Enable
DAC Clock Domain Enable
0: Disable
1: Enable
DAC Clock Domain Polarity
0: Normal
1: Invert
LCLK x 4 Enable
0: Disable
1: Enable
LINEBUF Clock Enable
0: Disable
1: Enable
Registers set Clock Enable
0: Disable
1: Enable
VD Clock Domain Clock Source Selection
0: From 27MHz
1: From 13.5MHz
AFE Buffer Clock Domain Clock Source Selection
0: From DVPCLK.
1: From AFECLK
AFE Buffer Clock Domain Polarity
0: Normal
1: Invert
AFE Clock Domain Clock Source Selection
0: From 27MHz
1: From 13.5MHz
AFE Clock Domain Polarity
0: Normal
1: Invert
AFE Clock Domain Enable
0: Disable
1: Enable
DVP Clock Domain Clock Source Selection
0: From PLL
1: From OSC
DVP Clock Domain Polarity
0: Normal
1: Invert
DVP Clock Domain Enable
0: Disable
1: Enable
CLK27 Domain Polarity
0: Normal
1: Invert
CLK27 Domain Enable
0: Disable
1: Enable
Line Buffer Clock 5 Polarity
0: Normal
1: Invert
Line Buffer Clock 4 Polarity
0: Normal
1: Invert
15
1
1
0
1
1
1
1
1
0
1
1
0
1
1
0
1
0
0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_LN3CLK_POL
0x0F7[2]
RW
R_LN2CLK_POL
0x0F7[1]
RW
R_LN1CLK_POL
0x0F7[0]
RW
Line Buffer Clock 3 Polarity
1 0: Normal
1: Invert
Line Buffer Clock 2 Polarity
1 0: Normal
1: Invert
Line Buffer Clock 1 Polarity
1 0: Normal
1: Invert
0
0
0
6.8 Panel Timing Setup
BIT1612 可分別針對Auto Switch所設定的顯示模式,分為Mode 0/1 兩組自動切換Panel Timing設定值,其相
關設定Register請參考 Table 6-11 所列,相對應之輸出波形請參考 Figure 6-4。
Table 6-11 Panel Timing Setup Register
Mnemonic
R_OS_XP
R_OS_XS
Address
0x013[0], 0x010[7:0]
0x013[1], 0x011[7:0]
0x013[6:4],
R_OS_XW
0x012[7:0]
0x016[2:0],
R_OS_XT_M0
0x014[7:0]
0x016[6:4],
R_OS_XT_M1
0x015[7:0]
R_OS_YP
0x017[7:0]
R_OS_YS
0x018[7:0]
0x01B[1:0],
R_OS_YW
0x019[7:0]
0x01B[3:2],
R_OS_YT
0x01A [7:0]
R/W
RW
RW
Bits
Description
9 HSYNC Pulse Width
9 Active Window Horizontal Start Position
RW
11
RW
11
RW
11
RW
RW
Active Window Horizontal End Position
Default
0x010
0x020
0x200
0x29D
8
8
Horizontal Total Length on Auto Switch
Mode 0
Horizontal Total Length on Auto Switch
Mode 1
VSYNC Pulse Width
Active Window Vertical Start Position
RW
10
Active Window Vertical End Position
0x0F0
RW
10
Vertical Total Length
0x0F4
(0,0)
0x326
0x02
0x05
HSYNC Output
R_OS_XS
R_OS_XW
VSYNC Output
R_OS_XT_M0
R_OS_XT_M1
Figure 6-4 Panel Timing Setup
16
R_OS_YT
Panel Active Window
R_OS_YW
R_OS_YP
Blank Range
R_OS_YS
R_OS_XP
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.9 Output Data Path
BIT1612 可針對輸出的Data Bus分別做Invert、Rotate和Swap的處理,其相關Registers設定請參考
Table 6-12,相對應方塊圖請參考 Figure 6-5。
Table 6-12 Output Data Path Register
Mnemonic
R_POL_ROUT
R_POL_GOUT
R_POL_BOUT
R_POL_OCLK
R_ROL_ROUT
R_ROL_GOUT
R_ROL_BOUT
R_DLYE_OR
R_DLYE_OG
R_DLYE_OB
R_ZERO2_EN
R_DLYO_OR
R_DLYO_OG
R_DLYO_OB
R_6BITS_EN
R_SWAPE_OGB
R_SWAPE_ORG
R_SWAPE_ORB
R_ZERO1_EN
R_SWAPO_ORB
R_SWAPO_ORG
R_SWAPO_OGB
R_SWAP_SRC
Address R/W Bits
Description
Default
0x01C[0] RW 1 R Data Output Polarity Î 0: Normal 1: Invert
0
0x01C[1] RW 1 G Data Output Polarity Î 0: Normal 1: Invert
0
0x01C[2] RW 1 B Data Output Polarity Î 0: Normal 1: Invert
0
0x01C[3] RW 1 Output Clock Polarity Î 0: Normal 1: Invert
0
0x01C[4] RW 1 R Data Rotate Î 0: Disable 1: Enable
0
0x01C[5] RW 1 G Data Rotate Î 0: Disable 1: Enable
0
0x01C[6] RW 1 B Data Rotate Î 0: Disable 1: Enable
0
0x01D[0] RW 1 R Channel Output Delay 1 Clock on Swap Source = 0
0
0x01D[1] RW 1 G Channel Output Delay 1 Clock on Swap Source = 0
0
0x01D[2] RW 1 B Channel Output Delay 1 Clock on Swap Source = 0
0
Data Tie to Zero after Gamma
0x01D[3] RW 1 0: Disable
0
1: Enable
0x01D[4] RW 1 R Channel Output Delay 1 Clock on Swap Source = 1
0
0x01D[5] RW 1 G Channel Output Delay 1 Clock on Swap Source = 1
0
B Channel Output Delay 1 Clock on Swap Source = 1
0x01D[6] RW 1 0: Disable
0
1: Enable
Data Bus Rotate Mode
0x01D[7] RW 1 0: 8 Bits
0
1: 6 Bits
G Data Output Swap with B Data Output on Swap
0x01E[0] RW 1 Source = 0
1
0: Swap Disable 1: Swap Enable
R Data Output Swap with G Data Output on Swap
0x01E[1] RW 1 Source = 0
0
0: Swap Disable 1: Swap Enable
R Data Output Swap with B Data Output on Swap
0x01E[2] RW 1 Source = 0
1
0: Swap Disable 1: Swap Enable
Data Tie to Zero before Gamma
0x01E[3] RW 1 0: Disable
0
1: Enable
R Data Output Swap with B Data Output on Swap
0x01E[6] RW 1 Source = 1
0
0: Swap Disable 1: Swap Enable
R Data Output Swap with G data Output on Swap
0x01E[5] RW 1 Source = 1
0
0: Swap Disable 1: Swap Enable
G Data Output Swap with B Data Output on Swap
0x01E[4] RW 1 Source = 1
0
0: Swap Disable 1: Swap Enable
Even / Odd Swap Source
0x01E[7] RW 1 0: Q2H
0
1: VCOM
17
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Figure 6-5 Output Data Path Selection
6.10 Special Output Setup
BIT1612 提供 3 組Special Output Pads (RTS1 (Pin 72)、RTS2 (Pin 71) 和RTS3 (Pin 70) ),可經由Register
分別設定特定輸出功能,其相關Registers設定及其意義請參考 Table 6-13。
R_RTS1_SEL = { 0x020[4], 0x01F[3:0] }, Default = 0x0F.
R_RTS2_SEL = { 0x020[5], 0x01F[7:4] }, Default = 0x0F.
R_RTS3_SEL = { 0x020[6], 0x020[3:0] }, Default = 0x0F.
Table 6-13 Special Output Setup
Mnemonic
R_RTSx_SEL
R/W Bits
RW
Description
0_0000: Output HSYNC Signal
1_0000: Inverse ( HSYNC )
0_0001: Output HREF Signal
1_0001: Inverse ( HREF )
0_0010: Output VSYNC Signal
1_0010: Inverse ( VSYNC )
0_0011: Output VREF Signal
1_0011: Inverse ( VREF )
0_0100: Output Data Enable Signal 1_0100: Inverse ( DE )
0_0101: Output EVEN/ODD Signal
1_0101: Inverse ( EVEN/ODD )
0_0110: STH
1_0110: Inverse ( STH )
0_0111: STV
1_0111: Inverse ( STV )
5
0_1000: Mode Type
1_1000: Inverse ( Mode Type )
0_1001: Auto-On
1_1001: Inverse ( Auto-On )
0_1010: Write Protect
1_1010: Inverse ( Write Protect )
0_1011: INT_O
1_1011: Inverse ( INT_O )
0_1100: GPO[7]
1_1100: Inverse ( GPO[7] )
0_1101: PWMx
1_1101: Inverse ( PWMx )
0_1110: GND
1_1110: VDD
0_1111: Tri-State
1_1111: Tri-State
18
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.11 Special Timing Adjustment
BIT1612 可針對不同的 Panel Timing 做微調設定,在 Timing 調整上特別提供兩種模式設定,以符合各類 panel
的需求。
6.11.1
Synchronization Timing
在這個模式下的 VSYNC 輸出將會與輸入訊號 VSYNC 同步。
Input VSYNC
Output VSYNC
Figure 6-6 Synchronization Timing
6.11.2
Two-Fields Synchronization Timing
在這個模式下的 VSYNC 輸出,將同時受控於所設定欲同步之 EVEN 或 ODD Field VSYNC 和
R_OS_YT (0x01B[3:2], 0x01A[7:0])。
Figure 6-7 Two-Fields Synchronization Timing
其相關 Registers 設定及其意義請參考下表。
Table 6-14 Special Timing Adjust Register
Mnemonic
Address R/W
Bits
R_PROTECT_MODE
0x01B[4]
RW
1
R_SYNCO_MODE
0x01B[5]
RW
1
R_SYNCO_EN
0x01B[6]
RW
1
Description
Minimum Output Lines Protection
0: Disable
1: Enable
Two-Field Synchronization Mode Selection
0: EVEN Field Synchronize
1: ODD Field Synchronize
Sync. With Input VSYNC Enable
0: Two-Field Synchronization Mode
1: Synchronization Mode
19
Default
0
0
1
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.12 TCON Function
BIT1612 內建 Programmable TCON Function 將可經由 BIT1612 直接驅動 Analog Interface Panels,其相關
Registers 設定請參考下表。
Table 6-15 TCON Function Register
Mnemonic
R/W Bits
R_POL_CKV
R_POL_STV
R_POL_STH
R_POL_LD
R_POL_FRP
Address
0x023[6:4],
0x021[7:0]
0x023[2:0],
0x022[7:0]
0x026[6:4],
0x024[7:0]
0x026[2:0],
0x025[7:0]
0x029[6:4],
0x027[7:0]
0x029[2:0],
0x028[7:0]
0x02C[6:4],
0x02A[7:0]
0x02C[2:0],
0x02B[7:0]
0x030[6:4],
0x02D[7:0]
0x030[3:2],
0x02E[7:0]
0x030[1:0],
0x02F[7:0]
0x031[0]
0x031[1]
0x031[2]
0x031[3]
0x031[4]
R_POL_OEH
Description
Default
RW
11 STH Signal Start
0x025
RW
11 STH Signal End
0x026
RW
11 LD Signal Start
0x001
RW
11 LD Signal End
0x037
RW
11 CKV Signal Start
0x027
RW
11 CKV Signal End
0x051
RW
11 OEH Signal Start
0x014
RW
11 OEH Signal End
0x015
RW
11 VCOM Shift
0x014
RW
10 STV Signal Start
0x003
RW
10 STV Signal End
0x004
RW
RW
RW
RW
RW
1
1
1
1
1
0x031[5]
RW
1
R_OEH_GATE
0x031[6]
RW
1
R_TCON_EN
0x031[7]
RW
1
R_STV_SEL
0x032[0]
RW
1
R_STH_SEL
0x032[1]
RW
1
R_TCON_UD
0x032[2]
RW
1
R_TCON_RL
0x032[3]
RW
1
R_POL_Q2H
0x032[4]
RW
1
R_STH_START
R_STH_END
R_LD_START
R_LD_END
R_CKV_START
R_CKV_END
R_OEH_START
R_OEH_END
R_VCOM_SHIFT
R_STV_START
R_STV_END
20
CKV Output Polarity
STV Output Polarity
STH Output Polarity
LD Output Polarity
FRP Output Polarity
OEH Output Polarity
0: Normal
1: Invert
OEH gated with output data enable
0: Disable
1: Enable
TCON Function Enable
0: Disable
1: Enable
STV Output Selection
0: STV1 = OUT, STV2= IN
1: STV1 = IN, STV2 = OUT
STH Output Selection
0: STH1 = OUT, STH2= IN
1: STH1 = IN, STH2 = OUT
TCON U/D Signal
0: Low Level
1: High Level
TCON R/L Signal
0: Low Level
1: High Level
Q2H Output Polarity
0: Normal
0
0
0
0
0
1
0
1
0
1
0
1
0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_LTPS_MODE
0x032[5]
RW
1
R_VCOM_SEL
0x032[7:6]
RW
2
R_VCOM_TYPE
0x033[7:6]
RW
2
R_BUS_INV
0x034[7:6]
RW
2
R_STV_SHIFT_E
R_STV_SHIFT_O
0x0F8[6:4],0x0F9[7:0] RW
0x0F8[2:0],0x0FA[7:0] RW
11
11
R_STV_SHIFT_SRC
0x036[0]
RW
1
R_STV_SHIFT_TYPE 0x036[1]
RW
1
R_STV_SHIFT_CUT
RW
1
0x036[2]
21
1: Invert
LTPS Mode Selection
0: Normal Mode
1: LTPS TCON Mode
VCOM Output Signal Selection
00: VCOM Signal
01: PREFRP Signal
10: FRP Signal
11: Q2H Signal
VCOM Signal TYPE
00: Always 0
01: Always 1
10: FRP Invert
11: FRP
Data Bus Control on FRP
00: Disable
01: Follow Shift VCOM
10: Follow FRP
11: Follow Invert FRP
STV Shift Start
STV Shift End
STV Output Selection
0: Type 0
1: Type 1
STV Output Type
0: Type 0
1: Type 1
STV Line Cut
0: Disable
1: Enable
0
00
11
11
0x000
0x000
0
0
0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.13 TCON Clock Mode
BIT1612 提供多種 TCON CPH Clock 模式,其相關 Registers 設定請參考下表。
Table 6-16 TCON Clock Mode Register
Mnemonic
R_CPH1E_CKSEL
R_CPH2E_CKSEL
R_CPH3E_CKSEL
R_CPH1O_CKSEL
R_CPH2O_CKSEL
R_CPH3O_CKSEL
R_CPH1_EN
R_CPH2_EN
Address
0x033[1:0]
0x033[3:2]
0x033[5:4]
0x034[1:0]
0x034[3:2]
0x034[5:4]
0x035[0]
0x035[1]
R_CPH3_EN
0x035[2]
R_CPH_HALF
0x035[3]
R_CPH1_POL
R_CPH2_POL
R_CPH3_POL
0x035[4]
0x035[5]
0x035[6]
R/W Bits
Description
Default
RW
2 CPH1 Clock Type Selection on Swap Source = 0
01
RW
2 CPH2 Clock Type Selection on Swap Source = 0
01
RW
2 CPH3 Clock Type Selection on Swap Source = 0
01
RW
2 CPH1 Clock Type Selection on Swap Source = 1
01
RW
2 CPH2 Clock Type Selection on Swap Source = 1
01
RW
2 CPH3 Clock Type Selection on Swap Source = 1
01
RW
1 CPH1 Output Enable
1
RW
1 CPH2 Output Enable
1
CPH3 Output Enable
RW
1 0: Disable
1
1: Enable
TCON Clock Output Mode
RW
1 0: Normal Mode
0
1: Half Clock Mode
RW
1 CPH1 Polarity
0
RW
1 CPH2 Polarity
0
RW
1 CPH3 Polarity
0
6.14 Display Layer
BIT1612 提供五層 Display Layer 以疊層架構顯示在 Panel 上,高優先權的 Layer 可覆蓋在低優先權的 Layer
相關說明請參考下圖。例如:Layer 5 優先權高於 Layer 4。
Layer 5
Internal OSD
External OSD
22
Panel
Layer 4
Background 1
Image Data
Layer 3
Layer 2
Background 2
Display Windows
Layer 1
Output Windows
Figure 6-8 Display Layer
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.15 Background 2
BIT1612 內部提供 64 種背景色以提供在 4:3 模式下的邊框顯示,其相關Registers設定及其意義請參考
Table 6-17。
Table 6-17 Background 2 Register
Mnemonic
Address
R/W
Bits
R_BG2_R
0x037[7:6]
RW
2
R_BG2_G
0x038[7:6]
RW
2
R_BG2_B
0x039[7:6]
RW
2
Description
Background 2’s R Color used for 4:3
display
Background 2’s G Color used for 4:3
display
Background 2’s B Color used for 4:3
display
Default
00
00
00
6.16 Background 1 and Test Pattern Setup
BIT1612 內部提供 8 種內定Test Patterns,分別為 262144 種純色、分隔線與漸層 (Ramp),其相關Registers
設定及其意義請參考 Table 6-18。
Table 6-18
Background and Test Pattern Register
Mnemonic
R_TESTPAT_R
R_TESTPAT_G
R_TESTPAT_B
R_TESTPAT_Q
Address
0x037[5:0]
0x038[5:0]
0x039[5:0]
0x03A[7:0]
R/W
RW
RW
RW
RW
Bits
6
6
6
8
R_TESTPAT_TYPE
0x03B[1:0]
RW
2
R_TESTPAT_DIR
0x03B[2]
RW
1
R_TESTPAT_HV
0x03B[3]
RW
1
R_BACKGROUND_EN
0x03B[6]
RW
1
R_FREERUN_EN
0x03B[7]
RW
1
Description
Test Pattern R Color Value
Test Pattern G Color Value
Test Pattern B Color Value
Test Pattern gradient ratio
Test Pattern Type
00: 262144 純色
01: 漸層(Ramp) Ratio = 1 pixel
10: 分隔線(Grid) Ratio = 16 pixels
11: 漸層(Ramp) Ratio = 16 pixels
漸層的變化
0: Decrease
1: Increase
漸層的方向
0: Vertical
1: Horizontal
Background Mode Enable
0: Disable
1: Enable
Free-Run Mode Enable
0: Disable
1: Enable
23
Default
0x00
0x00
0x3F
0x00
00
0
0
0
0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Figure 6-9 Free Run and Background
6.17 Auto Blank Screen
BIT1612 內建自動 Blank Screen Function,當訊號中斷或模式切換時將會自動啟動 Blank Screen 畫面,相關
Registers 設定請參考下表。
Table 6-19 Blank Screen Register
Mnemonic
Address
R/W
Bits
R_AUTOON_TIME
0x03C[6:0]
RW
7
R_AUTOON_EN
0x03C[7]
RW
1
R_NOSIG_SEL
0x0FC[5]
RW
1
0x0FC[0]
RW
1
0x0FC[1]
RW
1
0x0FC[2]
RW
1
0x0FC[3]
RW
1
0x0FC[4]
RW
1
R_HLCK_SEL
Description
Blank Screen to Normal Screen Delay
Times (Based on VSYNC)
Blank Screen Function Enable
0: Disable
1: Enable
Blank Screen Function Signal Selection
0: From VP Signal
1: From VD Signal (R_HLCK_SEL)
HLCK Detection Enable
0: Disable
1: Refer to HLCK
Sync Ready Detection Enable
0: Disable
1: Refer to SYNC
Standard Ready Detection Enable
0: Disable
1: Refer to STD
AGC1 Ready Detection Enable
0: Disable
1: Refer to AGC1
AGC2 Ready Detection Enable
0: Disable
1: Refer to AGC2
24
Default
0x0D
1
0
1
1
0
0
0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.18 Input Image Window Setup
設定Input Image Window,BIT1612 將針對此區域內的資料進行Scaling運算。其相關Registers設定請參考
Table 6-20,相對應之示意圖請參考 Figure 6-10。
Table 6-20 Input Crop Register
Mnemonic
Address
R/W
Auto Switch Mode 0 Input Widows Setup
0x040[1:0],
RW
R_IS_XS_M0
0x03E[7:0]
0x040[7:4],
RW
R_IS_XW_M0
0x03F[7:0]
0x043[1:0],
RW
R_IS_YS_M0
0x041[7:0]
0x043[6:4],
RW
R_IS_YW_M0
0x042[7:0]
Auto Switch Mode 1 Input Windows Setup
0x046[1:0],
RW
R_IS_XS_M1
0x044[7:0]
0x046[7:4],
RW
R_IS_XW_M1
0x045[7:0]
0x049[1:0],
RW
R_IS_YS_M1
0x047[7:0]
0x049[6:4],
RW
R_IS_YW_M1
0x048[7:0]
Bits
Description
Default
10 Input Window horizontal Start Position
0x09A
12 Input Window horizontal End Position
0x346
10 Input Window vertical Start Position
0x018
11 Input Window vertical End Position
0x133
10 Input Window horizontal Start Position
0x08C
12 Input Window horizontal End Position
0x33C
10 Input Window vertical Start Position
0x015
11 Input Window vertical End Position
0x100
(0,0)
Input Image Window
R_IS_YW
Blank Range
R_IS_YS
HSYNC Input
R_IS_XS
R_IS_XW
VSYNC Input
Figure 6-10 Input Window Setup
6.19 Input Data Path Setup
BIT1612 可針對輸入的Data Bus分別做Invert、Rotate 和 Swap 的處理,其相關Registers設定請參考
Table 6-21,相對應之方塊圖請參考 Figure 6-11。
Table 6-21 Input Data Path Register
Mnemonic
R_POL_RIN
R_POL_GIN
R_POL_BIN
Address R/W
0x04A[0] RW
0x04A[1] RW
0x04A[2] RW
Bits
Description
1 R Data input Polarity Î 0: Normal 1: Invert
1 G Data input Polarity Î 0: Normal 1: Invert
1 B Data input Polarity Î 0: Normal 1: Invert
25
Default
0
0
0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_ROL_RIN
R_ROL_GIN
R_ROL_BIN
R_ISWAP_RB
R_ISWAP_RG
R_ISWAP_GB
0x04A[3]
0x04A[4]
0x04A[5]
0x04C[0]
0x04C[1]
0x04C[2]
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
R_VD_PATH
0x04C[3] RW
1
R Port
Y
0
1
(Internal VD)
B Port
Cb
Cr
(Internal VD)
1
0
M
U
X
R_VD_PATH
R_POL_RIN
0
1
1
(Internal VD)
G Port
M
U
X
M
U
X
0
M
U
X
R_VD_PATH
R_POL_BIN
0
1
1
M
U
X
R_VD_PATH
0
R Data Rotate Î 0: Disable 1: Enable
G Data Rotate Î 0: Disable 1: Enable
B Data Rotate Î 0: Disable 1: Enable
R Data bus swap B Data bus Î 0: Disable 1: Enable
R Data bus swap G Data bus Î 0: Disable 1: Enable
G Data bus swap B Data bus Î 0: Disable 1: Enable
Bus Selection Î0: External RGB Port; 1: Internal
Video Decoder
0
1
M
U
X
1
0
R_ISWAP_RB
0
1
Rotate
M
U
X
0
M
U
X
Rotate
0
M
U
X
1
0
M
U
X
R_ISWAP_RG R_ISWAP_GB
Figure 6-11 Input Data Path Setup
26
1
0
R_ISWAP_GB
1
M
U
X
0
Pre_RIN
R_ROL_RIN
1
R_ISWAP_RB
1
0
R_ISWAP_RG
M
U
X
R_POL_GIN
M
U
X
0
0
0
0
0
0
M
U
X
Pre-BIN
R_ROL_BIN
Rotate
1
0
M
U
X
R_ROL_GIN
Pre-GIN
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.20 Input Format
BIT1612 支援七種輸入格式:ITU656、ITU656-Like、ITU601、RGB888、RGB565、Serial-RGB 和 YUV444
。
6.20.1
ITU656
標準 8 Bits ITU656 (CCIR-656) 訊號格式,所有的 EVEN/ODD、HSYNC、VSYNC、YUV Data 將會
由 8 Bits ITU656 Bus 解碼得到。(輸入頻率 27MHz)。
6.20.2
ITU656-Like
類標準 8 Bits ITU656 訊號格式,將會由 8 Bits ITU656 Bus 解碼得到 YUV Data,其餘 HSYNC、VSYNC
將由外部的 PAD 取得。(輸入頻率 27MHz)。
FF
00
00
EAV
80
10
....
FF
00
00
SAV
U0
Y0
V0
Y1
U2
Y2
....
....
Figure 6-12 ITU656/656-Like (27MHz)
6.20.3
ITU601
16 Bits ITU601(CCIR-601) Video 訊號格式。(輸入頻率 13.5MHz)。
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
U0
V0
U2
V2
U4
V4
U6
V6
U8
V8
U10
V10
U12
V12
U14
V14
U15
Figure 6-13 ITU601 (13.5MHz)
6.20.4
RGB888
RGB 8:8:8 訊號格式。BIT1612 在此模式下最大支援 1080i、720p 和 [email protected] 等解析度,在此
模式下最大支援 100MHz Data Rate。
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
Figure 6-14
6.20.5
....
RGB 8:8:8 (Max. 100MHz)
Serial-RGB
BIT1612 提供 Serial-RGB Interface 訊號格式,在此模式下最大支援 40MHz Data Rate。
R0
G0
B0
R1
G1
B1
R2
G2
B2
R3
G3
B3
R4
....
Rn
Gn
Bn
....
Figure 6-15 Serial-RGB (Max. 40MHz)
6.20.6
YUV444
YVU 4:4:4 訊號格式。BIT1612 針對 YUV Color Space Mode,BIT1612 在此模式下最大支援 1080i
、720p 和 [email protected] 等解析度。在此模式下最大支援 100MHz Data Rate。
27
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
U0
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
V0
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
....
Figure 6-16 YUV 4:4:4 (Max.100MHz)
6.20.7
RGB565
RGB 5:6:5 訊號格式。BIT1612 在此模式下最大支援 1080i、720p 和 [email protected] 等解析度,在此
模式下最大支援 100MHz Data Rate。
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
Figure 6-17
RGB 565 8:8:8 (Max. 100MHz)
RGB 5:6:5 Data Format 連線方式如下圖:
BIT1612
B7
B6
B5
B4
B3
G7
G6
G5
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
(PA = RIN or GIN or BIN)
G4
G3
G2
R7
R6
R5
R4
R3
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
(PB = RIN or GIN or BIN)
Figure 6-18
RGB 5:6:5 Setup
28
....
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.21 Input Mode Selection
BIT1612 經由Register設定決定輸入模式,其相關Registers設定,請參考下表,相對應之方塊圖請參考
Figure 6-19。
Table 6-22 Input Mode Selection Register
Mnemonic
Address
R/W
Bits
R_IHS_SEL
0x04B[0]
RW
1
R_IVS_SEL
0x04B[1]
RW
1
R_POL_IHS
R_POL_IVS
0x04B[2]
0x04B[3]
RW
RW
1
1
R_SEL_EVEN
0x04B[5:4] RW
2
R_EXT_SYNC
0x04B[6]
RW
1
R_SORT_656
0x04C[6:4] RW
3
R_VISUAL_TYPE
0x04C[7]
RW
1
R_SRC_SEL
0x04D[1:0] RW
2
R_SWAP_UV
0x04D[2]
1
RW
Description
Default
External HSYNC Source Selection
0
0: External HSYNC Pin
1: Built-in Video Decoder HSYNC
External VSYNC Source Selection
0
0: External VSYNC Pin
1: Built-in Video Decoder VSYNC
External HSYNC polarity Î 0: Normal, 1: Invert
0
External VSYNC polarity Î 0: Normal, 1: Invert
1
EVEN/ODD Signal Selection
00: ITU656-EVEN Signal
00
01: Visual EVEN/ODD Signal
10: Always EVEN Field
11: Always ODD Field
Sync Mode Selection
0: ITU656 Mode
0
1: From External Sync Pin or Built-In Video
Decoder
ITU656 / ITU601 Format Î Data Sequence Shift
Control
X00: No Shift
X01: Shift 1 Clock
X10: Shift 2 Clocks
X11: Shift 3 Clocks
Serial – RGB Format Î Serial-Bus Data Sort
Control
000: Always 0
001: R-G-B
000
010: R-B-G
011: G-R-B
100: G-B-R
101: B-G-R
110: B-R-G
111: Always 1
RGB 5:6:5 Format Î Data Compensation Mode
X0X: Compensate with R_SORT_656[0].
X1X: Compensate with LSB Data.
Visual EVEN/ODD Mode
0
0: Normal EVEN/ODD Mode
1: Always Change by VSYNC
Source Format Selection
RGB Domain Source Î R_IMODE= 1
00: Serial-RGB Format
01: RGB 5:6:5 Format
00
1x: RGB 8:8:8 Format
YUV Domain Source Î R_IMODE = 0
00: ITU656 / ITU656-Like Format
01: ITU601 Format
1x: YUV 4:4:4 Format
Swap U and V signal
0
0: Disable
29
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_IMODE
0x04D[3]
RW
1
R_PCLK_BASE
0x04D[5:4] RW
2
1: Enable
Input Mode Selection
0: YUV Domain Source Input
1: RGB Domain Source Input
Input Active Pixel Mode
00: 1-Pixel Mode (RGB888、RGB565、YUV444、
ITU601)
01: 2-Pixel Mode (ITU656/ITU656-Like)
10: 3-Pixel Mode (Serial RGB)
11: 4-Pixel Mode
Figure 6-19 Input Mode Selection
30
0
01
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.22 Auto Switch
BIT1612 針對Input Windows、Scaling Factor和Timing setup提供兩組Register設定,可分別設定為自動或手
動切換模式,當在自動模式時BIT1612 將會判別輸入訊號為 50Hz or 60Hz自動切換至相對應的Register群組,其
相關Registers設定請參考 Table 6-23。
Table 6-23
Auto Switch Register
Mnemonic
Address R/W
Bits
R_AUTO_SWITCH
0x04A[6]
RW
1
R_SWITCH_MODE
0x04A[7]
RW
1
Description
Auto Switch Mode
0: Manual Mode
1: Auto Mode
Manual Mode Selection
0: Select Mode 0
1: Select Mode 1
Default
1
1
6.23 Display Window Setup
BIT1612 定義了一個Display Window的區域,將Scaling後的影像資料顯示於此區域內,因此在Timing許可下
,可任意做上下左右Move (Pan) 和Resize的動作,其相關Registers設定請參考 Table 6-24,相對應之示意圖請
參考 Figure 6-20。
Table 6-24 Display Windows Register
Mnemonic
Address
R/W Bits
R_PRDIS_ACTX 0x052[6:4], 0x04F[7:0] RW
11
R_DIS_YS
R_DIS_YW
R_DIS_XS
R_DIS_XW
0x052[1:0], 0x050[7:0]
0x052[3:2], 0x051[7:0]
0x055[1:0], 0x053[7:0]
0x055[6:4], 0x054[7:0]
RW
RW
RW
RW
10
10
10
11
R_DIS_XW1
0x058[2:0], 0x056[7:0]
RW
11
R_DIS_XW2
0x058[6:4], 0x057[7:0]
RW
11
Description
Display Window Pre-Scaling Active
Horizontal Width
Display Window Vertical Start Position
Display Window Vertical End Position
Display Window Horizontal Start Position
Display Window Horizontal End Position
Display Window Active Horizontal Width
On Linear Mode: Define All Region
On Anzoom Mode: Define 2 Region
Display Window Active Horizontal Width
On Linear Mode: No Active
On Anzoom Mode: Define 1 and 3 Region
(0,0)
Default
0x1E0
0x005
0x0F0
0x020
0x200
0x320
0x320
HSYNC Output
R_DIS_ACTX
R_DIS_XS
VSYNC Output
R_DIS_XW
Figure 6-20
Display Window Setup
31
R_DIS_YW
Display Window
R_DIS_ACTY
R_OS_YP
Blank Range
Panel Active Window
R_DIS_YS
R_OS_XP
Background
Color
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.24 Scaling Engine
BIT1612 可分別針對垂直 (Vertical) 和水平 (Horizontal) 方向做 Scaling 處理,其相關設定及說明如下:
Data
Input
Horizontal
Scaling
Down
Vertical
Linear
Scaling
UP/Down
Buffer
800
ScaleRate
Horizontal
Scaling UP
Non-Linear
/ Linear
ScaleRate
ScaleRate
Position
Position
Linear
Mode
Data
Output
Three-Step
Mode
Position
Non-Linear
Mode
Figure 6-21 Scaling Function
6.24.1
Horizontal Scaling Down Engine
BIT1612 可針對水平方向預作縮小處理,以符合Buffer深度。其相關設定請參考 Table 6-25。
Table 6-25 Horizontal Scale Down Register
Mnemonic
Address
0x05B[7:4],
0x059[7:0]
0x05B[2:0],
0x05A[7:0]
0x05C[5:4],
0x05D[7:0]
R/W
Bits
Description
Default
RW
12
Horizontal Scaling Down Start Value
0x0B5
RW
11
Horizontal Scaling Down Shift Value
0x16A
RW
10
Horizontal Scaling Down Fix Value
0x140
0x05C[0]
RW
1
R_PRESCX_FILTER_EN 0x05C[1]
RW
1
R_PRESCX_FILTER
0x05C[2]
RW
1
R_PRE_FIX2_EN
0x05C[3]
RW
1
R_PRESCX_OVER
0x05C[7]
RW
1
R_PRESCX_START
R_PRESCX_SHIFT
R_PRESCX_FIX
R_PRESCX_EN
32
Horizontal Scaling Down Enable
0: Disable (Bypass Mode)
1: Enable (Scale Mode)
Horizontal Scaling Down Filter
Enable
0: Disable (Bypass Mode)
1: Enable (Filter Mode)
Horizontal Scaling Down Filter Type
0: Bi-Linear Filter
1: Box Filter
Scale Down Factor 2 Enable
0: Disable (Bypass Mode)
1: Enable (Scale Down 2 Mode)
Scale Down Factor over 2
0: Disable (Factor under 2)
1: Enable (Factor over 2)
1
1
0
0
0
BIT1612
6.24.2
10-Bit Digital Video Decoder with OSD and T-CON
Horizontal Scaling UP Engine
BIT1612 可針對水平方向作放大處理,以符合Panel解析度。其相關設定請參考 Table 6-26。
Table 6-26 Horizontal Scale UP Register
Mnemonic
R_SCX_START
R_SCX1_SHIFT
R_SCX1_FIX
R_SCX2_SHIFT
R_SCX2_FIX
R_SCX1_INC
R_SCX2_DEC
Address
0x061[1:0], 0x05E[7:0]
0x05F[7:0]
0x061[6:4], 0x060[7:0]
0x062[7:0]
0x066[2:0], 0x063[7:0]
0x066[5:4], 0x064[7:0]
0x066[7:6], 0x065[7:0]
R/W
RW
RW
RW
RW
RW
RW
RW
Bits
10
8
11
8
11
10
10
R_SCX_EN
0x067[0]
RW
1
R_SCX_FILTER
0x067[3:2]
RW
2
R_ANZOOM_TYPE
0x067[6]
RW
1
R_ANZOOM_EN
0x067[7]
RW
1
33
Description
Horizontal Start Value
Horizontal Zone 1 Shift Value
Horizontal Zone 1 Fix Value
Horizontal Zone 2 Shift Value
Horizontal Zone 2 Fix Value
Non-Linear Increase Value
Non-Linear Decrease Value
Horizontal Scaling Enable
0: Disable (Bypass Mode)
1: Enable (Scale Mode)
Horizontal Scaling Filter Type
11: Bypass Filter
10: Box Filter
01: Bi-Linear Filter
00: Catrom Filter
Wide Screen Type
0: 3-Zone Wide Screen
1: Non-Liner Wide Screen
Wide Screen Mode Enable
0: Disable
1: Enable
Default
0x06C
0xD8
0x1E0
0x00
0x000
0x000
0x000
0
00
0
0
BIT1612
6.24.3
10-Bit Digital Video Decoder with OSD and T-CON
Vertical Scaling Engine
BIT1612 可依據Auto Switch Mode所選擇的模式 (Mode 0/Mode 1),自動切換適合的參數,針對影像
垂直方向分別做放大或縮小處理,以符合panel解析度。其相關設定請參考 Table 6-27。
Table 6-27 Vertical Scale-Down Register
Mnemonic
Address
0x06C[1:0],
0x068[7:0]
0x06C[3:2],
0x069[7:0]
R/W Bits
R_SCY_SHIFT_M0
0x06C[4], 0x06A[7:0]
RW
R_SCY_FIX_M0
0x06C[6:5],
0x06B[7:0]
RW 10
R_UPDN_SEL_M0
0x06C[7]
RW
1
R_SCY_EN_M0
0x06D[0]
RW
1
R_SCY_FILTER_EN_M0
0x06D[1]
RW
1
R_SCY_FILTER_M0
0x06D[2]
RW
1
R_LINE_CUT_M0
0x06D[5]
RW
1
R_CUT_MODE_M0
0x06D[6]
RW
1
R_CUT_AUTO_M0
0x06D[7]
RW
1
R_SCYE_START_M0
R_SCYO_START_M0
R_SCYE_START_M1
R_SCYO_START_M1
0x072[1:0],
0x06E[7:0]
0x072[3:2],
0x06F[7:0]
RW 10
RW 10
9
RW 10
RW 10
R_SCY_SHIFT_M1
0x072[4], 0x070[7:0]
RW
R_SCY_FIX_M1
0x072[6:5], 0x071[7:0] RW 10
R_UPDN_SEL_M1
0x072[7]
RW
1
R_SCY_EN_M1
0x073[0]
RW
1
34
9
Description
Default
Vertical Start Value for EVEN Field
0x07A
on Switch Mode 0
Vertical Start Value for ODD Field
0x09E
on Switch Mode 0
Vertical Shift Value on Switch
0x130
Mode 0
Vertical Fix Value on Switch Mode
0x000
0
Vertical Scaling Mode
0
0: Scaling Down Mode
1: Scaling Up Mode
Vertical Scaling Function Enable
on Switch Mode 0
1
0: Disable (Bypass Mode)
1: Enable (Scale Mode)
Vertical Scaling Filter Enable
1
0: Disable
1: Enable
Vertical Scaling Filter Type on
Switch Mode 0
0
0: Bi-Linear Filter
1: Box Filter
Vertical Pre-Scaling Down Enable
on Auto Switch Mode 0
0
0: Disable
1: Enable
Vertical Pre-Scaling Down Mode
on Auto Switch Mode 0
0
0: EVEN Line
1: ODD Line
Vertical Pre-Scaling Change Mode
on Auto Switch Mode 0
0
0: Manual (R_CUT_MODE)
1: Auto (EVEN/ODD)
Vertical Start Value for EVEN Field
0x01B
on Switch Mode 1
Vertical Start Value for ODD Field
0x01B
on Switch Mode 1
Vertical Shift Value on Switch
0x0FF
Mode 1
Vertical Fix Value on Switch Mode
0x089
1
Vertical Scaling Mode on Switch
Mode 1
0
0: Scaling Down Mode
1: Scaling Up Mode
Vertical Scaling Function Enable
on Switch Mode 1
1
0: Disable (Bypass Mode)
1: Enable (Scale Mode)
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_SCY_FILTER_EN_M1
0x073[1]
RW
R_SCY_FILTER_M1
0x073[2]
RW
R_LINE_CUT_M1
0x073[5]
RW
R_CUT_MODE_M1
0x073[6]
RW
R_CUT_AUTO_M1
0x073[7]
RW
Vertical Scaling Filter Enable
1 0: Disable
1: Enable
Vertical Scaling Filter Enable on
Switch Mode 1
1
0: Bi-Linear Filter
1: Box Filter
Vertical Pre-Scaling Down Enable
on Auto Switch Mode 1
1
0: Disable
1: Enable
Vertical Pre-Scaling Down Mode
on Auto Switch Mode 1
1
0: EVEN Line
1: ODD Line
Vertical Pre-Scaling Change Mode
on Auto Switch Mode 1
1
0: Manual (R_CUT_MODE)
1: Auto (EVEN/ODD)
1
0
0
0
0
6.25 Timing Adjustment
BIT1612 Timing 調整原則:
1. IVREF (t1) 總長度與OVREF (t2) 相近且小於OVREF (t2) (參考 Figure 6-22)。
2. 修正 Line Buffer 所產生的 Error (Overflow or Underflow)。
Table 6-28 Timing Adjust Register
Mnemonic
Address
R/W Bits
R_MASTER_DLY_M0
0x074[7:0]
RW
8
R_DLYE_OCLK_M0
0x077[3:0], 0x075[7:0] RW
12
R_DLYO_OCLK_M0
0x077[7:4], 0x076[7:0] RW
12
R_MASTER_DLY_M1
0x078[7:0]
RW
8
R_DLYE_OCLK_M1
0x07B[3:0],
0x079[7:0]
RW
12
R_DLYO_OCLK_M1
0x07B[7:4],
0x07A[7:0]
RW
12
R_HCOUNT
0x169[6:0], 0x168[7:0]
R
15
35
Description
Output VSYNC Synchronize Delay
Time (Base on IHSYNC) on Switch
Mode 0
Even Field Output VSYNC
Synchronize Delay Time (Base on
LCLK) on Switch Mode 0
Odd Field Output VSYNC
Synchronize Delay Time (Base on
LCLK) on Switch Mode 0
Output VSYNC Synchronize Delay
Time (Base on IHSYNC) on Switch
Mode 1
Even Field Output VSYNC
Synchronize Delay Time(Base on
LCLK) on Switch Mode 1
Odd Field Output VSYNC
Synchronize Delay Time(Base on
LCLK) on Switch Mode 1
Horizontal Counter
Default
0x16
0x075
0x071
0x13
0x266
0x066
-
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
t1
IVREF
R_IS_YS
R_IS_YW
t2
OVREF
R_DIS_YS
R_DIS_YW
Figure 6-22 Timing Adjustment VREF Information
6.26 Image Enhancement
BIT1612 提供多樣的調整機制,使用者可依據需求針對影像作調整,以獲得最佳之顯示效果。處理單元包括
Scaler 之前的前置處理與 Scaler 之後的後置處理兩部份。相關架構請參考下圖。
Pre-Image Enhancement
Saturation
DAC
Adjustment
Dither
Gamma
Contrast
Sharpness
Brightness
Contast
Scaler
Broghtness
Post-Image Enhancement
CTI
Figure 6-23 Image Enhancement
6.26.1
Post-Processing Brightness and Contrast
BIT1612 針對 RGB Domain 的個別 Channel,分別提供 Brightness 和 Contrast 調整。其架構及相對
應設定如下所示。
Table 6-29 Color Adjustment Register
Mnemonic
R_BRIGHTNESS_R
R_BRIGHTNESS_G
R_BRIGHTNESS_B
R_CONTRAST_R
R_CONTRAST_G
R_CONTRAST_B
Address
0x07C[7:0]
0x07D[7:0]
0x07E[7:0]
0x07F[7:0]
0x080[7:0]
0x081[7:0]
R/W
RW
RW
RW
RW
RW
RW
Bits
8
8
8
8
8
8
R_CONTRAST_TYPE
0x090[0]
RW
1
Description
R Channel Brightness Value
G Channel Brightness Value
B Channel Brightness Value
R Channel Contrast Value
G Channel Contrast Value
B Channel Contrast Value
Contrast Adjust Type
0: Type 1
1: Type 2
36
Default
0x80
0x80
0x80
0x80
0x80
0x80
0
BIT1612
6.26.2
10-Bit Digital Video Decoder with OSD and T-CON
Pre-Processing Brightness/Contrast Adjustment
BIT1612 針對 Y Domain 提供 Brightness 和 Contrast 的調整。其輸入對輸出曲線及相對應設定如下所
示。
Table 6-30 Color Adjustment Register
Mnemonic
Address
R/W
Bits
R_BRIGHTNESS
0x082[7:0]
RW
8
R_CONTRAST
0x083[7:0]
RW
8
R_WHITE_SLOPE
0x084[7:0]
RW
8
R_BLACK_SLOPE
0x085[7:0]
RW
8
R_WHITE_START
0x086[4:0]
RW
5
R_BLACK_START
0x087[4:0]
RW
5
6.26.3
Description
Brightness Value (-128 ~ +127)
0x00=-128, 0x80=0, 0xFF=+127
Contrast Value for Middle Range
Adjustment Range (0.0 ~ 1.9922)
0x00=0.0, 0x80 = 1, 0xFF=1.9922
Contrast Value for White Range
Adjustment Range (0.0 ~ 1.9922)
0x00=0.0, 0x80 = 1, 0xFF=1.9922
Contrast Value for Black Range
Adjustment Range (0.0 ~ 1.9922)
0x00=0.0, 0x80 = 1, 0xFF=1.9922
White Range Start Position
Range : 0xE0 ~ 0xFF
0x00=0xE0, 0x3F=0xFF
Black Range Start Position
Range : 0x00 ~ 0x1F
0x00=0x00, 0x1F=0x1F
Default
0x80
0x80
0x80
0x80
0x00
0x00
Sharpness Process
BIT1612 針對 Y Domain Data 提供 Sharpness 處理可強化影像之銳利度,其相對應設定如下所示。
Table 6-31 Sharpness and Smoothness Process Register
Mnemonic
Address
R/W Bits
R_UNSHARP_VAL
0x08A[6:0]
RW
R_UNSHARP_EN
0x08A[7]
RW
R_UNSHARP_THD
0x08B[5:0]
RW
6.26.4
Description
Sharpness Value (0~127)
7 0x00: Least Sharpness
0x7F: Most Sharpness
Sharpness Enable
1 0: Disable
1: Enable
6 Sharpness Threshold Value
Default
0x00
0
0x00
Saturation and Kill Color Process
BIT1612 針對 UV Domain Data 提供 Saturation 和 Kill Color 的處理,可讓使用者依喜好調到較佳的
色彩影像,其相對應設定如下所示。
Table 6-32 UV Domain Register
Mnemonic
Address
R/W
Bits
R_SAT_U
0x08C[6:0] RW
7
R_SAT_V
0x08D[6:0] RW
7
R_SAT_MODE
0x08C[7]
RW
1
R_KILL_COLOR
0x090[6]
RW
1
Description
U Saturation Value (0.0 ~ 1.9843)
0x00=0.0, 0x40=1.0, 0x7F=1.9843
V Saturation Value (0.0 ~ 1.9843)
0x00=0.0, 0x40=1.0, 0x7F=1.9843
V Saturation Value Reference with
R_SAT_U
0: Disable
1: Simultaneously Adjust R_SAT_U and
R_SAT_V (From R_SAT_U)
Control Kill Color Enable
0: Disable
1: Enable
37
Default
0x40
0x40
1
0
BIT1612
6.26.5
10-Bit Digital Video Decoder with OSD and T-CON
Chroma Transient Improvement (CTI)
BIT1612 提供Chroma Transient Improvement (CTI),相關Registers請參考 Table 6-33。
Table 6-33 Chroma Transient Improvement Register
Mnemonic
R_CTI_THD
Address
0x08E[7:0]
R_CTI_U_SEL
0x08F[2:0]
R_CTI_V_SEL
0x08F[6:4]
R_CTI_EN
0x08F[7]
6.26.6
R/W Bits
Description
RW 8 CTI Process Threshold Value
CTI Level Selection for U Domain
RW 3 000: Least CTI Enhancement
111: Most CTI Enhancement
CTI Level Selection for V Domain
RW 3 000: Least CTI Enhancement
111: Most CTI Enhancement
CTI Enable
RW 1 0: Disable
1: Enable
Default
0x01
111
111
0
Color Space Conversion
BIT1612 提供兩種 Color Space Conversion,用以轉換YUV Color Domain to RGB Color Domain相
關Registers請參考 Table 6-34。
Table 6-34 Color Space Converter Register
Mnemonic
R_Y2R_SEL
6.26.7
Address
0x090[7]
R/W Bits
RW
Description
Color Space Conversion
1 0: No Gamma-Correction
1: Gamma-Correction
Default
0
LUT Gamma Correction
BIT1612 內建LUT-base Gamma Correction Function,其相關記憶體對應為 0x200~0x2FF,相關
Registers請參考 Table 6-35。
Table 6-35 LUT Gamma Register
Mnemonic
Address
R/W
Bits
R_GAMMA_EN
0x090[2]
RW
1
R_GAMMA_SEL
0x090[4:3] RW
2
6.26.8
Description
GAMMA LUT Enable
0: Gamma RAM R/W Mode
1: Gamma Correction Mode
GAMMA LUT RAM R/W Selection
00: Red
01: Green
10: Blue
11: Write RGB, Read Forbiddance
Default
0
00
Dither
BIT1612 內建 User Programmable Dither Function 能使 6 Bits Panel Display 得到更佳的顯示品質,
相關 Registers 請參考下表。
Table 6-36 Dither Register
Mnemonic
Address
R/W
Bits
R_DITHER_EN
0x090[1]
RW
1
R_DITHER_EVEN
R_DITHER_ODD
0x091[7:0]
0x092[7:0]
RW
RW
8
8
R_DITHER_MASK
0x090[5]
RW
1
Description
Dither Function Enable
0: Disable
1: Enable
EVEN Field Dither Factor
ODD Field Dither Factor
OSD Area Dither Mask Enable
0: Disable
1: Enable
38
Default
0
0x87
0x78
1
BIT1612
6.26.9
10-Bit Digital Video Decoder with OSD and T-CON
DAC Correction
BIT1612 有一 DAC 誤差修正演算法,可以修正 DAC 誤差,其相關 Registers 設定請參考下表。
Table 6-37 DAC Correction Register
Mnemonic
R_DAC_B
R_DAC_C
Address R/W Bits
Description
0x095[7:0] RW 8 B Offset Factor
0x096[7:0] RW 8 C Slope Factor
DAC Correct Function Enable
R_DAC_CEN
0x097[0]
RW 1 0: Disable
1: Enable
C Slope Type
R_DAC_CTYPE 0x097[1]
RW 1 0: Central Point Mode
1: Normal Mode
Default
0x80
0x80
0
0
6.26.10 Clamp and Linear Mapping
BIT1612 有輸出範圍線性對映運算單元,並附帶箝位功能,其運算單元位於Gamma Correction的後
級,可以對Gamma Correction後的RGB圖像再進行調整,其相關設定Registers請參考 Table 6-38。 當只
需要輸出箝位功能時,只要將R_CLAMP_EN設為 1,並由輸出最大值 MAX回推
R_OUT_DACMAP_SPACE值,最小值MIN回推R_OUT_DACMAP_LB值,即可使RGB輸出值介於MAX到
MIN之間。公式如下:
MAX = 256 + R_OUT_DACMAP_SPACE (V)
MIN = R_OUT_DACMAP_LB
(V)
當輸出需要線性對映功能時,則可以設定R_DACMAP_EN為 1,且將R_CLAMP_EN設為 0,其輸出
範圍與上面公式相同,比較輸入與輸出線性關係,在R_CLAMP_EN為 1 時,其輸入輸出轉換曲線斜率為 1
,而R_DACMAP_EN = 1 時,則可以透過R_OUT_DACMAP_LB與R_OUT_DACMAP_SPACE調整,其差
別可以參考 Figure 6-24 及 Figure 6-25。
Table 6-38 Clamp and Linear Mapping Register
Mnemonic
Address
R/W Bits
R_CLAMP_EN
0x97[2]
RW
1
R_DACMAP_EN
0x94[7]
RW
1
R_OUT_DACMAP_LB
R_OUT_DACMAP_SPACE
0x094[6:0] RW
0x093[7:0] RW
7
8
Description
Clamp Function
0: Disable
1: Enable
Linear Mapping Function
0: Disable (Bypass)
1: Enable
Low Bound
Up Bound – Low Bound
Figure 6-24 Linear Mapping
Figure 6-25
39
DAC Clamp
Default
0
0
0x67
0x99
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.27 PWM Function
BIT1612 提供三組可獨立設定之PWM輸出,可藉此控制背光、聲音等裝置,其相關Registers設定請參考下表
,相對應之示意圖請參考 Figure 6-26。
Table 6-39 PWM Function Register
Mnemonic
R_PWM1_FREQ
R_PWM1_REF
R_PWM1_DUTY
Address
0x099[3:0], 0x098[7:0]
0x099[7:4]
0x09B[3:0], 0x09A[7:0]
R/W Bits
Description
RW 12 PWM1 Output Cycles.
RW 4 PWM1 Reference Cycles.
RW 12 PWM1 Output Duty Cycle
PWM1 Function Enable
RW 1 0: Disable
1: Enable
PWM1 Output Polarity
RW 1 0: Normal
1: Invert
PWM1 Synchronized with VSYNC
11: Synchronized with
Input VSYNC
RW 2
10: Synchronized with
Output VSYNC
0x: Not Synchronized with VSYNC
PWM2 Output Selection
RW 1 0: PWM2 Signal
1: Invert PWM1 Signal
SRGB PWM Enable
RW 1 0: Disable
1: Enable
Default
0x100
0x1
0x080
R_PWM1_EN
0x09C[0]
R_PWM1_POL
0x09C[1]
R_PWM1_SYNC
0x09C[3:2]
R_PWM1_INV
0x09C[4]
R_PWM_OUT
0x09C[5]
R_PWM2_FREQ
R_PWM2_REF
R_PWM2_DUTY
0x09E[3:0], 0x09D[7:0]
0x09E[7:4]
0x0A0[3:0], 0x09F[7:0]
RW
RW
RW
0x200
0x3
0x100
R_PWM2_EN
0x0A1[0]
RW
R_PWM2_POL
0x0A1[1]
RW
R_PWM2_SYNC
0x0A1[3:2]
RW
12 PWM2 Output Cycles.
4 PWM2 Reference Cycles.
12 PWM2 Output Duty Cycle
PWM2 Function Enable
1 0: Disable
1: Enable
PWM2 Output Polarity
1 0: Normal
1: Invert
PWM2 Synchronized with VSYNC
11: Synchronized with
Input VSYNC
2
10: Synchronized with
Output VSYNC
0x: Not Synchronized with VSYNC
R_PWM3_FREQ
R_PWM3_REF
R_PWM3_DUTY
0x0A3[3:0], 0x0A2[7:0]
0x0A3[7:4]
0x0A5[3:0], 0x0A4[7:0]
RW
RW
RW
0x300
0x0
0x150
R_PWM3_EN
0x0A6[0]
RW
R_PWM3_POL
0x0A6[1]
RW
R_PWM3_SYNC
0x0A6[3:2]
RW
12 PWM3 Output Cycles.
4 PWM3 Reference Cycles.
12 PWM3 Output Duty Cycle
PWM3 Function Enable
1 0: Disable
1: Enable
PWM3 Output Polarity
1 0: Normal
1: Invert
2 PWM3 Synchronized with VSYNC
11: Synchronized with
Input VSYNC
40
1
0
00
0
0
1
0
11
1
0
11
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
10: Synchronized with
Output VSYNC
0x: Not Synchronized with VSYNC
Panel clock
R_PWM_REF
Reference clock
Base on panel clock
R_PWM_FREQ
PWM Output
Base on reference clock
R_PWM_DUTY
Figure 6-26 PWM Function
6.28 Video Decoder
6.28.1
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
Video Decoder Feature
Three analog inputs, internal analog source selectors, e.g. CVBS x3 or Y/C x1 or ( Y/C x1 and CVBS x1)
or YPbPr (480i or 576i)
Two 10-bit video CMOS Analog-to-Digital Converters (ADCs) in differential CMOS style for best
S/N-performance
Fully programmable static gain or automatic gain control (AGC) for the selected CVBS or Y/C channel :
0~12db (Analog) and 0~18db (Digital)
Automatic Clamp Control (ACC) for CVBS, Y and C
On-chip clock generator
Digital PLL for synchronization and clock generation from all standards and non-standard video sources
e.g. consumer grade VTR
Requires only one crystal (24.576 MHz) for all standards
Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC
standards
Accepts NTSC (J, M, 4.43), PAL (60, B, D, G, H, I, M, N), and SECAM (B, D, G, K, K1, L) video signal
User programmable luminance peaking or aperture correction
Adaptive 3/5-line comb filter for two dimensional chrominance/luminance separation
PAL delay line for correcting PAL phase errors
Brightness Contrast Saturation (BCS) and Hue control on-chip
Multi-standard VBI-data slicer decoding closed caption
MV copy protection detection
User programmable sharpness filter
User programmable U/V Gain and CTI function
41
BIT1612
6.28.2
10-Bit Digital Video Decoder with OSD and T-CON
Video Decoder Architectures
Figure 6-27 Video Decoder Block Diagram
6.28.3
Video Decoder Adjustment
BIT1612 針對內建之 Video Decoder 提供多樣的處理機制,使用者可依據需求針對影像作調整,以獲
得最佳之顯示效果。相關架構請參考下列小節。
6.28.3.1 Brightness and Contrast
BIT1612 針對 Y Domain 做 Brightness 和 Contrast 的調整。其相對應設定如下所示。
Table 6-40 Color Adjustment Register
Mnemonic
R_BRIGHTNESS_VD
R_CONTRAST_VD
R_BLACKLEVEL_VD
Address
0x0A8[7:0]
0x0A9[7:0]
0x0AA[7:0]
R/W
RW
RW
RW
Bits
Description
8 Brightness Value
8 Contrast Value
8 Black Level Value
Default
0x8A
0x71
0x80
6.28.3.2 Sharpness Process
BIT1612 針對 Y Domain Data 提供 Sharpness 處理,可強化影像之銳利度,其相對應設定如下
所示。
Table 6-41 Sharpness and Smoothness Process Register
Mnemonic
Address
R/W Bits
R_UNSHARP_VAL_VD
0x0B1[6:0]
RW
R_UNSHARP_EN_VD
0x0B1[7]
RW
R_UNSHARP_THD_VD
0x0B2[5:0]
RW
Description
Sharpness value (0~127)
7 0x00: Least sharpness
0x7F: Most sharpness
Sharpness Enable
1 0: Disable
1: Enable
6 Sharpness Threshold Value
42
Default
0x00
0
0x00
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.28.3.3 UV Gain, Saturation and Kill Color
BIT1612 針對 UV Domain Data 提供 UV gain、Saturation、Hue 和 Kill Color 的處理,可讓使用
者依喜好調到較佳的色彩影像,其相對應設定如下所示。
Table 6-42 UV Domain Register
Mnemonic
R_UGAIN_VD
R_VGAIN_VD
Address R/W
0x0AC[7:0] RW
0x0AD[7:0] RW
R_SAT_MODE_VD
0x0AE[7]
R_SAT_U_VD
0x0AE[6:0] RW
R_SAT_V_VD
0x0AF[6:0] RW
R_CHROMA_HUE_VD
0x0AB[7:0] RW
R_KILL_COLOR_VD
0x0B3[7]
RW
R_VDLY_VD
0x0B0[1:0]
RW
R_UDLY_VD
0x0B0[3:2]
RW
RW
Bits
Description
8 U Gain Value Adjustment
8 V Gain Value Adjustment
SAT Adjust Control
0: Normal
1
1: Simultaneously adjust R_SAT_U_VD
and R_SAT_V_VD (From R_SAT_U_VD)
U Saturation Value (0.0 ~ 1.9843)
7
0x00=0.0, 0x40=1.0, 0x7F=1.9843
V Saturation Value (0.0 ~ 1.9843)
7
0x00=0.0, 0x40=1.0, 0x7F=1.9843
Chrominance HUE control
01111111: +178.6°
8
0000000: 0°
1000000: -180°
Control Kill Color enable
1 0: Disable
1: Enable
V Data Delay
00: Delay 0
2 01: Delay 1
10: Delay 2
11: Delay 3
U Data Delay
00: Delay 0
2 01: Delay 1
10: Delay 2
11: Delay 3
Default
0x80
0x80
1
0x40
0x40
0x00
0
01
01
6.28.3.4 Chroma Transient Improvement (CTI)
BIT1612 提供Chroma Transient Improvement (CTI),相關Registers請參考 Table 6-43。
Table 6-43 Chroma Transient Improvement Register
Mnemonic
R_CTI_THD_VD
Address
0x0B4[7:0]
R_CTI_EN_VD
0x0B3[0]
R_CTI_USEL_VD
0x0B3[3:1]
R_CTI_VSEL_VD
0x0B3[6:4]
R/W Bits
Description
RW 8 CTI Process Threshold Value
CTI Enable
RW 1 0: Disable
1: Enable
CTI Level Selection for U Domain
RW 3 000: Least CTI Enhancement
111: Most CTI Enhancement
CTI Level Selection for V Domain
RW 3 000: Least CTI Enhancement
111: Most CTI Enhancement
43
Default
0x10
0
001
001
BIT1612
6.28.4
10-Bit Digital Video Decoder with OSD and T-CON
Synchronization Process
Synchronization Process Block 從 Y/C 分離後的 Luminance 的信號中,分離解出 HSYNC 和 VSYNC
的信號。
LUMA
SYNC
SLICER
PHASE
DETECTOR
Vertical
Processor
Reference
Clock
Generator
COUNTER
Reference
Clock
HSYNC
VSYNC
Figure 6-28 Synchronization Process
Table 6-44 Synchronization Process Register
Mnemonic
R_SYNC_IDEL
R_SYNC_HSYS
R_SYNC_HSYE
R_SYNC_HCS
R_SYNC_HCE
R_SYNC_HSS
R_BGPU_POINT_N
R_BGPU_POINT_P
R_SLICER_THD
Address
0x0B5[7:0]
0x0B6[7:0]
0x0B7[7:0]
0x0B8[7:0]
0x0B9[7:0]
0x0BA[7:0]
0x0BB[7:0]
0x0BC[7:0]
0x0BD[7:0]
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
Bits
8
8
8
8
8
8
8
8
8
R_VNOISE_MODE
0x0BE[1:0]
RW
2
R_FIDT_THD
R_SYNC_LPADJ
R_SYNC_PDGAIN
R_SYNC_LPLMT
0x0BE[7:4]
0x0BF[1:0]
0x0BF[3:2]
0x0BF[4]
RW
RW
RW
RW
4
2
2
1
R_SYNC_HPLL
0x0BF[6:5]
RW
2
R_VTRC
0x0BF[7]
RW
1
Description
Horizontal Increment Delay
Horizontal Sync Start
Horizontal Sync End
Clamp Signal Start
Clamp Signal End
Horizontal Delay
Burst Start Point for 60Hz Signal
Burst Start Point for 50Hz Signal
Sync-Slicer Threshold
VSYNC Noise Reduction Mode
00: Normal Mode
01: Fast Mode
10: Free-Run Mode
11: Bypass Mode
50/60Hz Detection Threshold
Loop Filter Tracker Speed
Loop Filter Phase Tracker Factor
Loop Filter Phase Adjustment Speed
PLL Free-Run Mode Enable
00: Free-Run on 23.928MHz
01: Disable (Normal)
10: Free-Run on 27MHz
11: Free-Run on 30.07MHz
VCR Mode Enable
0: Disable
1: Enable
44
Default
0x4A
0x2F
0xFF
0xF2
0xC0
0xFD
0x06
0x16
0x00
01
0x8
11
11
0
01
0
BIT1612
6.28.5
10-Bit Digital Video Decoder with OSD and T-CON
VBI Data Slicer
BIT1612 提供 Data Slicer 功能可依據針對所設定的 Lines 及 Even/Odd,分離出 16 Bits 的 Data,並
且經由 Interrupt 及 Register 提供 MCU 做後續處理,相關的 Registers 請參考下表。
Table 6-45 VBI Data Slicer Process Register
Mnemonic
Address R/W Bits
Description
R_DATA_SLICER_THD
0x0C0[7:0] RW 8 Data Slicer High/Low Threshold
R_DATA_SLICER_START 0x0C1[7:0] RW 8 Data Slicer Start Point
R_DATA_SLICER_LINE_E 0x0C2[5:0] RW 6 Data Slicer Line Selection for Even Field
Data Slicer Enable for Even Field
R_DATA_SLICER_EN_E
0x0C2[7]
RW 1 0: Disable
0: Enable
R_DATA_SLICER_LINE_O 0x0C3[5:0] RW 6 Data Slicer Line Selection for Odd Field
Data Slicer Enable for Odd Field
R_DATA_SLICER_EN_O 0x0C3[7]
RW 1 0: Disable
0: Enable
Data Slicer Output (0x17A, 0x17B) Selection
R_CC_DATA_SEL
0x17C[7]
RW 1 0: Even Field
1: Odd Field
R_CC_DATA1
0x17A[7:0] R
8 Data Slicer First Byte
R_CC_DATA2
0x17B[7:0] R
8 Data Slicer Second Byte
6.28.6
Default
0x26
0x99
0x11
1
0x10
1
0
-
Source Detection
BIT1612 提供 Source Detection 的功能可以自動偵測 AIN11 (SRC11)、AIN12 (SRC12)和 AIN2 (SRC2)
何者輸入有信號的變化,偵測的結果將經由 Interrupt 提供系統使用,相關的 Registers 設定請參考下表。
Table 6-46 Source Detection Process Register
Mnemonic
R_CH2_THD
R_CH12_THD
R_CH11_THD
Address
0x0C4[1:0]
0x0C4[3:2]
0x0C4[5:4]
R_SRCDET_MODE
0x0C4[7]
R_SRC2
R_SRC12
0x178[4]
0x178[5]
R_SRC11
0x178[6]
R/W Bits
Description
RW 2 Signal detection threshold for AIN2
RW 2 Signal detection threshold for AIN12
RW 2 Signal detection threshold for AIN11
Source Detection Mode
RW 1 0: Disable (Normal Mode)
1: Source Detection Mode
R
1 Source detection result for AIN2
R
1 Source detection result for AIN12
Source detection result for AIN11
R
1 0: No signal toggle
1: Signal toggle
45
Default
00
00
00
0
-
BIT1612
Contrast
Brightness
R_BLACKLEVEL_VD
R_CONTRAST_VD
R_BRIGHTNESS_VD
Path
Delay
YOUT
R_YDEL
Blacklevel
R_APER_SEL
R_COR_SEL
BandPass
Filter
R_BPASS_SEL
Chroma
Trap
R_CHT_EN
Pre
Filter
R_PREF_EN
YIN
Luminance Process
R_CHT_SEL
6.28.7
10-Bit Digital Video Decoder with OSD and T-CON
Figure 6-29 Luminance Process Block
Table 6-47 Luminance Process Register
Mnemonic
Address
R/W Bits
R_BPASS_SEL
0x0C5[1:0] RW
2
R_COR_SEL
0x0C5[3:2] RW
2
R_APER_SEL
0x0C5[5:4] RW
2
R_CHT_EN
0x0F0[5]
RW
1
R_CHT_SEL
0x0C5[7]
RW
1
R_PREF_EN
0x0C5[6]
RW
1
R_YDEL
0x0C6[3:0] RW
4
Description
Band Pass Frequency Selection
00: Frequency 1
01: Frequency 2
10: Frequency 3
11: Frequency 4
Coring circuit amplitude value
00: Coring factor 1
01: Coring factor 2
10: Coring factor 3
11: Coring factor 4
Aperture Factor
00: 0
01: 0.25
10: 0.5
11: 1.0
Chroma Trap Enable
0: Disable
1: Enable
Chroma-Trap Control (Internal Test)
0: Type 1
1: Type 2
Luma Pre-Filter Enable
0: Disable
1: Enable
Y Data Path Delay
1111: Delay 16 Clocks
1000: Delay 0 Clock
0000: Delay -15 Clocks
46
Default
00
00
00
1
1
0
0x8
BIT1612
6.28.8
10-Bit Digital Video Decoder with OSD and T-CON
Chroma Process
SECAM
Processing
AntiFilter
CIN
Demodulator
LowPass
Filter
ChromaGain
Processing
SubCarrier
Generator
Figure 6-30
UOUT
Comb
Filter
Color
Standard
Detector
VOUT
Color
Standard
Chroma Process Function Block
Table 6-48 Chroma Process Register
Mnemonic
Address
R/W Bits
R_CHROMA_GAIN
0x0C7[6:0]
RW
7
R_CHROMA_GAIN_SEL
0x0C7[7]
RW
1
R_GAIN_CTL_VALUE
0x0C9[0],
0x0C8[7:0]
RW
9
R_AUTO_KILL
0x0C9[1]
RW
1
R_CDV_SEL
0x0C9[2]
RW
1
R_CCIR_EN
0x0C9[3]
RW
1
R_GAIN_CTRL_SPEED
0x0C9[5:4]
RW
2
R_SECAM_INVERT
0x0C9[6]
RW
1
R_SXCR
0x0C9[7]
RW
1
R_THRESHOLD_SECAM
R_THRESHOLD_QAM
R_SECAM_SENSITIVE
R_PAL_SENSITIVE
R_LOWER_BOUND
R_UPPER_BOUND
R_CHROMA_LPPI1
R_CHROMA_LPPI2
R_SQP_LMT
0x0CA[7:0]
0x0CB[7:0]
0x0CC[7:0]
0x0CD[7:0]
0x0CE[3:0]
0x0CE[7:4]
0x0CF[1:0]
0x0CF[3:2]
0x0CF[4]
RW
RW
RW
RW
RW
RW
RW
RW
RW
8
8
8
8
4
4
2
2
1
47
Description
Chroma Fixed-Gain Value
000000: Minimum Gain (0.25)
010000: Normal Gain (1.0)
111111: Maximum Gain (3.5)
Chroma Gain Type Selection
0: Auto-Gain
1: Fixed-Gain (Defined on 0x609[6:0])
Default
Chroma Gain Reference Value
0x100
Auto Color Kill From Color Detection
0: Disable
1: Enable (Auto Kill from Color Detection)
TV / VCR Mode Selection
0: Mode 1
1: Mode 2
CCIR Mode
0: Disable
1: Enable
Auto Chroma Gain Loop Filter
00: Slow Time Constant
01: Medium Time Constant
10: Fast Time Constant
11: Frozen
SECAM Invert Enable
0: Disable
1: Enable
SECAM Cross Color Reduction
0: Disable
1: Enable
Color Killer Threshold for SECAM
Color Killer Threshold for PAL and NTSC
SECAM Switch Sensitive Level
PAL Switch Sensitive Level
Color Standard Detection Threshold 1
Color Standard Detection Threshold 2
Chroma Low Pass Filter Factor 1
Chroma Low Pass Filter Factor 2
Sub-Carrier Frequency Selection
0x21
0
0
0
0
00
0
1
0x80
0x80
0x50
0x50
0x4
0xC
01
10
0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_SQP_LPPI
R_SQP_SPUP
R_STD_COUNT
0x0CF[6:5]
0x0CF[7]
0x0D0[5:0]
RW
RW
RW
2
1
6
R_CHROMA_PHASE
0x0D0[6]
RW
1
R_STD_OFF00
R_STD_OFF01
R_STD_OFF10
0x0D1[7:0]
0x0D2[7:0]
0x0D3[7:0]
RW
RW
RW
8
8
8
6.28.9
0: Type 1
1: Type 2
Sub-Carrier Phase Detection Factor 1
Sub-Carrier Phase Detection Factor 2
Color Standard Detect Ready Threshold
Chroma Phase Detection Mode
0: Mode 1
1: Mode 2
Burst Freq. Offset for 3.57MHz
Burst Freq. Offset for 4.2MHz
Burst Freq. Offset for 4.43MHz
01
0
0x38
0
0x00
0x08
0x00
Comb Filter Process
BIT1612 Video Decoder 提供 NTSC 3-Line 和 PAL 5-Line 的 Adaptive Comb Filter 來做 Y/C 分離,
其相關設定請參考下表。
Table 6-49 Comb Filter Process Register
Mnemonic
Address
R/W Bits
R_COMB_EN
0x0F0[6]
RW
1
R_COMB_CTHD
0x0D4[6:0]
RW
7
R_COMB_YTHD12
0x0D5[7:0]
RW
8
R_COMB_YTHD3
0x0D6[7:0]
RW
8
R_LINE_THD1
R_LINE_THD2
0x0D7[7:0]
0x0D8[7:0]
RW
RW
8
8
R_SECS_AUTOSW
0x0D9[0]
RW
1
R_N44360_AUTOSW
0x0D9[1]
RW
1
R_NOCOR_AUTOSW 0x0D9[2]
RW
1
R_OUT_SEL
0x0D9[5:4]
RW
2
R_Y_SEL
0x0DA[1:0]
RW
2
R_Y_AUTO
0x0DA[2]
RW
1
R_Y1D_SEL
0x0DA[5:4]
RW
2
Description
Default
Comb Filter Enable
0
0: Disable
1: Enable
C Threshold Value
0x20
Y Threshold Value for
NTSC: Abs (Line0-Line1) or Abs (Line1-Line2) 0x20
PAL: Abs (Line0-Line2) or Abs (Line2-Line4)
Y Threshold Value for
NTSC: Abs (Line0-Line2)
0x10
PAL: Abs (Line0-Line4)
Y Line Threshold1 Value
0x10
Y Line Threshold2 Value
0x0A
SECAM Standard Control
1
0: Force 1 D
1: Auto
NTSC_4.43MHz_60Hz Standard Control
1
0: Force 1 D
1: Auto
No Color Burst Control
1
0: Force 1 D
1: Auto
Middle Filter Selection
00: Mode0
00
01: Mode1
10: Mode2
11: Mode3
Y Domain Force 1D Filter Selection (when
R_Y_AUTO = 0)
00: Notch Filter
00
01: Two-Line Filter (Mode 0)
10: Two-Line Filter (Mode 1)
11: Three-Line Filter
Y Domain Comb Filter Enable
1
0: Fixed Filter
1: Adaptive Comb Filter
Y Domain Notch Filter Selection
00
00: Type 0
01: Type 1
48
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_CP90_SEL
0x0DB[2:0]
RW
3
R_CP90_AUTO
0x0DB[3]
RW
1
R_CP180_SEL
0x0DB[6:4]
RW
3
R_CP180_AUTO
0x0DB[7]
RW
1
R_CP90TAB_SEL
0x0DC[1:0]
RW
2
R_CREFY_EN
0x0DC[4]
RW
1
R_YREFC_EN
0x0DC[5]
RW
1
R_YP90REF13_EN
0x0DC[6]
RW
1
10: Type 2
11: Type 3
C Domain Force 1D Filter Selection
(Phase 90)
000: High Pass Filter
001: Two-Line Filter (Mode 2)
01x: Two-Line Filter (Mode 0)
10x: Two-Line Filter (Mode 1)
11x: Three-Line Filter
C Domain Comb Filter Enable
(Phase 90)
0: Fixed Filter
1: Adaptive Comb Filter
C Domain Force 1D Filter Selection
(Phase 180)
000: High Pass Filter
001: Two-Line Filter (Mode 2)
01x: Two-Line Filter (Mode 0)
10x: Two-Line Filter (Mode 1)
11x: Three-Line Filter
C Domain Comb Filter Enable (Phase 180)
0: Fixed Filter
1: Adaptive Comb Filter
C Domain Filter Table Selection (Phase 90)
00: Table 0
01: Table 1
10: Table 2
11: Table 3
C Domain Refers to Y Domain
0: Disable
1: Enable
Y Domain Refers to C Domain
0: Disable
1: Enable
C Domain Refers to Line2 and Line4
(Phase 90)
0: Disable
1: Enable
49
010
1
010
1
11
1
1
1
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.28.10 AGC and ACC Process
BIT1612 提供 AGC (Auto Gain Control)功能以控制 Analog PGA 所提供 -6db、0db、6db 和 12db 四
種的 Gain Value 及 Digital PGA 所提供+18db ~ -18db Linear Digital PGA,及提供 ACC (Auto Clamp
Control)功能以控制 Analog Clamp 和 Digital Clamp。AGC 及 ACC 的控制可使輸入信號維持在正常的振幅
及準位,使得輸出的結果不會隨著信號的漂移改變而有所變化,進而影響畫面的穩定度。相關的示意圖請
參考下圖,相關的 Registers 設定請參考下表。
Table 6-50
Figure 6-31
AGC and Clamp Pulse
Figure 6-32
AGC Control Selection
AGC Control Register
Mnemonic
R_ACLAMP_SPEED
R_ACLAMP1_LEVEL
R_ACLAMP2_LEVEL
Address
0x0DD[7:0]
0x0DE[7:0]
0x0DF[7:0]
R_AAGC1_EN
0x0E0[0]
R/W Bits
Description
RW 8 Analog Clamp Tracer Speed
RW 8 Analog Clamp 1 Level
RW 8 Analog Clamp 2 Level
Analog AGC Enable for ADC1
RW 1 0: Disable (R_AAGC1_VALUE)
1: Enable (Auto Tracer)
50
Default
0x18
0x30
0x80
1
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_AAGC1_HOLD
0x0E0[1]
RW
1
R_AAGC1_VALUE
0x0E0[3:2] RW
2
R_ACLAMP1_EN
0x0E0[4]
RW
1
R_ACLAMP1_TYPE
0x0E0[5]
RW
1
R_SYNC1_CLAMP
0x0E0[6]
RW
1
R_AUTO1_HOLD
0x0E0[7]
RW
1
R_DAGC1_EN
0x0E1[0]
RW
1
R_DAGC1_HOLD
0x0E1[1]
RW
1
R_DCLAMP1_EN
0x0E1[2]
RW
1
R_DCLAMP1_HOLD
0x0E1[3]
RW
1
R_DAGC1_THD
R_DAGC1_VALUE
R_DCLAMP1_LEVEL
R_DCLAMP1_VALUE
R_DAGC1_SPEED
R_DIFFGAIN1_THD
0x0E1[7:4]
0x0E2[7:0]
0x0E3[7:0]
0x0E4[7:0]
0x0E5[5:0]
0x0E5[7:6]
RW
RW
RW
RW
RW
RW
4
8
8
8
6
2
R_DAGC1_VSUP
0x0EE[6]
RW
1
R_DAGC2_VSUP
0x0EE[7]
RW
1
R_AAGC2_EN
0x0E6[0]
RW
1
R_AAGC2_HOLD
0x0E6[1]
RW
1
R_AAGC2_VALUE
0x0E6[3:2] RW
2
Analog AGC Hold for ADC1
0: Disable (Tracer)
1: Enable (Hold)
Analog PGA 1 Value when AGC Disable
00: -6 db (x0.5)
01: 0 db (x1)
10: 6 db (x2)
11: 12 db (x4)
Analog Clamp 1 Enable
0: Disable (Turn Off Analog Clamp)
1: Enable
Analog Clamp 1 Level Selection
0: R_ACLAMP1_LEVEL
1: Middle Level
Analog Clamp 1 Update Signal
0: VSYNC
1: HSYNC
Auto ACC and AGC Hold when Tracer Stable
for ADC 1
0: Disable
1: Enable
Digital AGC Enable for ADC 1
0: Disable (R_DAGC1_VALUE)
1: Enable (Auto Tracer)
Digital AGC Hold for ADC 1
0: Disable (Tracer)
1: Enable (Hold)
Digital Clamp 1 Enable
0: Disable (R_DCLAMP1_VALUE)
1: Enable
Digital ACC Hold for ADC1
0: Disable (Tracer)
1: Enable (Hold)
Digital AGC 1 Tracer Level
Manual Digital AGC 1 value
Digital Clamp 1 Level
Manual Digital Clamp 1 Value
Digital AGC 1 Tracer Speed
AGC and ACC Ready Threshold for ADC 1
Digital AGC 1 Update Signal
0: HSYNC
1: VSYNC
Digital AGC 2 Update Signal
0: HSYNC
1: VSYNC
Analog AGC Enable for ADC 2
0: Disable (R_AAGC2_VALUE)
1: Enable (Auto Tracer)
Analog AGC Hold for ADC 2
0: Disable (Tracer)
1: Enable (Hold)
Analog PGA 2 Value when AGC Disable
00: -6 db (x0.5)
01: 0 db (x1)
10: 6 db (x2)
51
0
10
1
0
1
0
1
0
1
0
0x1
0x40
0x3F
0x00
0x04
00
1
1
1
0
10
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_ACLAMP2_EN
0x0E6[4]
RW
1
R_ACLAMP2_TYPE
0x0E6[5]
RW
1
R_SYNC2_CLAMP
0x0E6[6]
RW
1
R_AUTO2_HOLD
0x0E6[7]
RW
1
R_DAGC2_EN
0x0E7[0]
RW
1
R_DAGC2_HOLD
0x0E7[1]
RW
1
R_DCLAMP2_EN
0x0E7[2]
RW
1
R_DCLAMP2_HOLD
0x0E7[3]
RW
1
R_DAGC2_THD
R_DAGC2_VALUE
R_DCLAMP2_LEVEL
R_DCLAMP2_VALUE
R_DAGC2_SPEED
R_DIFFGAIN2_THD
0x0E7[7:4]
0x0E8[7:0]
0x0E9[7:0]
0x0EA[7:0]
0x0EB[5:0]
0x0EB[7:6]
RW
RW
RW
RW
RW
RW
4
8
8
8
6
2
11: 12 db (x4)
Analog Clamp 2 Enable
0: Disable (Turn Off Analog Clamp)
1: Enable
Analog Clamp 2 Level Selection
0: R_ACLAMP2_LEVEL
1: Middle Level
Analog Clamp 2 Update Signal
0: VSYNC
1: HSYNC
Auto ACC and AGC Hold when Tracer Stable
for ADC 2
0: Disable
1: Enable
Digital AGC Enable for ADC2
0: Disable (R_DAGC2_VALUE)
1: Enable (Auto Tracer)
Digital AGC Hold for ADC2
0: Disable (Tracer)
1: Enable (Hold)
Digital Clamp 2 Enable
0: Disable (R_DCLAMP2_VALUE)
1: Enable
Digital ACC Hold for ADC 2
0: Disable (Tracer)
1: Enable (Hold)
Digital AGC 2 Tracer Level
Manual Digital AGC 2 Value
Digital Clamp 2 Level
Manual Digital Clamp 2 Value
Digital AGC 2 Tracer Speed
AGC and ACC Ready Threshold for ADC 2
52
1
1
1
0
1
0
1
0
0x1
0x40
0x80
0x00
0x04
00
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.28.11 AFE and PLL Control
BIT1612 內建 AFE (Analog Front End) 設定參數,相關設定請參考下表。
Table 6-51
ADC Control Register
Mnemonic
R_AFE_CS
R_AFE_CTRPH
R_AFE_CTRIB
R_AFE_SH2VCM
R_AFE_ENIB
R_AFE_ENREF
R_AFE_ENVBG
Address
0x0EC[1:0]
0x0EC[3:2]
0x0EC[6:4]
0x0EC[7]
0x0ED[0]
0x0ED[1]
0x0ED[2]
R_AFE_ENVCM
0x0ED[3]
R_AFE_ENAY
0x0ED[4]
R_AFE_ENAC
0x0ED[5]
R_AFE_BYP
0x0ED[6]
R_AFE_DEC
0x0ED[7]
R_PLL_POR
0x0EE[0]
R_PLL_EAPLL
0x0EE[1]
R_PLL_ICP0
R_PLL_ICP1
0x0EE[2]
0x0EE[3]
R_PLLDTO_ROL
0x0EE[4]
R/W Bits
Description
RW 2 AFE Clamp Current
RW 2 AFE Phase Non-Overlap Time
RW 3 AFE Bias Current Control
RW 1 AFE Internal Shortcut On both PGA
RW 1 AFE Bias Current Enable
RW 1 AFE Reference Generator Enable
RW 1 AFE Bandgap Generator Enable
AFE Common Mode Voltage Generator
RW 1
Enable
Power Down Input for ADC 1
RW 1 0: Power Down
1: Normal Operation
Power Down Input for ADC 2
RW 1 0: Power Down
1: Normal Operation
RW 1 Bypass PGA for ADC Test
Control Output Data Decimator by 8 or None
RW 1
(Dec = 0: Normal Operation)
PLL Power On Reset
RW 1 0: Disable
1: Reset
PLL Enable
RW 1 0: Disable
1: Enable
RW 1 PLL Factor 0
RW 1 PLL Factor 1
PLL DTO Rotate
RW 1 0: Disable
1: Enable
53
Default
00
00
110
0
1
1
1
1
1
1
0
0
0
1
0
0
0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.28.12 Input Path Selection
BIT1612 Video Decoder內建兩組 10 Bits ADC,提供三組Analog信號輸入端,並可經由Register設定
,以支援CVBS、Y/C及YPbPr (480i or 576i) 的信號輸入,其相關架構示意圖請參考下圖,相關Registers
設定請參考 Table 6-52 及 Table 6-53。
Figure 6-33 Input Path
Table 6-52
Analog Input Path Register
Mnemonic
Address
R/W Bits
R_ANC_SEL
0x0F0[0]
RW
1
R_ANY_SEL
0x0F0[1]
RW
1
R_AFE_SEL
0x0F0[2]
RW
1
R_YC_EN
0x0F0[3]
RW
1
R_YPBPR_EN
0x0F0[4]
RW
1
Table 6-53
Description
Chroma Path Selection
0: Data Source form ADC2
1: Data Source from ADC1
Luma Path Selection
0: Data Source from ADC1
1: Data Source from ADC2
Video MUX Switch for ADC1
0: ADC1 Signal from AIN11 Pin
1: ADC1 Signal from AIN12 Pin
Y/C Mode Enable
0: Disable
1: Enable
YPbPr Mode Enable
0: Disable
1: Enable
Default
0
0
0
0
0
Analog Input Selection
Mode
CVBS Mode:
Signal Input from AIN11
CVBS Mode:
Signal Input from AIN12
CVBS Mode:
Signal Input from AIN2
Y/C Mode:
Y Signal Input from AIN11
C Signal Input from AIN2
Y/C Mode:
Y Signal Input from AIN12
C Signal Input from AIN2
R_ANC_SEL R_ANY_SEL
R_AFE_SEL R_YC_EN R_YPBPR_EN
0/1
0
0
0
0
0/1
0
1
0
0
0/1
1
0/1
0
0
0
0
0
1
0
0
0
1
1
0
54
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Y/C Mode:
Y Signal Input from AIN2
C Signal Input from AIN11
Y/C Mode:
Y Signal Input from AIN2
C Signal Input from AIN12
YPbPr Mode:
Y Signal Input from AIN2
Pb Signal Input from AIN11
Pr Signal Input from AIN12
1
1
0
1
0
1
1
1
1
0
1
1
0/1
1
1
6.28.13 Standard Setting and Detection
BIT1612 可以針對PAL、PAL60、PAL-N、SECAM、PAL-M、NTSC-443-50、NTSC-M、NTSC-443-60
和Black & White等Color Standard信號進行解碼,並提供自動、半自動和手動三種模式,以便使用者依據
其實際環境進行設定。相關架構示意圖請參考下圖,相關Registers設定請參考 Table 6-54。
VSYNC
Synchronize Process
VSYNC
HSYNC
50/60Hz
MUX
50/60 Detection
Fast 50/60
Detection
0
M
U
1 X
1
R_AUFD
0
R_FSEL
R_FSEL
Figure 6-34 Field Type Selection
Figure 6-35
Color Standard Selection
Table 6-54 Standard Setting and Detection Register
Mnemonic
Address
R/W Bits
R_AUFD
0x0F1[0]
RW
1
R_FSEL
0x0F1[1]
RW
1
Description
Auto 50/60Hz Detection
0: Manual 50/60Hz (Defined on 0x0F1[1])
1: Auto 50/60Hz Detection
Manual 50/60Hz Mode (R_AUFD=0)
55
Default
0
0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_STD_AUTO
0x0F1[2]
RW
1
R_STD_MOD
0x0F1[3]
RW
1
R_STD_SEL0
0x0F1[6:4] RW
3
R_STD_SEL1
0x0F2[2:0] RW
3
0: 50Hz
1: 60Hz
Auto 50/60Hz Detection Mode (R_AUFD=1)
0: Normal Mode
1: Fast Mode
Color Standard Detection
0: Manual Color Standard (Defined on 0x0F1[6:4])
1: Auto Color Standard
Auto Color Standard Detection Mode Selection
0: Semi-Auto Mode
1: Fully-Auto Mode
Color Standard Setup for Manual Setting and
Semi-Auto on 50Hz
Color Standard Setup for Semi-Auto on 60Hz
000: PAL/PAL-60
001: PAL_N
010: SECAM
011: PAL_M
100: NTSC_4.43_50Hz
101: NTSC_M / NTSC_J
110: NTSC_4.43_60Hz
111: Black & White
0
0
000
101
6.29 Video Decoder Status Register
BIT1612 Built-In Video Decoder 提供下列 Read Only Registers,以便讀取 BIT1612 內部 Status,相關
Registers 請參考下表。
Table 6-55 Video Decoder Status Register
Mnemonic
R_DAGC1_OUT
R_DCLAMP1_OUT
R_DAGC2_OUT
R_DCLAMP2_OUT
R_AAGC1_OUT
R_AAGC2_OUT
R_CHROMA_GAINOUT
Address
0x16E[7:0]
0x16F[7:0]
0x170[7:0]
0x171[7:0]
0x172[1:0]
0x172[3:2]
0x172[7:4],
0x173[7:0]
R/W
R
R
R
R
R
R
Bits
8
8
8
8
2
2
Description
Digital AGC1 Tracer Value
Digital Clamp1 Tracer Value
Digital AGC2 Tracer Value
Digital Clamp2 Tracer Value
Analog ACG1 Tracer Value
Analog AGC2 Tracer Value
Default
-
R
12
Chroma GAIN Tracer Value
-
R_COLOR_STANDARD
0x174[2:0]
R
3
R_FIDT_O
0x174[3]
R
1
R_HLCK_O
0x174[4]
R
1
R_SYNC_READY_O
R_STD_READY_O
R_COLORDET
0x174[5]
0x174[6]
0x174[7]
R
R
R
1
1
1
56
Color Standard Detection Result
000: PAL
001: PAL_N
010: SECAM
011: PAL_M
100: NTSC_4.43_50Hz
101: NTSC_M / NTSC_J
110: NTSC_4.43_60Hz
111: Black & White
50/60Hz Detection
0: 50Hz
1: 60Hz
H-LOCK Ready
0: Not Ready
1: Ready
Auto Sync Detection Ready
Auto Color Standard Detection Ready
Color Detection Result
-
-
-
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_SQP_COUNT
R_DAGC1_READY
0x175[3:0]
0x175[4]
R
R
4
1
R_DAGC2_READY
0x175[5]
R
1
R_STD_FREQ
0x175[7:6]
R
2
R_INCCHRO_O
0x17C[0],0x177[
7:0],0x176[7:0]
R
17
R_MV_DET_SYNC
0x178[0]
R
1
R_MV_DET_CHROMA
0x178[1]
R
1
R_MV_TYPE_CHROMA
0x178[2]
R
1
R_STD_PHASE
0x178[3]
R
1
R_SRC2
R_SRC12
0x178[4]
0x178[5]
R
R
1
1
R_SRC11
0x178[6]
R
1
R_CC_INT
0x178[7]
R
1
R_CC_DATA1
R_CC_DATA2
0x17A[7:0]
0x17B[7:0]
R
R
8
8
R_CC_ERROR
0x17C[1]
R
1
57
0: No Color or Low Color
1: Color Source
Burst Phase Detection
AGC1 Tracer Ready
AGC2 Tracer Ready
0: Not Ready
1: Ready
Color Burst Detection
00: 3.57MHz
01: 4.2MHz
10: 4.3MHz
11: Non-Standard
PLL Tracer Value
MV Source Detection
0: Not MV source
1: MV Source
MV Source on Chroma
0: Not MV Source
1: MV Source
MV Type on Chroma
0: Type 2
1: Type 3
Burst Phase Detection
0: 0 – 180 – 0
1: 0 – 90 – 180 – 270 – 0
Source Detection Result for AIN2
Source Detection Result for AIN12
Source Detection Result for AIN11
0: No Signal Toggle
1: Signal Toggle
Data Slicer Interrupt
0: No CC Data
1: Has CC Data
Data Slicer First Byte
Data Slicer Second Byte
Data Slicer Error
0: Normal
1: Error
-
-
-
-
-
-
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.30 Serial RGB Output
BIT1612 內建Serial RGB輸出介面,從可以SRGB[8:1] (Pin52~Pin45)輸出數位RGB信號,從RTSx輸出HSYNC
、VSYNC、DE等信號,從SRGB_CLK(Pin 54) 輸出Clock信號,符合多種LCD Panel的Serial RGB輸入規格。詳
細規格請參考 Table 6-56、Figure 6-36 及 Figure 6-37。
Table 6-56 Serial RGB Output Register
Mnemonic
R_SRGB_T_DLY
R_SRGB_L_DLY
R_SERIAL_DLY
Address
0x0F3[7:6]
0x0F3[5:4]
0x0F3[2]
R/W
RW
RW
RW
R_SRGB_4X
0x0F3[1]
RW
R_SRGB_EN
0x0F3[0]
RW
Bits
Description
Default
2
Hsync, Vsync, DE Latency Cycle (Tclk)
10
2
Hsync, Vsync, DE Latency Cycle (Lclk)
00
1
Serial Data Delay
0
0: 3T Serial RGB (RGB)
1
0
1: 4T Serial RGB (RGBB)
Serial RGB Enable
1
1
0: Disable
1: Enable
Figure 6-36
UPS051
Figure 6-37
UPS052
6.31 BIT1690 Interface
BIT1690 為 3-Channel Video DAC,可以驅動類比LCD Panel,BIT1612 內建與BIT1690 輸入相容的介面,
透過BIT1612 的Register可以直接對BIT1690 進行控制。控制方式請參考 Table 6-57 及 Figure 6-38 和BIT1690
Data Sheet。需特別注意的是,在 0x0F5 的部份,只有當ADDR[2:0]的值有改變時,命令才有效。
Table 6-57 BIT1690 Interface Register
Mnemonic
R_SPI1690_DATA
Address
0x0F4[7:0]
R/W
RW
R_SPI1690_EN
0x0F5[7]
RW
R_SPI1690_RW
0x0F5[6]
RW
R_SPI1690_LSB
0x0F5[5]
RW
Bits
Description
8 Write Data
BIT1690 Interface – Enable
1 0: Disable
1: Enable
BIT1690 Interface – Write / Read
1
0: Write
1: Read
1 BIT1690 Interface – Write Data LSB
58
Default
0x00
0
0
0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_SPI1690_DESYNC 0x0F5[4]
R_SPI1690_CHECKER 0x0F5[3]
R_SPI1690_ADDR
0x0F5[2:0]
SRGB_OUT
R1
G1
B1
RW
RW
RW
R2
G2
B2
1
1
3
R3
BIT1690 Interface – CMD Sync
BIT1690 Interface – CMD Checker
BIT1690 Interface – ADDR
G3
B3
R4
G4
B4
0
0
000
R5
SDIO
DAC
ODE
TCLK
OCLK
Figure 6-38 BIT1690 Interface
6.32 OSD Function
The embedded OSD supports the following features:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Three OSD Windows
128 Fixed FONT ROM / 48 User Programmable FONT RAM
16 Characters Color User Programmable FONT RAM
256 Characters Display RAM
Index-Based Display RAM Memory Management
Independent Zoom Ratio x0.5~x16 for Horizontal Direction
Independent Zoom Ratio x0.5~x8 for Vertical Direction
Programmable Vertical Direction Line Space
Fade IN/OUT Effect
16 Color Palette Items (64 Colors)
Blink Display Effect
Fringe Font Effect
Fringe Window Effect
Vertical and Horizontal Directions Window Overlap
External OSD interface
6.32.1
OSD Windows Function
With the embedded OSD, BIT1612 supports at most 3 OSD windows at the same time. Please refer
to Table 6-58 for related registers.
Table 6-58 OSD Windows Register
Mnemonic
R_W0_X
R_W0_Y
R_W0_W
R_W0_H
Address
0x104[2:0], 0x102[7:0]
0x104[5:4], 0x103[7:0]
0x105[6:0]
0x106[5:0]
R/W Bits
Description
RW 11 OSD0 Start X Position
RW 10 OSD0 Start Y Position
RW 7 OSD0 Width (in Characters)
RW 6 OSD0 Height (in Characters)
Default
0x196
0x014
0x06
0x01
R_W1_X
R_W1_Y
R_W1_W
R_W1_H
0x114[2:0], 0x112[7:0]
0x114[5:4], 0x113[7:0]
0x115[6:0]
0x116[5:0]
RW
RW
RW
RW
11
10
7
6
0x033
0x03F
0x09
0x06
R_W2_X
0x124[2:0], 0x122[7:0]
RW
11 OSD2 Start X Position
59
OSD1 Start X Position
OSD1 Start Y Position
OSD1 Width (in Characters)
OSD1 Height (in Characters)
0x080
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
10 OSD2 Start Y Position
7 OSD2 Width (in Characters)
6 OSD2 Height (in Characters)
OSD1
OSD2
R_W2_X
R_W2_W
R_W1_X
VSYNC
Figure 6-39
6.32.2
HSYNC
R_W0_W
OSD0
0x0D2
0x14
0x00
R_W2_H
R_W0_X
R_W0_Y
R_W1_Y
R_W2_Y
(0,0)
RW
RW
RW
R_W1_H
0x124[5:4], 0x123[7:0]
0x125[6:0]
0x126[5:0]
R_W0_H
R_W2_Y
R_W2_W
R_W2_H
R_W1_W
OSD Windows Setup
OSD Memory Mapping
OSD的架構如 Figure 6-39 所示:
使用 R_Wx_INDEXS 和 R_Wx_INDEXE 來指出要由 Display RAM 的第幾個 ”WORD” 開始取 Data (
同時取用 0x5xx 和 0x4xx 相對應的 Data),其中 0x5xx[6] 用來控制 ”Background Fade Enable” (須搭配
R_Wx_FADE)、0x5xx[5]用來控制 “Foreground Blink Enable” (須搭配 R_Wx_CYCLE)、0x5xx[3:0]用來選
擇 16 個 Palette 中的某一個和 { 0x5xx[4], 0x4xx[6:0] } 用來控制要選取那一個 Font (0x00~0x7F:定義為
“Fixed Font” (128 個) , 0x80~0xAF:定義為 “User Font” (48 個),和 0xB0~0xBF:定義為 “Color Font” (16
個) )。
另外在Palette RAM部份是以 4 個連續位址當一個屬性,位址 “0” 的 “bit5” 用來控制 “Fringe Enable”
、位址 “0” 的 “bit4” 用來控制 “Foreground Transparent Enable” (等於 1 時,完全透過去)、位址 ”0” 的
”bit3” 用來控制 ”Background Transparent Enable” (等於 1 時,完全透過去)、位址 ”0” 的 ”bit2~0” 及位
址 ”1” 的 ”bit5~0” 用來控制 ”Foreground Color”;位址 ”2” 的 ”bit4” 用來控制 ”Foreground Fade
Enable” (須搭配R_Wx_FADE);位址 ”2” 的 ”bit3” 用來控制 ”Background Blink Enable” (須搭配
R_Wx_CYCLE) 和位址 ”2” 的 ”bit2~0” 及位址 ”3” 的 ”bit5~0” 用來控制”Background Color”,可參考
Figure 6-40 及 Figure 6-41。
而在 ”User Font” 和 ”Color Font” 部份是採用共用RAM的方式來設計,分別有 48 及 16 個Font。在
”User Font” 的部份則是以 32 個RAM位址的Data來組合成一個Font (可參考”Figure 6-42”);在 ”Color
Font” 的部份則是以 96 個RAM位址的Data來組合成一個Font (可參考 Figure 6-43)。
60
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Font Select
0x7F
0x4xx[6:0]
0x5xx[4]
Font Select(bit7)
0x500 WORD0
WORD1
0x400
0x600~0x61F
(R_BANK_SEL = 000)
Font Select(bit6~0)
WORD0
WORD1
R_Wx_INDEXS
ATTR
CODE
Display RAM
0xAF
R_Wx_INDEXE
WORD 254
0x5FF WORD 255
B6
B5
B4
0xB0
WORD 254
0x4FF WORD 255
Palette RAM
Bit[3:0]
0x300
0x0
Palette Index
0xBF
0x6E0~0x6FF
(R_BANK_SEL = 101)
0x600~0x61F
(R_BANK_SEL = 000,R),
(R_BANK_SEL = 010,G),
(R_BANK_SEL = 100,B)
0x6E0~0x6FF
(R_BANK_SEL = 001,R),
(R_BANK_SEL = 011,G),
(R_BANK_SEL = 101,B)
Color FONT RAM
0x80
User Programmable
FONT RAM
Fixed ROM
0x00
0x1
0x5xx[3:0]
Select Palette
0xF
0x33F
Fringe Enable
Foreground Transparent Enable
Background Transparent Enable
Font Select(bit7)
Foreground Blink Enable
Background Fade Enable
Address xxxx00 B5
Address xxxx01
B3
Foreground G
Address xxxx10 B5
Address xxxx11
B4
Foreground R(3bit)
Foreground B
B3
Background R
Background G
Background B
B4
Background Blink
Enable
Foreground Fade
Enable
Figure 6-40
OSD Memory Mapping
61
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Palette RAM
Display RAM
0x400
0x42 `B'
0x401
0x49 `I'
0x402
0x54 `T'
0x580 0x20
0x581 0x42
0x582
0x61
0x0
0x2
0x1
0x300
0x17
0x301
0x00
0x302
0x00
0x303
0x07
0x304
0x00
0x305
0x07
0x306
0x0F
0x307
0x00
0x308
0x28
0x309
0x38
0x30A
0x00
0x30B
0x00
Border Enable=1
Foreground Transarent Enable=0
Background Transarent Enable=0
Foreground Fade Enable=0
Background Blink Enable=0
Foreground Color :
R=8'hff,G=8'h00,B=8'h00
Background Color :
R=8'h00,G=8'h00,B=8'hFF
B
Border Enable=0
Foreground Transarent Enable=0
Background Transarent Enable=0
Foreground Fade Enable=0
Background Blink Enable=1
Foreground Color :
R=8'h00,G=8'h00,B=8'hff
Background Color :
R=8'hff,G=8'h00,B=8'h00
I
Border Enable=1
Foreground Transarent Enable=0
Background Transarent Enable=1
Foreground Fade Enable=0
Background Blink Enable=0
Foreground Color :
R=8'h00,G=8'hff,B=8'h00
Background Color :
R=8'h00,G=8'h00,B=8'h00
T
0x5FF
0x33F
Figure 6-41 Palette RAM Example
User
Programmable
FONT RAM
0x620
0x621
0x622
0x623
0x624
0x625
0x626
0x627
0x628
0x629
0x62A
0x62B
0x62C
0x62D
0x3C
0x1F
0x3E
0x17
0x06
0x16
0x06
0x14
0x1C
0x63F
0x00
0x6FF
Figure 6-42
OSD User Programmable Font RAM
62
R_BANK_SEL = 000
If Display RAM
{0x503[4],0x403[6:0]} =
0x81
0x00
0x00
0x00
0x00
0x1F
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Color FONT RAM
Figure 6-43
0x608
0x609
0x60A
0x60B
0x60C
R_BANK_SEL = 000
0x3F
0x3F
0x1F
0x3E
0x07
0x608
0x609
0x60A
0x60B
0x60C
R_BANK_SEL = 010
0x01
0x20
0x01
0x20
0x00
0x608
0x609
0x60A
0x60B
0x60C
R_BANK_SEL = 100
If Display RAM
{0x501[4],0x401[6:0]}
= 0xB0
0x02
0x10
0x02
0x10
0x01
OSD Color Font RAM
Table 6-59 OSD Memory Mapping Table
Memory
Display RAM (CODE)
Display RAM (ATTR.)
Palette RAM
User Programmable Font RAM
(Color Font RAM)
6.32.3
Mapping Address
400H~4FFH
500H~5FFH
300H~33FH
(Same as 340H~37FH, 380H~3BFH, 3C0H~3FFH)
map to User Font 0~7
R_BANK_SEL=000
or Color R Font 0~7
map to User Font 8~15
R_BANK_SEL=001
or Color R Font 8~15
map to User Font 16~23
R_BANK_SEL=010
or Color G Font 0~7
600H~6FFH
map to User Font 24~31
R_BANK_SEL=011
or Color G Font 8~15
map to User Font 32~39
R_BANK_SEL=100
or Color B Font 0~7
map to User Font 40~47
R_BANK_SEL=101
or Color B Font 8~15
OSD Windows Attributes
BIT1612 可以分別為 3 個 OSD 視窗設定不同的屬性。
Table 6-60 OSD Windows Attribute Register
Mnemonic
R_W0_INDEX_S
R_W0_INDEX_E
R_W0_FADE
R_W0_WMIRX
Address
0x107[7:0]
0x108[7:0]
0x10B[3:0]
0x109[6]
R/W Bits
Description
RW 8 OSD0 Display RAM Start Index
RW 8 OSD0 Display RAM End Index
RW 4 OSD0 Fade In/Out Level
RW 1 OSD0 Window Mirror for Horizontal
63
Default
0x00
0xFF
0xF
0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_W0_WMIRY
R_W0_FMIRX
R_W0_FMIRY
0x10A[6]
0x109[7]
0x10A[7]
RW
RW
RW
1
1
1
R_W0_FFRI_SEL
0x10D[7:0] RW
8
R_W0_FFRI_H
0x10C[3:0] RW
4
R_W0_FFRI_V
0x10C[6:4] RW
3
R_W0_FFRI_COR
0x10E[2:0] RW
3
R_W0_MULX
0x109[4:0] RW
5
R_W0_MULY
0x10A[3:0] RW
4
R_W0_VANISH_LN
R_W0_VANISH_DIR
R_W0_WFRI_EN
R_W0_WFRI_H
R_W0_WFRI_V
0x10E[7:4]
0x10E[3]
0x10F[7]
0x10F[3:0]
0x10F[6:4]
RW
RW
RW
RW
RW
4
1
1
4
3
R_W0_WFRI_R
0x110[1:0] RW
2
R_W0_WFRI_G
0x110[3:2] RW
2
R_W0_WFRI_B
0x110[5:4] RW
2
R_W0_WFRI_FADE
R_W0_WFRI_BLEN
R_W0_WDLY
R_W0_EN
0x110[7]
0x110[6]
0x10B[6:4]
0x111[7]
RW
RW
RW
RW
1
1
3
1
R_W0_CYCLE
0x111[6:4] RW
3
R_W0_SPCY
0x111[2:0] RW
3
R_W1_INDEX_S
R_W1_INDEX_E
R_W1_FADE
R_W1_WMIRX
R_W1_WMIRY
R_W1_FMIRX
R_W1_FMIRY
0x117[7:0]
0x118[7:0]
0x11B[3:0]
0x119[6]
0x11A[6]
0x119[7]
0x11A[7]
RW
RW
RW
RW
RW
RW
RW
8
8
4
1
1
1
1
R_W1_FFRI_SEL
0x11D[7:0] RW
8
R_W1_FFRI_H
0x11C[3:0] RW
4
OSD0 Window Flip
OSD0 Characters Mirror for Horizontal
OSD0 Characters Mirror for Vertical
OSD0 Font Fringe Selection
Bit7: Left, Up;
Bit6: Up;
Bit5: Right, Up;
Bit4: Left;
Bit3: Right;
Bit2: Left, Down; Bit1: Down; Bit0: Right, Down;
OSD0 Font Fringe Horizontal Width
(R_W0_FFRI_H<=R_W0_MULX)
4’b0000: 1 Pixel; ~ 4’b1111: 16 Pixels;
OSD0 Font Fringe Vertical Width
(R_W0_FFRI_V<=R_W0_MULY)
3’b000: 1 Pixel; ~ 3’b111: 8 Pixels;
OSD0 Font Fringe Color
Bit2: Color R; Bit1: Color G;
Bit0: Color B
OSD0 Horizontal Character Size
5’b00000: x1; ~ 5’b01111: x16;
5’b10000: x0.5 (Odd); 5’b10001: x0.5 (Even);
5’b1001X: x0.5 (Field Change)
OSD0 Vertical Character Size
4’b0000: x1; ~ 4’b0111:x8
4’b1000: x0.5 (Odd); 4’b1001: x0.5 (Even),
4’b101x: x0.5 (Field Change)
OSD0 Vanish Line Number
OSD0 Vanish Line Direction
OSD0 Window Fringe Enable
OSD0 Window Fringe Horizontal Width (Pixel)
OSD0 Window Fringe Vertical Width (Line)
OSD0 Window Fringe Color
Color R
OSD0 Window Fringe Color
Color G
OSD0 Window Fringe Color
Color B
OSD0 Window Fringe Fade In/Out Enable
OSD0 Window Fringe Blink Enable
OSD0 Window Delay (Pixel)
OSD0 Window Enable
OSD0 Blink Period (in VSYNC)
3'b000 : 1;
3'b001 : 2;
3'b010 : 4;
3'b011 : 8;
3'b100 : 16;
3'b101 : 32;
3'b110 : 64;
3'b111 : 128;
OSD0 Vertical Character Space
OSD1 Display RAM Start Index
OSD1 Display RAM End Index
OSD1 Fade In/Out Level
OSD1 Window Mirror for Horizontal
OSD1 Window Flip
OSD1 Characters Mirror for Horizontal
OSD1 Characters Mirror for Vertical
OSD1 Font Fringe Selection
Bit7: Left, Up;
Bit6: Up;
Bit5: Right, Up;
Bit4: Left;
Bit3: Right;
Bit2: Left, Down; Bit1: Down; Bit0: Right, Down;
OSD1 Font Fringe Horizontal Width
(R_W1_FFRI_H<=R_W1_MULX)
64
0
0
0
0xFF
0x0
000
111
0x00
0x0
0x0
0
0
0x0
000
00
00
00
0
0
000
0
111
000
0x0F
0xFF
0xF
0
0
0
0
0xFF
0x0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_W1_FFRI_V
0x11C[6:4] RW
3
R_W1_FFRI_COR
0x11E[2:0] RW
3
R_W1_MULX
0x119[4:0] RW
5
R_W1_MULY
0x11A[3:0] RW
4
R_W1_VANISH_LN
R_W1_VANISH_DIR
R_W1_WFRI_EN
R_W1_WFRI_H
R_W1_WFRI_V
0x11E[7:4]
0x11E[3]
0x11F[7]
0x11F[3:0]
0x11F[6:4]
RW
RW
RW
RW
RW
4
1
1
4
3
R_W1_WFRI_R
0x120[1:0] RW
2
R_W1_WFRI_G
0x120[3:2] RW
2
R_W1_WFRI_B
0x120[5:4] RW
2
R_W1_WFRI_FADE
R_W1_WFRI_BLEN
R_W1_WDLY
R_W1_EN
0x120[7]
0x120[6]
0x11B[6:4]
0x121[7]
RW
RW
RW
RW
1
1
3
1
R_W1_CYCLE
0x121[6:4] RW
3
R_W1_SPCY
0x121[2:0] RW
3
R_W2_INDEX_S
R_W2_INDEX_E
R_W2_FADE
R_W2_WMIRX
R_W2_WMIRY
R_W2_FMIRX
R_W2_FMIRY
0x127[7:0]
0x128[7:0]
0x12B[3:0]
0x129[6]
0x12A[6]
0x129[7]
0x12A[7]
RW
RW
RW
RW
RW
RW
RW
8
8
4
1
1
1
1
R_W2_FFRI_SEL
0x12D[7:0] RW
8
R_W2_FFRI_H
0x12C[3:0] RW
4
R_W2_FFRI_V
0x12C[6:4] RW
3
R_W2_FFRI_COR
0x12E[2:0] RW
3
R_W2_MULX
0x129[4:0] RW
5
4’b0000: 1 Pixel; ~ 4’b1111: 16 Pixels;
OSD1 Font Fringe Vertical Width
(R_W1_FFRI_V<=R_W1_MULY)
3’b000: 1 Pixel; ~ 3’b111: 8 Pixels;
OSD1 Font Fringe Color
Bit2: Color R;
Bit1: Color G;
Bit0: Color B
OSD1 Horizontal Character Size
5’b00000: x1; ~ 5’b01111: x16;
5’b10000: x0.5 (Odd); 5’b10001: x0.5 (Even);
5’b1001X: x0.5 (Field Change)
OSD1 Vertical Character Size
4’b0000: x1; ~ 4’b0111:x8
4’b1000: x0.5 (Odd); 4’b1001: x0.5 (Even),
4’b101x: x0.5 (Field Change)
OSD1 Vanish Line Number
OSD1 Vanish Line Direction
OSD1 Window Fringe Enable
OSD1 Window Fringe Horizontal Width (Pixel)
OSD1 Window Fringe Vertical Width (Line)
OSD1 Window Fringe Color
Color R
OSD1 Window Fringe Color
Color G
OSD1 Window Fringe Color
Color B
OSD1 Window Fringe Fade In/Out Enable
OSD1 Window Fringe Blink Enable
OSD1 Window Delay (Pixel)
OSD1 Window Enable
OSD1 Blink Period (in VSYNC)
3'b000 : 1;
3'b001 : 2;
3'b010 : 4;
3'b011 : 8;
3'b100 : 16;
3'b101 : 32;
3'b110 : 64;
3'b111 : 128;
OSD1 Vertical Character Space
OSD2 Display RAM Start Index
OSD2 Display RAM End Index
OSD2 Fade In/Out Level
OSD2 Window Mirror for Horizontal
OSD2 Window Flip
OSD2 Characters Mirror for Horizontal
OSD2 Characters Mirror for Vertical
OSD2 Font Fringe Selection
Bit7: Left, Up;
Bit6: Up;
Bit5: Right, Up;
Bit4: Left;
Bit3: Right;
Bit2: Left, Down; Bit1: Down; Bit0: Right, Down;
OSD2 Font Fringe Horizontal Width
(R_W2_FFRI_H<=R_W2_MULX)
4’b0000: 1 Pixel; ~ 4’b1111: 16 Pixels;
OSD0 Font Fringe Vertical Width
(R_W2_FFRI_V<=R_W2_MULY)
3’b000: 1 Pixel; ~ 3’b111: 8 Pixels;
OSD2 Font Fringe Color
Bit2: Color R;
Bit1: Color G;
Bit0: Color B
OSD2 Horizontal Character Size
5’b00000: x1; ~ 5’b01111: x16;
5’b10000: x0.5 (Odd); 5’b10001: x0.5 (Even);
65
000
111
0x00
0x0
0x0
0
0
0x0
000
00
00
00
0
0
000
0
111
000
0x54
0xFF
0xF
0
0
0
0
0xFF
0x0
000
000
0x00
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_W2_MULY
0x12A[3:0] RW
4
R_W2_VANISH_LN
R_W2_VANISH_DIR
R_W2_WFRI_EN
R_W2_WFRI_H
R_W2_WFRI_V
0x12E[7:4]
0x12E[3]
0x12F[7]
0x12F[3:0]
0x12F[6:4]
RW
RW
RW
RW
RW
4
1
1
4
3
R_W2_WFRI_R
0x130[1:0] RW
2
R_W2_WFRI_G
0x130[3:2] RW
2
R_W2_WFRI_B
0x130[5:4] RW
2
R_W2_WFRI_FADE
R_W2_WFRI_BLEN
R_W2_WDLY
R_W2_EN
0x130[7]
0x130[6]
0x12B[6:4]
0x131[7]
RW
RW
RW
RW
1
1
3
1
R_W2_CYCLE
0x131[6:4] RW
3
R_W2_SPCY
0x131[2:0] RW
3
5’b1001X: x0.5 (Field Change)
OSD2 Vertical Character Size
4’b0000: x1; ~ 4’b0111:x8
4’b1000: x0.5 (Odd); 4’b1001: x0.5 (Even),
4’b101x: x0.5 (Field Change)
OSD2 Vanish Line Number
OSD2 Vanish Line Direction
OSD2 Window Fringe Enable
OSD2 Window Fringe Horizontal Width (Pixel)
OSD2 Window Fringe Vertical Width (Line)
OSD2 Window Fringe Color
Color R
OSD2 Window Fringe Color
Color G
OSD2 Window Fringe Color
Color B
OSD2 Window Fringe Fade In/Out Enable
OSD2 Window Fringe Blink Enable
OSD2 Window Delay (Pixel)
OSD2 Window Enable
OSD2 Blink Period (in VSYNC)
3'b000 : 1;
3'b001 : 2;
3'b010 : 4;
3'b011 : 8;
3'b100 : 16;
3'b101 : 32;
3'b110 : 64;
3'b111 : 128;
OSD2 Vertical Character Space
0x0
0x0
0
0
0x0
000
00
00
00
0
0
000
0
111
000
Display RAM
0x400
R_Wx_INDEX_S+1
R_Wx_INDEX_S = 0
R_Wx_INDEX_S
“B"
R_Wx_INDEX_S+5
R_Wx_INDEX_S+6
R_Wx_W = 5
“I"
B I
T
E
“E"
1
6
1
2
“K"
“"
R_Wx_H = 4
“T"
K
“1"
R_Wx_INDEX_E = 29
“6"
0x4FF
R_Wx_SPCY
0x5FF
Figure 6-44
OSD Windows Attribute
66
BIT1612
6.32.4
10-Bit Digital Video Decoder with OSD and T-CON
OSD Windows Overlap Selection
以下 Register 用來選擇 OSD 視窗重疊的順序。
Table 6-61 OSD Windows Overlap Selection
Mnemonic
R_OSD_LAYER
Address
R/W Bits
0x101[7:5] RW
3
Description
OSD Windows Overlap Selection
000
OSD0->OSD1->OSD2
001
OSD0->OSD2->OSD1
010
OSD1->OSD0->OSD2
011
OSD1->OSD2->OSD0
100
OSD2->OSD0->OSD1
101, 11x
OSD2->OSD1->OSD0
(0,0)
Default
000
HSYNC
R_OSD_LAYER[2:0] = 001
OSD0
OSD2
OSD1
VSYNC
Figure 6-45
OSD Windows Overlap
67
BIT1612
6.32.5
10-Bit Digital Video Decoder with OSD and T-CON
External OSD Interface
BIT1612 可連接外部 OSD 作為更複雜的 OSD 應用,共計可以顯示 8 種顏色。然而,因為 GIN Port
會被外部 OSD 佔用,在這樣情況下,BIT1612 無法支援 Graphic 輸入方式。
Table 6-62 External OSD Register
Mnemonic
Address
R/W Bits
R_EXTOSD_EN
0x100[0]
RW
1
R_POL_EXTBNK
0x100[1]
RW
1
R_POL_OSDHS
0x100[2]
RW
1
R_POL_OSDVS
0x100[3]
RW
1
R_POL_OSDCLK
0x100[4]
RW
1
6.32.6
Description
External OSD Enable
0: Disable
1: Enable
External OSD Blank Polarity
0: Normal
1: Invert
External OSD HSYNC Polarity
0: Normal
1: Invert
External OSD VSYNC Polarity
0: Normal
1: Invert
External OSD CLOCK Polarity
0: Normal
1: Invert
Default
0
0
0
0
0
OSD User Programmable RAM Selection
以下 Register 用來選擇讀/寫 OSD User Programmable RAM 時所用的 Memory Bank。
Table 6-63 User Programmable RAM Selection
Mnemonic
R_BANK_SEL
Address
R/W Bits
0x101[4:2] RW
Description
User Programmable RAM Banks Selection
Bank 0, Mapping to User Font 0~7
000
(Mapping to R Color Font 0~7)
Bank 1, Mapping to User Font 8~15
001
(Mapping to R Color Font 8~15)
Bank 2, Mapping to User Font 16~23
010
3
(Mapping to G Color Font 0~7)
Bank 3, Mapping to User Font 24~31
011
(Mapping to G Color Font 8~15)
Bank 4, Mapping to User Font 32~39
100
(Mapping to B Color Font 0~7)
Bank 5, Mapping to User Font 40~47
101
(Mapping to B Color Font 8~15)
68
Default
000
BIT1612
6.32.7
10-Bit Digital Video Decoder with OSD and T-CON
OSD Clock Control
BIT1612 OSD部份提供 Clock 開或關的功能,其相關Registers設定請參考 Table 6-64。
Table 6-64 OSD Clock Setting Register
Mnemonic
Address
R/W Bits
R_OSDCLK_EN
0x00B[0]
RW
R_OSDCLK_POL
0x00B[1]
RW
6.32.8
Description
OSD Clock Enable
1 0: Disable
1: Enable
OSD Clock Polarity
1 0: Normal
1: Invert
Default
1
1
OSD Built-In Fixed Font
BIT1612 已內建 128 種 OSD 字型,其定址如下:
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
Figure 6-46 Fixed Font
69
9
A
B
C
D
E
F
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.33 Timer
BIT1612 提供了兩個獨立 16 位元的計數器,相關說明及設定請參考下列圖表。
Table 6-65 Timer Register
Mnemonic
R_TIMER0_VAL
R_TIMER0_EN
R_TIMER0_MODE
R_TIMER0_BASE_MODE
R_TIMER1_VAL
R_TIMER1_EN
R_TIMER1_MODE
R_TIMER1_BASE_MODE
Address
R/W Bits
Description
0x143[7:0],0x142[7:0] RW 16 Timer 0 Count Value
Timer 0 Enable
0x144[0]
RW 1 0: Disable
1: Enable
Timer 0 Count Mode
0x144[1]
RW 1 0: Circulation
1: One-Shot
Timer 0 Count Base
00: Output VSYNC
0x144[3:2]
RW 2 01: Output HSYNC
10: Input VSYNC
11: Input HSYNC
0x146[7:0],0x145[7:0] RW 16 Timer 1 Count Value
Timer 1 Enable
0x147[0]
RW 1 0: Disable
1: Enable
Timer 1 Count Mode
0x147[1]
RW 1 0: Circulation
1: One-Shot
Timer 1 Count Base
00: Output VSYNC
0x147[3:2]
RW 2 01: Output HSYNC
10: Input VSYNC
11: Input HSYNC
Default
0x0000
0
0
00
0x0000
0
0
00
XCLK
TIMER0_OUT
COUNTER0
0
1
2
3
4
5
0
1
2
3
4
5
0
R_TIMER0_EN
R_TIMER0_MODE
R_TIMER0_BASE_MODE[1:0]
0
R_TIMER0_VAL[7:0]
5
Figure 6-47 Timer Mode 0 (Circulation)
XCLK
TIMER0_OUT
COUNTER0
0
1
2
3
4
5
R_TIMER0_EN
R_TIMER0_MODE
R_TIMER0_BASE_MODE[1:0]
0
R_TIMER0_VAL[7:0]
5
Figure 6-48 Timer Mode 1 (One-Shot)
70
0
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.34 IR Decoder Function
BIT1612 提供 NEC IR Decoder function,由 BIT1612 偵測 NEC IR Format,並經由 Interrupt 提供給 MCU 參
考,其相關 Registers 設定請參考下表:
Table 6-66 IR Pulse Detection Register
Mnemonic
R_IR_CC
R_POL_IR
Address
0x149[7:0]
0x148[7:0]
0x14A[0]
R_IR_DISREPT 0x14A[1]
R_IR_BASE
0x14A[4:2]
R_IR_CHECK
0x14A[7:5]
R_IR_EN
0x14B[0]
R_IR_DB
0x14B[3:2]
R_IR_TYPE
0x14B[4]
R_IR_CODE
0x14C[7:0]
0x14D[7:0]
0x14E[7:0]
0x14F[7:0]
R/W Bits
Description
RW
8 User Defined Customer Code
RW
8 User Defined Customer /Code
NEC IR Polarity
RW
1 0: Normal
1: Invert
Repeat Code Detection Enable
RW
1 0: Enable Repeat Code
1: Disable Repeat Code
NEC IR Clock Base
000: XCLK
001: XCLK/2
010: XCLK/3
RW
3 011: XCLK/4
100: XCLK/5
101: XCLK/6
110: XCLK/7
111: XCLK/8
NEC Interrupt Conditions
[5]: Check IR Code = ~IR /Code
[6]: Check IR Data = ~IR /Data
[7]: Check
RW
3
IR Code = User Defined Customer
Code and
IR /Code = User Defined Customer
/Code
NEC IR Decoder Enable
RW
1 0: Disable
1: Enable
RW
2 IR De-Bounce Setup
IR Code Type
R
1 0: First Code
1: Repeat Code
R
8 NEC IR /Data Byte
R
8 NEC IR /Code Byte
R
8 NEC IR Data Byte
R
8 NEC IR Code Byte
71
Default
0x00
0x00
0
0
000
000
0
00
-
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
6.35 GPI and KEY Function
BIT1612 內建 8 組GPI (General Purpose Input),並可針對各個GPI Pin分別規劃為Level Status,Key Down 或
Key Up三種觸發狀態,並可經由Interrupt (0x002[7])、R_KEY_STATUS (0x155) 及R_KEY_ACK (0x156) 讀回
其狀態。相關Registers設定請參考 Table 6-67 及 Figure 6-49。
Table 6-67 GPI and KEY Register
Mnemonic
R_KEY_STATUS
R_KEY_ACK
R_KEY_LONG_FLAG
R_KEY_LONG_ACK
R_KEY_TYPE
R_KEY_DEDGE
Address
0x155[7:0]
0x156[7:0]
0x157[7]
0x157[3:0]
0x150[7:0]
0x151[7:0]
R/W
R
R
R
R
RW
RW
Bits
8
8
1
4
8
8
R_KEY_SRC
0x152[7]
RW
1
R_KEY_DB
R_KEY_LONG_EN
R_KEY_LONG_STR
R_KEY_LONG_REP
R_KEY_CLEAR
R_KEY_TB
0x152[6:4]
0x152[3:0]
0x153[7:0]
0x154[7:0]
0x157[4]
0x157[6:5]
RW
RW
RW
RW
RW
RW
3
4
8
8
1
2
R_KEY_SRC_64
0x14B[1]
RW
1
Description
Real Time GPI Status
KEY Trigger Status
Long Key Trigger Flag
Long Key Trigger Status
0: Positive Edge; 1: Negative Edge
0: Single Edge; 1: Double Edge
R_KEY_SRC_64=0
0: TOUT_I
1: BIN
R_KEY_SRC_64=1
0: RIN
1: HSYNC (Key[1]), VSYNC (Key[0])
GPI De-Bounce Setup
GPI[3:0] Long Key Monitor Enable
Long Key Trigger Threshold
Long Key Trigger Interval
0: Normal; 1: Clear
Long Key Basic Clock Cycle
KEY Source Selection
0: Type 1
1: Type 2
Default
0x00
0x00
0
0x0
0x00
0x00
1
100
0x0
0xFF
0x50
1
01
0
GPI
debounce time
long key threshold
long key repeat interval
long key repeat interval
KEY_INT
Figure 6-49 Long Key Process
6.36 PLL and OSC Pads
BIT1612 內建一組PLL,並依據Oscillator所提供的頻率產生可程式化的Clock輸出。其相關公式及Registers
請參考 Table 6-68 及 Figure 6-50。
Table 6-68 PLL Register
Mnemonic
R_PLL_PD
Address
R/W Bits
0x158[0]
RW
R_PLL_RESETN 0x158[1]
RW
Description
PLL Power Down Enable
1 0: Normal
1: Disable
PLL Reset
1 0: Reset
1: Normal
72
Default
0
1
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_PLL_HALFCK
0x158[2]
R_PLL_SEL
0x158[3]
R_PLL_DM_M0
R_PLL_DN_M0
R_PLL_DP_M0
0x159[4:0]
0x15A[6:0]
0x15B[5:0]
R_PLL_DM_M1
R_PLL_DN_M1
R_PLL_DP_M1
0x15C[4:0]
0x15D[6:0]
0x15E[5:0]
PLL_OUT =
PLL Half Clock Output
1 0: Normal
1: Half Clock
PLL Clock Control
RW 1 0: Normal
1: DIV ((R_PLL_DP+1)*2)
Auto Switch Mode 0 Input Widows Setup
RW 5 PLL DM Value
RW 7 PLL DN Value
RW 6 PLL DP Value
Auto Switch Mode 1 Input Widows Setup
RW 5 PLL DM Value
RW 7 PLL DN Value
RW 6 PLL DP Value
RW
1
0
0x08
0x09
0x00
0x08
0x09
0x00
(R_PLL_DN+1)
1
1
*
*
* OSC_Freq_Sel
R_PLL_HALFCK
R_PLL_SEL
(R_PLL_DM+1) 2
((R_PLL_DP+1)*2)
Figure 6-50 PLL Frequency Formula
6.37 Auto Detection
BIT1612 提供七種輸入訊號偵測機制,分別為 PCLK Base SYNC Detection、XCLK Base HSYNC Detection
、Mode Change Detection、Mode Type Detection、Even/Odd Type Detection、Data Enable Signal Detection
和 No Signal Detection。
1.
PCLK Base SYNC Detection:
以 PCLK 偵測 External HSYNC、External VSYNC Low Pulse Width 及 Total SYNC Width,其主要作為
SYNC 極性判別及模式的偵測,此偵測機制 Power On 時就會自動啟動且無法由 MCU 去終止或啟動,
其操作步驟如下:
(讀取偵測 SYNC 資料:)
Register (0x160[7:0]):
HSYNC Low Pulse (in PCLK)。
Register (0x164[7:4], 0x161[7:0]): HSYNC Total Width (in PCLK)。
Register (0x162[7:0]):
VSYNC Low Pulse (in HSYNC)。
Register (0x164[2:0], 0x163[7:0]): VSYNC Total Width (in HSYNC)。
2.
XCLK Base HSYNC Detection:
以 XCLK 偵測 External HSYNC,其主要作為模式的判別。此偵測機制會以 XCLK 為基準計算 Input
HSYNC Low Level Width 和 HSYNC High Level Width,其操作步驟如下:
(讀取偵測 HSYNC 資料:)
Register (0x167[7:4], 0x165[7:0]): HSYNC High Level Width (in XCLK)。
Register (0x167[3:0], 0x166[7:0]): HSYNC Low Level Width (in XCLK)。
3.
Mode Change Detection:
偵測 VSYNC 變化量,如果 VSYNC 變化量大於 8 條 HSYNCs,將會經由 Interrupt 機制回應給 MCU 得
知,其操作步驟如下:
Set Interrupt Enable (Register: 0x004[2])。
如果 VSYNC 變化量大於 8,將會由 INT Pin 發出 Interrupt,亦可藉由輪詢的方式讀取 Interrupt Flag
(Register: 0x002[2]) 而得知。
4.
Mode Type Detection:
73
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
自動辦別 NTSC/PAL Mode 並可由 Register (0x16A[1]) 直接讀出其狀態。
5.
EVEN/ODD Type Detection:
自動判別 VSYNC 是否有 EVEN/ODD 相關變化,並可由 Register (0x16A[2]) 直接讀出其狀態。
6.
Data Enable Signal Detection:
自動偵測 Data Enable Signal Information 以供系統作為設定 Input Windows 的參考。
7.
No Signal Detection:
自動判別 HSYNC 是否有 Toggle,如果在 2047 XCLKs 內沒有變化將由 Interrupt (0x002[1:0]) 回應或
可由 Register (0x16A[3]) 直接讀出其狀態。
Table 6-69
Auto Detection Register
Mnemonic
Address
R/W Bits
R_IS_XP
0x160[7:0]
R
8
R_IS_XT
0x164[7:4], 0x161[7:0]
R
12
R_IS_YP
0x162[7:0]
R
8
R_IS_YT
0x164[2:0], 0x163[7:0]
R
11
R_DET_XP
0x167[7:4],0x165[7:0]
R
12
R_DET_XN
0x167[3:0],0x166[7:0]
R
12
R_HOUNT
0x169[6:0],0x168[7:0]
R
15
R_MODECHG
0x16A[0]
R
1
R_MODE_TYPE
0x16A[1]
R
1
R_EVENSAME
0x16A[2]
R
1
R_SIGIN
0x16A[3]
R
1
R_AUTOON
0x16A[4]
R
1
R_SWITCH
0x16A[5]
R
1
R_EVEN
0x16A[6]
R
1
R_IDE_INFO
0x16C[3:0],0x16B[7:0]
R
12
R_IDE_DET
0x4E[1:0]
RW
2
R_IDE_SEL
0x4E[3:2]
RW
2
74
Description
Default
HSYNC Low Pulse
(Base on PCLK)
HSYNC Total Width
(Base on PCLK)
VSYNC Low Pulse
(Base on HSYNC)
VSYNC Total width
(Base on HSYNC)
HSYNC High Level Width
(Base on XCLK)
HSYNC Low Level Width
(Base on XCLK)
Line Buffer Overflow/Underflow
Count
Mode Change Status
Î0: No Mode Change
Î1: VSYNC Variation Larger than 8
HSYNCs
Mode Status
Î0: 50Hz
Î1: 60Hz
EVEN Type Status
Î0: Had EVEN/ODD Information
Î1: No EVEN/ODD Information
Sync Status
Î0: Signal Ready
Î1: No Signal
Auto Blank Status
Î0: Normal Mode
Î1: Free-Run Mode
Auto Switch Status
Î0: Mode 0
Î1: Mode 1
EVEN/ODD Information
Î0: EVEN Field
Î1: ODD Field
Input Data Enable Information
Input Data Enable Mode Selection
00: HSYNC Low Pulse Information
00
01: HSYNC High Pulse Information
10: VSYNC Low Pulse Information
11: VSYNC High Pulse Information
Input Data Enable Source Selection
00
00: From HSYNC1 Pin
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
01: From VSYNC1 Pin
10: From HSYNC2 Pin
11: From VSYNC2 Pin
75
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
7 User Interface
BIT1612 提供二種 Interface Mode (Slave Mode 和 Script Master Mode),使其能應用在不同的環境中。
7.1 Options Pins
BIT1612 使用 6 根外部 Pins 來做 Mode 的選擇。主要可以分為 Master 與 Slave Mode。Slave Mode 下,外
部的 MCU 可以經由 Pin OP1、OP0 控制 BIT1612,並視需要選擇 Two-Wire Serial Interface (TWSI) Protocol 或
是 Bitek Bus Protocol。Master Mode 則是運用 BIT1612 內建 CPU 搭配外部程式記憶體完成系統設計。在 Master
Mode 下 Script MCU 則只需要搭配 24 系列的 Serial EEPROM,並利用 Bitek 自行定義的指令集,即可完成 BIT1612
的相關控制。
Script MCU支援三種工作模式,分別是Single 24C16、Single 24C32 與Dual 24C16。Single 24C16 Mode可
以支援單顆 24C16 以下的EEPROM;24C32 Mode可以支援單顆 24C32 系列的EEPROM (24C32/24C64);Dual
24C16 Mode可以運用 { OP2, OP3 } 做為第二組TWSI介面,擴充程式記憶體,最多可支援兩顆 24C16,定義及
使用方法請參考下表,其示意圖可參考 Figure 7-1、Figure 7-2、Figure 7-3 及 Figure 7-4。
Table 7-1 Options Pins Setup
OP5
0
0
1
1
1
1
1
1
1
1
1
OP4
0
1
X
0
0
0
0
1
1
1
1
OP3 OP2 OP1 OP0
Mode
SCL2 SDA2 SCL1 SDA1 EEPROM 24C16 Script Mode
SCL2 SDA2 SCL1 SDA1 EEPROM 24C32 Script Mode
SA[1] SA[0] SCL1 SDA1 Slave Mode
0
0
SCL1 SDA1 TWSI Mode Slave Address (0x00~0x0F)
0
1
SCL1 SDA1 TWSI Mode Slave Address (0x20~0x2F)
1
0
SCL1 SDA1 TWSI Mode Slave Address (0x40~0x4F)
1
1
SCL1 SDA1 TWSI Mode Slave Address (0x60~0x6F)
0
0
SCL1 SDA1 BiTEKBUS Mode Slave Address 0x81
0
1
SCL1 SDA1 BiTEKBUS Mode Slave Address 0x83
1
0
SCL1 SDA1 BiTEKBUS Mode Slave Address 0x85
1
1
SCL1 SDA1 BiTEKBUS Mode Slave Address 0x87
Figure 7-1 Slave Mode
76
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Figure 7-2 Master Mode with Single 24C16
Figure 7-3 Master Mode with Single 24C32
77
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Serial EEPROM
BIT1612
OP0
OP0
OP1
OP1
OP2
OP2
OP3
OP3
24C16
WP
24C02
Serial
addr
Parallel
data
WP
OP4
OP5
Script-CTRL
{R_EEPROM_BANK[4:0], ADDR[10:0]}
Figure 7-4 Master Mode with Dual EEPROM
78
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
7.2 Master Mode – Script MCU
BIT1612 內建 Script MCU,可提供使用者將程式碼儲存在 Serial EEPROM 中,BIT1612 將會依據使用者所
撰寫的程式碼內容,解碼後執行其相對的指令,目前僅支援 24 系列 (24C02~24C64) 的 Serial EEPROM。而執
行速度則依據於 TWSI 速度而定,透過設定 R_SERIAL_CKEN_SEL (0x138[2:0]) 可調整 TWSI 速度,從 98KHz
~ 384KHz,參考設定如下表。
Table 7-2 TWSI Speed
R_SERIAL_CKEN_SEL=0
R_SERIAL_CKEN_SEL=1
R_SERIAL_CKEN_SEL=2
R_SERIAL_CKEN_SEL=3
R_SERIAL_CKEN_SEL=4
R_SERIAL_CKEN_SEL=5
R_SERIAL_CKEN_SEL=6
R_SERIAL_CKEN_SEL=7
7.2.1
OSC/1
97KHz
189KHz
372KHz
585KHz
614KHz
768KHz
945KHz
x
R_XCLK_SEL
OSC/2
48KHz
95KHz
186KHz
292KHz
307KHz
384KHz
472KHz
558KHz
OSC/4
24KHz
47KHz
93KHz
146KHz
153KHz
192KHz
236KHz
279KHz
Architecture
BIT1612 內建之Script Control內含 4 個Internal Registers (A_REG、B_REG、C_REG、Z_REG) 及
5 組Internal Address Index (PC、EADDR、RADDR、IADDR、R_REG_ADDR),32 Bytes Internal RAM
(0x700~0x71F),BIT1612 指令集對EEPROM只能定址到 2KB,但可以運用R_EEPROM_BANK_SEL切換
EEPROM BANK方式擴増,最多可以定址到 64KB。相關Registers如 Table 7-3 所示,所有的算數及邏輯
運算皆在A_REG及B_REG內進行。
Table 7-3 Register and Address Index
Register and Address Index
A_REG
B_REG
C_REG
Z_REG
PC
EADDE
RADDR
IADDR
R_REG_ADDR
R_REG_NUM
R_REG_CNT
R_SERIAL_CKEN_SEL
R_SECOND_EEPROM
R_EEPROM_BANK_SEL
R_PG_EN
R_PG_POL
Address
0x13F[7:0]
0x140[7:0]
0x13E[6]
0x13E[5]
-
R/W Bits
Memo
R
8 Operand A Register
R
8 Operand B Register
R
1 Carry Flag Register
R
1 Zero Flag Register
11 Program Counter
11 EEPROM Address
11 Internal Register Setting Address
TWSI Address
8 Device Address <= R_TWSI_SLAVE
REG Address <= Instruction Byte 2
ADDR Register (Shared)
FILLR
0x137[2:0],0x136[7:0] RW 11
JMPR
TABLE
NUM Register (Shared)
0x134[7:0]
RW 8
FILLR
Count Register (Shared)
0x135[7:0]
RW 8
FILLR
TWSI SCL SPEED
0x138[2:0]
RW 3 98KHz ~ 384KHz
(111: Fastest; 000: Lowest)
Second EEPROM Enable
0x138[3]
RW 1 0: Single EEPROM
1: Dual EEPROM
0x137[7:3]
RW 5 EEPROM Bank Selection
0x138[4]
RW 1 Power Good Function Enable
Power Monitor Input Inverse
0x138[5]
RW 1 0: Low active
1: High active
79
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_POF
0x13E[4]
R
1
R_MCU_DEBUG
0x138[6]
RW
1
R_TWSI_SEC
0x138[7]
RW
1
R_TWSI_DET_VALUE
R_TWSI_DET_IN
0x139[7:0]
0x13A[7:0]
RW
RW
8
8
R_TWSI_DET_MODE
0x13B[1:0]
RW
2
R_TWSI_SEC_SLAVE
R_TWSI_DET_OUT
R_WDT_CLEAR
0x13B[3:2]
0x13D[7:0]
0x13B[4]
RW
R
RW
2
8
1
R_WDT_SEL
0x13B[7:5]
RW
3
R_WDT_OV
0x13E[7]
R
1
R_TWSI_SLAVE
0x136[6:0]
RW
7
R_SPI_CTRL
0x134[7:0]
RW
8
R_SPI_CTRL2
0x133[4:0]
RW
5
R_SPI_LOCK
0x13C[1]
RW
1
R_SPI1_EN
0x13C[2]
RW
1
80
Power Low Flag
0: Normal
1: Power Low Reset
MCU Debug Mode
0: Disable
1: Enable
Second EEPROM I/O Pin Enable
0: Disable
1: Enable
Second TWSI Bus Detection Value
Second TWSI Bus Read Value
Second TWSI Bus Detection Mode
(Trigger Condition)
00: ADDR[7:0] =
R_TWSI_DET_VALUE[7:0]
01: Write Trigger
10: Read Trigger
11: Write/Read Trigger
Second TWSI Bus Slave Address
Second TWSI Bus Detection Write Value
WDT Clear
WDT Interval Selection
000 : 20ms;
001 : 40ms;
010 : 80ms;
011 : 160ms;
100 : 320ms;
101 : 640ms;
110 : 1.28sec;
111 : 2.56sec;
WDT overflow
TWSI Slave Device Address (Shared)
For Instruction
MOV @IADDR, A
MOV A, @IADDR
SPI Function Control
[7] SPI CS Inverse
[6] SPI DATA Inverse
[5] SPI CLK Inverse
[4] SPI SYNC
0: Immediately
1: Synchronized with TCON
[3:2] SPI Mode
00: Mode 0
11: Mode 3
[1:0] SPI Speed
00: XCLK/8
01: XCLK/16
10: XCLK/32
11: XCLK/64
SPI Function Control Register 2
[4:0] SPI Bit Number (N)
N = 0~24: Bit Number = N
N > 24:
Bit Number = 24
SPI Mode Lock
0: Unlocked
1: Locked
BOUT[5] = SPI CLK
BOUT[4] = SPI DATA
BOUT[3] = SPI CS
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_SPI2_EN
0x13C[3]
RW
1
R_WP_EN
0x13C[6]
RW
1
7.2.2
SRGBOUT[8] = SPI CLK
SRGB_SDO = SPI DATA
SRGB_CS = SPI CS
EEPROM Write Protection Enable
0: Disable
1: Enable
Instruction Set
BIT1612 內建Script Control Function 提供下列的指令碼,相對應的Instruction Set與Instruction
Format,請參考 Table 7-4 及 Table 7-5。
Table 7-4 Instruction Set
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
1
0
R10
R9
R8
0
0
0
1
1
R10
R9
R8
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
Instruction
ADD
A_REG Í A_REG +B_REG
SUB
A_REG ÍA_REG – B_REG
INC
A_REG Í A_REG + 1
DEC
A_REG Í A_REG – 1
CLR
A_REG Í 0
COMP
A_REG – B_REG (Not Update A_REG)
MOV B,A
B_REG Í A_REG
HALT
Program Stop Into Standby Mode
AND
A_REG Í A_REG (AND) B_REG
OR
A_REG Í A_REG (OR) B_REG
XOR
A_REG Í A_REG (XOR) B_REG
NOT
A_REG Í ~A_REG
SHR
A_REG Í A_REG >> 1
SHL
A_REG Í A_REG << 1
SWAP
A_REG Ù B_REG
XCHG
A_REG[7:4] Ù A_REG[3:0]
MOV A, @R[ADDR]
A_REG Í R[ADDR]
MOV @R[ADDR], A
R[ADDR] Í A_REG
MOV A, #NUM
A_REG Í #NUM
MOV B, #NUM
B_REG Í #NUM
DELAY #NUM
Delay #NUM XCLK
NOTC
81
Command
C Z
Byte
1
● ●
1
● ●
1
● ●
1
● ●
1
●
1
● ●
1
1
1
●
1
●
1
●
1
●
1
●
1
●
1
●
●
2
●
2
2
●
2
2
1
●
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
0
0
1
0
1
E10
E9
E8
0
0
1
1
0
R10
R9
R8
0
0
1
1
1
R10
R9
R8
0
1
E10
E9
E8
R10
R9
R8
1
0
B2
B1
B0
E10
E9
E8
1
1
0
0
0
E10
E9
E8
1
1
0
0
1
E10
E9
E8
1
1
0
1
0
0
X
X
1
1
0
1
0
1
X
X
1
1
0
1
1
0
X
X
1
1
0
1
1
1
0
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
0
0
E10
E9
E8
1
1
1
0
1
E10
E9
E8
1
1
1
1
0
E10
E9
E8
1
1
1
1
1
E10
E9
E8
C_FLAG Í ~C_ FLAG
NOTZ
Z_ FLAG Í ~Z_ FLAG
RET
PC Í RET_ADDR
MOV E[ADDR], #NUM
E[ADDR] Í #NUM
MOV R[ADDR], #NUM
R[ADDR] Í #NUM
FILL R[ADDR], #NUM, CNT
Loop CNT [RADDR+CNT] Í #NUM
MOV R[ADDR], E[ADDR], CNT
Loop CNT
R[ADDR+CNT] Í E[ADDR+CNT]
JB EADDR, Bit
IF A.[Bit]=1 PC Í EADDR else PC+1
MOV E[ADDR], A
E[ADDR] Í A_REG
MOV A, E[ADDR]
A_REG Í E[ADDR]
MOV I[ADDR], A
I[ADDR] Í A_REG
MOV SPI, #NUM
SPI Í #NUM (3 Bytes)
MOV A, I[ADDR]
A_REG Í I[ADDR]
FILLR
LOOP R_REG_CNT
R[R_REG_ADDR+CNT] Í R_REG_NUM
TABLE
MOV A, E[R_REG_ADDR]
A_REG<=E[R_REG_ADDR]
RESERVED
(1617 MCALL)
JMPR
PC Í R_REG_ADDR
JC EADDR
IF C_REG=1 PCÍEADDR else PC+1
JZ EADDR
IF Z_REG=1 PCÍEADDR else PC+1
JMP EADDR
PC Í EADDR
CALL EADDR
RET_ADDR Í Next Command Address
PC Í EADDR
( 3 Layers of Address Stack)
82
1
●
1
3
3
4
4
2
2
2
●
2
4
2
●
1
1
2
1
2
2
2
2
●
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Table 7-5 Instruction Format
1 Byte–
OPCODE
|←
→|
1byte
Instruction: ADD; SUB; INC; DEC; CLR; COMP; MOV B A; HALT; AND; OR; XOR;
SHR; SHL; XCHG; SWAP; NOTC; NOTZ; RET; JMPR; FILLR; TABLE
NOT;
2 Bytes–
OPCODE
|←
1byte
A7 A6 A5 A4 A3 A2 A1 A0
→|←
Instruction: MOV A, @I[ADDR];
OPCODE
|←
A10 A9
1byte
→|
1byte
MOV @I[ADDR], A
A8 A7 A6 A5 A4 A3 A2 A1 A0
→|←
→|
1byte
Instruction: MOV A, @R[ADDR]; MOV @R[ADDR], A; MOV A, @E[ADDR];
JC EADDR; JZ EADDR; JMP EADDR; CALL EADDR
MOV @E[ADDR], A;
OPCODE B2 B1 B0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
|←
→|←
1byte
→|
1byte
Instruction: JB EADDR, Bit
|←
OPCODE
1byte
→|←
#NUMBER
1byte
→|
Instruction: MOV A, #NUM; MOV B, #NUM; DELAY #NUM
3 Bytes–
OPCODE
|←
A10 A9
1byte
A8 A7 A6 A5 A4 A3 A2 A1 A0
→|←
#NUMBER
→|←
1byte
1byte
→|
Instruction: MOV @E[ADDR], #NUM; MOV @R[ADDR], #NUM
4 Bytes–
OPCODE
|←
1byte
#NUMBER1
→|←
1byte
#NUMBER2
→|←
Instruction: MOV SPI, #NUM
83
1byte
#NUMBER3
→|←
1byte
→|
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
OPCODE
|←
A10 A9
1byte
A8 A7 A6 A5 A4 A3 A2 A1 A0
→|←
→|←
1byte
#NUMBER
1byte
COUNT VALUE
→|←
1byte
→|
Instruction: FILL @R[ADDR], #NUM, CNT
OPCODE
|←
E E E R R R E E E E E E E E R R R R R R R R
COUNT VALUE
10 9 8 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1byte
→|←
1byte
→|←
1byte
→|← 1byte
→|
Instruction: MOV @R[ADDR], @E[ADDR], CNT
7.2.3
Start and Interrupt
BIT1612 內建Script Control Function提供Interrupt Process機制,用以處理BIT1612 所產生的Interrupt
(0x002[7:0]),並且支援自動Re-ACK機制,以減少程式碼的複雜度。相關的程式起始位置請參考 Table 7-6
。
Table 7-6 Start and Interrupt
Event
POR (Power On Reset)
SIGIN (0x002[0])
NOSIG (0x002[1])
MODECHG (0x002[2])
VSYNC (0x002[3])
ERROR1 (0x002[4])
ERROR2 (0x002[5])
MV_CC (0x002[6])
IR_KEYIN (0x002[7])
7.2.4
Type
Immediate
Index
Index
Index
Index
Index
Index
Index
Index
Address
PC = 0x10
PC = 0x00, 0x01
PC = 0x02, 0x03
PC = 0x04, 0x05
PC = 0x06, 0x07
PC = 0x08, 0x09
PC = 0x0A, 0x0B
PC = 0x0C, 0x0D
PC = 0x0E, 0x0F
Serial EEPROM and ROM Space Mapping
BIT1612 在硬體上可支援 24C16 及 24C32 兩種Serial EEPROM的通訊協定,指令集支援最高 2K的
定址空間。使用小於 2KB程式記憶體時可以完全對映,但使用超過 2KB時,則需利用Bank Selection的方
式擴增定址空間,運用R_EEPROM_BANK_SEL可以支援到 64KB的ROM Size (24C512),如 Figure 7-5
所示。
84
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Figure 7-5 BIT1612 Script Controller Addressing Space
有些應用上希望使用超過 2KB的程式記憶體,除了使用 24C32 外,BIT1612 提供兩組TWSI的方式來
進行程式記憶體空間的擴充,如 Figure 7-4。無論使用單 24C32 或是雙 24C16 的方式,在做跨Bank的動
作時,一定要先設定R_EEPROM_BANK_SEL到正確的BANK。以 Figure 7-4 的情況為例:
……
MOV R_EEPROM_BANK_SEL, 001h
MOV R_REG_ADDR_L, 0A0h
MOV R_REG_ADDR_H, 003h
TABLE
MOV B, A
DEC
……
; ROM 1, BANK0
; A<= ROM2[0A0h], BANK1
; ROM1, BANK0
而在定址空間邊界上,則不能讓單一指令跨 BANK,如 MOV S, #NUM 為 4-Byte 的指令,則 MOV S,
#NUM 不能存放於 0x7FD、0x7FE、0x7FF,但可以存放在 0x7FC ~ 0x7FF。
0x7FC MOV S, NUM (OP Code)
0x7FD NUM 1
0x7FE NUM 2
0x7FF NUM 3
7.2.5
Serial EEPROM Write Protection and Power Monitor
BIT1612 新增Power Monitor 與Dynamic Write Protection功能,避免EEPROM在惡劣環境下產生非
預期的誤動作。Dynamic Write Protection功能可以參考 Figure 7-2,將BIT1612 的OP2 接至 24C16 的WP
Pin,並將R_WP_EN設為 1 即可。Power Monitor功能則是會監控電壓是否正常,若不正常將停止對Serial
EEPROM讀寫,並對Script MCU Reset,要使用此功能只要將R_PG_EN設為 1,經過電壓比較器輸出的
訊號接至BIT1612 的GIN7 即可。
7.2.6
Watch Dog Timer
BIT1612 有一 Watch Dog Timer (WDT),R_WDT_SEL 可以選擇 Timer 的 Interval,當超過此 Interval
85
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
沒有對 R_WDT_CLEAR 執行寫入 1、寫入 0 的動作,Script MCU 會自動 Reset,透過 R_WDT_OV 可以
得知本次 Reset 是起因於正常開機還是 WDT Overflow 所導致。
7.2.7
Second TWSI for Multi-Processor Communication
BIT1612 預留OP2 and OP3 為Multi-Processor Communication Port,其Protocol與TWSI相容,透過
設定R_TWSI_SEC可以開啟此功能,其示意圖如 Figure 7-3。其工作原理是在此BUS上的動作符合預設的
條件時,就會產生中斷,此時中斷服務程式就可以執行Multi-Processor Communication的程式。
設定 R_TWSI_DET_MODE 可以決定 TWSI 何種動作會觸動 Interrupt[3];R_TWSI_SEC_SLAVE[1:0]
決定 BIT1612 在 TWSI 上的 Device Address,R_TWSI_DET_IN[7:0]及 R_TWSI_DET_OUT[7:0]則是透過
此 BUS 讀寫的資料,R_TWSI_DET_VALUE 配合 R_TWSI_DET_MODE 可以在特定的 Register Address
下產生中斷。
7.2.8
TWSI Write/Read
BIT1612 可以運用 MOV @IADDR, A 和 MOV A, @IADDR 指令,與 R_TWSI_SLAVE 方便地存取位
於 { OP1, OP0 } 上的元件內部資料,與 Serial EEPROM 相同,透過最省成本的分時多工方式完成周邊控
制,要注意 TWSI 由於是分享給不同的 Device,所以不允許此 TWSI 上同時有第二個 Device Address 是
1010XXX 的元件出現。
7.2.9
SPI Interface
BIT1612 為了支援 SPI Interface 的 LCD Panel,附加了符合多種規格的 SPI Interface 的功能,透過
R_SPI_CTRL 及 MOV S, #NUM 指令可輕易地完成 LCD Panel 設定功能。SPI 信號可由 R_SPI1_EN 及
R_SPI2_EN 選擇由 BOUT Port 或是 SRGB_D Port 輸出。
7.2.10
Debug Mode
為了方便在韌體工程師設計 Master Mode 的程序,將 R_MCU_DEBUG 設為 1,切換 Master 與 Slave
時將不會 Reset,因此可以運用 Master 執行到一 HALT 點後,再切換至 Slave Mode 讀回 BIT1612 內部狀
態的技巧進行 Debug。若應用於 Slave Mode 則必須將 R_MCU_DEBUG 設為 0。
86
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
7.3 Slave Mode
BIT1612 提供 BiTEKbus 或 Two-Wire Serial Interface (TWSI) 兩種 Protocol 來存取 Register Sets,並由 OP4
Pin 來決定所選用的 Protocol。當 OP4 為 1,選用 BiTEKbus Protocol;當 OP4 為 0,則選用 TWSI Protocol。
7.3.1
BiTEKbus Protocol
BIT1612 可由外部 Pins (OP3 and OP2) 來決定 Slave Address,相關的 Slave Address 請參考下表。
Table 7-7 BiTEKbus Slave Address
OP3
0
0
1
1
OP2
0
1
0
1
Slave Address
Slave Address = 0x81
Slave Address = 0x83
Slave Address = 0x85
Slave Address = 0x87
Figure 7-6 Bitek Serial Interface Bus – Extension Mode
87
BIT1612
7.3.2
10-Bit Digital Video Decoder with OSD and T-CON
TWSI Protocol
BIT1612 Slave Address 也支援 Two-Wire Serial Interface (TWSI) Protocol,以便對 BIT1612 Register
Sets 做存取動作。
7.3.2.1 TWSI Protocol Device Address
BIT1612 TWSI Protocol 須在送出 Start Bit 之後送出 8 Bits Device Address (Slave Address),並
可由外部 PIN (OP3 and OP2)決定其 Device Address 的 Bit6 and Bit5 位址。相關設定請參考下表。
Table 7-8 TWSI Protocol Device Address
Internal Register Address
0x000~0x0FF
(Register Bank1)
0x100~0x17F
(Register Bank2)
0x200~0x2FF
(Gamma Table)
0x300~0x33F
(OSD Attribute RAM)
0x400~0x4FF
(OSD Display RAM)
0x500~0x5FF
(OSD Display RAM)
0x600~0x6FF
(OSD User Font RAM)
0x700~0x71F
(Buffer)
Write Device Address
0x00(PIN104 = 0、PIN105=0)
0x20(PIN104 = 0、PIN105=1)
0x40(PIN104 = 1、PIN105=0)
0x60(PIN104 = 1、PIN105=1)
0x02(PIN104 = 0、PIN105=0)
0x22(PIN104 = 0、PIN105=1)
0x42(PIN104 = 1、PIN105=0)
0x62(PIN104 = 1、PIN105=1)
0x04(PIN104 = 0、PIN105=0)
0x24(PIN104 = 0、PIN105=1)
0x44(PIN104 = 1、PIN105=0)
0x64(PIN104 = 1、PIN105=1)
0x06(PIN104 = 0、PIN105=0)
0x26(PIN104 = 0、PIN105=1)
0x46(PIN104 = 1、PIN105=0)
0x66(PIN104 = 1、PIN105=1)
0x08(PIN104 = 0、PIN105=0)
0x28(PIN104 = 0、PIN105=1)
0x48(PIN104 = 1、PIN105=0)
0x68(PIN104 = 1、PIN105=1)
0x0A(PIN104 = 0、PIN105=0)
0x2A(PIN104 = 0、PIN105=1)
0x4A(PIN104 = 1、PIN105=0)
0x6A(PIN104 = 1、PIN105=1)
0x0C(PIN104 = 0、PIN105=0)
0x2C(PIN104 = 0、PIN105=1)
0x4C(PIN104 = 1、PIN105=0)
0x6C(PIN104 = 1、PIN105=1)
0x0E(PIN104 = 0、PIN105=0)
0x2E(PIN104 = 0、PIN105=1)
0x4E(PIN104 = 1、PIN105=0)
0x6E(PIN104 = 1、PIN105=1)
88
Read Device Address
0x01(PIN104 = 0、PIN105=0)
0x21(PIN104 = 0、PIN105=1)
0x41(PIN104 = 1、PIN105=0)
0x61(PIN104 = 1、PIN105=1)
0x03(PIN104 = 0、PIN105=0)
0x23(PIN104 = 0、PIN105=1)
0x43(PIN104 = 1、PIN105=0)
0x63(PIN104 = 1、PIN105=1)
0x05(PIN104 = 0、PIN105=0)
0x25(PIN104 = 0、PIN105=1)
0x45(PIN104 = 1、PIN105=0)
0x65(PIN104 = 1、PIN105=1)
0x07(PIN104 = 0、PIN105=0)
0x27(PIN104 = 0、PIN105=1)
0x47(PIN104 = 1、PIN105=0)
0x67(PIN104 = 1、PIN105=1)
0x09(PIN104 = 0、PIN105=0)
0x29(PIN104 = 0、PIN105=1)
0x49(PIN104 = 1、PIN105=0)
0x69(PIN104 = 1、PIN105=1)
0x0B(PIN104 = 0、PIN105=0)
0x2B(PIN104 = 0、PIN105=1)
0x4B(PIN104 = 1、PIN105=0)
0x6B(PIN104 = 1、PIN105=1)
0x0D(PIN104 = 0、PIN105=0)
0x2D(PIN104 = 0、PIN105=1)
0x4D(PIN104 = 1、PIN105=0)
0x6D(PIN104 = 1、PIN105=1)
0x0F(PIN104 = 0、PIN105=0)
0x2F(PIN104 = 0、PIN105=1)
0x4F(PIN104 = 1、PIN105=0)
0x6F(PIN104 = 1、PIN105=1)
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
TWSI
Slave Address
0x00
0x0F
0x00~0x0F
OP3=0
OP2=0
0x20~0x2F
OP3=0
OP2=1
0x40~0x4F
OP3=1
OP2=0
0x60~0x6F
OP3=1
OP2=1
0x20
0x2F
0x40
0x4F
0x60
0x6F
0xFF
Figure 7-7 TWSI Slave Mapping Address
89
BIT1612
From Pin 105 Setting
From Pin 104 Setting
10-Bit Digital Video Decoder with OSD and T-CON
Figure 7-8 TWSI Read/Write Mode
90
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
8 Timing Diagram
8.1 Hardware Reset
8.2 Clock and Interrupt
…
XCLK
Interrupt condition occur
INT
MCU read Reg[0x002] from BIT1612
Write Reg[0x004] by MCU
8.3 Input Signal
TI0S
PCLK
TI0H
IHS
IVS
TI1S
PCLK
TI1H
RDIN7~0
GDIN7~0
91
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Symbol
TI0S, TI1S
TI0H, TI1H
Describe
Input Setup time
Input Hold time
Max.
Min.
2
2
Unit
Ns
Ns
8.4 Output Signal
TOCK
TO_MAX_DL
OCLK
TO_MIN_DL
Data Output
Symbol
TOCK
TO_MAX_DL
TO_MIN_DL
Valid
Describe
Output clock half period
Output signal Max delay
Output signal Min delay
92
Timing
TOCK - 1
TOCK - 4
Unit
ns
ns
ns
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
9 Electrical Characteristic
9.1 Absolute Maximum Rating
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
AVDD
Supply Voltage for Analog Core
-0.5
3.6
V
VDD18
Supply Voltage for Digital Core
- 0.5
2.5
V
- 0.5
6
V
- 40
125
℃
Input Voltage for Digital Core (5V
VIN
Tolerant)
TSTG
Storage Temperature
9.2 Recommend Operating Condition
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
AVDD
Supply Voltage for Analog Core
3.0
3.3
3.6
V
VDD18
Supply Voltage for Digital Core
1.62
1.8
1.98
V
VDD33
Supply Voltage for I/O Pad
3.0
3.3
3.6
V
70
℃
TOPR
Operating Temperature
0
9.3 DC Electrical Characters
(under Recommend Operating Condition and TJ =0℃ to 115℃)
SYMBOL
PARAMETER
IIL
Input Leakage Current
IOZ
Tri-state Leakage Current
VIL
Input Low Voltage
CONDITION
MIN
TYP
No pull-up nor
pull-down
MAX
UNIT
10
uA
10
uA
CMOS
-0.3
0.8
V
2.0
5.5
V
0.4
V
VIH
Input High Voltage
CMOS
VOL
Output Low Voltage
IOL= 4,8,16 mA
VOH
Output High Voltage
IOH= 4,8, 16 mA
2.4
CMOS
0.89
0.94
0.99
V
CMOS
1.44
1.50
1.56
V
VtVt+
Schmitt trigger negative
going threshold voltage
Schmitt trigger positive going
threshold voltage
V
Rpu
Pull-up Resistance
39
65
116
KΩ
Rpd
Pull-down Resistance
40
56
108
KΩ
Note: The capacitance listed above does not include pad capacitance and package capacitance.
One can estimate pin capacitance by adding pad capacitance about 0.5pF and the package
capacitance.
93
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
10 Soldering Information
10.1 Reflow Soldering
The choice of heating method may be influenced by plastic QFP package). If infrared or vapor phase
heating is used and the package is not absolutely dry (less than 0.1% moisture content by weight),
vaporization of the small amount of moisture in them can cause cracking of the plastic body. Preheating is
necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be
applied to the printed-circuit board by screen printing, stenciling or pressure-syringe dispensing before
package placement. Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100
and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder paste material. The
top-surface temperature of the packages should preferable be kept below 245 °C for thick/large packages
(packages with a thickness ≧ 2.5 mm or with a volume ≧ 350 mm3 so called thick/large packages). The
top-surface temperature of the packages should preferable be kept below 260 °C for thin/small packages
(packages with a thickness < 2.5 mm and a volume < 350 mm3 so called thin/small packages).
Stage
1’st Ram Up Rate
Preheat
2’nd Ram Up
Solder Joint
Peak Temp
Ram Down rate
Condition
max3.0+/-2℃/sec
150℃~200℃
max3.0+/-2℃/sec
217℃ above
260 +0/-5℃
6℃/sec max
Duration
60~180 sec
60~150 sec
20~40 sec
-
Temp (℃)
260
217
200
150
25
RT
60~180
60~150
Time (sec)
10.2 Wave Soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or
printed-circuit boards with a high component density, as solder bridging and non-wetting can present major
problems.
10.3 Manual Soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less)
soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
94
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
11 Package Information
95
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
Index
R_6BITS_EN .............................................................17
R_ANZOOM_EN........................................................33
R_AAGC1_EN ...........................................................50
R_ANZOOM_TYPE ...................................................33
R_AAGC1_HOLD ......................................................51
R_APER_SEL............................................................46
R_AAGC1_OUT ........................................................56
R_AUFD ..............................................................55, 56
R_AAGC1_VALUE .............................................. 50, 51
R_AUTO_KILL ...........................................................47
R_AAGC2_EN ...........................................................51
R_AUTO_SWITCH ....................................................31
R_AAGC2_HOLD ......................................................51
R_AUTO1_HOLD ......................................................51
R_AAGC2_OUT ........................................................56
R_AUTO2_HOLD ......................................................52
R_AAGC2_VALUE ....................................................51
R_AUTOON ...............................................................74
R_ACLAMP_SPEED .................................................50
R_AUTOON_EN ........................................................24
R_ACLAMP1_EN ......................................................51
R_AUTOON_TIME ....................................................24
R_ACLAMP1_LEVEL .......................................... 50, 51
R_BACKGROUND_EN..............................................23
R_ACLAMP1_TYPE ..................................................51
R_BANK_SEL......................................................63, 68
R_ACLAMP2_EN ......................................................52
R_BG2_B...................................................................23
R_ACLAMP2_LEVEL .......................................... 50, 52
R_BG2_G ..................................................................23
R_ACLAMP2_TYPE ..................................................52
R_BG2_R ..................................................................23
R_AFE_BYP ..............................................................53
R_BGPU_POINT_N...................................................44
R_AFE_CS ................................................................53
R_BGPU_POINT_P...................................................44
R_AFE_CTRIB ..........................................................53
R_BIN_REN...............................................................12
R_AFE_CTRPH.........................................................53
R_BLACK_SLOPE.....................................................37
R_AFE_DEC .............................................................53
R_BLACK_START.....................................................37
R_AFE_ENAC ...........................................................53
R_BLACKLEVEL_VD ................................................42
R_AFE_ENAY ...........................................................53
R_BOUT_TRI.............................................................12
R_AFE_ENIB.............................................................53
R_BPASS_SEL..........................................................46
R_AFE_ENREF .........................................................53
R_BRIGHTNESS .......................................................37
R_AFE_ENVBG.........................................................53
R_BRIGHTNESS_B...................................................36
R_AFE_ENVCM ........................................................53
R_BRIGHTNESS_G ..................................................36
R_AFE_SEL ..............................................................54
R_BRIGHTNESS_R ..................................................36
R_AFE_SH2VCM ......................................................53
R_BRIGHTNESS_VD ................................................42
R_AFEBUF_POL.......................................................15
R_BUS_INV ...............................................................21
R_AFEBUF_SEL .......................................................15
R_CC_DATA_SEL.....................................................45
R_AFECLK_EN .........................................................15
R_CC_DATA1......................................................45, 57
R_AFECLK_POL .......................................................15
R_CC_DATA2......................................................45, 57
R_AFECLK_SEL .......................................................15
R_CC_ERROR ..........................................................57
R_ANC_SEL..............................................................54
R_CC_INT .................................................................57
R_ANY_SEL ..............................................................54
R_CCIR_EN...............................................................47
96
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_CDV_SEL..............................................................47
R_CPH1_POL............................................................22
R_CH11_THD............................................................45
R_CPH1E_CKSEL.....................................................22
R_CH12_THD............................................................45
R_CPH1O_CKSEL ....................................................22
R_CH2_THD..............................................................45
R_CPH2_EN..............................................................22
R_CHROMA_GAIN ...................................................47
R_CPH2_POL............................................................22
R_CHROMA_GAIN_SEL...........................................47
R_CPH2E_CKSEL.....................................................22
R_CHROMA_GAINOUT............................................56
R_CPH2O_CKSEL ....................................................22
R_CHROMA_HUE_VD..............................................43
R_CPH3_EN..............................................................22
R_CHROMA_LPPI1 ..................................................47
R_CPH3_POL............................................................22
R_CHROMA_LPPI2 ..................................................47
R_CPH3E_CKSEL.....................................................22
R_CHROMA_PHASE ................................................48
R_CPH3O_CKSEL ....................................................22
R_CHT_EN................................................................46
R_CREFY_EN ...........................................................49
R_CHT_SEL ..............................................................46
R_CTI_EN .................................................................38
R_CKV_END .............................................................20
R_CTI_EN_VD...........................................................43
R_CKV_START .........................................................20
R_CTI_THD ...............................................................38
R_CLAMP_EN...........................................................39
R_CTI_THD_VD ........................................................43
R_CLK27_EN ............................................................15
R_CTI_U_SEL ...........................................................38
R_CLK27_POL ..........................................................15
R_CTI_USEL_VD ......................................................43
R_COLOR_STANDARD............................................56
R_CTI_V_SEL ...........................................................38
R_COLORDET ..........................................................56
R_CTI_VSEL_VD ......................................................43
R_COMB_CTHD .......................................................48
R_CUT_AUTO_M0 ....................................................34
R_COMB_EN ............................................................48
R_CUT_AUTO_M1 ....................................................35
R_COMB_YTHD12....................................................48
R_CUT_MODE_M0 ...................................................34
R_COMB_YTHD3......................................................48
R_CUT_MODE_M1 ...................................................35
R_CONTRAST ..........................................................37
R_DAC_B ..................................................................39
R_CONTRAST_B ......................................................36
R_DAC_C ..................................................................39
R_CONTRAST_G......................................................36
R_DAC_CEN .............................................................39
R_CONTRAST_R......................................................36
R_DAC_CTYPE.........................................................39
R_CONTRAST_TYPE ...............................................36
R_DACCLK_EN.........................................................15
R_CONTRAST_VD ...................................................42
R_DACCLK_POL.......................................................15
R_COR_SEL .............................................................46
R_DACMAP_EN ........................................................39
R_CP180_AUTO .......................................................49
R_DAGC1_EN ...........................................................51
R_CP180_SEL ..........................................................49
R_DAGC1_HOLD ......................................................51
R_CP90_AUTO .........................................................49
R_DAGC1_OUT ........................................................56
R_CP90_SEL ............................................................49
R_DAGC1_READY....................................................57
R_CP90TAB_SEL .....................................................49
R_DAGC1_SPEED....................................................51
R_CPH_HALF ...........................................................22
R_DAGC1_THD.........................................................51
R_CPH1_EN .............................................................22
R_DAGC1_VALUE ....................................................51
97
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_DAGC1_VSUP ......................................................51
R_DITHER_ODD .......................................................38
R_DAGC2_EN...........................................................52
R_DLYE_OB..............................................................17
R_DAGC2_HOLD......................................................52
R_DLYE_OCLK_M0 ..................................................35
R_DAGC2_OUT ........................................................56
R_DLYE_OCLK_M1 ..................................................35
R_DAGC2_READY ...................................................57
R_DLYE_OG .............................................................17
R_DAGC2_SPEED....................................................52
R_DLYE_OR..............................................................17
R_DAGC2_THD ........................................................52
R_DLYO_OB .............................................................17
R_DAGC2_VALUE ....................................................52
R_DLYO_OCLK_M0..................................................35
R_DAGC2_VSUP ......................................................51
R_DLYO_OCLK_M1..................................................35
R_DATA_SLICER_EN_E ..........................................45
R_DLYO_OG .............................................................17
R_DATA_SLICER_EN_O..........................................45
R_DLYO_OR .............................................................17
R_DATA_SLICER_LINE_E .......................................45
R_DVPCLK_EN .........................................................15
R_DATA_SLICER_LINE_O .......................................45
R_DVPCLK_POL.......................................................15
R_DATA_SLICER_START ........................................45
R_DVPCLK_SEL .......................................................15
R_DATA_SLICER_THD ............................................45
R_EEPROM_BANK_SEL ..............................79, 84, 85
R_DCLAMP1_EN ......................................................51
R_ERROR_TYPE ........................................................9
R_DCLAMP1_HOLD .................................................51
R_EVEN ....................................................................74
R_DCLAMP1_LEVEL ................................................51
R_EVENSAME ..........................................................74
R_DCLAMP1_OUT....................................................56
R_EXT_SYNC ...........................................................29
R_DCLAMP1_VALUE ...............................................51
R_EXTOSD_EN.........................................................68
R_DCLAMP2_EN ......................................................52
R_FIDT_O .................................................................56
R_DCLAMP2_HOLD .................................................52
R_FIDT_THD .............................................................44
R_DCLAMP2_LEVEL ................................................52
R_FREERUN_EN ......................................................23
R_DCLAMP2_OUT....................................................56
R_FSEL .....................................................................55
R_DCLAMP2_VALUE ...............................................52
R_GAIN_CTL_VALUE ...............................................47
R_DET_XN ................................................................74
R_GAIN_CTRL_SPEED ............................................47
R_DET_XP ................................................................74
R_GAMMA_EN..........................................................38
R_DIFFGAIN1_THD ..................................................51
R_GAMMA_SEL ........................................................38
R_DIFFGAIN2_THD ..................................................52
R_GIN_REN ..............................................................12
R_DIS_XS .................................................................31
R_GIN1_REN ............................................................12
R_DIS_XW ................................................................31
R_GOUT_TRI ............................................................12
R_DIS_XW1 ..............................................................31
R_GPO_OUT.............................................................13
R_DIS_XW2 ..............................................................31
R_GPO_REG.............................................................13
R_DIS_YS .................................................................31
R_GPO_SEL..............................................................13
R_DIS_YW ................................................................31
R_GPO_TYPE ...........................................................13
R_DITHER_EN..........................................................38
R_HCOUNT ...............................................................35
R_DITHER_EVEN .....................................................38
R_HLCK_O ................................................................56
R_DITHER_MASK.....................................................38
R_HLCK_SEL ............................................................24
98
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_HOUNT .................................................................74
R_IS_XS_M0 .............................................................25
R_HW_VER.................................................................8
R_IS_XS_M1 .............................................................25
R_IDE_DET ...............................................................74
R_IS_XT ....................................................................74
R_IDE_INFO..............................................................74
R_IS_XW_M0 ............................................................25
R_IDE_SEL ...............................................................74
R_IS_XW_M1 ............................................................25
R_IHS_SEL ...............................................................29
R_IS_YP ....................................................................74
R_IHSPS_SEL.............................................................9
R_IS_YS_M0 .............................................................25
R_IMODE ............................................................ 29, 30
R_IS_YS_M1 .............................................................25
R_INCCHRO_O.........................................................57
R_IS_YT ....................................................................74
R_INT_ACK .................................................................9
R_IS_YW_M0 ............................................................25
R_INT_ERRSEL ..........................................................9
R_IS_YW_M1 ............................................................25
R_INT_FLAG ...............................................................9
R_ISWAP_GB............................................................26
R_INT_MASK ..............................................................9
R_ISWAP_RB............................................................26
R_INT_TYPE ...............................................................9
R_ISWAP_RG ...........................................................26
R_INT_VSSE...............................................................9
R_IVS_SEL................................................................29
R_INTAGC1_EN........................................................10
R_KEY_ACK..............................................................72
R_INTAGC2_EN........................................................10
R_KEY_CLEAR .........................................................72
R_INTCC_EN ............................................................10
R_KEY_DB ................................................................72
R_INTHLCK_EN..........................................................9
R_KEY_DEDGE ........................................................72
R_INTMODECHG_SEL...........................................8, 9
R_KEY_LONG_ACK..................................................72
R_INTMV_EN ............................................................10
R_KEY_LONG_EN ....................................................72
R_INTSIGIN_SEL....................................................8, 9
R_KEY_LONG_FLAG................................................72
R_INTSRC11_EN......................................................10
R_KEY_LONG_REP..................................................72
R_INTSRC12_EN......................................................10
R_KEY_LONG_STR..................................................72
R_INTSRC2_EN........................................................10
R_KEY_SRC..............................................................72
R_INTSTDRDY_EN...................................................10
R_KEY_SRC_64........................................................72
R_INTSYNCRDY_EN................................................10
R_KEY_STATUS .......................................................72
R_INTVS_POL ........................................................8, 9
R_KEY_TB ................................................................72
R_IR_BASE ...............................................................71
R_KEY_TYPE............................................................72
R_IR_CC ...................................................................71
R_KILL_COLOR ........................................................37
R_IR_CHECK ............................................................71
R_KILL_COLOR_VD .................................................43
R_IR_CODE ..............................................................71
R_LCLK_4X ...............................................................15
R_IR_DB ...................................................................71
R_LCLK_EN ..............................................................14
R_IR_DISREPT .........................................................71
R_LCLK_POL ............................................................14
R_IR_EN ...................................................................71
R_LCLK_SEL.............................................................14
R_IR_REN .................................................................12
R_LD_END ................................................................20
R_IR_TYPE ...............................................................71
R_LD_START ............................................................20
R_IS_XP ....................................................................74
R_LINE_CUT_M0 ......................................................34
99
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_LINE_CUT_M1......................................................35
R_OS_YT ............................................................16, 19
R_LINE_THD1...........................................................48
R_OS_YW .................................................................16
R_LINE_THD2...........................................................48
R_OSD_LAYER .........................................................67
R_LINEBUF_CKEN ...................................................15
R_OSDCLK_EN.........................................................69
R_LN1CLK_POL .......................................................16
R_OSDCLK_POL ......................................................69
R_LN2CLK_POL .......................................................16
R_OUT_DACMAP_LB ...............................................39
R_LN3CLK_POL .......................................................16
R_OUT_DACMAP_SPACE .......................................39
R_LN4CLK_POL .......................................................15
R_OUT_SEL ..............................................................48
R_LN5CLK_POL .......................................................15
R_PAL_SENSITIVE...................................................47
R_LOAD_EN ............................................................. 11
R_PCLK_BASE .........................................................30
R_LOAD_TYPE ......................................................... 11
R_PCLK_EN ..............................................................14
R_LOWER_BOUND ..................................................47
R_PCLK_POL............................................................14
R_LTPS_MODE ........................................................21
R_PCLK_SEL ............................................................14
R_MASTER_DLY_M0 ...............................................35
R_PG_EN ............................................................79, 85
R_MASTER_DLY_M1 ...............................................35
R_PG_POL ................................................................79
R_MCLK_EN .............................................................14
R_PLL_DM_M0 .........................................................73
R_MCLK_POL ...........................................................14
R_PLL_DM_M1 .........................................................73
R_MCLK_SEL ...........................................................14
R_PLL_DN_M0..........................................................73
R_MCU_DEBUG ................................................. 80, 86
R_PLL_DN_M1..........................................................73
R_MODE_TYPE ........................................................74
R_PLL_DP_M0 ..........................................................73
R_MODECHG ...........................................................74
R_PLL_DP_M1 ..........................................................73
R_MV_DET_CHROMA..............................................57
R_PLL_EAPLL...........................................................53
R_MV_DET_SYNC....................................................57
R_PLL_HALFCK........................................................73
R_MV_TYPE_CHROMA ...........................................57
R_PLL_ICP0 ..............................................................53
R_N44360_AUTOSW................................................48
R_PLL_ICP1 ..............................................................53
R_NOCOR_AUTOSW ...............................................48
R_PLL_PD .................................................................72
R_NOSIG_SEL..........................................................24
R_PLL_POR ..............................................................53
R_OCLK_TRI.............................................................12
R_PLL_RESETN .......................................................72
R_OEH_END.............................................................20
R_PLL_SEL ...............................................................73
R_OEH_GATE...........................................................20
R_PLLDTO_ROL .......................................................53
R_OEH_START.........................................................20
R_POF.......................................................................80
R_OS_XP ..................................................................16
R_POL_BIN ...............................................................25
R_OS_XS ..................................................................16
R_POL_BOUT ...........................................................17
R_OS_XT_M0 ...........................................................16
R_POL_CKV..............................................................20
R_OS_XT_M1 ...........................................................16
R_POL_EXTBNK.......................................................68
R_OS_XW .................................................................16
R_POL_FRP ..............................................................20
R_OS_YP ..................................................................16
R_POL_GIN...............................................................25
R_OS_YS ..................................................................16
R_POL_GOUT...........................................................17
100
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_POL_IHS ...............................................................29
R_PWM2_POL ..........................................................40
R_POL_INT .................................................................9
R_PWM2_REF ..........................................................40
R_POL_IR .................................................................71
R_PWM2_SYNC........................................................40
R_POL_IVS ...............................................................29
R_PWM2_TRI............................................................12
R_POL_LD ................................................................20
R_PWM3_DUTY........................................................40
R_POL_OCLK ...........................................................17
R_PWM3_EN.............................................................40
R_POL_OEH .............................................................20
R_PWM3_FREQ........................................................40
R_POL_OSDCLK ......................................................68
R_PWM3_POL ..........................................................40
R_POL_OSDHS ........................................................68
R_PWM3_REF ..........................................................40
R_POL_OSDVS ........................................................68
R_PWM3_SYNC........................................................40
R_POL_Q2H .............................................................20
R_REG_ADDR ..............................................79, 82, 85
R_POL_RIN...............................................................25
R_REG_CNT .......................................................79, 82
R_POL_ROUT...........................................................17
R_REG_NUM ......................................................79, 82
R_POL_STH..............................................................20
R_REGS_CKEN ........................................................15
R_POL_STV ..............................................................20
R_RIN_REN...............................................................12
R_PRDIS_ACTX........................................................31
R_ROL_BIN ...............................................................26
R_PRE_FIX2_EN ......................................................32
R_ROL_BOUT ...........................................................17
R_PREF_EN .............................................................46
R_ROL_GIN...............................................................26
R_PRESCX_EN ........................................................32
R_ROL_GOUT...........................................................17
R_PRESCX_FILTER .................................................32
R_ROL_RIN...............................................................26
R_PRESCX_FILTER_EN ..........................................32
R_ROL_ROUT...........................................................17
R_PRESCX_FIX........................................................32
R_ROUT_TRI ............................................................12
R_PRESCX_OVER ...................................................32
R_RTS1_SEL ............................................................18
R_PRESCX_SHIFT ...................................................32
R_RTS2_SEL ............................................................18
R_PRESCX_START..................................................32
R_RTS3_SEL ............................................................18
R_PROTECT_MODE ................................................19
R_SAT_MODE...........................................................37
R_PWM_OUT............................................................40
R_SAT_MODE_VD....................................................43
R_PWM1_DUTY........................................................40
R_SAT_U .............................................................37, 43
R_PWM1_EN ............................................................40
R_SAT_U_VD............................................................43
R_PWM1_FREQ .......................................................40
R_SAT_V .............................................................37, 43
R_PWM1_INV ...........................................................40
R_SAT_V_VD ............................................................43
R_PWM1_POL ..........................................................40
R_SCX_EN ................................................................33
R_PWM1_REF ..........................................................40
R_SCX_FILTER.........................................................33
R_PWM1_SYNC .......................................................40
R_SCX_START .........................................................33
R_PWM1_TRI............................................................12
R_SCX1_FIX .............................................................33
R_PWM2_DUTY........................................................40
R_SCX1_INC.............................................................33
R_PWM2_EN ............................................................40
R_SCX1_SHIFT.........................................................33
R_PWM2_FREQ .......................................................40
R_SCX2_DEC ...........................................................33
101
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_SCX2_FIX .............................................................33
R_SQP_COUNT ........................................................57
R_SCX2_SHIFT ........................................................33
R_SQP_LMT..............................................................47
R_SCY_EN_M0.........................................................34
R_SQP_LPPI .............................................................48
R_SCY_EN_M1.........................................................34
R_SQP_SPUP ...........................................................48
R_SCY_FILTER_EN_M0 ..........................................34
R_SRC_SEL ..............................................................29
R_SCY_FILTER_EN_M1 ..........................................35
R_SRC11.............................................................45, 57
R_SCY_FILTER_M0 .................................................34
R_SRC12.............................................................45, 57
R_SCY_FILTER_M1 .................................................35
R_SRC2...............................................................45, 57
R_SCY_FIX_M0 ........................................................34
R_SRCDET_MODE...................................................45
R_SCY_FIX_M1 ........................................................34
R_SRGB_4X..............................................................58
R_SCY_SHIFT_M0 ...................................................34
R_SRGB_EN .............................................................58
R_SCY_SHIFT_M1 ...................................................34
R_SRGB_L_DLY .......................................................58
R_SCYE_START_M0................................................34
R_SRGB_T_DLY .......................................................58
R_SCYE_START_M1................................................34
R_SRGB_TRI ............................................................12
R_SCYO_START_M0 ...............................................34
R_STD_AUTO ...........................................................56
R_SCYO_START_M1 ...............................................34
R_STD_COUNT ........................................................48
R_SECAM_INVERT ..................................................47
R_STD_FREQ ...........................................................57
R_SECAM_SENSITIVE.............................................47
R_STD_MOD.............................................................56
R_SECOND_EEPROM .............................................79
R_STD_OFF00 ..........................................................48
R_SECS_AUTOSW...................................................48
R_STD_OFF01 ..........................................................48
R_SEL_EVEN............................................................29
R_STD_OFF10 ..........................................................48
R_SERIAL_CKEN_SEL.............................................79
R_STD_PHASE .........................................................57
R_SERIAL_DLY ........................................................58
R_STD_READY_O ....................................................56
R_SIGIN ....................................................................74
R_STD_SEL0 ............................................................56
R_SLICER_THD........................................................44
R_STD_SEL1 ............................................................56
R_SORT_656 ............................................................29
R_STH_END..............................................................20
R_SPI_CTRL .............................................................80
R_STH_SEL ..............................................................20
R_SPI_CTRL2 ...........................................................80
R_STH_START .........................................................20
R_SPI_LOCK.............................................................80
R_STV_END..............................................................20
R_SPI1_EN ......................................................... 80, 86
R_STV_SEL...............................................................20
R_SPI1690_ADDR ....................................................59
R_STV_SHIFT_CUT..................................................21
R_SPI1690_CHECKER.............................................59
R_STV_SHIFT_E.......................................................21
R_SPI1690_DATA.....................................................58
R_STV_SHIFT_O ......................................................21
R_SPI1690_DESYNC ...............................................59
R_STV_SHIFT_SRC .................................................21
R_SPI1690_EN .........................................................58
R_STV_SHIFT_TYPE................................................21
R_SPI1690_LSB........................................................58
R_STV_START..........................................................20
R_SPI1690_RW ........................................................58
R_SW_VER .................................................................8
R_SPI2_EN ......................................................... 81, 86
R_SWAP_SRC ..........................................................17
102
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_SWAP_UV.............................................................29
R_TESTPAT_TYPE...................................................23
R_SWAPE_OGB .......................................................17
R_THRESHOLD_QAM ..............................................47
R_SWAPE_ORB .......................................................17
R_THRESHOLD_SECAM .........................................47
R_SWAPE_ORG .......................................................17
R_TIMER0_BASE_MODE .........................................70
R_SWAPO_OGB.......................................................17
R_TIMER0_EN ..........................................................70
R_SWAPO_ORB .......................................................17
R_TIMER0_MODE ....................................................70
R_SWAPO_ORG.......................................................17
R_TIMER0_VAL.........................................................70
R_SWITCH................................................................74
R_TIMER1_BASE_MODE .........................................70
R_SWITCH_MODE ...................................................31
R_TIMER1_EN ..........................................................70
R_SXCR ....................................................................47
R_TIMER1_MODE ....................................................70
R_SYNC_HCE...........................................................44
R_TIMER1_VAL ........................................................70
R_SYNC_HCS...........................................................44
R_TOUT_REN ...........................................................12
R_SYNC_HPLL .........................................................44
R_TOUT_TRI.............................................................12
R_SYNC_HSS...........................................................44
R_TWSI_DET_IN.................................................80, 86
R_SYNC_HSYE ........................................................44
R_TWSI_DET_MODE .........................................80, 86
R_SYNC_HSYS ........................................................44
R_TWSI_DET_OUT.............................................80, 86
R_SYNC_IDEL ..........................................................44
R_TWSI_DET_VALUE ........................................80, 86
R_SYNC_LPADJ .......................................................44
R_TWSI_SEC ......................................................80, 86
R_SYNC_LPLMT.......................................................44
R_TWSI_SEC_SLAVE ........................................80, 86
R_SYNC_PDGAIN ....................................................44
R_TWSI_SLAVE............................................79, 80, 86
R_SYNC_READY_O .................................................56
R_UDLY_VD ..............................................................43
R_SYNC_REN...........................................................12
R_UGAIN_VD ............................................................43
R_SYNC1_CLAMP....................................................51
R_UNSHARP_EN......................................................37
R_SYNC2_CLAMP....................................................52
R_UNSHARP_EN_VD...............................................42
R_SYNCO_EN ..........................................................19
R_UNSHARP_THD ...................................................37
R_SYNCO_MODE.....................................................19
R_UNSHARP_THD_VD ............................................42
R_TCLK_EN ..............................................................14
R_UNSHARP_VAL ....................................................37
R_TCLK_POL............................................................14
R_UNSHARP_VAL_VD .............................................42
R_TCLK_SEL ............................................................14
R_UPDN_SEL_M0 ....................................................34
R_TCON_EN .............................................................20
R_UPDN_SEL_M1 ....................................................34
R_TCON_RL .............................................................20
R_UPPER_BOUND ...................................................47
R_TCON_UD.............................................................20
R_VCOM_SEL...........................................................21
R_TESTPAT_B..........................................................23
R_VCOM_SHIFT .......................................................20
R_TESTPAT_DIR......................................................23
R_VCOM_TYPE ........................................................21
R_TESTPAT_G .........................................................23
R_VD_PATH..............................................................26
R_TESTPAT_HV .......................................................23
R_VDCLK_SEL..........................................................15
R_TESTPAT_Q .........................................................23
R_VDLY_VD ..............................................................43
R_TESTPAT_R .........................................................23
R_VGAIN_VD ............................................................43
103
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_VISUAL_TYPE ......................................................29
R_W1_FFRI_COR .....................................................65
R_VNOISE_MODE....................................................44
R_W1_FFRI_H ..........................................................64
R_VP_ERR2_EN.........................................................9
R_W1_FFRI_SEL ......................................................64
R_VTRC ....................................................................44
R_W1_FFRI_V...........................................................65
R_W0_CYCLE...........................................................64
R_W1_FMIRX............................................................64
R_W0_EN..................................................................64
R_W1_FMIRY............................................................64
R_W0_FADE .............................................................63
R_W1_H ....................................................................59
R_W0_FFRI_COR.....................................................64
R_W1_INDEX_E........................................................64
R_W0_FFRI_H ..........................................................64
R_W1_INDEX_S........................................................64
R_W0_FFRI_SEL ......................................................64
R_W1_MULX .............................................................65
R_W0_FFRI_V ..........................................................64
R_W1_MULY .............................................................65
R_W0_FMIRX............................................................64
R_W1_SPCY .............................................................65
R_W0_FMIRY............................................................64
R_W1_VANISH_DIR .................................................65
R_W0_H ....................................................................59
R_W1_VANISH_LN ...................................................65
R_W0_INDEX_E .......................................................63
R_W1_W ...................................................................59
R_W0_INDEX_S .......................................................63
R_W1_WDLY.............................................................65
R_W0_MULX.............................................................64
R_W1_WFRI_B .........................................................65
R_W0_MULY.............................................................64
R_W1_WFRI_BLEN ..................................................65
R_W0_SPCY .............................................................64
R_W1_WFRI_EN.......................................................65
R_W0_VANISH_DIR .................................................64
R_W1_WFRI_FADE ..................................................65
R_W0_VANISH_LN...................................................64
R_W1_WFRI_G .........................................................65
R_W0_W ...................................................................59
R_W1_WFRI_H .........................................................65
R_W0_WDLY.............................................................64
R_W1_WFRI_R .........................................................65
R_W0_WFRI_B .........................................................64
R_W1_WFRI_V .........................................................65
R_W0_WFRI_BLEN ..................................................64
R_W1_WMIRX...........................................................64
R_W0_WFRI_EN.......................................................64
R_W1_WMIRY...........................................................64
R_W0_WFRI_FADE ..................................................64
R_W1_X ....................................................................59
R_W0_WFRI_G.........................................................64
R_W1_Y ....................................................................59
R_W0_WFRI_H .........................................................64
R_W2_CYCLE ...........................................................66
R_W0_WFRI_R .........................................................64
R_W2_EN ..................................................................66
R_W0_WFRI_V .........................................................64
R_W2_FADE .............................................................65
R_W0_WMIRX ..........................................................63
R_W2_FFRI_COR .....................................................65
R_W0_WMIRY ..........................................................64
R_W2_FFRI_H ..........................................................65
R_W0_X ....................................................................59
R_W2_FFRI_SEL ......................................................65
R_W0_Y ....................................................................59
R_W2_FFRI_V...........................................................65
R_W1_CYCLE...........................................................65
R_W2_FMIRX............................................................65
R_W1_EN..................................................................65
R_W2_FMIRY............................................................65
R_W1_FADE .............................................................64
R_W2_H ....................................................................60
104
BIT1612
10-Bit Digital Video Decoder with OSD and T-CON
R_W2_INDEX_E .......................................................65
R_W2_Y ....................................................................60
R_W2_INDEX_S .......................................................65
R_WDT_CLEAR ..................................................80, 86
R_W2_MULX.............................................................65
R_WDT_OV .........................................................80, 86
R_W2_MULY.............................................................66
R_WDT_SEL .............................................................80
R_W2_SPCY .............................................................66
R_WHITE_SLOPE.....................................................37
R_W2_VANISH_DIR .................................................66
R_WHITE_START .....................................................37
R_W2_VANISH_LN...................................................66
R_WP_EN ...........................................................81, 85
R_W2_W ...................................................................60
R_XCLK_SEL ......................................................14, 79
R_W2_WDLY.............................................................66
R_Y_AUTO ................................................................48
R_W2_WFRI_B .........................................................66
R_Y_SEL ...................................................................48
R_W2_WFRI_BLEN ..................................................66
R_Y1D_SEL...............................................................48
R_W2_WFRI_EN.......................................................66
R_Y2R_SEL...............................................................38
R_W2_WFRI_FADE ..................................................66
R_YC_EN ..................................................................54
R_W2_WFRI_G.........................................................66
R_YDEL.....................................................................46
R_W2_WFRI_H .........................................................66
R_YP90REF13_EN ...................................................49
R_W2_WFRI_R .........................................................66
R_YPBPR_EN ...........................................................54
R_W2_WFRI_V .........................................................66
R_YREFC_EN ...........................................................49
R_W2_WMIRX ..........................................................65
R_ZERO1_EN ...........................................................17
R_W2_WMIRY ..........................................................65
R_ZERO2_EN ...........................................................17
R_W2_X ....................................................................59
105