HX8353-C - NewHaven Display

( DOC No. HX8353-C(N)-DS )
HX8353-C
132RGB x 162 dot, 262K Color,
with Internal GRAM,
TFT Mobile Single Chip Driver
Preliminary version 01, February 2008
HX8353-C
132RGB x 162 dot, 262K Color, with Internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
February, 2008
1. General Description......................................................................................................................................8
2. Features .........................................................................................................................................................9
3. Block Diagram.............................................................................................................................................11
4. Pin Description ...........................................................................................................................................12
4.1 Pin Description ................................................................................................................................... 12
4.2 Pin assignment ................................................................................................................................... 16
4.4 Alignment mark................................................................................................................................... 21
4.5 Bump arrangement............................................................................................................................. 22
5. Function Description..................................................................................................................................23
5.1 System Interface................................................................................................................................. 23
5.1.1 Parallel Bus System Interface .................................................................................................. 24
5.1.2 Serial Interface ......................................................................................................................... 39
5.1.3 Display Module Data Transfer Recovery ................................................................................. 45
5.1.4 Display Module Data Transfer Pause ...................................................................................... 46
5.1.5 Display Module Data Transfer Modes ...................................................................................... 47
5.2 Address Counter (AC) ........................................................................................................................ 47
5.2.1 MCU to memory write/read direction ....................................................................................... 48
5.3 Source, Gate and Memory Map ......................................................................................................... 50
5.3.1 When using 132 x 162 GRAM resolution, display resolution 132RGB x 162 and support S45AP
spec (RSO[2:0]=3’b000 & STE_SEL=0) ........................................................................................... 50
5.3.2 When using 132 x 162 GRAM resolution, display resolution 128RGB x 160 and support S43AP
spec (RSO[2:0]=3’b000 & STE_SEL=1) ........................................................................................... 51
5.3.3 When using 128 x 160 GRAM resolution, display resolution 128RGB x 160 and support S44AP
spec (RSO[2:0]=3’b011) .................................................................................................................... 52
5.3.4 When using 120 x 160 GRAM resolution, display resolution 120RGB x 160 (RSO[2:0]=3’b010)
........................................................................................................................................................... 53
5.3.5 When using 128 x 128 GRAM resolution, display resolution 128RGB x 128 (RSO[2:0]=3’b001)
........................................................................................................................................................... 54
5.3.6 When using 96 x 68 GRAM resolution, display resolution 96RGB x 68 (RSO[2:0]=3’b100)... 55
5.3.7 When using 96 x 64 GRAM resolution, display resolution 96RGB x 64 (RSO[2:0]=3’b101)... 56
5.3.8 Normal Display On or Partial Display On................................................................................. 57
5.4 Vertical Scrolling Display .................................................................................................................... 71
5.5 Tearing Effect Output Line .................................................................................................................. 73
5.5.1 Tearing Effect Line Modes........................................................................................................ 73
5.5.2 Tearing Effect Line Timing........................................................................................................ 75
5.5.3 Example 1: MPU Write is faster than Panel Read ................................................................... 76
5.5.4 Example 2: MPU Write is slower than Panel Read.................................................................. 77
5.6 Color Depth Conversion Look-up Tables............................................................................................ 78
5.7 Oscillator............................................................................................................................................. 82
5.8 Source Driver...................................................................................................................................... 82
5.9 Gate Driver ......................................................................................................................................... 82
5.10 LCD POWER GENERATION CIRCUIT ........................................................................................... 83
5.10.1 LCD Power Generation Scheme............................................................................................ 83
5.10.2 Various Boosting Steps .......................................................................................................... 84
5.11 Gray Voltage Generator for Source Driver ....................................................................................... 85
5.11.1 Structure of Grayscale Voltage Generator ............................................................................. 86
5.11.2 Gamma-Characteristics Adjustment Register ........................................................................ 87
5.11.3 Gamma Macro Adjustment Registers..................................................................................... 87
5.11.4 Gamma Resister Stream and 8 to 1 Selector......................................................................... 88
5.11.5 Variable Resister .................................................................................................................... 89
5.11.6 Gamma Curve Control ........................................................................................................... 95
5.12 Oscillator........................................................................................................................................... 96
5.13 Power On/Off Sequence .................................................................................................................. 97
5.13.1 Case 1 – NRESET line is hold High or Unstable by Host at Power On................................. 98
5.13.2 Case 2 – NRESET line is held Low by host at Power On...................................................... 99
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.1February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, with Internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
February, 2008
5.14 Uncontrolled Power Off .................................................................................................................. 100
5.15 Power Flow Chart for Different Power Mode.................................................................................. 101
5.16 Input/Output Pin State .................................................................................................................... 102
5.16.1 Output or Bi-directional (I/O) Pins ........................................................................................ 102
5.16.2 Input Pins ............................................................................................................................. 102
5.17 Sleep Out – Command and Self-Diagnostic Functions of the Display Module.............................. 103
5.17.1 Register loading Detection ................................................................................................... 103
5.17.2 Functionality Detection......................................................................................................... 104
5.18 OTP Programming.......................................................................................................................... 105
5.19 Free Running Mode Specification .................................................................................................. 109
6. Command ..................................................................................................................................................112
6.1 Command Compare Table.................................................................................................................112
6.2 User Define Command List Table......................................................................................................115
6.2.1 Command List .........................................................................................................................115
6.3 Command Description ...................................................................................................................... 121
6.3 Command Description ...................................................................................................................... 121
6.3.1 NOP........................................................................................................................................ 121
6.3.2 Software Reset (01h) ............................................................................................................. 122
6.3.3 Read Display Identification Information (04h) ........................................................................ 123
6.3.4 Read Display Status (09h) ..................................................................................................... 124
6.3.5 Read Display Power Mode (0Ah)........................................................................................... 127
6.3.6 Read Display MADCTL (0Bh) ................................................................................................ 129
6.3.7 Read Display Pixel Format (0Ch) .......................................................................................... 131
6.3.8 Read Display Image Mode (0Dh)........................................................................................... 132
6.3.9 Read Display Signal Mode (0Eh) ........................................................................................... 133
6.3.10 Read Display Self-Diagnostic Result (0Fh).......................................................................... 134
6.3.11 Sleep In (10h) ....................................................................................................................... 135
6.3.12 Sleep Out (11h) .................................................................................................................... 136
6.3.13 Partial Mode On (12h).......................................................................................................... 138
6.3.14 Normal Display Mode On (13h)............................................................................................ 139
6.3.15 Display Inversion Off (20h)................................................................................................... 140
6.3.16 Display Inversion On (21h)................................................................................................... 141
6.3.17 Gamma Set (26h)................................................................................................................. 142
6.3.18 Display Off(28h) ................................................................................................................... 143
6.3.19 Display On (29h) .................................................................................................................. 144
6.3.20 Column Address Set (2Ah)................................................................................................... 145
6.3.21 Page Address Set (2Bh)....................................................................................................... 147
6.3.22 Memory Write (2Ch) ............................................................................................................. 148
6.3.23 Colour Set (2Dh) .................................................................................................................. 149
6.3.24 Memory Read (2Eh) ............................................................................................................. 150
6.3.25 Partial Area (30h) ................................................................................................................. 152
6.3.26 Vertical Scrolling Definition (33h) ......................................................................................... 154
6.3.27 Tearing Effect Line Off (34h) ................................................................................................ 157
6.3.28 Tearing Effect Line On (35h) ................................................................................................ 158
6.3.29 Memory Access Control (36h).............................................................................................. 159
6.3.30 Vertical Scrolling Start Address (37h)................................................................................... 161
6.3.31 Idle Mode Off (38h) .............................................................................................................. 162
6.3.32 Idle Mode On (39h) .............................................................................................................. 163
6.3.33 Interface Pixel Format (3Ah) ................................................................................................ 164
6.3.34 Read ID1 (DAh).................................................................................................................... 165
6.3.35 Read ID2 (DBh).................................................................................................................... 166
6.3.36 Read ID3 (DCh) ................................................................................................................... 167
6.4 Himax Command.............................................................................................................................. 168
6.4.1 SETOSC: Set Internal Oscillator (B0h) .................................................................................. 168
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.2February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, with Internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
February, 2008
6.4.2 SETPOWER: Set Power (B1h) .............................................................................................. 169
6.4.3 SETDISP: Set Display Related Register (B2h)...................................................................... 173
6.4.4 SETLUT: Set LUT Enable Related Register (B3h)................................................................. 176
6.4.5 SETCYC: Set Display Waveform Cycles (B4h) ..................................................................... 177
6.4.6 SETBGP: Set BGP Voltage (B5h).......................................................................................... 179
6.4.7 SETVCOM: Set VCOM Voltage (B6h) ................................................................................... 180
6.4.8 SETGAMMA: Set Gamma Curve Related Setting (B7) ......................................................... 184
6.4.9 PASSWDEN: Set Password enable command (B9h) ............................................................ 185
6.4.10 PASSWDDISAB: Password Disable command (BAh) ......................................................... 186
6.4.11 SETOTP: Set OTP Related Setting (BBh) ........................................................................... 187
6.4.12 SETVDC: Set Internal Digital Voltage (BCh)........................................................................ 188
6.4.13 SETSPULSE: Set Arbiter Pulse Width (BDh) ...................................................................... 189
6.4.14 SETPROBE: Set Probe Signal Group (BEh) ....................................................................... 190
6.4.15 SETPTBA: Set Power Option (BFh) .................................................................................... 191
6.4.16 SETSTBA: Set Source Option (C0h) ................................................................................... 192
6.4.17 SETID: Set ID (C4h)............................................................................................................. 193
6.4.18 SETECO: Set ECO (C6h) .................................................................................................... 194
6.4.19 SETMREV: Set Free Running Mode (CAh) ......................................................................... 195
6.4.20 SETIOOPT: Set IO_OPT (CBh) ........................................................................................... 196
6.4.21 SETPANEL: Set PANEL (CCh) ............................................................................................ 196
6.4.22 GETOSC: Read Internal Oscillator (E0h) ............................................................................ 197
6.4.23 GETPOWER: Read Power (E1h) ........................................................................................ 198
6.4.24 GETDISP: Read Display Related Register (E2h) ................................................................ 199
6.4.25 GETLUT: ReadLUT Enable Related Register (E3h) ............................................................ 200
6.4.26 GETCYC: Read Display Waveform Cycle(E4h) .................................................................. 201
6.4.27 GETBGP: Read BGP Voltage Setting (E5h) ........................................................................ 202
6.4.28 GETVCOM: Read VCOM Voltage Setting (E6h) ................................................................. 203
6.4.29 GETGAMMA: Read Gamma Curve Related Setting (E7h) ................................................. 204
6.4.30 GETOTP: Read OTP Related Setting (EBh)........................................................................ 205
6.4.31 GETVDC: Read Internal Digital Voltage Setting (ECh)........................................................ 206
6.4.32 GETSPULSE: Read Arbiter Pulse Width (EDh)................................................................... 207
6.4.33 GETPROBE: Read Probe Signal Group (EEh).................................................................... 208
6.4.34 GETPTBA: Read Power Option (EFh) ................................................................................. 209
6.4.35 GETSTBA: Read Source Option (F0h) ................................................................................ 210
6.4.36 GETPFUSE: Get Internal OTP (F1h) ....................................................................................211
6.4.37 GETHXID: Read Himax ID (F4h) ......................................................................................... 212
6.4.38 GETECO: Read TECO(F6h)................................................................................................ 213
6.4.39 GETMREV: Get Free Running Mode (FAh) ......................................................................... 214
6.4.40 GETIOOPT: Get IO_OPT (FBh) ........................................................................................... 215
6.4.41 GETPANEL: Get PANEL (FCh)............................................................................................ 215
7. Electrical Characteristic...........................................................................................................................216
7.1 Absolute Maximum Ratings.............................................................................................................. 216
7.2 ESD Protection Level ....................................................................................................................... 216
7.3 Maximum Series Resistance............................................................................................................ 216
7.4 DC Characteristics ........................................................................................................................... 217
7.4.1 DC Characteristics List........................................................................................................... 217
7.4.2 Current Consumption ............................................................................................................. 218
7.5 AC CHARACTERISTICS.................................................................................................................. 219
7.5.1 Parallel Interface Characteristics (8080-series MPU) ............................................................ 219
7.5.2 Serial Interface Characteristics .............................................................................................. 221
7.5.3 Reset Input Timing ................................................................................................................. 222
7.5.4 Measurement Conditions ....................................................................................................... 223
8. Reference Application..............................................................................................................................227
8.1 Example Connection with Panel....................................................................................................... 227
8.2 Connection Example with External Components ............................................................................. 228
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.3February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, with Internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
February, 2008
8.3 External Components ....................................................................................................................... 229
9. Layout Recommedacation.......................................................................................................................230
10. Ordering Information..............................................................................................................................231
11. Revision History .....................................................................................................................................231
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.4February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, with Internal
GRAM, TFT Mobile Single Chip Driver
List of Figures
February, 2008
Figure 5. 1 Register Read/Write Timing in Parallel Bus System Interface (for I80 series MPU) ...... 25
Figure 5. 2 Register Read/Write Timing in Parallel Bus System Interface (for M68 series MPU) .... 26
Figure 5. 3 GRAM Read/Write Timing in Parallel Bus System Interface (for I80 series MPU) ......... 27
Figure 5. 4 GRAM Read/Write Timing in Parallel Bus System Interface (for M68 series MPU)....... 28
Figure 5. 5 Example of 80- / 68- System 8-bit bus Interface ............................................................ 29
Figure 5. 6 Write data for RGB 6-6-6-bits input (support DMIF-S43AP-J124 and LUT_EN=1) ....... 30
Figure 5. 7 Write data for RGB 4-4-4-bits input (support Look-up table and LUT_EN=0) ................ 31
Figure 5. 8 Write data for RGB 5-6-5-bits input (support Look-up table and LUT_EN=0) ................ 32
Figure 5. 9 Example of I80- / M68- System 16-bit Parallel Bus Interface ......................................... 33
Figure 5. 10 GRAM Write Data for RGB 6-6-6-(262k colours) bits input (LUT_EN=1)..................... 33
Figure 5. 11 Write data for RGB 4-4-4 (4k colours) bits input on 16-bit parallel Interface (when
support Look-up table and LUT_EN=0) ..................................................................................... 34
Figure 5. 12 Write data for RGB 5-6-5 (65k colours) bits input on 16-bit parallel Interface (when
support Look-up table and LUT_EN=0) ..................................................................................... 34
Figure 5. 13 Example of I80- / M68- System 18-bit Parallel Bus Interface ....................................... 35
Figure 5. 14 Write data for RGB 4-4-4 (4k colours) bits input in 18-bit parallel Interface (when support
Look-up table and LUTENB=0).................................................................................................. 35
Figure 5. 15 Write data for RGB 5-6-5 (65k colours) bits input in 18-bit parallel Interface (when
support Look-up table and LUT_EN=0) ..................................................................................... 36
Figure 5. 16 Write data for RGB 6-6-6(262k colours) bits input in 18-bit parallel Interface (LUT_EN=1)
................................................................................................................................................... 36
Figure 5. 17 Example of 80- / 68- System 9-bit bus Interface .......................................................... 37
Figure 5. 18 Write data for RGB 4-4-4 (4k colours) bits input in 9-bit parallel Interface (when support
Look-up table and LUT_EN=0) .................................................................................................. 37
Figure 5. 19 Write data for RGB 5-6-5(65k colours) bits input in 9-bit parallel Interface (when support
Look-up table and LUT_EN=0) .................................................................................................. 38
Figure 5. 20 Write data for RGB 6-6-6-bits (262kcolours) input in 9-bit parallel Interface (LUT_EN=1)
................................................................................................................................................... 38
Figure 5. 21 Serial Interface protocol data stream format................................................................. 39
Figure 5. 22 Serial Interface protocol 3 wire/4 wire, write mode....................................................... 40
Figure 5. 23 3 Wires Serial Interface protocol, read mode ............................................................... 41
Figure 5. 24 4 wire Serial Interface protocol, read mode .................................................................. 42
Figure 5. 25 3W Serial write data for RGB (6-6-6) bits input (LUT_EN=1) ....................................... 43
Figure 5. 26 3W Serial write data for RGB 4-4-4-bits input (support Look-up table and LUT_EN=0)
................................................................................................................................................... 43
Figure 5. 27 3W Serial write data for RGB 5-6-5-bits input (support Look-up table and LUT_EN=0)
................................................................................................................................................... 43
Figure 5. 28 4W Serial write data for RGB (6-6-6) bits input (LUT_EN=1) ....................................... 44
Figure 5. 29 4W Serial write data for RGB 4-4-4-bits input (support Look-up table and LUT_EN=0)
................................................................................................................................................... 44
Figure 5. 30 4W Serial write data for RGB 5-6-5-bits input (support Look-up table and LUT_EN=0)
................................................................................................................................................... 44
Figure 5. 31 Display Module Data Transfer Recovery ...................................................................... 45
Figure 5. 32 MCU to memory write/read direction ............................................................................ 48
Figure 5. 33 MY, MX, MV Setting...................................................................................................... 48
Figure 5. 34 Address Direction Settings............................................................................................ 49
Figure 5. 35 Memory Map, 132 x 162 GRAM resolution, display resolution 132RGB x 162............ 50
Figure 5. 36 Memory Map, 132 x 162 GRAM resolution ,display resolution 128RGB x 160............ 51
Figure 5. 37 Memory Map, 128 x 160 GRAM resolution, display resolution 128RGB x 160............ 52
Figure 5. 38 Memory Map, 120 x 160 GRAM resolution, display resolution 120RGB x 160............ 53
Figure 5. 39 Memory Map, 128 x 128 GRAM resolution, display resolution 128RGB x 128............ 54
Figure 5. 40 Memory Map, 96 x 68 GRAM resolution, display resolution 96RGB x 68.................... 55
Figure 5. 41 Memory Map, 96 x 64 GRAM resolution, display resolution 96RGB x 64.................... 56
Figure 5. 41 ....................................................................................................................................... 71
Figure 5. 43 ....................................................................................................................................... 72
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.5February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, with Internal
GRAM, TFT Mobile Single Chip Driver
List of Figures
February, 2008
Figure 5. 44 ....................................................................................................................................... 72
Figure 5. 45 ....................................................................................................................................... 73
Figure 5. 46 ....................................................................................................................................... 74
Figure 5. 47 ....................................................................................................................................... 74
Figure 5. 48 ....................................................................................................................................... 75
Figure 5. 49 ....................................................................................................................................... 75
Figure 5. 50 ....................................................................................................................................... 76
Figure 5. 51 ....................................................................................................................................... 76
Figure 5. 52 ....................................................................................................................................... 77
Figure 5. 53 LCD power generation scheme .................................................................................... 83
Figure 5. 54 Block Diagram of Power Supply Circuit ........................................................................ 84
Figure 5. 55 Grayscale Control ......................................................................................................... 85
Figure 5. 56 Structure of Grayscale Voltage Generator .................................................................... 86
Figure 5. 57 Gamma Resister Stream and Gamma Reference Voltage .......................................... 88
Figure 5. 58 Relationship between Source Output and Vcom.......................................................... 94
Figure 5. 59 Relationship between GRAM Data and Output Level .................................................. 94
Figure 5. 60 Gamma Curve according to the GC0 to GC3 bit (GC_SEL=low)................................. 95
Figure 5. 61 Oscillation Circuit .......................................................................................................... 96
Figure 5. 62 Case 1 – NRESET line is hold High or Unstable by Host at Power On........................ 98
Figure 5. 63 NRESET line is held Low by host at Power On ............................................................ 99
Figure 5. 64 Power Flow Chart for Different Power Modes ............................................................ 101
Figure 5. 65 Register loading Detection Flow ................................................................................. 103
Figure 5. 66 Functionality Detection Flow....................................................................................... 104
Figure 5. 67 OTP Programming Flow ............................................................................................. 107
Figure 5. 68 Power On Sequence of FR-mode (for Normally–White Panel) ...................................110
Figure 5. 69 Power Off Sequence of FR-mode................................................................................110
Figure 7. 1 Parallel Interface characteristics (8080-series MPU) ................................................... 219
Figure 7. 2 Chip select timing.......................................................................................................... 220
Figure 7. 3 Write to read and read to write timing........................................................................... 220
Figure 7. 4 Serial Interface Characteristics ..................................................................................... 221
Figure 7. 5 Reset input timing ......................................................................................................... 222
Figure 7. 6 ....................................................................................................................................... 223
Figure 7. 7 ....................................................................................................................................... 223
Figure 7. 8 ....................................................................................................................................... 224
Figure 7. 9 ....................................................................................................................................... 225
Figure 7. 10 ..................................................................................................................................... 225
Figure 7. 11 ..................................................................................................................................... 226
Figure 8. 1 ....................................................................................................................................... 227
Figure 8. 2 Example connection with external components............................................................ 228
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.6February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, with Internal
GRAM, TFT Mobile Single Chip Driver
List of Tables
February, 2008
Table 5. 1 Interface selection ............................................................................................................ 23
Table 5. 2 Interface Mode Selection.................................................................................................. 23
Table 5. 3 Data Pin Function for I80 Series CPU .............................................................................. 24
Table 5. 4 Data Pin Function for M68 Series CPU............................................................................ 24
Table 5. 5 MY, MX, MV Setting ......................................................................................................... 48
Table 5. 6........................................................................................................................................... 57
Table 5. 7........................................................................................................................................... 58
Table 5. 8........................................................................................................................................... 59
Table 5. 9........................................................................................................................................... 60
Table 5. 10......................................................................................................................................... 61
Table 5. 11 ......................................................................................................................................... 62
Table 5. 12......................................................................................................................................... 63
Table 5. 13......................................................................................................................................... 64
Table 5. 14......................................................................................................................................... 65
Table 5. 15......................................................................................................................................... 66
Table 5. 16......................................................................................................................................... 67
Table 5. 17......................................................................................................................................... 68
Table 5. 18......................................................................................................................................... 69
Table 5. 19......................................................................................................................................... 70
Table 5. 20 AC characteristics of Tearing Effect Signal .................................................................... 75
Table 5. 21 Gamma-Adjustment Registers ....................................................................................... 87
Table 5. 22 Offset Adjustment 0
Table 5. 23 Offset Adjustment 1 ............................................ 89
Table 5. 24 Center Adjustment.......................................................................................................... 89
Table 5. 25 Output Voltage of 8 to 1 Selector ................................................................................... 90
Table 5. 26 Voltage Calculation Formula .......................................................................................... 91
Table 5. 27 Voltage Calculation Formula of Grayscale Voltage........................................................ 92
Table 5. 28 Voltage Calculation Formula of Grayscale Voltage V2~V7 and V56~V61..................... 93
Table 5. 29 The State of Output or Bi-directional (I/O) Pins ............................................................ 102
Table 5. 30 The State of Input Pins ................................................................................................. 102
Table 5. 31 OTP memory table........................................................................................................ 105
Table 5. 32 Pin Information ............................................................................................................. 109
Table 5. 33 Frequency Definition of Free Running Mode Display.................................................... 111
Table 6. 1 MPU Interface Command Set .........................................................................................112
Table 6. 2 User Command Set .........................................................................................................115
Table 7. 1 Absolute Maximum Ratings............................................................................................ 216
Table 7. 2 ESD Protection Level ..................................................................................................... 216
Table 7. 3......................................................................................................................................... 216
Table 7. 4 DC Characteristics 1....................................................................................................... 217
Table 7. 5 DC Characteristics 2....................................................................................................... 217
Table 7. 6 Current Consumption ..................................................................................................... 218
Table 7. 7 Parallel Interface characteristics (8080-series MPU) ..................................................... 219
Table 7. 8 Serial Interface Characteristics ...................................................................................... 221
Table 7. 9......................................................................................................................................... 222
Table 8. 1 Example capacitor connection........................................................................................ 229
Table 8. 2 Adoptability of Capacitor................................................................................................. 229
Table 8. 3 Adoptability of Variable resistor ...................................................................................... 229
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.7February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, with Internal
GRAM, TFT Mobile Single Chip Driver
Preliminary Version 01
February, 2008
1. General Description
This manual describes the Himax’s HX8353-C 132RGB*162 dots resolution driving
controller. The HX8353-C(N) is designed to provide a single-chip solution that
combined a gate driver, a source driver, power supply circuit, and internal graphics
RAM for 262,144 colors to drive a TFT panel with 128RGB*160 dots at maximum.
The HX8353-C can be operated in low-voltage (1.65V) condition to the interface and
integrated internal boosters that produce the liquid crystal voltage, breeder resistance
and the voltage follower circuit for liquid crystal driver. In addition, The HX8353-C also
supports various functions to reduce the power consumption of a LCD system via
software control.
The HX8353-C is suitable for any small portable battery-driven product and requiring
long-term driving capabilities, such as small PDAs, digital cellular phones and
bi-directional pagers.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.8February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
2. Features

Single chip solution to drive a TFT panel

132RGB x 162-dot graphics display LCD controller/driver and 262,144 TFT colors

Support resolution:
 132RGB x 162-dot: Display with 132 x 18-bits x 162 display RAM (S45AP)
 128RGB x 160-dot

Type 1: Display with 128 x 18-bits x 160 display RAM (S44AP)

Type 2: Display with 132 x 18-bits x 162 display RAM (S43AP)
 128RGB x 128-dot
 120RGB x 160-dot
 96RGB x 68-dot: Display with 96 x 18-bits x 68 display RAM (S31AL)
 96RGB x 64-dot

Internal operation circuit of liquid crystal display:
 Source channel: 396ch (132RGB)
 Gate line: 162 Gate output

Display mode (Color modes):
 Full colors

262k colours (18bit 6(R):6(G):6(B))
 Reduce color mode:

65k colours (16bit 5(R):6(G):5(B))

4k colours (12bit 4(R):4(G):4(B))

8 colors (Idle mode on): 8 colors (3 bit binary mode)

Internal graphics RAM capacity: 132 x 162 x 18-bit = 0.38M bit:

Support interface mode:
 I80 System interface: 8-bits / 9-bits / 16-bits / 18bits bus
 m68 System interface: 8-bits / 9-bits / 16-bits / 18bits bus
 3W/4W Serial Data Transfer Interface

Display features
 Area scrolling
 Partial display mode
 Software programmable color depth mode

On chip features:
 DC/DC converter
 OTP to store initialization register setting
 Oscillator for display clock generation
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.9February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
 Line inversion, frame inversion
 OTP to store initialization register setting
 Support default value for factory use

Low-power consumption architecture supports:
 Logic supply voltage range for VDD to VSSD: 1.65 to 3.3V
 Analog supply voltage range for VDDI to VSSA: 2.3 to 3.3V

Output voltage range:
 VLCD = 4.0 to 5.5V
 VCL = -2V to -3.3V
 VREG1OUT = 3.0 to (VLCD-0.5V) (Source output reference voltage range)
 VCOMH = 2.5V to 4.5V (Common electrode output high voltage)
 VCOML = -2V to 0V (Common electrode output low voltage)
 VGH = +9.0 to +16V (Positive Gate output voltage range)
 VGL = -9.0 to -16V (Negative Gate output voltage range)
(note: VDD – VCL ≦ 6V, VGH – VGL ≦ 32V)

Low power consumption, suitable for battery operated systems

Suitable for all brand LCM module
 Command set:

128RGB x 160-dot : DMIF-S43AP-J124 but support LUT table

132RGB x 162-dot : DMIF-S45AP-J12

128RGB x 160-dot : DMIF-S44AP-J12

96RGB x 68-dot : DMIF-S31AL-J124 but support LUT table
 Himax defined command set

CMOS compatible inputs

Optimized layout for COG assembly

OTP memory to store initialization register settings

Temperature range: -30 ~ 85℃
Note: (1) Blank display means: Normal White Display = White, Normal Black Display = Black.
(2) Timing and voltage level specification apply for the complete display module including LCD glass,
Flex cable (FPC) and driver IC. Signal timings and levels are measured on the host interface
connector.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.10February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
3. Block Diagram
S396~1
VDDI
GND
Index Register
(IR)
P68
BS0
BS1
BS2
TE
Address Counter
(AC)
System I/F
I80 & m68:
- 8 bits
- 9 bits
- 16 bits
-18 bits
18
16
NRESET
GC_SEL
VDDI
D/A converter circuit
Latch
circuit
18
18
TEST2~0
LC_SEL1~0
STE_SEL
RSO0
RSO1
RSO2
Source
driver
18
Instruction
Controller
Read data
latch
Write data
latch
18
18
V0~63
VGS
Grayscale voltage
generator
132x18x162 bits
Power
Regulator
OSC
VTESTOUT
Graphic RAM
(GRAM)
Gamma adjusting
circuit
VDDD
Timing
generator
RSOC
Gate
Driver
NCS
DNC_SCL
NRD_E
NWR_RNW
EXTC
SDA
DB 17~0
7
Control
Register
(CR)
VSSD
VSSA
G1~G162
LCD driving power
circuit
VDDD
VCOMH
VCOML
VCOM
VGH
VGL
C21A/C21B
C22A/C22B
C23A/C23B
VCL
C12A/C12B
VLCD
C11A/C11B
VCI1
VREG1OUT
VDD
VGH / VGL
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.11February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4. Pin Description
4.1 Pin Description
Input Parts
Signals
I/O
Pin
Number
Connected
with
Descriptions
Select the MPU interface mode as listed below
P68,
BS2,BS1,BS0
I
4
VSSD/
VDDI
P68
BS2
BS1
BS0
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
x
0
x
x
Interface mode
8-bit bus interface,
80-system,
16-bit bus interface,
80-system,
9-bit bus interface,
80-system,
18-bit bus interface,
80-system,
8-bit bus interface,
68-system,
16-bit bus interface,
68-system,
9-bit bus interface,
68-system,
18-bit bus interface,
68-system,
3W/4W Serial interface
DB pins
D17-D8:Unused,
D7-D0: Data
D17-D16:Unused,
D15-D0: Data
D17-D9:Unused,
D8-D0: Data
D17-D0: Data
D17-D8:Unused,
D7-D0: Data
D17-D16:Unused,
D15-D0: Data
D17-D9:Unused,
D8-D0: Data
D17-D0: Data
D17-D0:Unused
SDA: Data input/output
Note:Must be connected to VSSD or VDD1.(latch type)
Interface format select pin (latch type)
SPI_SEL
I
1
SPI_SEL
0
1
MPU
NCS
I
1
MPU
DNC_SCL
I
1
MPU
NRD_E
I
1
MPU
NWR_RNW
I
1
MPU
EXTC
I
1
MPU
STE_SEL
I
1
MPU
GC_SEL
I
1
MPU
LC_SEL1-0
I
2
MPU
Serial Interface Format Selection
3W Serial Interface (default)
4W Serial Interface
Chip select signal.
Low: chip can be accessed;
High: chip cannot be accessed.
Must be connected to VSSD or VDDI if not in use. (latch type)
The signal for command or parameter select under parallel mode(i.e. Not
serial interface):
Low: command. High: parameter.
When under serial interface, it servers as SCL.
If not used, let it open or connected to VDD1. (latch type)
I80 system: Serves as a read signal and read data at the low level.
M68 system: 0: Read/Write disable, 1: Read/Write enable.
Fix it to VDDI or VSSD level when using serial interface. (latch type)
I80 system: Serves as a write signal and writes data at the rising edge.
M68 system: 0: Write, 1: Read.
Fix it to VDDI or VSSD level when using serial interface.
If not used, let it open or connected to VDD1. (latch type)
Extended command set enable. (Only support Command-Parameter
Interface mode)
Low (VSSD): extended command set is discarded
High (VDDI): extended command set is accepted
If not used, let it open or connected to VSSD.(weak pull low)
This Pin is only valid for RSO[2:0]=3’b000.
There is a internal pull-high resistor on this pad. (latch type)
Low (VSSD): Scrolling function enable and TE lines is meet definition of
S45AP (162 lines)  Support document of S45AP.
High (VDDI): Scrolling function disable and TE lines is meet definition of
S43AP (160 lines)  Support document of S43AP.
This signal is used to select gamma curve order. (latch type)
Low (VSSD): GC0(1.0), GC1(2.5), GC2(2.2), GC3(1.8)
High (VDDI): GC0(2.2), GC1(1.8), GC2(2.5), GC3(1.0)
The selection pins of different liquid crystal type. (latch type)
LC_SEL1
LC_SEL0
Different liquid crystal type Selection
0
0
0
1
LC type 1
LC type 2
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.12February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Input Parts
1
1
0
1
LC type 3
LC type 4
Input Parts
Signals
I/O
RSO0
I
RSO1
RSO2
NRESET
I
I
Pin
Connected
Number
with
1
1
1
I
1
I
1
VDC_ENB
SS_PANEL
MPU
Description
Resolution selection pins. RSO[2:0] is used for selecting resolution. If
not used, please let it open. (latch type)
RSO2
RSO1
RSO0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
1
1
0
1
MPU
MPU
Resolution
GRAM resolusion (Size): 132RGBX162
Display resolusion:
Type1 :132RGBx162 (S1~S396 and
G1~G162)S45AP
Type2 :128RGBx160 (S7~S390 and
G2~G161)S43AP
GRAM resolusion (Size): 128RGBx128
Display resolusion:
128RGBx128 (S7~S390 and G2~G129)
GRAM resolusion (Size): 120RGBx160
Display resolusion:
120RGBx160 (S7~S366, G2~G161)
GRAM resolusion (Size): 128RGBx160
Display resolusion:
128RGBx160 (S7~S390 and G2~G161) S44AP
GRAM resolusion: 96RGBx68
Display resolusion:
96RGBx68 (S55~S342, G1~G68)
GRAM resolusion: 96RGBx64
Display resolusion:
96RGBx64 (S55~S342, G1~G64)
Setting disable
Setting disable
Reset pin. Setting this pin low initializes the LSI. Must be reset after
MPU or reset
power is supplied.
circuit
Must be connected to VSSD or VDD1. (latch type)
Input pin to select the logice power. (latch type)
VSSD : Enable internal VDDD generator
VDDI : Disable internal VDDD generator, VDDD should connect to
external 1.65v~1.95v power
Input pin to select the source driver scan direction on panel module.
(1: VDDI, 0: VSSD) (latch type)
MPU
SS_Panel
0
1
RSO[2:0]
=3b’011
S7 -> S390
S390 -> S7
Module source output direction
RSO[2:0]
RSO[2:0]
RSO[2:0]
=3b’010
=3b’001
=3b’000
S7 -> S366
S7 -> S390
S1 -> S396
S366 -> S7
S390 -> S7
S396 -> S1
Input pin to select the Gate driver scan direction on panel module.
(1: VDDI, 0: VSSD) (latch type)
GS_PANEL
I
1
MPU
GS_Panel
0
1
RSO[2:0]
=3b’011
G2 -> G161
G161 -> G2
Module Gate output direction
RSO[2:0]
RSO[2:0]
RSO[2:0]
=3b’010
=3b’001
=3b’000
G2 -> G161
G2 -> G129
G1 -> G162
G161 -> G2
G129 -> G2
G162 -> G1
Input pin to select the display reversion (1: VDDI, 0: VSSD) (latch type)
REV_PANEL
I
1
MPU
REV_Panel
0
1
Mapping data
“0” to minimum pixel voltage for normal black pane
“0” to maximum pixel voltage for normal white pane
Input pin to select the color mapping. (1: VDDI, 0: VSSD) (latch type)
BGR_PANEL
I
1
MPU
TEST1
TEST2
TEST3
I
I
I
1
1
1
OSC
I
1
VSSD
VSSD
VSSD
Open or
Connect to
BGR_panel
0
1
Color mapping
R->G->B
B->G->R
A test pin. Make sure to fix it to the VSSD level.(weak pull low)
A test pin. Make sure to fix it to the VSSD level. (weak pull low)
A test pin. Make sure to fix it to the VSSD level. (weak pull low)
Oscillator input for test purpose.
If not used, please let it open or connected to VSSD. (weak pull low)
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.13February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Input Parts
VSSD
BURN
I
1
MPU
Free Running mode (weak pull low)
If BURN=Hi, this can enable free running mode for burn in test.
The display data alternates between full black and full white independent
of input data in free running mode.
Output Part
Signals
I/O
Pin
Connected
Number
with
S1~396
O
396
LCD
G1~162
O
160
LCD
VCOM
O
2
TFT
common
electrode
VCOMH
O
1
Stabilizing
capacitor
or open
VCOML
O
1
Stabilizing
capacitor
or open
VREG1OUT
O
1
Stabilizing
capacitor
or open
VLCD
O
1
Stabilizing
capacitor
VGL
O
1
Stabilizing
capacitor
VCL
O
1
Stabilizing
capacitor
TE
O
1
MPU or
open
VTESTOUT
O
1
VDDD
O
4
VREF
0
1
Open
VGH
O
1
Stabilizing
capacitor
Open
Stabilizing
capacitor
Description
Output voltages applied to the liquid crystal.
The shift direction of segment signal outputs is changeable with the SS
bit. For example, if SS=0, DATA IN THE ram address “0000” is output
from S1.If SS=1, the same data in the ram address “0000” is output from
S396.
S1,S4,S7,… display red (R),S2,S5,S8,… display green (G),and
S3,S6,S9,… display blue(B) (SS=0, BGR=0).
Output signals from gate lines.
VGH: the level to select the gate lines
VGL: the level not to select the gate lines
The power supply of common voltage in TFT driving. The voltage
amplitude between VCOMH and VCOML is output. The alternation cycle
can be set by the POL pin. Connect this pin to the common electrode in
TFT panel.
Connect this pin to the capacitor for stabilization. This pin indicates a high
level of VCOM amplitude generated in driving the VCOM alternation.
When the VCOM alternation is driven, this pin indicates a low level of
VCOM amplitude. Connect this pin to a capacitor for stabilization. When
the VCOMG bit is low, the VCOML output stops and a capacitor for
stabilization is not needed.
A reference voltage for VGAM between VSSD and VGL from the
reference voltage between VDD and VSSD that is generated internally.
The factor of step-up can be set through an internal register. Connect a
capacitor for stabilization. As it is the reference voltage for generating
VgoffOUT. Connect to an external power supply lower than VGL, if not
using the adjustment circuit 2. VGAM1OUT = 3.0 ~ (VLCD – 0.5)V
An output from the step-up circuit1, of twice the VDD level.
Connect to a stabilizing capacitor 1uF between VLCD and VSSD.
VLCD=4.0 to 5.5V, Connect to VLCDC.
An output from the step-up circuit2.or -3~-5 time the VDD level.
The step-up rate is determined with BT3-0 bits. Connect to a stabilizing
capacitor 1uF between VSSD and VGL. Min. VGL = -16V
A power supply for the VCOML level.
Connect to a stabilizing capacitor 1uF between VSSD and VCL.
VCL=-2V ~ -3.3V
A frame start pulse output (amplitude: VDDI-VSSD). Use when writing
data to RAM in synchronization with FLM. When FLM is not used,
disconnect it
A test pin. Disconnect it.
A stabilizing capacitor for logic power.
Connect with the capacitor 1uF.
Reference voltage for power circuit
Please open this pads.
An output from the step-up circuit2.or 4~6 time the VDD level.
The step-up rate is determined with BT3-0 bits. Connect to a stabilizing
capacitor 1uF between VGH and VSSD. Place a Schottky barrier diode
between VDD and VGH. (See “configuration of the power supply”).
Max. VGH=16V.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.14February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Input/Output Part
Signals
I/O
Pin
Number
Connected
Description
with
Step-up
Connect to the step-up capacitors according to the step-up factor. Leave
Capacitor this pin open if the internal step-up circuit is not used.
C11A,C11B
I/O
2
C12A, C12B
C23A, C23B
I/O
2
Open
C21A, C21B
C22A, C22B
I/O
8
Step-up
Capacitor
DB0_SDA
I/O
1
MPU
DB0~17
I/O
18
MPU
DUMMY
-
16
Open
DUMMYR1~R2
-
2
-
Dummy pads. Please open this pin.
Connect these pins to the capacitors for the step-up circuit 2. According
to the step-up rate. When not using the step-up circuit2, disconnect
them.
When it Operates in system interface mode, This pin (DB0) is used on
bi-directional data bus.
For serial interface, this pin (SDA) is for serial data pin when operate on
serial data transfer interface mode of Command-parameter Interface
mode. Data would be latched on the rising edge of the SCL signal. Let it
open if this pin is not used.
When Operates in system interface mode, it is used liked an 18-bit
bi-directional data bus.
8-bit bus: use DB17-DB10
9-bit bus: use DB17-DB9
16-bit bus: use DB17-DB10 and DB8-DB1
18-bit bus: use DB17-DB0
6-bit bus: use PD17-PD12
16-bit bus: use PD17-PD13 and PD11-PD1
18-bit bus: use PD17-PD0
Let unused data pins open.
Dummy pads. Disconnect them.
Dummy pads. Available for measuring the COG contact resistance.
DUMMYR1 and DUMMYR2 are short-circuited within the chip.
Power Part
Pin
Connected
Description
Number
with
1
Power supply Power supply for interface pin. VDDI = 1.65 ~3.3 V.
1
Power supply Ground for the logic side. VSSD = 0V
Signals
I/O
VDDI
VSSD
P
P
VSSA
P
1
VDD
P
1
Analog ground. VSSA = 0V. When using the COG method, connect to
Power supply VSSD on the FPC to prevent noise.
Power supply A power supply for the analog circuit. VDD = 2.3 ~ 3.3V
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.15February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4.2 Pin assignment
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.16February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4.3 PAD Coordinate
No. PAD NAME
X
Y
-4750
-231
1
Dummy
2
IOVCC
-4700
-231
3
EXTC
-4650
-231
4
VSSD
-4600
-231
5
BS0
-4550
-231
6
IOVCC
-4500
-231
7
BS1
-4450
-231
8
VSSD
-4400
-231
9
P68
-4350
-231
10
IOVCC
-4300
-231
11
Dummy
-4250
-231
12
VSSD
-4200
-231
13
Dummy
-4150
-231
14
IOVCC
-4100
-231
15
BGR_PANEL -4050
-231
16
VSSD
-4000
-231
17
SS_PANEL
-3950
-231
18
IOVCC
-3900
-231
19
GS_PANEL
-3850
-231
20
VSSD
-3800
-231
21
VDCENB
-3750
-231
22
IOVCC
-3700
-231
23
REV_PANEL -3650
-231
24
VSSD
-3600
-231
25
Dummy
-3550
-231
26
IOVCC
-3500
-231
27
TEST3
-3450
-231
28
VSSD
-3400
-231
29
BURN
-3350
-231
30
IOVCC
-3300
-231
31
LC_SEL0
-3250
-231
32
VSSD
-3200
-231
33
LC_SEL1
-3150
-231
34
IOVCC
-3100
-231
35
RSO2
-3050
-231
36
VSSD
-3000
-231
37
RSO1
-2950
-231
38
IOVCC
-2900
-231
39
RSO0
-2850
-231
40
VSSD
-2800
-231
41
Dummy
-2750
-231
42
GC_SEL
-2700
-231
43
SPI_SEL
-2650
-231
44
IOVCC
-2600
-231
45
TS[6]
-2550
-231
46
TS[5]
-2500
-231
47
TS[4]
-2450
-231
48
TS[3]
-2400
-231
49
TEST1
-2350
-231
50
OSC
-2300
-231
51
VCI
-2250
-231
52
VCI
-2200
-231
53
VCI
-2150
-231
54
VCI
-2100
-231
55
VCI
-2050
-231
56
VCI
-2000
-231
57
VSSA
-1950
-231
58
VSSA
-1900
-231
59
VSSA
-1850
-231
60
VSSA
-1800
-231
61
VSSA
-1750
-231
62
VSSA
-1700
-231
63
NRD_E
-1630
-231
64
DNC_SCL
-1570
-231
65
STE_SEL
-1510
-231
66
VSSD
-1450
-231
67
DB17
-1390
-231
68
DB16
-1330
-231
69
DB15
-1270
-231
70
DB14
-1210
-231
Bump Size
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
I/O Pad
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
No.
PAD NAME
X
Y
71
DB13
-1150
-231
72
DB12
-1090
-231
73
DB11
-1030
-231
74
DB10
-970
-231
75
DB9
-910
-231
76
DB8
-850
-231
77
DB1
-790
-231
78
DB3
-730
-231
79
DB5
-670
-231
80
DB7
-610
-231
81
TE
-550
-231
82
NRESET
-490
-231
83
NCS
-430
-231
84
DB6
-370
-231
85
DB4
-310
-231
86
DB2
-250
-231
87
BS2
-190
-231
88
DB0_SDA
-130
-231
89
NWR_RNW
-70
-231
90
Dummy
0
-231
91
Dummy
50
-231
92
Dummy
100
-231
93
Dummy
150
-231
94
TS[2]
200
-231
95
TS[1]
250
-231
96
TS[0]
300
-231
97
VSSD
350
-231
98
VSSD
400
-231
99
VSSD
450
-231
100
VSSD
500
-231
101
VSSD
550
-231
102
VSSD
600
-231
103
IOVCC
650
-231
104
IOVCC
700
-231
105
IOVCC
750
-231
106
IOVCC
800
-231
107
IOVCC
850
-231
108
IOVCC
900
-231
109
VDDD
950
-231
110
VDDD
1000
-231
111
VDDD
1050
-231
112
Dummy
1100
-231
113
Dummy
1150
-231
114
Dummy
1200
-231
115
VREF
1250
-231
116
VREF
1300
-231
117
VREF
1350
-231
118
TEST2
1400
-231
119
VTESTOUT
1450
-231
120
VLCD(DDVDH) 1500
-231
121
VLCD(DDVDH) 1550
-231
122
VLCD(DDVDH) 1600
-231
123
VLCD(DDVDH) 1650
-231
124
VLCD(DDVDH) 1700
-231
125
VREG1OUT
1750
-231
126
VREG1OUT
1800
-231
127
VREG1OUT
1850
-231
128
DUMMYR1
1900
-231
129
DUMMYR2
1950
-231
130
C11A
2000
-231
131
C11A
2050
-231
132
C11A
2100
-231
133
C11A
2150
-231
134
C11B
2200
-231
135
C11B
2250
-231
136
C11B
2300
-231
137
C11B
2350
-231
138
Dummy
2400
-231
139
Dummy
2450
-231
140
Dummy
2500
-231
Bump Size
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
40 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
I/O Pad
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Input
Input
Input
Output
Output
Output
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
No.
PAD NAME
X
Y
141
Dummy
2550
-231
142
Dummy
2600
-231
143
Dummy
2650
-231
144
Dummy
2700
-231
145
Dummy
2750
-231
146
VSSA
2800
-231
147
VSSA
2850
-231
148
VSSA
2900
-231
149
VCL
2950
-231
150
VCL
3000
-231
151
VCL
3050
-231
152
C21A
3100
-231
153
C21A
3150
-231
154
C21A
3200
-231
155
C21B
3250
-231
156
C21B
3300
-231
157
C21B
3350
-231
158
C22A
3400
-231
159
C22A
3450
-231
160
C22A
3500
-231
161
C22B
3550
-231
162
C22B
3600
-231
163
C22B
3650
-231
164
C12A
3700
-231
165
C12A
3750
-231
166
C12A
3800
-231
167
C12B
3850
-231
168
C12B
3900
-231
169
C12B
3950
-231
170
VGL
4000
-231
171
VGL
4050
-231
172
VGL
4100
-231
173
VGH
4150
-231
174
VGH
4200
-231
175
VGH
4250
-231
176
VCOMH
4300
-231
177
VCOMH
4350
-231
178
VCOMH
4400
-231
179
VCOML
4450
-231
180
VCOML
4500
-231
181
VCOML
4550
-231
182
VCOM
4600
-231
183
VCOM
4650
-231
184
VCOM
4700
-231
185
DUMMY
4750
-231
186
DUMMY
4772
110
187
DUMMY
4756
227
188
G162
4740
110
189
G160
4724
227
190
G158
4708
110
191
G156
4692
227
192
G154
4676
110
193
G152
4660
227
194
G150
4644
110
195
G148
4628
227
196
G146
4612
110
197
G144
4596
227
198
G142
4580
110
199
G140
4564
227
200
G138
4548
110
201
G136
4532
227
202
G134
4516
110
203
G132
4500
227
204
G130
4484
110
205
G128
4468
227
206
G126
4452
110
207
G124
4436
227
208
G122
4420
110
209
G120
4404
227
210
G118
4388
110
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
Bump Size
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
35 X 90
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
I/O Pad
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
-P.17February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
No. PAD NAME
X
Y
211
G116
4372
227
212
G114
4356
110
213
G112
4340
227
214
G110
4324
110
215
G108
4308
227
216
G106
4292
110
217
G104
4276
227
218
G102
4260
110
219
G100
4244
227
220
G98
4228
110
221
G96
4212
227
222
G94
4196
110
223
G92
4180
227
224
G90
4164
110
225
G88
4148
227
226
G86
4132
110
227
G84
4116
227
228
G82
4100
110
229
G80
4084
227
230
G78
4068
110
231
G76
4052
227
232
G74
4036
110
233
G72
4020
227
234
G70
4004
110
235
G68
3988
227
236
G66
3972
110
237
G64
3956
227
238
G62
3940
110
239
G60
3924
227
240
G58
3908
110
241
G56
3892
227
242
G54
3876
110
243
G52
3860
227
244
G50
3844
110
245
G48
3828
227
246
G46
3812
110
247
G44
3796
227
248
G42
3780
110
249
G40
3764
227
250
G38
3748
110
251
G36
3732
227
252
G34
3716
110
253
G32
3700
227
254
G30
3684
110
255
G28
3668
227
256
G26
3652
110
257
G24
3636
227
258
G22
3620
110
259
G20
3604
227
260
G18
3588
110
261
G16
3572
227
262
G14
3556
110
263
G12
3540
227
264
G10
3524
110
265
G8
3508
227
266
G6
3492
110
267
G4
3476
227
268
G2
3460
110
269
DUMMY
3444
227
270
DUMMY
3428
110
271
DUMMY
3412
227
272
DUMMY
3396
110
273
S396
3380
227
274
S395
3364
110
275
S394
3348
227
276
S393
3332
110
277
S392
3316
227
278
S391
3300
110
279
S390
3284
227
280
S389
3268
110
Bump Size
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
I/O Pad
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
No.
PAD NAME
X
Y
281
S388
3252
227
282
S387
3236
110
283
S386
3220
227
284
S385
3204
110
285
S384
3188
227
286
S383
3172
110
287
S382
3156
227
288
S381
3140
110
289
S380
3124
227
290
S379
3108
110
291
S378
3092
227
292
S377
3076
110
293
S376
3060
227
294
S375
3044
110
295
S374
3028
227
296
S373
3012
110
297
S372
2996
227
298
S371
2980
110
299
S370
2964
227
300
S369
2948
110
301
S368
2932
227
302
S367
2916
110
303
S366
2900
227
304
S365
2884
110
305
S364
2868
227
306
S363
2852
110
307
S362
2836
227
308
S361
2820
110
309
S360
2804
227
310
S359
2788
110
311
S358
2772
227
312
S357
2756
110
313
S356
2740
227
314
S355
2724
110
315
S354
2708
227
316
S353
2692
110
317
S352
2676
227
318
S351
2660
110
319
S350
2644
227
320
S349
2628
110
321
S348
2612
227
322
S347
2596
110
323
S346
2580
227
324
S345
2564
110
325
S344
2548
227
326
S343
2532
110
327
S342
2516
227
328
S341
2500
110
329
S340
2484
227
330
S339
2468
110
331
S338
2452
227
332
S337
2436
110
333
S336
2420
227
334
S335
2404
110
335
S334
2388
227
336
S333
2372
110
337
S332
2356
227
338
S331
2340
110
339
S330
2324
227
340
S329
2308
110
341
S328
2292
227
342
S327
2276
110
343
S326
2260
227
344
S325
2244
110
345
S324
2228
227
346
S323
2212
110
347
S322
2196
227
348
S321
2180
110
349
S320
2164
227
350
S319
2148
110
Bump Size
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
I/O Pad
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
No.
PAD NAME
X
Y
351
S318
2132
227
352
S317
2116
110
353
S316
2100
227
354
S315
2084
110
355
S314
2068
227
356
S313
2052
110
357
S312
2036
227
358
S311
2020
110
359
S310
2004
227
360
S309
1988
110
361
S308
1972
227
362
S307
1956
110
363
S306
1940
227
364
S305
1924
110
365
S304
1908
227
366
S303
1892
110
367
S302
1876
227
368
S301
1860
110
369
S300
1844
227
370
S299
1828
110
371
S298
1812
227
372
S297
1796
110
373
S296
1780
227
374
S295
1764
110
375
S294
1748
227
376
S293
1732
110
377
S292
1716
227
378
S291
1700
110
379
S290
1684
227
380
S289
1668
110
381
S288
1652
227
382
S287
1636
110
383
S286
1620
227
384
S285
1604
110
385
S284
1588
227
386
S283
1572
110
387
S282
1556
227
388
S281
1540
110
389
S280
1524
227
390
S279
1508
110
391
S278
1492
227
392
S277
1476
110
393
S276
1460
227
394
S275
1444
110
395
S274
1428
227
396
S273
1412
110
397
S272
1396
227
398
S271
1380
110
399
S270
1364
227
400
S269
1348
110
401
S268
1332
227
402
S267
1316
110
403
S266
1300
227
404
S265
1284
110
405
S264
1268
227
406
S263
1252
110
407
S262
1236
227
408
S261
1220
110
409
S260
1204
227
410
S259
1188
110
411
S258
1172
227
412
S257
1156
110
413
S256
1140
227
414
S255
1124
110
415
S254
1108
227
416
S253
1092
110
417
S252
1076
227
418
S251
1060
110
419
S250
1044
227
420
S249
1028
110
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
Bump Size
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
I/O Pad
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
-P.18February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
No. PAD NAME
X
Y
421
S248
1012
227
422
S247
996
110
423
S246
980
227
424
S245
964
110
425
S244
948
227
426
S243
932
110
427
S242
916
227
428
S241
900
110
429
S240
884
227
430
S239
868
110
431
S238
852
227
432
S237
836
110
433
S236
820
227
434
S235
804
110
435
S234
788
227
436
S233
772
110
437
S232
756
227
438
S231
740
110
439
S230
724
227
440
S229
708
110
441
S228
692
227
442
S227
676
110
443
S226
660
227
444
S225
644
110
445
S224
628
227
446
S223
612
110
447
S222
596
227
448
S221
580
110
449
S220
564
227
450
S219
548
110
451
S218
532
227
452
S217
516
110
453
S216
500
227
454
S215
484
110
455
S214
468
227
456
S213
452
110
457
S212
436
227
458
S211
420
110
459
S210
404
227
460
S209
388
110
461
S208
372
227
462
S207
356
110
463
S206
340
227
464
S205
324
110
465
S204
308
227
466
S203
292
110
467
S202
276
227
468
S201
260
110
469
S200
244
227
470
S199
228
110
471
DUMMY
212
227
472
DUMMY
196
110
473
DUMMY
-196
110
474
DUMMY
-212
227
475
S198
-228
110
476
S197
-244
227
477
S196
-260
110
478
S195
-276
227
479
S194
-292
110
480
S193
-308
227
481
S192
-324
110
482
S191
-340
227
483
S190
-356
110
484
S189
-372
227
485
S188
-388
110
486
S187
-404
227
487
S186
-420
110
488
S185
-436
227
489
S184
-452
110
490
S183
-468
227
Bump Size
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
I/O Pad
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
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Output
Output
Output
Output
Output
Output
No.
PAD NAME
X
Y
491
S182
-484
110
492
S181
-500
227
493
S180
-516
110
494
S179
-532
227
495
S178
-548
110
496
S177
-564
227
497
S176
-580
110
498
S175
-596
227
499
S174
-612
110
500
S173
-628
227
501
S172
-644
110
502
S171
-660
227
503
S170
-676
110
504
S169
-692
227
505
S168
-708
110
506
S167
-724
227
507
S166
-740
110
508
S165
-756
227
509
S164
-772
110
510
S163
-788
227
511
S162
-804
110
512
S161
-820
227
513
S160
-836
110
514
S159
-852
227
515
S158
-868
110
516
S157
-884
227
517
S156
-900
110
518
S155
-916
227
519
S154
-932
110
520
S153
-948
227
521
S152
-964
110
522
S151
-980
227
523
S150
-996
110
524
S149
-1012
227
525
S148
-1028
110
526
S147
-1044
227
527
S146
-1060
110
528
S145
-1076
227
529
S144
-1092
110
530
S143
-1108
227
531
S142
-1124
110
532
S141
-1140
227
533
S140
-1156
110
534
S139
-1172
227
535
S138
-1188
110
536
S137
-1204
227
537
S136
-1220
110
538
S135
-1236
227
539
S134
-1252
110
540
S133
-1268
227
541
S132
-1284
110
542
S131
-1300
227
543
S130
-1316
110
544
S129
-1332
227
545
S128
-1348
110
546
S127
-1364
227
547
S126
-1380
110
548
S125
-1396
227
549
S124
-1412
110
550
S123
-1428
227
551
S122
-1444
110
552
S121
-1460
227
553
S120
-1476
110
554
S119
-1492
227
555
S118
-1508
110
556
S117
-1524
227
557
S116
-1540
110
558
S115
-1556
227
559
S114
-1572
110
560
S113
-1588
227
Bump Size
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
I/O Pad
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
No.
PAD NAME
X
Y
561
S112
-1604
110
562
S111
-1620
227
563
S110
-1636
110
564
S109
-1652
227
565
S108
-1668
110
566
S107
-1684
227
567
S106
-1700
110
568
S105
-1716
227
569
S104
-1732
110
570
S103
-1748
227
571
S102
-1764
110
572
S101
-1780
227
573
S100
-1796
110
574
S99
-1812
227
575
S98
-1828
110
576
S97
-1844
227
577
S96
-1860
110
578
S95
-1876
227
579
S94
-1892
110
580
S93
-1908
227
581
S92
-1924
110
582
S91
-1940
227
583
S90
-1956
110
584
S89
-1972
227
585
S88
-1988
110
586
S87
-2004
227
587
S86
-2020
110
588
S85
-2036
227
589
S84
-2052
110
590
S83
-2068
227
591
S82
-2084
110
592
S81
-2100
227
593
S80
-2116
110
594
S79
-2132
227
595
S78
-2148
110
596
S77
-2164
227
597
S76
-2180
110
598
S75
-2196
227
599
S74
-2212
110
600
S73
-2228
227
601
S72
-2244
110
602
S71
-2260
227
603
S70
-2276
110
604
S69
-2292
227
605
S68
-2308
110
606
S67
-2324
227
607
S66
-2340
110
608
S65
-2356
227
609
S64
-2372
110
610
S63
-2388
227
611
S62
-2404
110
612
S61
-2420
227
613
S60
-2436
110
614
S59
-2452
227
615
S58
-2468
110
616
S57
-2484
227
617
S56
-2500
110
618
S55
-2516
227
619
S54
-2532
110
620
S53
-2548
227
621
S52
-2564
110
622
S51
-2580
227
623
S50
-2596
110
624
S49
-2612
227
625
S48
-2628
110
626
S47
-2644
227
627
S46
-2660
110
628
S45
-2676
227
629
S44
-2692
110
630
S43
-2708
227
Bump Size
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
I/O Pad
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
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Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
-P.19February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
No.
PAD NAME
X
Y
631
S42
-2724
110
632
S41
-2740
227
633
S40
-2756
110
634
S39
-2772
227
635
S38
-2788
110
636
S37
-2804
227
637
S36
-2820
110
638
S35
-2836
227
639
S34
-2852
110
640
S33
-2868
227
641
S32
-2884
110
642
S31
-2900
227
643
S30
-2916
110
644
S29
-2932
227
645
S28
-2948
110
646
S27
-2964
227
647
S26
-2980
110
648
S25
-2996
227
649
S24
-3012
110
650
S23
-3028
227
651
S22
-3044
110
652
S21
-3060
227
653
S20
-3076
110
654
S19
-3092
227
655
S18
-3108
110
656
S17
-3124
227
657
S16
-3140
110
658
S15
-3156
227
659
S14
-3172
110
660
S13
-3188
227
661
S12
-3204
110
662
S11
-3220
227
663
S10
-3236
110
664
S9
-3252
227
665
S8
-3268
110
666
S7
-3284
227
667
S6
-3300
110
668
S5
-3316
227
669
S4
-3332
110
670
S3
-3348
227
671
S2
-3364
110
672
S1
-3380
227
673
DUMMY
-3396
110
674
DUMMY
-3412
227
675
DUMMY
-3428
110
676
DUMMY
-3444
227
677
G1
-3460
110
678
G3
-3476
227
679
G5
-3492
110
680
G7
-3508
227
681
G9
-3524
110
682
G11
-3540
227
683
G13
-3556
110
684
G15
-3572
227
685
G17
-3588
110
686
G19
-3604
227
687
G21
-3620
110
688
G23
-3636
227
689
G25
-3652
110
690
G27
-3668
227
691
G29
-3684
110
692
G31
-3700
227
693
G33
-3716
110
694
G35
-3732
227
695
G37
-3748
110
696
G39
-3764
227
697
G41
-3780
110
698
G43
-3796
227
699
G45
-3812
110
700
G47
-3828
227
Bump Size
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
Alignment mark
X
Y
A1
A2
-4841
4841
-220
-220
I/O Pad
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
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Output
Output
Output
Output
Output
Output
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Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
No.
PAD NAME
X
Y
701
G49
-3844
110
702
G51
-3860
227
703
G53
-3876
110
704
G55
-3892
227
705
G57
-3908
110
706
G59
-3924
227
707
G61
-3940
110
708
G63
-3956
227
709
G65
-3972
110
710
G67
-3988
227
711
G69
-4004
110
712
G71
-4020
227
713
G73
-4036
110
714
G75
-4052
227
715
G77
-4068
110
716
G79
-4084
227
717
G81
-4100
110
718
G83
-4116
227
719
G85
-4132
110
720
G87
-4148
227
721
G89
-4164
110
722
G91
-4180
227
723
G93
-4196
110
724
G95
-4212
227
725
G97
-4228
110
726
G99
-4244
227
727
G101
-4260
110
728
G103
-4276
227
729
G105
-4292
110
730
G107
-4308
227
731
G109
-4324
110
732
G111
-4340
227
733
G113
-4356
110
734
G115
-4372
227
735
G117
-4388
110
736
G119
-4404
227
737
G121
-4420
110
738
G123
-4436
227
739
G125
-4452
110
740
G127
-4468
227
741
G129
-4484
110
742
G131
-4500
227
743
G133
-4516
110
744
G135
-4532
227
745
G137
-4548
110
746
G139
-4564
227
747
G141
-4580
110
748
G143
-4596
227
749
G145
-4612
110
750
G147
-4628
227
751
G149
-4644
110
752
G151
-4660
227
753
G153
-4676
110
754
G155
-4692
227
755
G157
-4708
110
756
G159
-4724
227
757
G161
-4740
110
758
DUMMY
-4756
227
759
DUMMY
-4772
110
Bump Size
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
16 X 98
I/O Pad
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
No.
PAD NAME
X
Y
Bump Size I/O Pad
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.20February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4.4 Alignment mark
A_MARK (A1)
10 um 5um
15 um
10 um
15 um
5 um
20 um
15 um
15 um
15um 15 um 20um 15 um
15 um
A_MARK (A2)
5 um 10 um
15 um
10um
15 um
5 um
20um
15um
15um
15 um 15 um 20 um 15um
15um
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.21February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4.5 Bump arrangement
90um
35X90
50um
35um
Input/Output
PAD
90um
40X90
60um
40um
Note: 35X90 : Pad no. 1~62
Pad no. 90~185
40X90: pad no. 63~89
16u
m
19um
Output PAD
98u
m
16 X 98
32u
m
Note: 16X98 : Pad no.186~759
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.22February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5. Function Description
5.1 System Interface
The HX8353-C supports parallel 80-system and 68-system 18-/16-/9-/8-bits bus bus
interface mode and 3W/4W serial interface mode. When NCS = “L”, the parallel and
serial bus system interface of the HX8353-C become active and data transfer through
the interface circuit is available. The DNC_ SCL pin specifies whether the system
interface circuit access is to the register command or to the GRAM. The input bus width
format of system interface circuit is selected by external pins BS(2-0). For selecting the
format of input bus, please refer to Table 5.1 and Table 5.2.
HX8353-C includes command code and the following parameter and GRAM data. The
command code can be written through data bus by setting DNC_ SCL=0. Then the
command or GRAM data can be written to register at which that index pointer pointed by
setting DNC_ SCL=1.
Furthermore, there are two 18-bit bus control registers used to temporarily store the data
written to or read from the GRAM. When the data is written into the GRAM from the
MPU, it is first written into the write-data latch and then automatically written into the
GRAM by internal operation. Data is read through the read-data latch when reading from
the GRAM. Therefore, the first read data operation is invalid and the following read data
operations are valid.
SPI_SEL
P68
x
x
0
0
0
0
1
1
1
1
x
x
x
x
x
x
x
x
0
1
BS2
BS1
BS0
1
0
0
1
0
1
1
1
0
1
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
x
x
0
x
x
Table 5. 1 Interface selection
Interface
E_NRD
RW_NWR
DNC_SCL
SDA
80-system 8-bit Parallel
NRD
NWR
DNC
Unused
80-system 9-bit Parallel
NRD
NWR
DNC
Unused
80-system 16-bit Parallel
NRD
NWR
DNC
Unused
80-system 18-bit Parallel
3 wire serial Interface
NRD
Unused
NWR
--
DNC
SCL
Unused
SDA
68-system 8-bit Parallel
E
RW
DNC
Unused
68-system 9-bit Parallel
E
RW
DNC
Unused
68-system 16-bit Parallel
E
RW
DNC
Unused
68-system 18-bit Parallel
4 wire serial Interface
E
Unused
RW
DNC
DNC
SCL
Unused
SDA
Interface
80-system 8-bit Parallel
80-system 16-bit Parallel
80-system 9-bit Parallel
80-system 18-bit Parallel
68-system 8-bit Parallel
68-system 16-bit Parallel
68-system 9-bit Parallel
68-system 18-bit Parallel
3 wire serial Interface only
4 wire serial Interface only
D17 – D0
DB17-DB8: Unused,
DB7-DB0: 8 bit data bus
DB17-DB9: Unused,
DB8-DB0: 9 bit data bus
DB17-DB16: Unused,
DB15-DB0: 16 bit data bus
DB17-DB0: 18 bit data bus
Unused
DB17-D8: Unused,
DB7-DB0: 8 bit data bus
DB17-D9: Unused,
DB8-DB0: 9 bit data bus
DB17-DB16: Unused,
D15-DB0: 16 bit data bus
DB17-DB0: 18 bit data bus
Unused
Table 5. 2 Interface Mode Selection
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.23February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.1.1 Parallel Bus System Interface
The input / output data from data pins (D17-0) and signal operation of the I80/M68 series
parallel bus interface as listed in Table 5.3 and Table 5.4.
Operations
NWR_RNW
NRD_E
Writes command code
0
1
Reads internal status
1
0
Writes parameter into command or data into GRAM
0
1
Reads parameter from command or data from GRAM
1
0
Table 5. 3 Data Pin Function for I80 Series CPU
DNC_SCL
0
0
1
1
Operations
NWR_RNW
NRD_E
Writes command code
1
0
Reads internal status
1
1
Writes parameter into command or data into GRAM
1
0
Reads parameter from command or data from GRAM
1
1
Table 5. 4 Data Pin Function for M68 Series CPU
DNC_SCL
0
0
1
1
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.24February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Write to register
1 byte command
2
S
CMD
byte command
CMD
PA1
n byte command
CMD
PA1
PAn-3
PAn-2
PA n-1
CMD
PA1
PAn-3
PAn-2
PA n-1
NCS
DNC_SCL
NRD_E
NWR_RNW
HOST D7-0
(MPU to LCD)
CMD
Driver D7-0
( LCD to MPU)
CMD
PA1
Hi - Z
CMD: command code
PA: parameter
Read from register
2 byte command
S
n byte command
CMD
dummy
PA1
CMD
dummy
CMD
dummy
PA1
CMD
dummy
PA1
PAn-3
PAn-2
PAn-1
PAn-3
PAn-2
PAn-1
PAn-3
PAn-2
PAn-1
NCS
DNC _ SCL
NRD_E
NWR_RNW
D7-0
HOST D7-0
( MPU to LCD )
Driver D7-0
( LCD to MPU)
CMD
Hi-Z
Hi-Z
dummy
CMD : command code
PA1
Hi-Z
CMD
PA1
Hi-Z
Hi-Z
dummy
PA1
Hi-Z
PA: parameter
Figure 5. 1 Register Read/Write Timing in Parallel Bus System Interface (for I80 series MPU)
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.25February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Write to register
1 byte command
2 byte command
S
CMD
CMD
CMD
CMD
PA1
n byte command
CMD
PA1
PAn-3
PAn-2
PA n-1
CMD
PA1
PAn-3
PAn-2
PA n-1
NCS
DNC_SCL
NWR_RNW
NRD_E
HOST D7-0
(MPU to LCD)
PA1
H
-Z
i
Driver D7-0
(LCD to MPU)
CMD : command code
PA: parameter
Read from register
2 byte command
S
n byte command
CMD
dummy
PA1
CMD
dummy
CMD
dummy
PA1
CMD
dummy
PA1
PAn-3
PAn-2
PA n-1
NCS
DNC _ SCL
NWR_RNW
NRD_E
DB 7 -0
HOST D7-0
( MPU to LCD )
Driver D7-0
(LCD to MPU)
Hi-Z
CMD
Hi-Z
dummy
CMD : command code
PA1
Hi-Z
PAn-3
PAn-2
PA n-1
PAn-3
PAn-2
PA n-1
Hi-Z
CMD
PA1
Hi-Z
dummy
PA1
Hi-Z
PA: parameter
Figure 5. 2 Register Read/Write Timing in Parallel Bus System Interface (for M68 series MPU)
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.26February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Write to GRAM
n pixel RAM data write
S
2Ch
Data 1
Data n-2
Data n-1
Data n
2Ch
Data 1
Data n-2
Data n-1
Data n
NCS
DNC_SCL
NRD_E
NWR_RNW
(MPU to LCD)
Hi - Z
(LCD to MPU )
CMD: command code
PA: parameter
Read from GRAM
n pixel RAM data read
S
2Eh
dummy
Data 1
2Eh
dummy
Data1
Data n-2
Data n-1
Data n
Data n-2
Data n-1
Data n
NCS
DNC _ SCL
NRD_E
NWR_WNR
( MPU to LCD )
(LCD to MPU)
Hi - Z
2Eh
Hi - Z
Hi - Z
dummy
Data 1
Hi - Z
Data n-2
Data n-1
Data n
Figure 5. 3 GRAM Read/Write Timing in Parallel Bus System Interface (for I80 series MPU)
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.27February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Write to GRAM
n pixel RAM data write
S
2Ch
Data 1
Data n-2
Data n-1
Data n
2Ch
Data 1
Data n-2
Data n-1
Data n
NCS
DNC_SCL
NWR_RNW
NRD_E
(MPU to LCD)
Hi - Z
(LCD to MPU)
CMD: command code
PA: parameter
Read from GRAM
n pixel RAM data read
S
2Eh
dummy
Data 1
2Eh
dummy
Data1
Data n-1
Data n
Data n-2
Data n-1
Data n
Data n-2
Data n-1
Data n
Data n-2
NCS
DNC _ SCL
NWR_RNW
NRD_E
( MPU to LCD )
(LCD to MPU)
Hi - Z
2Eh
Hi - Z
Hi - Z
dummy
Data 1
Hi - Z
:
Figure 5. 4 GRAM Read/Write Timing in Parallel Bus System Interface (for M68 series MPU)
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.28February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8-bit bus Interface
The I80-system 8-bit parallel bus interface can be used by setting external pins “P68,
BS2, BS1, BS0” pins to “0100”. And the M68-system 8-bit parallel bus interface can
be used by setting “P68, BS2, BS1, and BS0” pins to “1100”. Figure 5.5 is the
example of interface with I80/M68 microcomputer system interface and Figure 5.6
~Figure 5.9 is bit format per pixel color order.
Figure 5. 5 Example of 80- / 68- System 8-bit bus Interface
The data format of write display data at 8-bit bus Interface. See Figure 5.6 ~Figure
5.9.
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.29February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
262k Color
Data
MEMWR
1st write
2nd write
3rd write
4th write
5th write
6th write
DNC/
RS
0
1
1
1
1
1
1
D7
R15
G15
B15
R25
G25
B25
D6
D5
D4
D3
D2
D1
GRAM Write command code
R14 R13 R12 R11 R10
x
G14 G13 G12 G11 G10 x
B14 B13 B12 B11 B10
x
R24 R23 R22 R21 R20
x
G24 G23 G22 G21 G20 x
B24 B23 B22 B21 B20
x
18-bit
D0
GRAM Write
x
x
x
x
x
x
1st pixel (R1/G1/B1)
2nd pixel (R2/G2/B2)
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5. 6 Write data for RGB 6-6-6-bits input (support DMIF-S43AP-J124 and LUT_EN=1)
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.30February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4k Color
Data
MEMWR
1st write
2nd write
3rd write
DNC/
RS
0
1
1
1
D7
D6
D5
D4
D3
D2
D1
D0
GRAM Write command code
R13 R12 R11 R10 G13 G12 G11 G10
B13 B12 B11 B10 R23 R22 R21 R20
G23 G22 G21 G20 B23 B22 B21 B20
GRAM Write
1st pixel (R1/G1/B1)
2nd pixel (R2/G2/B2)
12-bit
12-bit
Look-Up Table for 4k Color data mapping (12-bit to 18-bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5. 7 Write data for RGB 4-4-4-bits input (support Look-up table and LUT_EN=0)
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.31February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6 5 k C o lo r
D a ta
MEMW R
1 s t w r ite
2 n d w r ite
3 r d w r ite
4 th w r ite
DNC/
RS
0
1
1
1
1
D7
D6
R 14
G 12
R 24
G 22
D5
D4
D3
D2
D1
G R A M W r ite c o m m a n d c o d e
R13 R 12 R11 R10 G 15 G 14
G 11 G 10 B14 B13 B12 B11
R23 R 22 R21 R20 G 25 G 24
G 21 G 20 B24 B23 B22 B21
1 6 - b it
D0
G R A M W r ite
G 13
B10
G 23
B20
1 s t p ix e l ( R 1 /G 1 /B 1 )
2 n d p ix e l (R 2 /G 2 /B 2 )
1 6 - b it
L o o k - U p T a b le fo r 6 5 k C o lo r d a ta m a p p in g ( 1 6 - b it to 1 8 - b it )
1 8 - b it
1 8 - b it
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5. 8 Write data for RGB 5-6-5-bits input (support Look-up table and LUT_EN=0)
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.32February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
16-bit Parallel Bus System Interface
The I80-system 16-bit parallel bus interface in command-parameter interface mode
can be used by setting external pins “P68, BS2, BS1, BS0” pins to “0101”. And the
M68-system 16-bit parallel bus interface in MPU interface mode can be used by
setting “P68, BS2, BS1”pins to “1101”. The Figure 5.9 is the example of interface with
I80/M68 microcomputer system interface. There are three types of data format to
write display data at 18-bit bus Interface. See Figure 5.10 Figure 5.12.
Figure 5. 9 Example of I80- / M68- System 16-bit Parallel Bus Interface
Figure 5. 10 GRAM Write Data for RGB 6-6-6-(262k colours) bits input (LUT_EN=1)
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.33February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4k Color
Data
DNC/R
S
MEMWR
1st write
2nd write
0
1
1
D15
D14
D13
D12
D11
D10
D9
D8
D7
D4
D3
D2
D1
D0
GRAM Write
x
x
x
x
x
x
x
x
R13
R23
GRAM Write command code
R12 R11 R10 G13 G12 G11 G10
R22 R21 R20 G23 G22 G21 G20
B13
B23
B12
B22
B11
B21
B10
B20
1st pixel (R1/G1/B1)
2nd pixel (R2/G2/B2)
12-bit
D6
D5
12-bit
Look-Up Table for 4k Color data mapping (12-bit to 18-bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5. 11 Write data for RGB 4-4-4 (4k colours) bits input on 16-bit parallel Interface (when support
Look-up table and LUT_EN=0)
65k Color
Data
DNC/R
S
D15
D14
D13
D12
D11
D1
D0
GRAM Write
MEMWR
1st write
2nd write
0
1
1
x
R14
R24
x
R13
R23
x
R12
R22
x
R11
R21
x
x
x
x
GRAM Write command code
R10 G15 G14 G13 G12 G11 G10 B14 B13 B12 B11
R20 G25 G24 G23 G22 G21 G20 B24 B23 B22 B21
B10
B20
1st pixel (R1/G1/B1)
2nd pixel (R2/G2/B2)
D10
D9
D8
D7
16-bit
D6
D5
D4
D3
D2
16-bit
Look-Up Table for 65k Color data mapping (16-bit to 18-bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5. 12 Write data for RGB 5-6-5 (65k colours) bits input on 16-bit parallel Interface (when support
Look-up table and LUT_EN=0)
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in whole or in part without prior written permission of Himax.
-P.34February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
18-bit Parallel Bus System Interface
The I80-system 18-bit parallel bus interface in MPU interface mode can be used by
setting external pins “P68, BS2, BS1, BS0” pins to “0111”. And the M68-system 18-bit
parallel bus interface in MPU interface mode can be used by setting “P68, BS2, BS1,
BS0” pins to “1111”. The Figure5.13 is the example of interface with I80/M68
microcomputer system
interface.
Figure 5. 13 Example of I80- / M68- System 18-bit Parallel Bus Interface
There are three types of data format to write display data at 18-bit bus Interface. See
Figure 5.14 ~ Figure 5. 16.
4k Color
Data
MEMWR
1st write
2nd write
DNC/
RS
0
1
1
D17 D16 D15 D14 D13 D12 D11 D10 D9
x
x
x
x
x
x
x
x
x
x
x
x
D8
D7
D6
D5
D4
D3
D2
D1
D0
GRAM Write
GRAM Write command code
R13 R12 R11 R10 G13 G12 G11 G10 B13 B12 B11 B10 1st pixel (R1/G1/B1)
R23 R22 R21 R20 G23 G22 G21 G20 B23 B22 B21 B20 2nd pixel (R2/G2/B2)
12-bit
12-bit
Look-Up Table for 4k Color data mapping (12-bit to 18-bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5. 14 Write data for RGB 4-4-4 (4k colours) bits input in 18-bit parallel Interface (when support
Look-up table and LUTENB=0)
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.35February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
65k Color
DNC/RS D17
Data
MEMWR
1st write
2nd write
0
1
1
x
x
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
x
x
R14
R24
R13
R23
R12
R22
R11
R21
GRAM Write command code
R10 G15 G14 G13 G12 G11 G10
R20 G25 G24 G23 G22 G21 G20
16-bit
D6
D5
D4
D3
D2
D1
D0
GRAM Write
B14
B24
B13
B23
B12
B22
B11
B21
B10
B20
1st pixel (R1/G1/B1)
2nd pixel (R2/G2/B2)
16-bit
Look-Up Table for 65k Color data mapping (16-bit to 18-bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5. 15 Write data for RGB 5-6-5 (65k colours) bits input in 18-bit parallel Interface (when support
Look-up table and LUT_EN=0)
Figure 5. 16 Write data for RGB 6-6-6(262k colours) bits input in 18-bit parallel Interface (LUT_EN=1)
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.36February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
9-bit Bus Interface
The I80-system 9-bit parallel bus interface in MPU interface mode can be used by
setting external pins “P68, BS2, BS1, BS0” pins to “0110”. And the M68-system 9-bit
parallel bus interface in MPU interface mode can be used by setting “P68, BS2, BS1,
BS0” pins to “1110”. The Figure5.13 is the example of interface with I80/M68
microcomputer system interface.
NCS
DNC_SCL
MPU
NRD_E HX8353-C
NWR_RNW
/
DB8-0
9
Figure 5. 17 Example of 80- / 68- System 9-bit bus Interface
There are five types data format to write display data at 9-bit bus Interface. See
Figure 5. 18 ~ Figure 5. 22
4k Color
Data
DNC
D8
MEMWR
1st write
2nd write
3rd write
0
1
1
1
x
x
x
D7
D6
D5
D4
D3
D2
D1
D0
GRAM Write command code
R13 R12 R11 R10 G13 G12 G11 G10
B13 B12 B11 B10 R23 R22 R21 R20
G23 G22 G21 G20 B23 B22 B21 B20
GRAM Write
1st pixel (R1/G1/B1)
2nd pixel (R2/G2/B2)
12-bit
12-bit
Look-Up Table for 4k Color data mapping (12-bit to 18-bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5. 18 Write data for RGB 4-4-4 (4k colours) bits input in 9-bit parallel Interface (when support
Look-up table and LUT_EN=0)
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.37February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
65k Color
Data
DNC
D8
D7
MEMWR
1st write
2nd write
3rd write
4th write
0
1
1
1
1
x
x
x
x
R14
G12
R24
G22
D6
D5
D4
D3
D2
D1
D0
GRAM Write command code
R13 R12 R11 R10 G15 G14 G13
G11 G10 B14 B13 B12 B11 B10
R23 R22 R21 R20 G25 G24 G23
G21 G20 B24 B23 B22 B21 B20
16-bit
GRAM Write
1st pixel (R1/G1/B1)
2nd pixel (R2/G2/B2)
16-bit
Look-Up Table for 65k Color data mapping ( 16-bit to 18-bit )
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5. 19 Write data for RGB 5-6-5(65k colours) bits input in 9-bit parallel Interface (when support
Look-up table and LUT_EN=0)
262k Color
Data
DNC
MEMWR
1st write
2nd write
3rd write
4th write
0
1
1
1
1
D8
R15
G12
R25
G22
D7
R14
G11
R24
G21
D6
D5
D4
D3
D2
GRAM Write command code
R13 R12 R11 R10 G15
G10 B15 B14 B13 B12
R23 R22 R21 R20 G25
G20 B25 B24 B23 B22
18-bit
D1
D0
G14 G13
B11 B10
G24 G23
B21 B20
GRAM Write
1st pixel (R1/G1/B1)
2nd pixel (R2/G2/B2)
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5. 20 Write data for RGB 6-6-6-bits (262kcolours) input in 9-bit parallel Interface (LUT_EN=1)
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in whole or in part without prior written permission of Himax.
-P.38February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.1.2 Serial Interface
The HX8353-C supports serial data transfer interface. The interface selection by
setting BS2=0 for serial interface mode. The 3 wires serial bus and 4 wires serial bus
is select by SPI_SEL pin. When SPI_SEL pin is low (VSSD), it is selected by 3 wires
serial bus and use: chip select line (NCS), serial input/output data (SDA), and the
serial transfer clock line (DNC _SCL). When SPI_SEL pin is high (VDDI), it is selected
by 4 wires serial bus and use: chip select line (NCS), serial input/output data (SDA),
and the serial transfer clock line (DNC _SCL) and NWR_RNW.
Serial data write mode
The 3-Pin serial data packet contains a control bit DNC and a transmission byte and in
4-pin serial case, data packet contains just transmission byte and control bit DNC is
transferred by NWR_RNW pin. If NWR_RNW is low, the transmission byte is
command byte. If NWR_RNW is high, the transmission byte is stored to command
register or GRAM. The MSB is transmitted first. The serial interface is initialized when
NCS is high. In this state, DNC_SCL clock pulse or SDA data have no effect. A falling
edge on NCS enables the serial interface and indicates the start of data transmission.
3 wire Serial Data Stream Format
Transmission byte (TB) may be a Command or a Data
MSB
LSB
DNC D7 D6 D5 D4 D3 D2 D1 D0
TB
DNC
DNC
TB
DNC
TB
4 wire Serial Data Stream Format
Transmission byte (TB) may be a Command or a Data
MSB
LSB
D7 D6 D5 D4 D3 D2 D1 D0
TB
TB
TB
Figure 5. 21 Serial Interface protocol data stream format
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in whole or in part without prior written permission of Himax.
-P.39February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Figure 5. 22 Serial Interface protocol 3 wire/4 wire, write mode
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.40February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Serial data read mode
The micro controller first has to send a command and then the following byte is
transmitted in the opposite direction. The read mode has three type command data
transmitted (8- / 24- / 32-bit) is according command code.
3 Wires Serial Interface Protocol
Figure 5. 23 3 Wires Serial Interface protocol, read mode
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.41February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4 Wires Serial Interface Protocol
Figure 5. 24 4 wire Serial Interface protocol, read mode
There are four types of data format to write display data at Serial data bus Interface
and it is the same as 8-bit bus Interface.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.42February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
The data format that write display data to SRAM at Serial data bus Interface is shown
as Figure5. 25 ~ Figure5. 30.
Figure 5. 25 3W Serial write data for RGB (6-6-6) bits input (LUT_EN=1)
SCL
SDA
1
R13 R12 R11 R10 G13 G12 G11 G10
1
B13 B12 B11 B10 R23 R22 R21 R20
12-bit
Look-Up Table for 4K Color data mapping (12-bit to 18-bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5. 26 3W Serial write data for RGB 4-4-4-bits input (support Look-up table and LUT_EN=0)
SCL
SDA
1
R14 R13 R12 R11 R10 G15 G14 G13
1
G12 G11 G10 B14 B13 B12 B11 B10
16-bit
Look-Up Table for 65K data mapping (16-bit to 18 bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5. 27 3W Serial write data for RGB 5-6-5-bits input (support Look-up table and LUT_EN=0)
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.43February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
SCL
SDA
R15
NWR_RNW
R14
R13
R11
R12
R10
G15 G14
1
G13 G12 G11
G10
B15
1
B14
B13
B12
B11
B10
1
18- bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5. 28 4W Serial write data for RGB (6-6-6) bits input (LUT_EN=1)
SCL
SDA
R13 R12 R11 R10 G13 G12 G11 G10
NWR_RNW
B13 B12 B11 B10 R23 R22 R21 R20
1
1
12-bit
Look-Up Table for 4 K Color data mapping (12- bit to18-bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5. 29 4W Serial write data for RGB 4-4-4-bits input (support Look-up table and LUT_EN=0)
SCL
SDA
NWR_RNW
R14 R13 R12 R11 R10 G15 G14 G13 G12 G11 G10 B14 B13 B12 B11 B10
1
1
16-bit
Look- Up Table for 65K data mapping (16- bit to 18 bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5. 30 4W Serial write data for RGB 5-6-5-bits input (support Look-up table and LUT_EN=0)
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.44February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.1.3 Display Module Data Transfer Recovery
If there is a break on data transmission when transmitting a command before a whole
byte has been completed, then the display module will reset the interface so that it will
be ready to receive the same byte re-transmitted when the chip select line (NCS) is
next activated. See the following figure.
Figure 5. 31 Display Module Data Transfer Recovery
If 1 or more parameter command is being sent and a break occurs while sending any
parameter before the last one and if the host then sends a new command rather than
re-transmitting the parameter that was interrupted, then the parameters that were
successfully sent are stored and the parameter where the break occurred is rejected.
The interface is ready to receive next byte as shown:
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-P.45February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.1.4 Display Module Data Transfer Pause
It will be possible when transferring a Command, Frame Memory Data or Multiple
Parameter Data to invoke a pause in the data transmission. If the Chip Select Line is
released after a whole byte of a Frame Memory Data or Multiple Parameter Data has
been completed, then the Display Module will wait and continue the Frame Memory
Data or Parameter Data Transmission from the point where it was paused. If the Chip
Select Line is released after a whole byte of a command has been completed, then
the Display Module will receive either the command’s parameters (if appropriate) or a
new command when the Chip Select Line is next enabled as shown below:
Serial Interface Pause
This applies to the following 4 conditions:
a. Command-Pause-Command
b. Command-Pause-Parameter
c. Parameter-Pause-Command
d. Parameter-Pause-Parameter
Parallel Interface Pause
This applies to the following 4 conditions:
a. Command-Pause-Command
b. Command-Pause-Parameter
c. Parameter-Pause-Command
d. Parameter-Pause-Parameter
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.46February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.1.5 Display Module Data Transfer Modes
The Module has three colour modes for transferring data to the display RAM. These
are 12-bit colour per pixel, 16-bit colour per pixel and 18-bit colour per pixel. The data
format is described for each interface. Data can be downloaded to the Frame Memory
by 2 methods.
Method 1:
The Image data is sent to the Frame Memory in successive Frame writes, each time
the Frame Memory is filled, the Frame Memory pointer is reset to the start point and
the next Frame is written.
Method 2:
Image Data is sent and at the end of each Frame Memory download, a command is
sent to stop Frame Memory Write. Then Start Memory Write command is sent, and a
new Frame is downloaded.
Stop
Start
Start Frame
Image Data
Memory
Frame 1
Write
Any
Command
Start Frame
Image Data
Memory
Frame 2
Write
Any
Command
Any
Command
Note: (1) These apply to all Data Transfer Colour modes on both Serial and Parallel interfaces.
(2) The Frame Memory can contain both odd and even number of pixels for both Methods. Only
complete pixel data will be stored in the Frame Memory.
5.2 Address Counter (AC)
The HX8353-C contains an address counter (AC) which assigns address for
writing/reading pixel data to/from GRAM. The address pointers set the position of
GRAM whose addresses range X=0~131d (0~83h) and Y=0~161d (0~A1h).
Every time when a pixel data is written/read the GRAM, the X address or Y address of
AC will be automatically increased by 1 (or decreased by 1), which is decided by the
register (MV, MX and MY bit) setting.
To simplify the address control of GRAM access, the window address function allows
for writing data only to a window area of GRAM specified by registers. After data
being written to the GRAM, the AC will be increased or decreased within setting
window address-range which is specified by the horizontal address register (start: SC,
end: EC) or the vertical address register (start: SP, end: EP). Therefore, the data can
be written consecutively without thinking a data wrap by those bit function.
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.47February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.2.1 MCU to memory write/read direction
Data stream from MCU is like
this figure
B
E
Figure 5. 32 MCU to memory write/read direction
The data is written in the order illustrated above. The Counter which dictates where in
the physical memory the data is to be written is controlled by “Memory Data Access
Control” Command, Bits MY, MX, MV as described below.
Figure 5. 33 MY, MX, MV Setting
MV
0
MX
0
MY
0
CASET
Direct to Physical Column Pointer
PASET
Direct to Physical Page Pointer
Direct to (161-Physical Page Pointer)
Direct to (131-Physical Page Pointer)
Direct to Physical Page Pointer
Direct to (161-Physical Page Pointer)
Direct to (131-Physical Page Pointer)
Direct to Physical Column Pointer
0
0
1
Direct to Physical Column Pointer
0
1
0
Direct to (131-Physical Column Pointer)
0
1
1
Direct to (131-Physical Column Pointer)
1
0
0
1
0
1
1
1
0
1
1
1
Direct to Physical Page Pointer
Direct to (161-Physical Page Pointer)
Direct to Physical Column Pointer
Direct to (131-Physical Page Pointer)
Direct to Physical Page Pointer
Direct to (131-Physical Column Pointer)
Direct to (161-Physical Page Pointer)
Direct to (131-Physical Column Pointer)
Direct to (131-Physical Page Pointer)
Table 5. 5 MY, MX, MV Setting
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in whole or in part without prior written permission of Himax.
-P.48February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
The following figure depicts the update method with MV, MX and MY bit
Display
MADCTR
Data
parameter
Direction MV MX MY
Image in the
Host
Image in the Driver (GRAM)
H/W Position (0,0)
B
Normal
0
0
B
X,Y address (0,0)
X: CASET
Y: RASET
0
E
E
B
Y-Mirror
0
0
H/W Position (0,0)
1
X,Y address (0,0)
X: CASET
Y: RASET
E
B
E
B
X-Mirror
0
1
H/W Position (0,0)
B
X,Y address (0,0)
X: CASET
Y: RASET
0
E
E
H/W Position (0,0)
B
X-Mirror
Y-Mirror
0
1
E
1
X,Y address (0,0)
X: CASET
Y: RASET
B
E
B
X-Y
Exchange
1
0
H/W Position (0,0)
B
X,Y address (0,0)
X: CASET
Y: RASET
0
E
E
H/W Position (0,0)
B
X-Y
Exchange
Y-Mirror
1
0
1
X,Y address (0,0)
X: CASET
Y: RASET
E
B
X-Y
Exchange
X-Mirror
1
1
H/W
Position (0,0)
1
B
X,Y address (0,0)
X: CASET
Y: RASET
E
H/W Position (0,0)
B
1
B
0
E
X-Y
Exchange
X-Mirror
Y-Mirror
E
E
1
E
B
X,Y address (0,0)
X: CASET
Y: RASET
Figure 5. 34 Address Direction Settings
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in whole or in part without prior written permission of Himax.
-P.49February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.3 Source, Gate and Memory Map
5.3.1 When using 132 x 162 GRAM resolution, display resolution 132RGB x 162 and
support S45AP spec (RSO[2:0]=3’b000 & STE_SEL=0)
Note: RA = Row Address,
CA = Column Address,
SA = Scan Address,
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command
ML = Scan direction parameter, D4 parameter of MADCTL command
RGB= Red, Green and Blue pixel position change, D3 parameter of MADCTL command
Figure 5. 35 Memory Map, 132 x 162 GRAM resolution, display resolution 132RGB x 162
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.50February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.3.2 When using 132 x 162 GRAM resolution, display resolution 128RGB x 160 and
support S43AP spec (RSO[2:0]=3’b000 & STE_SEL=1)
Note: RA = Row Address,
CA = Column Address,
SA = Scan Address,
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command
ML = Scan direction parameter, D4 parameter of MADCTL command
RGB= Red, Green and Blue pixel position change, D3 parameter of MADCTL command
Figure 5. 36 Memory Map, 132 x 162 GRAM resolution ,display resolution 128RGB x 160
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in whole or in part without prior written permission of Himax.
-P.51February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.3.3 When using 128 x 160 GRAM resolution, display resolution 128RGB x 160 and
support S44AP spec (RSO[2:0]=3’b011)
Note: RA = Row Address,
CA = Column Address,
SA = Scan Address,
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command
ML = Scan direction parameter, D4 parameter of MADCTL command
RGB= Red, Green and Blue pixel position change, D3 parameter of MADCTL command
Figure 5. 37 Memory Map, 128 x 160 GRAM resolution, display resolution 128RGB x 160
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.52February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.3.4 When using 120 x 160 GRAM resolution, display resolution 120RGB x 160
(RSO[2:0]=3’b010)
Note: RA = Row Address,
CA = Column Address,
SA = Scan Address,
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command
ML = Scan direction parameter, D4 parameter of MADCTL command
RGB= Red, Green and Blue pixel position change, D3 parameter of MADCTL command
Figure 5. 38 Memory Map, 120 x 160 GRAM resolution, display resolution 120RGB x 160
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.53February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.3.5 When using 128 x 128 GRAM resolution, display resolution 128RGB x 128
(RSO[2:0]=3’b001)
Note: RA = Row Address,
CA = Column Address,
SA = Scan Address,
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command
ML = Scan direction parameter, D4 parameter of MADCTL command
RGB= Red, Green and Blue pixel position change, D3 parameter of MADCTL command
Figure 5. 39 Memory Map, 128 x 128 GRAM resolution, display resolution 128RGB x 128
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in whole or in part without prior written permission of Himax.
-P.54February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.3.6 When using 96 x 68 GRAM resolution, display resolution 96RGB x 68
(RSO[2:0]=3’b100)
Note: RA = Row Address,
CA = Column Address,
SA = Scan Address,
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command
ML = Scan direction parameter, D4 parameter of MADCTL command
RGB= Red, Green and Blue pixel position change, D3 parameter of MADCTL command
Figure 5. 40 Memory Map, 96 x 68 GRAM resolution, display resolution 96RGB x 68
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in whole or in part without prior written permission of Himax.
-P.55February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.3.7 When using 96 x 64 GRAM resolution, display resolution 96RGB x 64
(RSO[2:0]=3’b101)
Note: RA = Row Address,
CA = Column Address,
SA = Scan Address,
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command
ML = Scan direction parameter, D4 parameter of MADCTL command
RGB= Red, Green and Blue pixel position change, D3 parameter of MADCTL command
Figure 5. 41 Memory Map, 96 x 64 GRAM resolution, display resolution 96RGB x 64
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-P.56February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.3.8 Normal Display On or Partial Display On
The HX8353-C has an internal GRAM that store 48,114 bytes bit pattern data, where
one pixel is expressed by 18 bits.
5.3.8.1 132X162 GRAM resolution (Size) (display resolution 132RGB x 162 and
support S45AP spec (RSO[2:0]=3’b000 & STE_SEL=0)
(a)Normal Display On
In this mode, contents of the frame memory within an area where column pointer is
00h to 83h and page pointer is 00h to A1h is displayed. To display a dot on leftmost
top corner, store the dot data at (column pointer, row pointer) = (0, 0).
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
80h
DB---DB
17 ---0
0080H
0180H
0280H
0380H
0480H
0580H
---------------------------------------------------------
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
---------
-------
-------
9C00H
9D00H
9E00H
9F00H
A000H
A100H
---------
-------
-------
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
-------
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S396
---------
S395
S394
S3
S2
S1
LCD panel
S/G pins
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
G1
G2
G3
G4
G5
G6
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
-------
---------
-------
G157
G158
G159
G160
G161
G162
9C00H
9D00H
9E00H
9F00H
A000H
A100H
-------------------------------------------------
9C83H
9D83H
9E83H
9F83H
A083H
A183H
0083H
0183H
0283H
0383H
0483H
0583H
Table 5. 6
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.57February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(b)Partial Display On
PSL[15:0]=02h, PEL[15:0]=9Fh, ML=0.
-------
-------
-------
9C00H
9D00H
9E00H
9F00H
A000H
A100H
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
-------------------------------------------------
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S396
S395
S394
S3
S2
---------
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
-------
---------
-------
G157
G158
G159
G160
G161
G162
9C00H
9D00H
9E00H
9F00H
A000H
A100H
-------------------------------------------------
9C83H
9D83H
9E83H
9F83H
A083H
A183H
Display area
158 lines
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
---------
G1
G2
G3
G4
G5
G6
non-display
area 2 lines
Non-display
area 2 lines
S1
LCD panel
S/G pins
---------
80h
DB---DB
17 ---0
0080H
0180H
0280H
0380H
0480H
0580H
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---------
-------
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
0083H
0183H
0283H
0383H
0483H
0583H
Table 5. 7
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.58February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.3.8.2 132X162 GRAM resolution (Size) (display resolution 128RGB x 160 and
support S43AP spec (RSO[2:0]=3’b000 & STE_SEL=1)
(a)Normal Display On
In this mode, contents of the frame memory within an area where column pointer is
00h to 83h and page pointer is 00h to A1h is displayed. To display a dot on leftmost
top corner, store the dot data at (column pointer, row pointer) = (0, 0).
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
80h
DB---DB
17 ---0
0080H
0180H
0280H
0380H
0480H
0580H
---------------------------------------------------------
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
---------
-------
-------
9C00H
9D00H
9E00H
9F00H
A000H
A100H
---------
-------
-------
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
-------
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S390
---------
S389
S388
S9
S8
S7
LCD panel
S/G pins
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
G2
G3
G4
G5
G6
G7
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
-------
---------
-------
G158
G159
G160
G161
9C00H
9D00H
9E00H
9F00H
---------------------------------
9D81H
9E81H
9F81H
A081H
0181H
0281H
0381H
0481H
0581H
0681H
Table 5. 8
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.59February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(b)Partial Display On
PSL[15:0]=03h, PEL[15:0]=9Eh, ML=0.
-------
-------
-------
9C00H
9D00H
9E00H
9F00H
A000H
A100H
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
---------
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S390
S389
S388
S9
S8
---------
G2
G3
G4
G5
G6
G7
0102H
0202H
0302H
0402H
0502H
0602H
-------------------------------------------------
-------
---------
-------
G158
G159
G160
G161
9D02H
9E02H
9F02H
A002H
---------------------------------
9D81H
9E81H
9F81H
A081H
Display area
156 lines
Non-display
area 2 lines
-------------------------------------------------
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
-------
non-display
area 2 lines
S7
LCD panel
S/G pins
---------
80h
DB---DB
17 ---0
0080H
0180H
0280H
0380H
0480H
0580H
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---------
-------
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
0181H
0281H
0381H
0481H
0581H
0681H
Table 5. 9
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.60February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.3.8.3 128X160 GRAM resolution (Size) (display resolution 128RGB x 160 and
support S44AP spec (RSO[2:0]=3’b011)
(a)Normal Display On
In this mode, contents of the frame memory within an area where column pointer is
00h to 7Fh and page pointer is 00h to 9Fh is displayed. To display a dot on leftmost
top corner, store the dot data at (column pointer, row pointer) = (0, 0).
-------
-------
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
---------
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
9C7FH
9D7FH
9E7FH
9F7FH
A07FH
A17FH
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S390
---------
S389
S388
S9
S8
S7
LCD panel
S/G pins
-------------------------------------------------
80h
DB---DB
17 ---0
0080H
0180H
0280H
0380H
0480H
0580H
-------
------9C00H
9D00H
9E00H
9F00H
A000H
A100H
---------
7Fh
DB---DB
17 ---0
007FH
017FH
027FH
037FH
047FH
057FH
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---------
-------
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
G2
G3
G4
G5
G6
G7
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
-------
---------
-------
G158
G159
G160
G161
9C00H
9D00H
9E00H
9F00H
---------------------------------
9C7FH
9D7FH
9E7FH
9F7FH
007FH
017FH
027FH
037FH
047FH
057FH
Table 5. 10
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.61February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(b)Partial Display On
PSL[15:0]=02h, PEL[15:0]=9Dh, ML=0.
-------
-------
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
---------
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
9C7FH
9D7FH
9E7FH
9F7FH
A07FH
A17FH
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S390
S389
S388
S9
S8
---------
G2
G3
G4
G5
G6
G7
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
---------
-------
G158
G159
G160
G161
9C00H
9D00H
9E00H
9F00H
---------------------------------
9C7FH
9D7FH
9E7FH
9F7FH
Display area
156 lines
Non-display
area 2 lines
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
-------
non-display
area 2 lines
S7
LCD panel
S/G pins
80h
DB---DB
17 ---0
0080H
0180H
0280H
0380H
0480H
0580H
-------
------9C00H
9D00H
9E00H
9F00H
A000H
A100H
---------------------------------------------------------
7Fh
DB---DB
17 ---0
007FH
017FH
027FH
037FH
047FH
057FH
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---------
-------
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
007FH
017FH
027FH
037FH
047FH
057FH
Table 5. 11
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.62February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.3.8.4 120X160 GRAM resolution (Size) (display resolution 120RGB x 160 
RSO[2:0]=3’b001)
(a)Normal Display On
In this mode, contents of the frame memory within an area where column pointer is
00h to 77h and page pointer is 00h to 9Fh is displayed. To display a dot on leftmost
top corner, store the dot data at (column pointer, row pointer) = (0, 0).
-------
-------
-------
---------
9C00H
9D00H
9E00H
9F00H
A000H
A100H
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
---------
---------------------------------------------------------
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
---------
9C77H
9D77H
9E77H
9F77H
A077H
A177H
-------------------------------------------------
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S366
S365
S364
S9
S8
S7
---------
---------
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---------
-------
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
LCD panel
S/G pins
-------------------------------------------------
77h
DB---DB
17 ---0
0077H
0177H
0277H
0377H
0477H
0577H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
G2
G3
G4
G5
G6
G7
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
-------
---------
-------
G158
G159
G160
G161
9C00H
9D00H
9E00H
9F00H
---------------------------------
9C77H
9D77H
9E77H
9F77H
0077H
0177H
0277H
0377H
0477H
0577H
Table 5. 12
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.63February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(b)Partial Display On
PSL[15:0]=02h, PEL[15:0]=9Dh, ML=0.
-------
-------
-------
9C00H
9D00H
9E00H
9F00H
A000H
A100H
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
-------------------------------------------------
-------------------------------------------------
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
---------
9C77H
9D77H
9E77H
9F77H
A077H
A177H
-------------------------------------------------
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S366
S365
S364
S9
S8
S7
---------
---------
G2
G3
G4
G5
G6
G7
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
---------
-------
G158
G159
G160
G161
9C00H
9D00H
9E00H
9F00H
---------------------------------
9C77H
9D77H
9E77H
9F77H
Display area
156 lines
Non-display
area 2 lines
9C03H
9D03H
9E03H
9F03H
A003H
A103H
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
-------
non-display
area 2 lines
---------
---------
---------
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---------
-------
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
LCD panel
S/G pins
-------------------------------------------------
77h
DB---DB
17 ---0
0077H
0177H
0277H
0377H
0477H
0577H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
0077H
0177H
0277H
0377H
0477H
0577H
Table 5. 13
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.64February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.3.7.5 128X128 GRAM resolution (Size) (display resolution 128RGB x 128 
RSO[2:0]=3’b010)
(a)Normal Display On
In this mode, contents of the frame memory within an area where column pointer is
00h to 7Fh and page pointer is 00h to 7Fh is displayed. To display a dot on leftmost
top corner, store the dot data at (column pointer, row pointer) = (0, 0).
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
GRAM
---------
-------------------------------------------------
7Fh
DB---DB
17 ---0
007FH
017FH
027FH
037FH
047FH
057FH
---------
-----------------------------------------------------------------
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
-------
-------
-------
7E00H
7F00H
7E01H
7F01H
7E02H
7F02H
7E03H
7F03H
-----------------
7E7FH
7E7FH
-----------------
-------
-------
-------
-------
-------
---------
-------
---------
-------
-------
-------
9Ch
9Dh
9Eh
9Fh
A0h
A1h
9C00H
9D00H
9E00H
9F00H
A000H
A100H
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
9C7FH
9D7FH
9E7FH
9F7FH
A07FH
A17FH
-------------------------------------------------
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
7E81H
7F81H
7E82H
7F82H
7E83H
7F83H
S390
---------
S389
S388
S9
S8
S7
LCD panel
S/G pins
-------
-------
7Eh
7Fh
-------
-------
---------
-------
-------
---------
G2
G3
G4
G5
G6
G7
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
-------
---------
-------
G126
G127
G128
G129
9C00H
9D00H
9E00H
9F00H
---------------------------------
9C7FH
9D7FH
9E7FH
9F7FH
007FH
017FH
027FH
037FH
047FH
057FH
Table 5. 14
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.65February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(b)Partial Display On
PSL[15:0]=02h, PEL[15:0]=7Dh, ML=0.
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
GRAM
---------
-------------------------------------------------
7Fh
DB---DB
17 ---0
007FH
017FH
027FH
037FH
047FH
057FH
---------
---------
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
---------------------------------------------------------
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
-------
-------
-------
7E00H
7F00H
7E01H
7F01H
7E02H
7F02H
7E03H
7F03H
-----------------
7E7FH
7E7FH
-----------------
-------
-------
-------
-------
-------
---------
-------
---------
-------
-------
-------
9Ch
9Dh
9Eh
9Fh
A0h
A1h
9C00H
9D00H
9E00H
9F00H
A000H
A100H
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
9C7FH
9D7FH
9E7FH
9F7FH
A07FH
A17FH
-------------------------------------------------
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
7E81H
7F81H
7E82H
7F82H
7E83H
7F83H
S390
S389
S387
S9
S8
G2
G3
G4
G5
G6
G7
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
---------
-------
G158
G159
G160
G161
7C00H
7D00H
7E00H
7F00H
---------------------------------
7C7FH
7D7FH
7E7FH
7F7FH
Display area
124 lines
Non-display
area 2 lines
---------
-------
non-display
area 2 lines
S7
LCD panel
S/G pins
-------
-------
7Eh
7Fh
-------
-------
---------
-------
-------
---------
007FH
017FH
027FH
037FH
047FH
057FH
Table 5. 15
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.66February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.3.8.6 96x68 resolution (RSO[2:0]=3’b100)
(a)Normal Display On
In this mode, contents of the frame memory within an area where column pointer is
00h to 5Fh and page pointer is 00h to 43h is displayed. To display a dot on leftmost
top corner, store the dot data at (column pointer, row pointer) = (0, 0).
00h
01h
02h
03h
GRAM DB---DB DB---DB DB---DB DB---DB
17 ---0 17 ---0 17 ---0 17 ---0
0000H
0001H
0002H
0003H
00h
0100H
0101H
0102H
0103H
01h
0200H
0201H
0202H
0203H
02h
0300H
0301H
0302H
0303H
03h
0400H
0401H
0402H
0403H
04h
0500H
0501H
0502H
0503H
05h
---
-----
9C5DH
9D5DH
9E5DH
9F5DH
A05DH
A15DH
9C5EH
9D5EH
9E5EH
9F5EH
A05EH
A15EH
9C5FH
9D5FH
9E5FH
9F5FH
A05FH
A15FH
---
-------------
---------
---
-------------
4180H
4280H
4380H
4181H
4281H
4381H
4182H
4282H
4382H
4183H
4283H
4383H
-------
415FH
425FH
435FH
---
0083H
0183H
0283H
0383H
0483H
0583H
-------
415EH
425EH
435EH
---
0082H
0182H
0282H
0382H
0482H
0582H
-------
---
---
0081H
0181H
0281H
0381H
0481H
0581H
-------
-------------------------------------------------
415DH
425DH
435DH
---
---
0080H
0180H
0280H
0380H
0480H
0580H
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S342
0500H
---
S341
0000H
0100H
0200H
0300H
0400H
---
S340
S57
S56
G1
G2
G3
G4
G5
G6
S55
LCD panel
S/G pins
---
---
-------
------9C03H
9D03H
9E03H
9F03H
A003H
A103H
---
-------
------9C02H
9D02H
9E02H
9F02H
A002H
A102H
005FH
015FH
025FH
035FH
045FH
055FH
80h
81h
82h
83h
DB---DB DB---DB DB---DB DB---DB
17 ---0
17 ---0
17 ---0
17 ---0
-------
------9C01H
9D01H
9E01H
9F01H
A001H
A101H
005EH
015EH
025EH
035EH
045EH
055EH
---
---
-------
------9C00H
9D00H
9E00H
9F00H
A000H
A100H
005DH
015DH
025DH
035DH
045DH
055DH
---
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---
-------
------4103H
4103H
4303H
5Fh
DB---DB
17 ---0
-------
------4102H
4102H
4302H
5Eh
DB---DB
17 ---0
-------
------4101H
4201H
4301H
5Dh
DB---DB
17 ---0
-------
------4100H
4200H
4300H
---
-------
------41h
42h
43h
---
005FH
015FH
025FH
035FH
045FH
055FH
-------
-------
-------
-------
G67
G68
4200H
4300H
-----------------
425FH
435FH
Table 5. 16
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.67February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(b)Partial Display On
PSL[15:0]=02, PEL[15:0]=41, ML=0.
00h
01h
02h
03h
GRAM DB---DB DB---DB DB---DB DB---DB
17 ---0
17 ---0
17 ---0
17 ---0
0000H
0001H
0002H
0003H
00h
0100H
0101H
0102H
0103H
01h
0200H
0201H
0202H
0203H
02h
0300H
0301H
0302H
0303H
03h
0400H
0401H
0402H
0403H
04h
0500H
0501H
0502H
0503H
05h
-------
---------
---
-------------
4180H
4280H
4380H
4181H
4281H
4381H
4182H
4282H
4382H
4183H
4283H
4383H
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S342
-------------------------------------------------
S341
0500H
9C5FH
9D5FH
9E5FH
9F5FH
A05FH
A15FH
S340
S57
0000H
0100H
0200H
0300H
0400H
9C5EH
9D5EH
9E5EH
9F5EH
A05EH
A15EH
---
0083H
0183H
0283H
0383H
0483H
0583H
-------
---
9C5DH
9D5DH
9E5DH
9F5DH
A05DH
A15DH
---
0082H
0182H
0282H
0382H
0482H
0582H
-------
---
---
0081H
0181H
0281H
0381H
0481H
0581H
-------
---
415FH
425FH
435FH
---
0080H
0180H
0280H
0380H
0480H
0580H
-------
---
415EH
425EH
435EH
005FH
015FH
025FH
035FH
045FH
055FH
-------
-------
-------
Non-display
area 2 lines
---
415DH
425DH
435DH
-------
Display area
64 lines
G1
G2
G3
G4
G5
G6
S56
Non-display
area 2 lines
S55
LCD panel
S/G pins
---
---
-------
------9C03H
9D03H
9E03H
9F03H
A003H
A103H
---
---
81h
82h
83h
DB---DB DB---DB DB---DB
17 ---0
17 ---0
17 ---0
-------
------9C02H
9D02H
9E02H
9F02H
A002H
A102H
---
005FH
015FH
025FH
035FH
045FH
055FH
80h
DB---DB
17 ---0
-------
------9C01H
9D01H
9E01H
9F01H
A001H
A101H
---
005EH
015EH
025EH
035EH
045EH
055EH
---
-------
------9C00H
9D00H
9E00H
9F00H
A000H
A100H
---
005DH
015DH
025DH
035DH
045DH
055DH
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---
---
-------
------4103H
4203H
4303H
---
5Fh
DB---DB
17 ---0
-------
------4102H
4202H
4302H
---
5Eh
DB---DB
17 ---0
-------
------4101H
4201H
4301H
---
5Dh
DB---DB
17 ---0
-------
------4100H
4200H
4300H
---
-------
------41h
42h
43h
---
G66
G67
G68
4100H
4200H
4300H
-------------------------
415FH
425FH
435FH
Table 5. 17
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.68February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.3.8.7 96x64 resolution (RSO[2:0]=3’b101)
(a)Normal Display On
In this mode, contents of the frame memory within an area where column pointer is
00h to 5Fh and page pointer is 00h to 43h is displayed. To display a dot on leftmost
top corner, store the dot data at (column pointer, row pointer) = (0, 0).
00h
01h
02h
03h
GRAM DB---DB DB---DB DB---DB DB---DB
17 ---0 17 ---0 17 ---0 17 ---0
0000H
0001H
0002H
0003H
00h
0100H
0101H
0102H
0103H
01h
0200H
0201H
0202H
0203H
02h
0300H
0301H
0302H
0303H
03h
0400H
0401H
0402H
0403H
04h
0500H
0501H
0502H
0503H
05h
---
-----
9C5DH
9D5DH
9E5DH
9F5DH
A05DH
A15DH
9C5EH
9D5EH
9E5EH
9F5EH
A05EH
A15EH
9C5FH
9D5FH
9E5FH
9F5FH
A05FH
A15FH
---
-------------
---------
---
-------------
3F80H
4080H
4180H
3F81H
4081H
4181H
3F82H
4082H
4182H
3F83H
4083H
4183H
-------
3F5FH
405FH
415FH
---
0083H
0183H
0283H
0383H
0483H
0583H
-------
3F5EH
405EH
415EH
---
0082H
0182H
0282H
0382H
0482H
0582H
-------
---
---
0081H
0181H
0281H
0381H
0481H
0581H
-------
-------------------------------------------------
3F5DH
405DH
415DH
---
---
0080H
0180H
0280H
0380H
0480H
0580H
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S342
0500H
---
S341
0000H
0100H
0200H
0300H
0400H
---
S340
S57
S56
G1
G2
G3
G4
G5
G6
S55
LCD panel
S/G pins
---
---
-------
------9C03H
9D03H
9E03H
9F03H
A003H
A103H
---
-------
------9C02H
9D02H
9E02H
9F02H
A002H
A102H
005FH
015FH
025FH
035FH
045FH
055FH
80h
81h
82h
83h
DB---DB DB---DB DB---DB DB---DB
17 ---0
17 ---0
17 ---0
17 ---0
-------
------9C01H
9D01H
9E01H
9F01H
A001H
A101H
005EH
015EH
025EH
035EH
045EH
055EH
---
---
-------
------9C00H
9D00H
9E00H
9F00H
A000H
A100H
005DH
015DH
025DH
035DH
045DH
055DH
---
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---
-------
------3F03H
4003H
4103H
5Fh
DB---DB
17 ---0
-------
------3F02H
4002H
4102H
5Eh
DB---DB
17 ---0
-------
------3F01H
4001H
4101H
5Dh
DB---DB
17 ---0
-------
------3F00H
4000H
4100H
---
-------
------3Fh
40h
41h
---
005FH
015FH
025FH
035FH
045FH
055FH
-------
-------
-------
-------
G63
G64
3E00H
3F00H
-----------------
3E5FH
3F5FH
Table 5. 18
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.69February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(b)Partial Display On
PSL[15:0]=02, PEL[15:0]=3D, ML=0.
00h
01h
02h
03h
GRAM DB---DB DB---DB DB---DB DB---DB
17 ---0 17 ---0 17 ---0 17 ---0
0000H
0001H
0002H
0003H
00h
0100H
0101H
0102H
0103H
01h
0200H
0201H
0202H
0203H
02h
0300H
0301H
0302H
0303H
03h
0400H
0401H
0402H
0403H
04h
0500H
0501H
0502H
0503H
05h
-----
-----
9C5DH
9D5DH
9E5DH
9F5DH
A05DH
A15DH
9C5EH
9D5EH
9E5EH
9F5EH
A05EH
A15EH
9C5FH
9D5FH
9E5FH
9F5FH
A05FH
A15FH
---
-------------
---------
---
-------------
3F80H
4080H
4180H
3F81H
4081H
4181H
3F82H
4082H
4182H
3F83H
4083H
4183H
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S342
0500H
-------------------------------------------------
S341
S340
S57
0000H
0100H
0200H
0300H
0400H
---
0083H
0183H
0283H
0383H
0483H
0583H
-------
3F5FH
405FH
415FH
---
0082H
0182H
0282H
0382H
0482H
0582H
-------
3F5EH
405EH
415EH
---
0081H
0181H
0281H
0381H
0481H
0581H
-------
---
---
0080H
0180H
0280H
0380H
0480H
0580H
-------
3F5DH
405DH
415DH
---
005FH
015FH
025FH
035FH
045FH
055FH
-------
-------
-------
Non-display
area 2 lines
---
-------
Display area
60 lines
G1
G2
G3
G4
G5
G6
S56
Non-display
area 2 lines
S55
LCD panel
S/G pins
---
---
-------
------9C03H
9D03H
9E03H
9F03H
A003H
A103H
---
-------
------9C02H
9D02H
9E02H
9F02H
A002H
A102H
005FH
015FH
025FH
035FH
045FH
055FH
80h
81h
82h
83h
DB---DB DB---DB DB---DB DB---DB
17 ---0
17 ---0
17 ---0
17 ---0
-------
------9C01H
9D01H
9E01H
9F01H
A001H
A101H
005EH
015EH
025EH
035EH
045EH
055EH
---
---
-------
------9C00H
9D00H
9E00H
9F00H
A000H
A100H
005DH
015DH
025DH
035DH
045DH
055DH
---
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---
-------
------3F03H
4003H
4103H
5Fh
DB---DB
17 ---0
-------
------3F02H
4002H
4102H
5Eh
DB---DB
17 ---0
-------
------3F01H
4001H
4101H
5Dh
DB---DB
17 ---0
-------
------3F00H
4000H
4100H
---
-------
------3Fh
40h
41h
---
G63
G64
3E00H
3F00H
-----------------
3E5FH
3F5FH
Table 5. 19
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.70February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.4 Vertical Scrolling Display
The vertical scrolling display is specified by SCRLAR instruction (R33h) and VSCSAD
instruction (R37h). The Vertical scrolling is only enable when using 132 x 162 GRAM
resolution, display resolution 132RGB x 162 and support S45AP spec
(RSO[2:0]=3’b000 & STE_SEL=0)
Original
Scrolling
TFA
VSA
BFA
Figure 5. 42
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.71February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
RSO[2:0]=3’b000 (132RGBx162)
When RSO[2:0]=3’b000(132RGB x 162) and Vertical Scrolling Definition Parameters
(TFA+VSA+BFA)=162 (other setting is prohibited). In this case, scrolling is applied as
shown below.
Example 1: RSO=2’b00(132RGB x 162), TFA =3, VSA=157, BFA=2, VSP=4,
MADCTR(ML)=0: Scrolling
TFA
01
02
03
04
01h
10
11
12
13
14
02h
20
21
22
23
03h
30
31
32
04h
40
41
05h
50
0V 0W 0X 0Y 0Z
1st
0
G1
00
01
02
03
04
1W 1X 1Y 1Z
2nd
1
G2
10
11
12
13
14
2X 2Y 2Z
3nd
2
G3
20
21
22
23
3Y 3Z
160th
3
G4
40
41
42
4Y 4Z
4th
4
G5
50
51
5Z
5th
5
G6
60
VSP
9Ch
U0
9Dh
V0 V1
9Eh
W0 W1
9Fh
X0 X1 X2
A0h
Y0 Y1 Y2 Y3
A1h
Z0 Z1
Z2
Z3
Z4
Z5
05
0V 0W 0X 0Y 0Z
1W 1X 1Y 1Z
5Y 5Z
6Z
132 x 162 LCD Panel
UZ 156th 156
G157
V0 V1
VY VZ
VY VZ 157th 157
G158
W0 W1
WY WZ
WY WZ 158th
158
G159
X0 X1 X2
XX XY XZ 159th 159
G160
30
31
TFA
2X 2Y 2Z
4X 4Y 4Z
132 x 162 x 18 bit
Frame memory
VSA
BFA
80h 81h 82h 83h
05
XX XY XZ
32
3X 3Y 3Z
YW YX YY YZ 161th
160
G161
Y0 Y1 Y2 Y3
YW YX YY YZ
ZV ZW ZX ZY ZZ 162th
161
G162
Z0 Z1 Z2 Z3 Z4 Z5
ZV ZW ZX ZY ZZ
Scroll area = 157 lines
00
S1
00h 01h 02h 03h 04h
00h
S396
Scan order
BFA
Scan Address
Figure 5. 43
Example 2: RSO=2’b00(132RGB x 162), TFA =3, VSA=157, BFA=2, SSA=4,
MADCTR (ML)=1: Scrolling (TFA and BFA are exchanged)
BFA
01
02
03
04
01h
10
11
12
13
14
02h
20
21
22
23
03h
30
31
32
04h
40
41
05h
50
VSA
TFA
80h 81h 82h 83h
05
0V 0W 0X 0Y 0Z 162th
0
G1
00
01
02
03
04
1W 1X 1Y 1Z 161th
1
G2
10
11
12
13
14
2X 2Y 2Z 159th
2
G3
W0 W1
3Y 3Z 158th
3
G4
20 21
22
23
4Y
4Z 157th
4
G5
30
31
32
5Z 156th
5
G6
40
41
U0
UZ
5th
156
9Dh
V0 V1
VY VZ
4th
157
9Eh
W0 W1
WY WZ 160th 158
9Fh
X0 X1 X2
A0h
Y0 Y1 Y2 Y3
A1h
Z0
Z3
Z4
Z5
1W 1X 1Y 1Z
2X 2Y 2Z
3X 3Y 3Z
4Y
4Z
132 x 162 LCD Panel
9Ch
Z2
0V 0W 0X 0Y 0Z
WY WZ
132 x 162 x 18 bit
Frame memory
Z1
05
G157 T0
VSP
G158
TZ
U0 U1
UY UZ
G159 V0 V1
VY VZ
XX XY XZ
3nd
159
G160
YW YX YY YZ
2nd
160
G161 Y0 Y1 Y2 Y3
1st
161
ZV ZW ZX
ZY
ZZ
G162
X0 X1 X2
Z0
Z1 Z2
BFA
Scroll area = 157 lines
00
S1
00h 01h 02h 03h 04h
00h
S396
Scan order
XX XY XZ
Z3
YW YX YY YZ
Z4 Z5
TFA
ZV ZW ZX ZY ZZ
Scan Address
Figure 5. 44
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.72February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.5 Tearing Effect Output Line
The Tearing Effect output line supplies to the MPU a Panel synchronization signal.
This signal can be enabled or disabled by the Tearing Effect Line Off & On commands.
The mode of the Tearing Effect signal is defined by the parameter of the Tearing
Effect Line On command. The signal can be used by the MPU to synchronize Frame
Memory Writing when displaying video images.
5.5.1 Tearing Effect Line Modes
Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:
Figure 5. 45
tVREG1= The LCD display is not updated from the Frame Memory
tvdl = The LCD display is updated from the Frame Memory (except Invisible Line –
see below)
Mode 2, The Tearing Effect Output signal consists of V-Blanking and H-Blanking
Information, there is one V-sync and N H-sync pulses per field on different
resolution.
128RGBx160 (Support S43AP and S44AP): N=160
132RGBx162 (Support S45AP): N=162
96x68: N=68
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.73February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
96x64: N=64
Figure 5. 46
thdh= The LCD display is not updated from the Frame Memory
thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see
above.)
Note: During Sleep In Mode, the Tearing Output Pin is active Low
Figure 5. 47
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.74February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.5.2 Tearing Effect Line Timing
The Tearing Effect signal is described below.
Figure 5. 48
Symbol
tvdl
tVREG1
thdl
thdh
Parameter
Vertical Timing Low Duration
Vertical Timing High Duration
Horizontal Timing Low Duration
Horizontal Timing High Duration
Min.
TBD
1000
TBD
TBD
Idle Mode Off (Frame Rate = TBDHz)
Max.
Unit
Description
ms
us
us
500
us
-
Note: The timings in Table 5.12 apply when MADCTL ML=0 and ML=1
Table 5. 20 AC characteristics of Tearing Effect Signal
The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
Figure 5. 49
The Tearing Effect Output Line is fed back to the MPU and should be used as shown
below to avoid Tearing Effect:
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in whole or in part without prior written permission of Himax.
-P.75February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.5.3 Example 1: MPU Write is faster than Panel Read
MCU to Memory
Time
1st 162th
TE output signal
Time
Memory to LCD
1st
Image on LCD
a
Time
162th
b
c
d
Figure 5. 50
Data write to Frame Memory is now synchronized to the Panel Scan. It should be
written during the vertical sync pulse of the Tearing Effect Output Line. This ensures
that data is always written ahead of the panel scan and each Panel Frame refresh has
a complete new image:
Figure 5. 51
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.76February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.5.4 Example 2: MPU Write is slower than Panel Read
MCU to Memory
1st
Time
162th
TE output signal
Time
Memory to LCD
1st
Image on LCD
a
Time
162th
b
c
d
e
f
Figure 5. 52
The MPU to Frame Memory write begins just after Panel Read has commenced i.e.
after one horizontal sync pulse of the Tearing Effect Output Line. This allows time for
the image to download behind the Panel Read pointer and finishing download during
the subsequent Frame before the Read Pointer “catches” the MPU to Frame memory
write position.
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.77February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.6 Color Depth Conversion Look-up Tables
R input (4bit)
12 bit/pixel -mode
R input (5 bit)
16 bit/pixel -mode
R output (6bit)
18 bit/pixel -mode
4,096 colours
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
65,536 colours
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
262,144 colours
RGBSET Parameter
R005R004 R003 R002 R001 R000
R015R014 R013 R012 R011 R010
R025R024 R023 R022 R021 R020
R035R034 R033 R032 R031 R030
R045R044 R043 R042 R041 R040
R055R054 R053 R052 R051 R050
R065R064 R063 R062 R061 R060
R075R074 R073 R072 R071 R070
R085R084 R083 R082 R081 R080
R095R094 R093 R092 R091 R090
R105R104 R103 R102 R101 R100
R115R114 R113 R112 R111 R110
R125R124 R123 R122 R121 R120
R135R134 R133 R132 R131 R130
R145R144 R143 R142 R141 R140
R155R154 R153 R152 R151 R150
R165R164 R163 R162 R161 R160
R175R174 R173 R172 R171 R170
R185R184 R183 R182 R181 R180
R195R194 R193 R192 R191 R190
R205R204 R203 R202 R201 R200
R215R214 R213 R212 R211 R210
R225R224 R223 R222 R221 R220
R235R234 R233 R232 R231 R230
R245R244 R243 R242 R241 R240
R255R254 R253 R252 R251 R250
R265R264 R263 R262 R261 R260
R275R274 R273 R272 R271 R270
R285R284 R283 R282 R281 R280
R295R294 R293 R292 R291 R290
R305R304 R303 R302 R301 R300
R315R314 R313 R312 R311 R310
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
-P.78February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
G input (4bit)
12 bit/pixel -mode
4,096 colours
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
G input (6 bit)
16 bit/pixel -mode
65,536 colours
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
G output (6bit)
18 bit/pixel -mode
262,144 colours
RGBSET Parameter
G005G004 G003 G002 G001 G000
G015G014 G013 G012 G011 G010
G025G024 G023 G022 G021 G020
G035G034 G033 G032 G031 G030
G045G044 G043 G042 G041 G040
G055G054 G053 G052 G051 G050
G065G064 G063 G062 G061 G060
G075G074 G073 G072 G071 G070
G085G084 G083 G082 G081 G080
G095G094 G093 G092 G091 G090
G105G104 G103 G102 G101 G100
G115G114 G113 G112 G111 G110
G125G124 G123 G122 G121 G120
G135G134 G133 G132 G131 G130
G145G144 G143 G142 G141 G140
G155G154 G153 G152 G151 G150
G165G164 G163 G162 G161 G160
G175G174 G173 G172 G171 G170
G185G184 G183 G182 G181 G180
G195G194 G193 G192 G191 G190
G205G204 G203 G202 G201 G200
G215G214 G213 G212 G211 G210
G225G224 G223 G222 G221 G220
G235G234 G233 G232 G231 G230
G245G244 G243 G242 G241 G240
G255G254 G253 G252 G251 G250
G265G264 G263 G262 G261 G260
G275G274 G273 G272 G271 G270
G285G284 G283 G282 G281 G280
G295G294 G293 G292 G291 G290
G305G304 G303 G302 G301 G300
G315G314 G313 G312 G311 G310
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.79February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
G input (4bit)
12 bit/pixel -mode
4,096 colours
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
G input (6 bit)
16 bit/pixel -mode
65,536 colours
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
G output (6bit)
18 bit/pixel -mode
262,144 colours
RGBSET Parameter
G325 G324 G323 G322 G321 G320
G335 G334 G333 G332 G331 G330
G345 G344 G343 G342 G341 G340
G355 G354 G353 G352 G351 G350
G365 G364 G363 G362 G361 G360
G375 G374 G373 G372 G371 G370
G385 G384 G383 G382 G381 G380
G395 G394 G393 G392 G391 G390
G405 G404 G403 G402 G401 G400
G415 G414 G413 G412 G411 G410
G425 G424 G423 G422 G421 G420
G435 G434 G433 G432 G431 G430
G445 G444 G443 G442 G441 G440
G455 G454 G453 G452 G451 G450
G465 G464 G463 G462 G461 G460
G475 G474 G473 G472 G471 G470
G485 G484 G483 G482 G481 G480
G495 G494 G493 G492 G491 G490
G505 G504 G503 G502 G501 G500
G515 G514 G513 G512 G511 G510
G525 G524 G523 G522 G521 G520
G535 G534 G533 G532 G531 G530
G545 G544 G543 G542 G541 G540
G555 G554 G553 G552 G551 G550
G565 G564 G563 G562 G561 G560
G575 G574 G573 G572 G571 G570
G585 G584 G583 G582 G581 G580
G595 G594 G593 G592 G591 G590
G605 G604 G603 G602 G601 G600
G615 G614 G613 G612 G611 G610
G625 G624 G623 G622 G621 G620
G635 G634 G533 G632 G631 G630
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.80February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
B input (4bit)
12 bit/pixel -mode
4,096 colours
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
B input (5 bit)
16 bit/pixel -mode
65,536 colours
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
B output (6bit)
18 bit/pixel -mode
262,144 colours
RGBSET Parameter
B005B004 B003 B002 B001 B000
B015B014 B013 B012 B011 B010
B025B024 B023 B022 B021 B020
B035B034 B033 B032 B031 B030
B045B044 B043 B042 B041 B040
B055B054 B053 B052 B051 B050
B065B064 B063 B062 B061 B060
B075B074 B073 B072 B071 B070
B085B084 B083 B082 B081 B080
B095B094 B093 B092 B091 B090
B105B104 B103 B102 B101 B100
B115B114 B113 B112 B111 B110
B125B124 B123 B122 B121 B120
B135B134 B133 B132 B131 B130
B145B144 B143 B142 B141 B140
B155B154 B153 B152 B151 B150
B165B164 B163 B162 B161 B160
B175B174 B173 B172 B171 B170
B185B184 B183 B182 B181 B180
B195B194 B193 B192 B191 B190
B205B204 B203 B202 B201 B200
B215B214 B213 B212 B211 B210
B225B224 B223 B222 B221 B220
B235B234 B233 B232 B231 B230
B245B244 B243 B242 B241 B240
B255B254 B253 B252 B251 B250
B265B264 B263 B262 B261 B260
B275B274 B273 B272 B271 B270
B285B284 B283 B282 B281 B280
B295B294 B293 B292 B291 B290
B305B304 B303 B302 B301 B300
B315B314 B313 B312 B311 B310
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.81February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.7 Oscillator
The HX8353-C has an internal oscillator without extra external components that
provide a source for system clock generator.
5.8 Source Driver
The HX8353-C contains a 396 channels of source driver (S1~S396) which is used for
driving the source line of TFT LCD panel. The source driver converts the digital data
from GRAM into the analog voltage for 396 channels and generates corresponding
gray scale voltage output, which can realize a 262,144 colors display simultaneously.
Since the output circuit of this source driver incorporates an operational amplifier, a
positive and a negative voltage can be alternately output from each channel.
5.9 Gate Driver
The HX8353-C contains a 160 gate channels of gate driver (G1~G160) which is used
for driving the gate. The gate driver level is VGH when scan some line, VGL the other
lines.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.82February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.10 LCD POWER GENERATION CIRCUIT
5.10.1 LCD Power Generation Scheme
The boost voltage generated is shown as below.
Figure 5. 53 LCD power generation scheme
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.83February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.10.2 Various Boosting Steps
The boost steps of each boosting voltage are selected according to how the external
capacitors are connected. Different booster applications are shown as below.
VLCD=2xVDD
VLCD
C11A
C11B
VGH=6xVDD
VGL=-5xVDD
C21A
VGH
C21B
C22A
VGL
C22B
Figure 5. 54 Block Diagram of Power Supply Circuit
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.84February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.11 Gray Voltage Generator for Source Driver
The HX8353-C incorporates gamma adjustment function for the 262,144-color display
(64 grayscale for each R, G, B color). Gamma adjustment operation is implemented
by deciding the 8 grayscale levels firstly in gamma adjustment control registers to
match the LCD panel. These registers are available for both polarities.
Graphics
RAM
(GRAM)
R R R R R R GG G G GG B B B B B B
5 432 10 5 43 2 10 543 2 10
OP03 OP02 OP01 OP00
OP13 OP
OP11 OP
OP
12
10
14
CP CP02 CP01 CP00
03
CP
CP
CP11 CP10
12
13
CP23 CP
CP21 CP20
22
CP
33
6
6
CP32 CP31 CP30
CP
CP
CP41 CP40
42
43
6
MP MP01 MP
00
02
Positive
polarity
V0
6-bit Grayscale
6-bit Grayscale
6-bit Grayscale
D/A Converter
D/A Converter
D/A Converter
Register
V1
Output Driver Output Driver
MP
MP
MP20
22
21
MP32 MP31 MP30
Grayscale
MP42 MP41 MP40
Voltage
MP52 MP51 MP50
Generator
Output Driver
MP12 MP11 MP10
V63
ON
ON
ON01 ON
02
03
00
ON
ON13 ON
ON11 ON10
14
12
CN03 CN
CN01 CN00
02
CN03 CN
CN11 CN
10
12
CN21 CN20
CN23 CN
22
R
G
B
CN
CN32 CN
33
31
CN CN CN CN
43
42
LCD
CN30
Negative
polarity
Registre
41
40
MN MN MN
02
01
00
MN
MN MN
12
10
11
MN MN
MN
21
20
22
MN
MN31 MN30
32
MN
MN41 MN
42
40
MN MN MN
52
51
50
Figure 5. 55 Grayscale Control
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.85February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.11.1 Structure of Grayscale Voltage Generator
Eight reference gamma voltages VgP/N(0, 1, 8, 20, 43, 55, 62, 63) for positive and
negative polarity are specified by the center adjustment, the micro adjustment and the
offset adjustment registers firstly. With those eight voltage injected into specified node
of grayscale voltage generator, totally 64 grayscale voltages (V0-V63) can be
generated from grayscale amplifier for LCD panel.
Micro Adjust Register ( 6x3 bits)
VREG1
MP/N5 MP/N4 MP/N3 MP/N2
3
3
3
3
MP/N1 MP/N0
3
3
RVP/N0
V0P/N
CP/N0
3
8 to 1
select
RVP/N1
V1P/N
V2P/N
CP/N1
3
8 to 1
select
4
OP/N0
Offset
Adjust
Register
OP/N1
8 to 1
select
RVP/N8
V8 P/N
V9 P/N
RVP/N20
V20 P/N
V21P/N
CP/N2
3
8 to 1
select
RVP/N43
3
8 to 1
select
RVP/N55
Gray Scale
Voltage
Generator
V43P/N
V44P/N
V55 P/N
V56 P/N
CP/N3
3
8 to 1
select
RVP/N62
V62 P/N
CP/N4
3
RVP/N63
V63 P/N
VGS
Figure 5. 56 Structure of Grayscale Voltage Generator
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.86February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.11.2 Gamma-Characteristics Adjustment Register
This HX8353-C has register groups for specifying a series grayscale voltage that
meets the Gamma-characteristics for the LCD panel. These registers are divided into
two groups, which correspond to the gradient, amplitude, and macro adjustment of
the voltage for the grayscale characteristics. The polarity of each register can be
specified independently. (R, G, and B are common.)
5.11.2.1 Offset Adjustment Registers 0/1
The offset adjustment variable registers are used to adjust the amplitude of the
grayscale voltage. This function is implemented by controlling these variable resisters
in the top and bottom of the gamma resister stream for reference gamma voltage
generation. These registers are available for both positive and negative polarities
5.11.2.2 Gamma Center Adjustment Registers
The gamma center adjustment registers are used to adjust the reference gamma
voltage in the middle level of grayscale without changing the dynamic range. This
function is implemented by choosing one input of 8 to 1 selector in the gamma resister
stream for reference gamma voltage generation. These registers are available for both
positive and negative polarities.
5.11.3 Gamma Macro Adjustment Registers
The gamma macro adjustment registers can be used for fine adjustment of the
reference gamma voltage. This function is implemented by controlling the 8-to-1
selectors (MP/N0~5), each of which has 8 inputs and generate one reference voltage
output (RVP/N 0, 1, 8, 20, 44, 56, 63, 64). These registers are available for both positive
and negative polarities.
Register
Groups
Center
Adjustment
Macro
Adjustment
Offset
Adjustment
Positive
Polarity
CP/N0 3-0
CP/N1 3-0
CP/N2 3-0
CP/N3 3-0
CP/N4 3-0
MP/N0 2-0
MP/N1 2-0
MP/N2 2-0
MP/N3 2-0
MP/N4 2-0
MP/N5 2-0
OP/N0 3-0
OP/N1 4-0
Description
Variable resistor (VRTP/N) for center adjustment
Variable resistor (VRCP/N0)for center adjustment
Variable resistor (VRMP/N) for center adjustment
Variable resistor (VRCP/N1)for center adjustment
Variable resistor (VRBP/N)for center adjustment
8-to-1 selector (reference voltage level of grayscale 1)
8-to-1 selector (reference voltage level of grayscale 8)
8-to-1 selector (reference voltage level of grayscale 20)
8-to-1 selector (reference voltage level of grayscale 43)
8-to-1 selector (reference voltage level of grayscale 55)
8-to-1 selector (reference voltage level of grayscale 62)
Variable resistor (VRP/N0)for offset adjustment
Variable resistor (VRP/N1)for offset adjustment
Table 5. 21 Gamma-Adjustment Registers
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.87February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.11.4 Gamma Resister Stream and 8 to 1 Selector
The block consists of two gamma resister streams, one is for positive polarity and the
other is for negative polarity, each one includes eight gamma reference voltages
(Vg(P/N)0, 1, 8, 20, 43, 55, 62, 63). Furthermore, the block has a pin (VGS) to
connect a variable resistor outside the chip for the variation between panels, if
needed.
OP/N1
VP/N0
VREG1
0-60R
0-93R
VRP/N1 VRTP/N
2R*7
VRCP/N0
0-45R
2R*7
20R
2R*7
VRMP/N
0-30R
VgP/N0
Center adjustment CP/N0
V0 P/N
KVP/N1
VP/N1
KVP/N2
VP/N2
KVP/N3
VP/N3
KVP/N4
VP/N4
KVP/N5
VP/N5
KVP/N6
VP/N6
KVP/N7
VP/N7
KVP/N8
VgP/N1
V1 P/N
Buffer
0
1R
1R
1R
1R
1R
1R
1R
Center adjustment CP/N1
KVP/N9
VP/N8
KVP/N10
VP/N9
KVP/N11
VP/N10
KVP/N12
VP/N11
KVP/N13
VP/N12
KVP/N14
VP/N13
KVP/N15
VP/N14
KVP/N16
VP/N15
VgP/N2
R1
CGM0
1
3R
2
3
5R 2R
1.5R 3.33R 1.83R
2R 2.67R1.67R
1R 1R 1.5R
1R 1R 1.33R
1R 1R 1.17R
1R 1R 1R
V2 P/N
R2
V3 P/N
R3
V4 P/N
R4
V5 P/N
R5
V6 P/N
R6
V7 P/N
R7
V8 P/N
R8
Buffer
V9 P/N
R9
V10 P/N
KVP/N17
VP/N16
KVP/N18
VP/N17
KVP/N19
VP/N18
KVP/N20
VP/N19
KVP/N21
VP/N20
KVP/N22
VP/N21
KVP/N23
VP/N22
KVP/N24
V19 P/N
VgP/N3
R19
V20 P/N
R20
Buffer
V21 P/N
R21
V22 P/N
Center adjustment CP/N2
KVP/N25
2R*7
20R
2R*7
VRCP/N1 0-45R
2R*7
VP/N23
KVP/N26
VP/N24
KVP/N27
VP/N26
KVP/N28
VP/N27
KVP/N29
VP/N28
KVP/N30
VP/N29
KVP/N31
VP/N30
KVP/N32
VP/N31
0-60R
VRP/N0 0-45R
VSS
V41 P/N
R41
VgP/N4
V42 P/N
V43 P/N
R42
R43
Buffer
V44 P/N
R44
V45 P/N
KVP/N33
VP/N32
KVP/N34
VP/N33
KVP/N35
VP/N34
KVP/N36
VP/N35
KVP/N37
VP/N36
KVP/N38
VP/N37
KVP/N39
VP/N38
KVP/N40
R53
VgP/N5
R54
Buffer
Center adjustment CP/N3
KVP/N41
VP/N39
KVP/N42
VP/N40
KVP/N43
VP/N41
KVP/N44
VP/N42
KVP/N45
VP/N43
KVP/N46
VP/N44
KVP/N47
VP/N45
VRBP/N
KVP/N0
VgP/N6
CGM1
0
1R
1R
1R
1R
1R
1R
1R
1
1R
1R
1R
1R
2R
V54 P/N
V55 P/N
R55
2
3
1R 1R
1R 1.17R
1R 1.33R
1R 1.5R
2.67R1.67R
1.5R 3.33R 1.83R
3R 5R 2R
V56 P/N
R56
V57 P/N
R57
R58
R59
R60
R61
V58 P/N
V59 P/N
V60 P/N
V61 P/N
V62 P/N
Buffer
KVP/N48
Center adjustment CP/N4
VgP/N7
OP/N0
V63 P/N
Figure 5. 57 Gamma Resister Stream and Gamma Reference Voltage
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.88February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.11.5 Variable Resister
There are two types of variable resistors, one is for center adjustment and the other is
for offset adjustment. The resistances are decided by setting values in the center
adjustment, offset adjustment registers. Their relationship is shown as below.
Value in Register
OP/N0 3-0
0000
0001
0010


1101
1110
1111
Resistance
VRP/N0
0R
3R
6R


39R
42R
45R
Table 5. 22 Offset Adjustment 0
Value in Register
CP/N0 3-0
0000
0001
0010


1100
1101
1110
1111
Resistance
VRTP/N
0R
4R
8R


52R
56R
60R
Value in Register
CP/N4 3-0
0000
0001
0010


1100
1101
1110
1111
Value in Register
OP/N1 4-0
00000
00001
00010


11101
11110
11111
Resistance
VRP/N1
0R
3R
6R


87R
90R
93R
Table 5. 23 Offset Adjustment 1
Resistance
VRBP/N
0R
4R
8R


48R
52R
56R
60R
Value in Register
CP/N3 3-0
0000
0001
0010


1100
1101
1110
1111
Resistance
VRCP/N1
0R
3R
6R


36R
39R
42R
45R
Value in Register
CP/N1 3-0
0000
0001
0010


1100
1101
1110
1111
Resistance
VRCP/N0
0R
3R
6R


36R
39R
42R
45R
Value in Register
CP/N2 3-0
0000
0001
0010


1100
1101
1110
1111
Resistance
VRMP/N0
0R
2R
4R


24R
26R
28R
30R
Table 5. 24 Center Adjustment
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.89February, 2008
HX8353-C
132RGB x 162 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8 to 1 Selector
The 8 to 1 selector has eight input voltages generated by gamma resister stream, and
outputs one reference voltages selected from inputs for gamma reference voltage
generation by setting value in macro adjustment register. There are six 8 to 1
selectors and the relationship is shown as below.
Value in Register
M(P/N) 2-0
000
001
010
011
100
101
110
111
Vg(P/N) 1
VP(N)1
VP(N)2
VP(N)3
VP(N)4
VP(N)5
VP(N)6
VP(N)7
VP(N)8
Vg(P/N) 2
VP(N)9
VP(N)10
VP(N)11
VP(N)12
VP(N)13
VP(N)14
VP(N)15
VP(N)16
Voltage level
Vg(P/N) 3
Vg(P/N) 4
VP(N)17
VP(N)25
VP(N)18
VP(N)26
VP(N)19
VP(N)27
VP(N)20
VP(N)28
VP(N)21
VP(N)29
VP(N)22
VP(N)30
VP(N)23
VP(N)31
VP(N)24
VP(N)32
Vg(P/N) 5
VP(N)33
VP(N)34
VP(N)35
VP(N)36
VP(N)37
VP(N)38
VP(N)39
VP(N)40
Vg(P/N) 6
VP(N)41
VP(N)42
VP(N)43
VP(N)44
VP(N)45
VP(N)46
VP(N)47
VP(N)48
Table 5. 25 Output Voltage of 8 to 1 Selector
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.90February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
The grayscale levels are determined by the following formulas.
Reference
Voltage
VgP/N0
VgP1/VgN7
VgP2/VgN2
VgP3/VgN3
VgP4/VgN4
VgP5Vg/N5
VgP6/VgN6
Formula
---MP/N0 2-0=000
MP/N0 2-0=001
MP/N0 2-0=010
MP/N0 2-0=011
MP/N0 2-0=100
MP/N0 2-0=101
MP/N0 2-0=110
MP/N0 2-0=111
MP/N1 2-0=000
MP/N1 2-0=001
MP/N1 2-0=010
MP/N1 2-0=011
MP/N1 2-0=100
MP/N1 2-0=101
MP/N1 2-0=110
MP/N1 2-0=111
MP/N2 2-0=000
MP/N2 2-0=001
MP/N2 2-0=010
MP/N2 2-0=011
MP/N2 2-0=100
MP/N2 2-0=101
MP/N2 2-0=110
MP/N2 2-0=111
MP/N3 2-0=000
MP/N3 2-0=001
MP/N3 2-0=010
MP/N3 2-0=011
MP/N3 2-0=100
MP/N3 2-0=101
MP/N3 2-0=110
MP/N3 2-0=111
MP/N4 2-0=000
MP/N4 2-0=001
MP/N4 2-0=010
MP/N4 2-0=011
MP/N4 2-0=100
MP/N4 2-0=101
MP/N4 2-0=110
MP/N4 2-0=111
MP/N5 2-0=000
MP/N5 2-0=001
MP/N5 2-0=010
MP/N5 2-0=011
MP/N5 2-0=100
MP/N5 2-0=101
MP/N5 2-0=110
MP/N5 2-0=111
VgP7/VgN7
----
Pin
VREG1-VD*VRP/N0 /sumRP/N
VREG1 –VD((VRP/N0+VRTP/N) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +2R) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +4R) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +6R) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +8R) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +10R) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +12R) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +14R) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +14R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +16R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +18R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +20R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +22R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +24R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +26R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +28R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+48R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+50R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+52R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+54R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+56R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+58R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+60R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+62R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +62R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +64R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +66R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +68R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +70R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +72R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +74R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +76R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +96R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +98R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +100R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +102R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +104R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +106R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +108R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +110R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N+110R+VRCP/N0 +VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +112R+VRCP/N0+VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +114R+VRCP/N0+VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +116R+VRCP/N0+VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +118R+VRCP/N0+VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +120R+VRCP/N0+VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +122R+VRCP/N0+VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +124R+VRCP/N0+VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N0+ VRBP/N+ VRTP/N+ VRMP/N +104R+VRCP/N0+VRCP/N1)
/sumRP/N
KVP0/KVN49
KVP1/KVN48
KVP2/ KVN47
KVP3/ KVN46
KVP4/ KVN45
KVP5/ KVN44
KVP6/ KVN43
KVP7/ KVN42
KVP8/ KVN41
KVP9/ KVN40
KVP10/ KVN39
KVP11/ KVN38
KVP12/ KVN37
KVP13/ KVN36
KVP14/ KVN35
KVP15/ KVN34
KVP16/ KVN33
KVP17/ KVN32
KVP18/ KVN31
KVP19/ KVN30
KVP20/KVN29
KVP21/KVN28
KVP22/ KVN27
KVP23/ KVN26
KVP24/ KVN25
KVP25/ KVN24
KVP26/ KVN23
KVP27/ KVN22
KVP28/ KVN21
KVP29/ KVN20
KVP30/ KVN19
KVP31/ KVN18
KVP32/ KVN17
KVP33/ KVN16
KVP34/ KVN15
KVP35/ KVN14
KVP36/ KVN13
KVP37/ KVN12
KVP38/ KVN11
KVP39/ KVN10
KVP40/ KVN9
KVP41/ KVN8
KVP42/ KVN7
KVP43/ KVN6
KVP44/ KVN5
KVP45/ KVN4
KVP46/ KVN3
KVP47/ KVN2
KVP48/ KVN1
KVP49/ KVN0
SumRP=124R+VRP0+ VRP1+ VRTP+ VRCP0+VRMP+VRCP1+VRBP
SumRN=124R+ VRP0+ VRP1+ VRTP+ VRCP0+VRMP+VRCP1+VRBP
VD=(VREG1–VSS)
Table 5. 26 Voltage Calculation Formula
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.91February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Grayscale
Voltage
V0P/V63N
V1P/V62N
V2P/V61N
V3P/V60N
V4P/V59N
V5P/V58N
V6P/V57N
V7P/V56N
V8P/V55N
V9P/V54N
V10P/V53N
V11P/V52N
V12P/V51N
V13P/V50N
V14P/V49N
V15P/V48N
V16P/V47N
V17P/V46N
V18P/V45N
V19P/V44N
V20P/V43N
V21P/V42N
V22P/V41N
V23P/V40N
V24P/V39N
V25P/V38N
V26P/V37N
V27P/V36N
V28P/V35N
V29P/V34N
V30P/V33N
V31P/V32N
Formula
VgP/N0
VgP/N1
VgP/N2+(VgP/N1-VgP/N2)*CT1
VgP/N2+(VgP/N1-VgP/N2)*CT2
VgP/N2+(VgP/N1-VgP/N2)*CT3
VgP/N2+(VgP/N1-VgP/N2)*CT4
VgP/N2+(VgP/N1-VgP/N2)*CT5
VgP/N2+(VgP/N1-VgP/N2)*CT6
VgP/N2
VgP/N3+(VgP/N2-VgP/N3)*(22/24)
VgP/N3+(VgP/N2-VgP/N3)*(20/24)
VgP/N3+(VgP/N2-VgP/N3)*(18/24)
VgP/N3+(VgP/N2-VgP/N3)*(16/24)
VgP/N3+(VgP/N2-VgP/N3)*(14/24)
VgP/N3+(VgP/N2-VgP/N3)*(12/24)
VgP/N3+(VgP/N2-VgP/N3)*(10/24)
VgP/N3+(VgP/N2-VgP/N3)*(8/24)
VgP/N3+(VgP/N2-VgP/N3)*(6/24)
VgP/N3+(VgP/N2-VgP/N3)*(4/24)
VgP/N3+(VgP/N2-VgP/N3)*(2/24)
VgP/N3
VgP/N4+(VgP/N3-VgP/N4)*(22/23)
VgP/N4+(VgP/N3-VgP/N4)*(21/23)
VgP/N4+(VgP/N3-VgP/N4)*(20/23)
VgP/N4+(VgP/N3-VgP/N4)*(19/23)
VgP/N4+(VgP/N3-VgP/N4)*(18/23)
VgP/N4+(VgP/N3-VgP/N4)*(17/23)
VgP/N4+(VgP/N3-VgP/N4)*(16/23)
VgP/N4+(VgP/N3-VgP/N4)*(15/23)
VgP/N4+(VgP/N3-VgP/N4)*(14/23)
VgP/N4+(VgP/N3-VgP/N4)*(13/23)
VgP/N4+(VgP/N3-VgP/N4)*(12/23)
Grayscale
Voltage
V32P/V31N
V33P/V30N
V34P/V29N
V35P/V28N
V36P/V27N
V37P/V26N
V38P/V25N
V39P/V24N
V40P/V23N
V41P/V22N
V42P/V21N
V43P/V20N
V44P/V19N
V45P/V18N
V46P/V17N
V47P/V16N
V48P/V15N
V49P/V14N
V50P/V13N
V51P/V12N
V52P/V11N
V53P/V10N
V54P/V9N
V55P/V8N
V56P/V7N
V57P/V6N
V58P/V5N
V59P/V4N
V60P/V3N
V61P/V2N
V62P/V1N
V63P/V0N
Formula
VgP/N4+(VgP/N3-VgP/N4)*(11/23)
VgP/N4+(VgP/N3-VgP/N4)*(10/23)
VgP/N4+(VgP/N3-VgP/N4)*(9/23)
VgP/N4+(VgP/N3-VgP/N4)*(8/23)
VgP/N4+(VgP/N3-VgP/N4)*(7/23)
VgP/N4+(VgP/N3-VgP/N4)*(6/23)
VgP/N4+(VgP/N3-VgP/N4)*(5/23)
VgP/N4+(VgP/N3-VgP/N4)*(4/23)
VgP/N4+(VgP/N3-VgP/N4)*(3/23)
VgP/N4+(VgP/N3-VgP/N4)*(2/23)
VgP/N4+(VgP/N3-VgP/N4)*(1/23)
VgP/N4
VgP/N5+(VgP/N4-VgP/N5)*(22/24)
VgP/N5+(VgP/N4-VgP/N5)*(20/24)
VgP/N5+(VgP/N4-VgP/N5)*(18/24)
VgP/N5+(VgP/N4-VgP/N5)*(16/24)
VgP/N5+(VgP/N4-VgP/N5)*(14/24)
VgP/N5+(VgP/N4-VgP/N5)*(12/24)
VgP/N5+(VgP/N4-VgP/N5)*(10/24)
VgP/N5+(VgP/N4-VgP/N5)*(8/24)
VgP/N5+(VgP/N4-VgP/N5)*(6/24)
VgP/N5+(VgP/N4-VgP/N5)*(4/24)
VgP/N5+(VgP/N4-VgP/N5)*(2/24)
VgP/N5
VgP/N6+(VgP/N5-VgP/N6)*CB1
VgP/N6+(VgP/N5-VgP/N6)*CB2
VgP/N6+(VgP/N5-VgP/N6)*CB3
VgP/N6+(VgP/N5-VgP/N6)*CB4
VgP/N6+(VgP/N5-VgP/N6)*CB5
VgP/N6+(VgP/N5-VgP/N6)*CB6
VgP/N6
VgP/N7
Table 5. 27 Voltage Calculation Formula of Grayscale Voltage
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HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
CGM0[1:0]
“00”
“01”
“10”
“11”
CGM1[1:0]
“00”
“01”
“10”
“11”
CT1
6/7
7.5/10.5 10/15
8.5/10.5
CB1
6/7
9.5/10.5
14/15
9.5/10.5
CT2
5/7
6/10.5 6.67/15 6.67/10.5
CB2
5/7
8.5/10.5
13/15 8.33/10.5
CT3
4/7
4/10.5
4/15
5.0/10.5
CB3
4/7
7.5/10.5
12/15
7.0/10.5
CT4
3/7
3/10.5
3/15
3.5/10.5
CB4
3/7
6.5/10.5
11/15
5.5/10.5
CT5
2/7
2/10.5
2/15
2.17/10.5
CB5
2/7
4.5/10.5 8.33/15 3.83/10.5
CT6
1/7
1/10.5
1/15
1/10.5
CB6
1/7
3.0/10.5
5/15
2.0/10.5
Note: Negative gamma don’t have CGM0/CGM1 setting, the ratio V2~V7 and V56~V61 is automatically mapping from
positive side.
Table 5. 28 Voltage Calculation Formula of Grayscale Voltage V2~V7 and V56~V61
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HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Relationship between GRAM Data and Output Level (REV = “0”)
Sn
Vcom
Positive polarity
Negative polarity
Figure 5. 58 Relationship between Source Output and Vcom
V0
Output Level
Negative polarity
Positive polarity
V63
000000
RAM Data
111111
(Same characteristic for each RGB)
Figure 5. 59 Relationship between GRAM Data and Output Level
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HX8353-C
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DATA SHEET Preliminary V01
5.11.6 Gamma Curve Control
There are four kind of Gamma Curve is selected by GAMSET command. The
parameter GC[7:0] is stored in internal register and used to select one set of gamma
correction register.
GC_SEL= Low(VSSD):
Figure 5. 60 Gamma Curve according to the GC0 to GC3 bit (GC_SEL=low)
GC_SEL= high (VDDI):
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HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.12 Oscillator
The HX8353-C can oscillate an internal R-C oscillator with an internal oscillation
resistor (Rf). The oscillation frequency is changed according to the CADJ[3:0] and
RADJ[2:0] internal register. Please refer to extended command set B0h. The default
frequency is 1.5MHz.
Figure 5. 61 Oscillation Circuit
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HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.13 Power On/Off Sequence
VDDI, VDD can be applied in any order. VDDI and VDD can be powered down in any
order. During power off, if LCD is in the Sleep Out mode, VDDI and VDD must be
powered down minimum 120msec after NRESET has been released. During power
off, if LCD is in the Sleep In mode, VDDI or VDD can be powered down minimum
0msec after NRESET has been released. NCS can be applied at any timing or can be
permanently grounded. NRESET has priority over NCS. There will be no damage to
the display module if the power sequences are not met. There will be no abnormal
visible effects on the display panel during the Power On/Off Sequences. There will be
no abnormal visible effects on the display between end of Power On Sequence and
before receiving Sleep Out command. Also between receiving Sleep In command and
Power Off Sequence. If NRESET line is not held stable by host during Power On
Sequence as defined in Sections 5.16.1 and 5.16.2, then it will be necessary to apply
a Hardware Reset (NRESET) after Host Power On Sequence is complete to ensure
correct operation. Otherwise function is not guaranteed. The power on/off sequence
is illustrated below:
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HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.13.1 Case 1 – NRESET line is hold High or Unstable by Host at Power On
If NRESET line is held high or unstable by the host during Power On, then a
Hardware Reset must be applied after both VDD and VDDI have been applied otherwise correct functionality is not guaranteed. There is no timing restriction upon
this hardware reset.
Figure 5. 62 Case 1 – NRESET line is hold High or Unstable by Host at Power On
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HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.13.2 Case 2 – NRESET line is held Low by host at Power On
If NRESET line is held Low (and stable) by the host during Power On, then the
NRESET must be held low for minimum 10μsec after both VDD and VDDI have been
applied.
Figure 5. 63 NRESET line is held Low by host at Power On
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HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.14 Uncontrolled Power Off
The uncontrolled power off means a situation when e.g. there is removed a battery
without the controlled power off sequence. There will not be any damages for the
display module or the display module will not cause any damages for the host or lines
of the interface. At an uncontrolled power off the display will go blank and there will
not be any visible effects within 1 second on the display (blank display) and remains
blank until “Power On Sequence” powers it up.
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HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.15 Power Flow Chart for Different Power Mode
Figure 5. 64 Power Flow Chart for Different Power Modes
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HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.16 Input/Output Pin State
5.16.1 Output or Bi-directional (I/O) Pins
Output or Bi-directional
pins
TE
DB17 to DB0
(Output driver)
VTESTOUT
Low
After Hardware
Reset
Low
High-Z (Inactive)
High-Z (Inactive)
High-Z (Inactive)
Low
Low
Low
After Power On
After Software Reset
Low
Note: There will be no output from D17-D0 during Power On/Off sequence, Hardware Reset and Software Reset.
Table 5. 29 The State of Output or Bi-directional (I/O) Pins
5.16.2 Input Pins
Input pins
NRESET
NCS
SPI_SEL
GC_SEL
LC_SEL0, LC_SEL1
DNC_SCL
NWR_RNW
NRD_E
DB17 to DB0
OSC,P68,BS1,BS2,BS0
EXTC
TEST1
TEST2
TEST3
RSO0
RSO1
RSO2
During
After
After
Power
Power
Hardware
On Process
On
Reset
See Section
Input valid
Input valid
5.17
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Table 5. 30 The State of Input Pins
After
Software
Reset
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
During
Power
Off Process
See Section
5.17
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
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HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.17 Sleep Out – Command and Self-Diagnostic Functions of the Display Module
5.17.1 Register loading Detection
Sleep Out-command (See section 6.2.12 “Sleep Out (11h)”) is a trigger for an internal
function of the display module, which indicates, if the display module loading function
of factory default values from OTP (or similar device) to registers of the display
controller is working properly.
There are compared factory values of the OTP and register values of the display
controller by the display controller. If those both values (OTP and register values) are
same, there is inverted (=increased by 1) a bit, which is defined in command 6.2.10
“Read Display Self-Diagnostic Result (0Fh)” (=RDDSDR) (The used bit of this
command is D7). If those both values are not same, this bit (D7) is not inverted (=
increased by 1).
The flow chart for this internal function is following:
Power on sequence
HW reset
SW reset
Sleep In (10h)
Sleep Out
Mode
Sleep In
Mode
RDDSDR`s D7=0
Sleep Out (11h)
Compares E-Fuse and register values
Load
EEPROM to
register
NO
Are E-FUSE and
register values the
same
YES
D7 inverted
Note: There is not compared and loaded register values, which can be changed by User (User area commands: 00h to
AFh and DAh to DDh), by the display module.
Figure 5. 65 Register loading Detection Flow
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HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.17.2 Functionality Detection
Sleep Out-command (See section 6.2.12 “Sleep Out (11h)”) is a trigger for an internal
function of the display module, which indicates, if the display module is still running
and meets functionality requirements.
The internal function (= the display controller) is comparing, if the display module is
still meeting functionality requirements (e.g. booster voltage levels, timings, etc.). If
functionality requirement is met, there is inverted (= increased by 1) a bit, which
defined in command 6.2.10 “Read Display Self- Diagnostic Result (0Fh)”(= RDDSDR)
(The used bit of this command is D6). If functionality requirement is not same, this bit
(D6) is not inverted (= increased by 1). The flow chart for this internal function is
following:
Power on sequence
HW reset
SW reset
Sleep In (10h)
Sleep Out
Mode
Sleep In
Mode
RDDSDR`s D6=0
Sleep Out (11h)
Checks timings, voltage levels and other
functionalities
NO
Is functionality
requirement meet ?
YES
D6 inverted
Note: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In –mode to Sleep Out
-mode, before there is possible to check if User’s functionality requirements are met and a value of RDDSDR’s D6
is valid. Otherwise, there is 5msec delay for D6’s value, when Sleep Out –command is sent in Sleep Out -mode.
Figure 5. 66 Functionality Detection Flow
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DATA SHEET Preliminary V01
5.18 OTP Programming
OTP index
[7:0]
0
CADJ[3]
CADJ[2]
CADJ[1]
CADJ[0]
BGP[3]
BGP[2]
BGP[1]
BGP[0]
1
ID1[7]
ID1[6]
ID1[5]
ID1[4]
ID1[3]
ID1[2]
ID1[1]
ID1[0]
2
NVALID_VCM0
VCM0[6]
VCM0[5]
VCM0[4]
VCM0[3]
VCM0[2] VCM0[1] VCM0[0]
3
NVALID_VCM1
VCM1[6]
VCM1[5]
VCM1[4]
VCM1[3]
VCM1[2] VCM1[1] VCM1[0]
4
NVALID_VCM2
VCM2[6]
VCM2[5]
VCM2[4]
VCM2[3]
VCM2[2] VCM2[1] VCM2[0]
5
LUT_EN
RADJ[1]
RADJ[0]
VDV[4]
VDV[3]
VDV[2]
VDV[1]
VDV[0]
6
NVALID1
ID2[6]
ID2[5]
ID2[4]
ID2[3]
ID2[2]
ID2[1]
ID2[0]
7
ID3[7]
ID3[6]
ID3[5]
ID3[4]
ID3[3]
ID3[2]
ID3[1]
ID3[0]
Table 5. 31 OTP memory table
For OSC adjust and BGAP voltage adjust are valid only Himax provide)
For Module suplier program
For Module suplier program
For Module suplier program
For Module suplier program
Note 1: (1) The default value of OTP memory bits are all “0”.
Note 2: NAVLID1, NVALID_VCM[2:0] bit decide the OPT reload Enable/Disable, the default value is “0”. If
the own OTP area of NAVILD bit had been programmed, the NAVILD bit will be changed to “1”
automatically and execute the OTP reload.
For example:
Condition 1: Programmed all index of 0X01h, 0X06h and 0X07h
NAVILD1 =
0
Programmed
0x01h, 0x06h,
0x07h
(NAVLID= 1" )
Check
NAVILD1= 1"
Reload
0x01h, 0x06h,
0x07h
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DATA SHEET Preliminary V01
Condition 2: Do not program all index of 0X01h, 0X06h and 0X07h
Note 3: There are some conditions that HX8353-C can reload OTP.
1. Hardware reset
2. Software reset
3. SLPOUT command.
Note 4: User can use GETOTP command to read back the OTP values. Similarly, the user also can use
GETOTP to read the index 0x02h, 0x03h and 0x04h that is defined the NVALID bit for VCM0,
VCM1 and VCM2 (NVALID_VCM0, NAVLID_VCM1 and NAVLID_VCM2). User can read back the
NVALID_VCM0, NAVLID_VCM1 and NAVLID_VCM2 (use GETOTP command to know how many
times of VCM had programmed on OTP.
NVALID_VCM2
NVALID_VCM1
NVALID_VCM0
Programed 0 time
0
0
0
Programed 1 time
0
0
1
Programed 2 times
0
1
1
Programed 3 times
1
1
1
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DATA SHEET Preliminary V01
Programming Flow
OTP Program Flow
No
VCM0[6:0], VCM1[6:0], VCM2[6:0]
Yes
VCM0[6:0], VCM1[6:0],
VCM2[6:0]
Yes
Yes
VCM0[6:0], VCM1[6:0], VCM2[6:0]
No
No
END
Figure 5. 67 OTP Programming Flow
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HX8353-C
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DATA SHEET Preliminary V01
Programming sequence
Step
1
2
3
4
Operation
Power on and reset the module
Set OTP_LOAD_DISABLE=1, disable the auto-loading function.
SLPOUT command (11h)
Wait 120ms
Write optimized value to related register
Command
Register
VCM[6:0]
5
SETVCOM (B6h)
VDV[4:0]
SETID (C4h)
6
7
8
9
10
11
12
13
ID1[7:0]
ID2[6:0]
ID3[7:0]
Description
VcomH voltage for normal mode, Idle mode
and Partial Idle mode
(High level voltage of VCOM)
Vcom amplitude (VcomL = VcomH – Vcom
amplitude, VcomL ≥ VCL+0.5V)
LCD module/driver version
LCD module/driver version
Identifies the LCD module/driver
Set OTP_ DCCLK_DISABLE=1, disable internal pumping clock.
Connect external power 6.5V to VGH pin
Wait 100ms for external power 6.5V to stabilize.
Specify OTP_index
OTP_index
OTP_index
(Write – For Program) (Read – For get OTP value)
Parameter
0x05h
0x05h
VDV[4:0],
0x06h
0x06h
ID2[6:0]
0x07h
0x07h
ID3[7:0]
0x01h
0x01h
ID1[7:0]
0x02h
0x02h
VCM0[6:0]
0x03h
0x03h
VCM1[6:0]
0x04h
0x04h
VCM2[6:0]
Set OTP_Mask=0x00h, programming the entire bit of one parameter.
Set OTP_EN=1, Internal register begin write to OTP according to OTP_index.
Wait 1 ms
Complete programming one parameter to OTP. If continue to programming other parameter, return to
step (9). Otherwise, power off the module and remove the external power on VGH pin.
Programming circuitry
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162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.19 Free Running Mode Specification
Burn-in of TFT displays consists of driving each module for 10hr at a temperature of
60C. In order to drive the modules, it requires extra electronics. To reduce the
burn-in cost, it is requested that the driver IC will generate the required display image
without requiring extra electronics. We term this a free running mode (FR-mode). For
burn-in, it is sufficient that the display is powered up with a plane saturated black or
saturated white pattern. Black should be used for burn-in, since this result in a larger
pixel voltage. White is used to verify if the free running mode is properly functioning.
Please note that the black and the white pattern are reversed in case of a normally
black display.
Parameter
Power supply pins
Free running mode
Reset
(1)
Chip select
(1)
Reads/not write
(1)
Data/not command
(1)
SPI I/F select
TE select
(1)
CPU I/F Data
SPI I/F
Symbol
VDDI, VDD
BURN
NRESET
NCS
NWR_RNW
DNC_SCL
SPI_SEL
STE_SEL
D[0..17]
SCL
Description
All power supply pins
BURN=1, FR-mode is enabled.
Active low pulse in order to start the FR-mode.
This pin will be left open during FRM mode.
This pin will be left open during FRM mode.
This pin will be left open during FRM mode.
This pin will be left open during FRM mode.
This pin will be left open during FRM mode.
This pin will be left open during FRM mode.
This pin will be left open during FRM mode.
Note: (1) As a general rule, all control pins of the interfaces like chip-select, data-enable, etc, must be disabled, all
modes select pins like data-not-command, interface-select etc and all data-bus pins must be set to
either logic high or logic low during the FR-mode.
Table 5. 32 Pin Information
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HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Power-on Sequence of Free Running Mode
The FR-mode starts automatically after the power supply is switched on and a reset
pulse is applied to the Reset-pin, if the BURN pin is set to logical high. In case of
separate supply pins for the analogue supply and digital supply, both supply pins will
be connected together, if it is supported by the driver specification. Otherwise, each
supply voltage will be switched on separately according to the requested power-on
sequence. The BURN and all other digital I/F pins, which will be set to logic high
during the free running mode, can be switched to logic high together with the digital
supply pin. The FR-mode will be restarted if the reset pulse is applied a second time.
The OTP starts to load when Reset leaves low to high.
Figure 5. 68 Power On Sequence of FR-mode (for Normally–White Panel)
Power off Sequence of Free Running Mode
The power supply can be switched off any time.
VCI
BURN
Mdk
(Option)
Figure 5. 69 Power Off Sequence of FR-mode
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.110February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Free Running Mode Display
The display will show an alternating black and white picture for about the first 5
minutes. The black to white ratio shell be 50%/50%. The time of the black and white
pattern shell is around 1 second in order to avoid a too long waiting time to verify that
the FR-mode is functioning properly. The display is switched to a static black pattern
after the alternating mode is finished. Thus, most efficient burn-in stress is ensured.
The display shall work in idle-mode. There is no special restriction for the frame
frequency. The frame frequency will be set according to the parameter in the OTP.
Alternating Black and White Pattern tAlternating - 5
min
f
Master Clock Frequency
- - 1.5 MHz
Mclk
Table 5. 33 Frequency Definition of Free Running Mode Display
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.111February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6. Command
6.1 Command Compare Table
Table 6. 1 MPU Interface Command Set
Operation
(Hex)
DNC NWR NRD D15-8 D7
Code
00
NOP
0
↑
1
0
01
SWRESET
0
↑
1
0
04
09
0A
RDDIDIF
RDDST
RDDPM
0B
RDDMADCTL
0C
RDDCOLM
OD
0D
0E
0F
RDDIM
RDDSM
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Function
No Operation
Software reset
Read Display
0 Identification
Information
- Dummy read
xx ID1 read
V0 ID2 read
xx ID3 read
Read Display
1
Status
- Dummy read
0
↑
1
-
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
↑
↑
↑
↑
-
xx
1
xx
xx
V6
xx
xx
V5
xx
xx
V4
xx
xx
V3
xx
xx
V2
xx
xx
V1
xx
0
↑
1
-
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
↑
↑
↑
↑
↑
-
-
-
-
-
D[31:24]
D[23:16]
D[15:8]
D[7:0]
-
0
↑
1
-
0
0
0
0
1
0
1
0
1
1
1
1
↑
↑
-
-
-
-
-
D[7:0]
-
-
-
0
↑
1
-
0
0
0
0
1
0
1
1
1
1
1
1
↑
↑
-
-
-
-
-
D[7:0]
-
-
-
0
↑
1
-
0
0
0
0
1
1
0
0
1
1
1
1
↑
↑
-
-
-
-
-
D[7:0]
-
-
-
0
↑
1
-
0
0
0
0
1
1
0
1
1
1
1
1
↑
↑
-
-
-
-
-
D[7:0]
-
-
-
0
↑
1
-
0
0
0
0
1
1
1
0
1
1
1
1
↑
↑
-
-
-
-
-
D[7:0]
-
-
-
0
↑
1
-
0
0
0
0
1
1
1
1
1
1
1
1
↑
↑
-
-
-
-
D[7:0]
-
-
-
RDDSDR
Himax Confidential
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in whole or in part without prior written permission of Himax.
Read Display
Power Mode
Dummy read
Read Display
MADCTL
Dummy read
Read Display
Pixel Format
Dummy read
Read Display
Image Mode
Dummy read
Read Display
Signal Mode
Dummy read
Read Display
Self-Diagnostic
Result
Dummy read
-P.112February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(Hex)
Operation
Code
10
SLPIN
0
↑
1
-
11
SLPOUT
0
↑
1
12
PTLON
0
↑
13
NORON
0
20
INVOFF
21
INVON
26
GAMSET
28
29
DISPOFF
DISPON
2A
CASET
2B
PASET
2C
RAMWR
2D
Colour set
2E
RAMRD
30
PLTAR
33
VSCRDEF
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
0
0
0
-
0
0
0
1
0
0
0
1
1
-
0
0
0
1
0
0
1
0
↑
1
-
0
0
0
1
0
0
1
1
0
↑
1
-
0
0
1
0
0
0
0
0
0
↑
1
-
0
0
1
0
0
0
0
1
0
1
0
0
↑
↑
↑
↑
1
1
1
1
-
0
0
1
0
1
0
0
0
0
0
1
1
0
1
GC[7:0]
0
1
0
0
1
0
0
0
0
1
0
↑
1
-
0
0
1
↑
1
-
1
↑
1
-
1
↑
1
-
1
↑
1
-
0
1
1
1
1
0
1
0
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
-
0
0
0
0
-
0
0
1
↑
1
-
X
X
1
1
1
1
1
1
1
0
1
1
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
1
↑
↑
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Rnn5
R315
G005
Gnn5
G635
B005
B315
Rnn2
R312
G002
Gnn2
G632
B002
B312
Rnn1
R311
G001
Gnn1
G631
B001
B311
Rnn0
R310
G000
Gnn0
G630
B000
B310
0
-
0
-
1
-
1
-
1
-
0
-
0
↑
1
-
0
0
1
1
0
0
0
1
1
1
1
0
↑
↑
↑
↑
↑
1
1
1
1
1
-
1
SR[15:8]
SR[7:0]
ER[15:8]
ER[7:0]
1
0
0
1
1
1
↑
1
-
1
↑
1
-
1
↑
1
-
0
0
Function
Sleep in and
charge-pump off
Sleep out and
charge-pump on
Partial Mode On
Normal Display
Mode On
Display Inversion
Off
Display Inversion
On
Gamma Set
Display off
Display on
Read Display
1
0
1
0
1
0
Status
Column address
SC[15:8]
start
Column address
SC[7:0]
start
Column address
EC[15:8]
end
Column address
EC[7:0]
end
1
0
1
0
1
1 Row address set
SP[15:8]
Row address start
SP[7:0]
Row address start
EP[15:8]
Row address end
EP[7:0]
Row address end
1
0
1
1
0
0 Memory write
D[15:0]
Write data
1
0
1
1
0
0 Colour set
Total 128
R005 R004 R003 R002 R001 R000
parameters
Rnn4
R314
G004
Gnn4
G634
B004
B314
Rnn3
R313
G003
Gnn3
G633
B003
B313
0
1
D[15:0]
0
TFA1 TFA1 TFA1 TFA1
TFA1
TFA11
TFA9 TFA8
5
4
3
2
0
TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0
VSA1 VSA1 VSA1 VSA1 VSA1 VSA1
VSA9 VSA8
5
4
3
2
1
0
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
Memory read
Dummy read
Read data
Partial start end
address set
Start row
Start row
End row
End row
Vertical Scrolling
Definition
-P.113February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
34
TEOFF
35
TEON
36
MADCTL
37
VSCRSADD
1
↑
1
-
1
↑
1
-
1
0
0
1
↑
↑
↑
↑
1
1
1
1
-
0
↑
1
-
0
↑
1
-
0
↑
1
-
1
↑
1
-
VSP15 VSP14 VSP13 VSP12 VSP11 VSP10
1
↑
1
-
VSP7 VSP6 VSP5 VSP4 VSP3 VSP2 VSP1 VSP0
VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0
BFA1 BFA1 BFA1 BFA1
BFA1
BFA11
BFA9 BFA8
5
4
3
2
0
BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
1
1
MY MX
(0) (0)
0
0
MV
(0)
1
ML BGR SS
(0) (0) (0)
1
0
1
0 Tear Effect On/Off
1 Tear Effect Mode
M(0)
Memory Access
0
Control
0
0
1
1
Vertical Scrolling
Start Address
VSP9 VSP8
38
IDMOFF
0
↑
1
-
0
0
1
1
1
0
0
0
Idle Mode off
39
IDMON
0
↑
1
-
0
0
1
1
1
0
0
1
3A
COLMOD
0
↑
1
-
0
0
1
1
1
0
1
0
Idle Mode on
Interface Pixel
Format
1
0
0
1
0
1
1
0
1
1
↑
↑
1
1
↑
1
1
↑
1
1
1
1
↑
↑
1
↑
↑
1
↑
↑
-
1
-
DA
RDID1
DB
RDID2
DC
RDID3
1
1
1
-
CSEL_RGB[2:0] CSEL[2:0]
1
0
1
1
0
1
0
module’s manufacturer[7:0]
1
0
1
1
0
1
1
V6 V5 V4 V3
V2 V1
V0
1
0
1
1
1
0
0
LCD module/driver ID[7:0]
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
Read ID1
Dummy read
Read ID2
Dummy read
Read ID3
Dummy read
-P.114February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.2 User Define Command List Table
User define command list is available only under “EXTC=1” or enable PASSWDEN
command (even EXTC = low), if EXTC=0 (No enable PASSWDEN command )all user
define write command is seen as “NOP”, of Hi-Z data bus if any user defined read
command.
6.2.1 Command List
Table 6. 2 User Command Set
Operation
D15(Hex)
DNC NWR NRD
Code
8
B0
B1
B2
B3
SETOSC
SETPOWER
SETDISP
SETCYC
B5
SETBGP
B6
SETVCOM
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
0
0
0
0
OSC_
EN_C
ON(0)
-
UADJ[2:0](001)
-
-
-
OSC_E
N (0)
-
0
↑
1
-
1
1
↑
↑
1
1
-
1
↑
1
-
-
-
-
0
↑
1
-
1
0
1
1
0
0
0
1
1
↑
1
-
GASE
NB (0)
-
-
PON (0)
DK (1)
-
-
STB(0)
1
1
1
1
1
1
1
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
-
-
1
↑
1
-
-
0
↑
1
-
1
1
↑
1
-
1
1
1
1
1
1
1
1
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
-
1
↑
0
↑
SETLUT
B4
D7
-
-
CADJ[3:0](1000)
-
Set Internal
Oscillator
RADJ[1:0](01)
Set power
AP[2:0] (000)
VC1[2:0] (011)
VRH[3:0](0100)
BT[3:0] (0011)
FS1[1:0] (01)
FS0[1:0] (00)
N_DC[7:0] (0100_1010)
E_DC[7:0](0100_1010)
DCCLK_SYNC
(1)
0
PT[1:0] (00)
-
Function
-
-
-
-
-
-
-
1
-
-
-
1
-
1
1
GON
(1)
-
-
1
0
0
1
DTE
D[1:0] (00)
(0)
N_BP[3:0] (1101)
N_FP[3:0] (1010)
SAP[7:0]
EQS[7:0]
EQP[7:0]
GEN_OFF[3:0]
PTG[1:0] (10)
SAP_I[7:0]
Set display
related register
0
-
ISC[3:0] (0010)
-
-
-
-
-
OPTION_DISP(
0)
0
1
1
0
0
1
1
-
-
-
-
-
1
0
1
0
0
1
1
↑
-
-
-
LUT_E
NB(0)
0
↑
1
-
1
0
1
1
1
1
1
1
1
0
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
-
N_RTN[3:0] (1101)
N_NW[2:0] (001)
E_RTN[3:0] (1101)
E_NW[2:0] (000)
DIV_E[1:0] (00)
SON[7:0] (0001_1001)
GDON[7:0] (0001_1110)
GDOF[7:0] (0111_1000)
1
0
1
1
0
1
0
1
1
↑
1
-
-
-
-
-
0
↑
1
-
1
0
1
1
0
1
1
0
1
↑
1
-
-
-
-
-
-
-
-
1
↑
1
-
VCO
MG (0)
-
1
↑
1
-
-
(P/H default)
Set Display
cycles
Set BGP Voltage
BGP[3:0] (1000)
Set VCOM
Voltage
VCMN [6:0] (100_0100)
-
-
VDV[4:0] (0_1101)
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.115February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(Hex)
B7
Operation
DNC NWR NRD D15-8 D7
Code
SETGAMMA
B9
PASSWDEN
BA
PASSWDDIS
AB
(Hex)
BC
BD
BE
BF
C0
SETVDC
SETSPULSE
SETPROBE
SETPTBA
SETSTBA
C1
SETPFUSE
C4
SETID
C6
SETECO
D4
0
----
1
D0
1
-----
0
↑
1
-
1
0
1
1
1
0
0
1
1
1
↑
↑
1
1
-
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
1
0
↑
1
-
1
0
1
1
1
0
1
0
D7
D6
D5
D4
D3
D2
1
0
1
↑
↑
↑
1
1
1
-
1
D1
-
-----
1
MP1[2:0](101)
MP3[2:0](101)
MP5[2:0](000)
--CP2[3:0](1001)
----------MN1[2:0](111)
MN3[2:0](001)
MN5[2:0](100)
--CN2[3:0](1000)
---------
D2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
----------
0
D3
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
Operation
DNC NWR NRD D15-8
Code
SETOTP
D5
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
BB
D6
------
-----
1
1
MP0[2:0](000)
MP2[2:0](101)
MP4[2:0](101)
CP0[3:0](0010)
CP1[3:0](1111)
CP3[3:0](0101)
CP4[3:0](0010)
OP0[3:0](0010)
OP1[4:0](0_0110)
CGM1[1:0](10)
CGM0[1:0](10)
-MN0[2:0](101)
-MN2[2:0](000)
-MN4[2:0](000)
CN0[3:0](0011)
CN1[3:0](0011)
CN3[3:0](1111)
CN4[3:0](0000)
ON0[3:0](0001)
ON1[4:0](1_0111)
1
1
0
OTP_ MASK[7:0] (0000_0000)
OTP_INDEX[7:0] (1111_1111)
Function
Set Gamma
Pass word enable
command
17H == >04H
ccH == >17H
Pass word disable
command
D1
D0
1
1
Function
Set OTP
OTP_L DCCLK
OTP_ OTP_P OTP_E OTPTEST
OAD_
_
VPP_SE OTP_PRO
WE
N
DISAB DISABL POR
L(0)
G(0)
_EN(0)
LE
E
(0)
(0)
(0)
(0)
(0)
OTP_PTM[1:0](0
OTP_VRADJ[1:0](00)
0)
1
↑
1
-
1
↑
1
-
0
↑
1
-
1
0
1
1
1
1
↑
1
-
-
-
-
-
-
0
↑
1
-
1
0
1
1
1
1
1
0
↑
↑
↑
1
1
1
-
1
0
1
1
↑
1
-
-
-
-
1
0
1
1
0
0
1
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
-
1
↑
1
-
0
1
0
1
1
1
0
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
-
1
↑
1
1
0
1
1
1
0
1
1
0
0
1
0
1
-
0
-
-
0
Set internal
digital and
GRAM voltage
VDC_SEL[2:0] (010)
1
RTBA[13:8](000000)
RTBA[7:0](1101_1011)
1
1
1
-
PROB[7:0] (8'b0)
1
1
1
PTBA[15:8] (00100100)
PTBA[7:0] (00000100)
0
0
0
STBA[7:0] (1000_1011)
STESTOE[1:0](00
)
0
0
0
0
0
1
ID1[7:0] (0100_0111)
ID2[6:0] (000_0001)
ID3[7:0] (0000_0000)
0
0
1
ECO0[7:0] (0000_0000)
ECO1[7:0] (0000_0000)
VTESTSEL[3:0] (0000)
1
1
1
0
1
1
TEST_
MODE(0)
0
TEST_
OE(0)
1
1
0
0
STBA[8](1)
-
-
0
0
1
PFUSE(0)
0
1
0
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
Set SRAM
Arbiter pulse
-P.116February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(Hex)
CA
CB
CC
Operation
DNC NWR NRD D15-8 D7
Code
D6
D5
D4
D3
D2
D1
D0
0
↑
1
-
1
1
0
0
1
0
1
0
1
↑
1
-
-
-
-
-
-
-
SFULL(0)
-
0
1
↑
↑
1
1
-
1
1
0
1
↑
1
-
0
↑
1
-
1
↑
1
-
SETMREV
SETIOOPT
SETPANEL
0
1
0
IO_OPT[7:0] (0101_0101)
1
1
0
0
1
SM_PA SS_PA
NEL(0) NEL(0)
For Free Running
Mode
1
IO_OPT2[7:6]=>
SDI
IO_OPT2[7:0] (0000_0000)
1
Function
1
0
0
-
-
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
Set Panel
characteristics
-P.117February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(Hex)
E0
E1
E2
E3
E4
Operation
DNC NWR NRD D15-8 D7
Code
D6
D5
D4
D3
D2
D1
D0
0
↑
1
-
1
1
0
0
0
0
0
1
1
1
1
1
1
↑
↑
↑
-
1
1
↑
-
-
0
↑
1
-
1
1
1
↑
1
1
↑
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
↑
↑
↑
↑
↑
↑
↑
-
1
1
↑
-
-
0
↑
1
-
1
1
1
↑
1
1
↑
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
↑
↑
↑
↑
↑
↑
↑
↑
↑
-
1
1
↑
-
0
↑
1
-
1
1
↑
1
1
↑
-
-
-
0
↑
1
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
↑
↑
↑
↑
↑
↑
↑
-
GETOSC
GETPOWER
GETDISP
GETLUT
GETCYC
1
Dummy Read or Dummy Clock
CADJ[3:0] (1000)
UADJ[2:0] (011)
RADJ[2:0]
OSC_E
OSC_E
N_CON
N(0)
(1)
1
1
0
0
0
0
Function
Get Internal
Oscillator
-
-
1
Get power
Dummy Read or Dummy Clock
-
GASE
B(0)
-
-
-
PON(0) DK(1)
-
-
-
-
1
1
0
0
--
--
STB(0)
AP[2:0] (000)
VC1[2:0] (011)
VRH[3:0] (0010)
BT[3:0] (0011)
FS1[1:0]
FS01[1:0] (00)
N_DC[7:0] (0011_0111)
E_DC[7:0] (0011_0111)
DCCLK_SYNC(
1)
0
1
Get display
related register
0
Dummy Read or Dummy Clock
GON(
DTE(0)
PT[1:0](00)
D[1:0](00)
0
0
1)
N_BP[3:0](1101)
N_FP[3:0] (1010)
SAP [7:0]
EQS[7:0]
EQP[7:0]
GEN_OFF[3:0]
PTG[1:0](10)
ISC[3:0] (0010)
SAP_I[7:0]
PTG[1:0]
ISC[3:0]
OPTION_DISP(
0)
1
-
1
1
0
0
0
1
Dummy Read or Dummy Clock
LUT_E
N(0)
1
0
0
1
0
1
Get LUT interface
related register
-
0
Get Display
waveform cycle
Dummy Read or Dummy Clock
N_RTN[3:0](1101)
N_NW[2:0] (001)
E_RTN[3:0] (1101)
E_NW[2:0] (000)
DIV_E[1:0]
SON[7:0](0001_1001)
GDON[7:0] (0001_1110)
GDOF[7:0] (0111_1000)
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.118February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(Hex)
E5
E6
E7
E8
EB
EC
ED
EE
EF
Operation
DNC NWR NRD D15-8 D7
Code
D6
D5
D4
D3
D2
D1
D0
0
↑
1
-
1
1
1
0
0
1
0
1
Get BGP
Voltage
1
1
1
1
↑
↑
-
-
-
-
0
↑
1
-
1
1
1
0
0
1
1
0
Get VCOM
Voltage
1
1
↑
-
-
-
-
-
-
-
-
1
1
1
1
↑
↑
-
-
0
↑
1
1
1
1
1
↑
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
-
VCO
MG(0)
-
1
1
↑
-
1
1
1
1
0
1
1
1
1
↑
↑
↑
↑
↑
1
1
1
1
1
↑
↑
0
↑
1
-
1
1
1
1
1
1
↑
↑
↑
-
1
1
↑
-
1
1
1
1
↑
↑
0
↑
1
1
GETBGP
GETVCOM
GETGAMMA
GETCPCRC
GETOTP
1
Dummy Read or Dummy Clock
BGP[3:0](1000)
VCMPN[6:0](101_0101)
VDV[4:0] (1_0000)
0
0
1
1
1
GETPROBE
MP12
MP32
MP52
-CP23 CP22
-----MN12
MN32
MN52
-CN2
CN22
3
----1
1
-
MP11
MP31
MP51
-CP21
----
MP10
MP30
MP50
-CP20
----OP14
--MN11 MN10
MN31 MN30
MN51 MN50
---
-MP02
-MP22
-MP42
CP03 CP02
CP13 CP12
CP33 CP32
CP43 CP42
OP03 OP02
OP13 OP12
CGM1[1:0]
-MN02
-MN22
-MN42
CN03 CN02
MP01
MP00
MP21
MP20
MP41
MP40
CP01
CP00
CP11
CP10
CP31
CP30
CP41
CP40
OP01
OP00
OP11
OP10
CGM0[1:0]
MN01
MN00
MN21
MN20
MN41
MN40
CN01
CN00
CN21
CN20 CN13
CN12
CN11
CN10
----
---CN43
-ON03
ON14 ON13
0
1
CN32
CN42
ON02
ON12
0
CN31
CN49
ON01
ON11
0
CN30
CN40
ON00
ON10
0
1
1
VPP_SEL
OTP_PROG
--
1
1
1
1
0
1
0
OTP_
POR
-
-
--
--
1
-
1
1
1
1
1
↑
↑
-
-
-
-
0
↑
1
-
1
1
1
1
1
1
1
↑
-
1
1
0
↑
↑
↑
1
1
↑
-
1
1
1
1
↑
-
-
-
-
-
-
1
1
1
0
GETPTBA
1
↑
↑
1
1
1
1
1
1
1
↑
↑
↑
Get OTP
Dummy Read or Dummy Clock
OTP_ MASK[7:0]
OTP_INDEX[7:0]
DCCLK_
DISABLE
1
Get CPCRC
Dummy Read or Dummy Clock
CPCRC7:0]
OTP_L
OAD_
DISABL
E
0
Get Gamma
Dummy Read or Dummy Clock
OTP_PWE OTP_EN
--
OTPEST_
ENB
OTP_PTM[1:0](00)
OTP_VRADJ[1:0](00)
OTP_DATA[7:0]
0
1
1
0
0
Get internal
digital and
GRAM voltage
1
Get SRAM
Arbiter pulse
GETVDC
GETSPULSE
Function
Dummy Read or Dummy Clock
VDC_SEL[2:0]
0
1
1
0
Dummy Read or Dummy Clock
RTBA[15:8]
-
RTBA[7:0]
1
1
0
1
1
1
0
-
TEST_
MODE(0)
TEST_
OE(0)
1
1
1
Dummy Read or Dummy Clock
PROB[7:0](8’b0)
1
Dummy Read or Dummy Clock
PTBA[15:8](0010_0100)
PTBA[7:0] (0000_0100)
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.119February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(Hex)
F0
F1
F4
Operation
DNC NWR NRD D15-8 D7
Code
D6
D5
D4
D3
D2
D1
D0
Function
0
↑
1
-
1
1
1
0
0
0
0
Get Source
option
1
1
1
1
1
1
↑
↑
↑
-
1
1
↑
-
1
0
1
↑
↑
1
-
1
1
↑
0
1
1
1
1
0
1
1
1
1
0
1
↑
1
1
1
1
↑
↑
↑
↑
↑
↑
1
1
↑
↑
↑
↑
1
1
1
1
1
1
↑
-
1
1
↑
-
-
-
-
0
1
1
↑
1
1
1
↑
↑
-
1
1
1
1
1
↑
-
0
1
↑
1
1
↑
-
1
1
1
↑
-
0
1
↑
1
1
↑
-
1
↑
1
-
1
1
1
1
1
1
1
1
1
0
1
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
1
1
↑
-
GETSTBA
GETPFUSE
GETHXID
F6
GETECO
FA
GETMREV
FB
FC
GETIOOPT
1
Dummy Read or Dummy Clock
STBA[8]
STBA[7:0](1000_1011)
STESTOE[1:0](00
VTESTSEL[3:0](0000)
)
-
1
1
1
1
0
0
0
1
-
-
-
-
-
-
-
PFUSE(0)
1
1
1
1
0
1
0
0
1
0
1
0
-
Dummy Read or Dummy Clock
ID_version[7:0](53h)
ID2_version [7:0](0Ch)
VersionID[7:0](00h)
-
1
1
FE
FF
GETTS
1
1
0
1
Dummy Read or Dummy Clock
ECO0[7:0](8’b0)
ECO1[7:0] (8’b0)
1
1
1
1
1
0
Dummy Read or Dummy Clock
-
-
-
SFULL(0)
-
1
1
0
1
1
For Free
Running Mode
Dummy Read or Dummy Clock
IO_OPT[7:0] (0101_0101)
IO_OPT2[7:0] (0000_0000)
1
1
0
0
-
-
Dummy Read or Dummy Clock
SM_PA SS_PA
NEL
NEL
-
-
-
1
1
1
1
0
GETPANEL
GETWINDO
W
Get internal
OTP
Get Himax ID
1
1
1
1
1
1
Dummy Read or Dummy Clock
It is for internal
use, not open.
SC[7:0]
1
-
1
EC[7:0]
SP[7:0]
EP[7:0]
PSL[7:0]
PEL[7:0]
TFA[7:0]
VSA[7:0]
BFA[7:0]
VSP[7:0]
1
1
1
1
Dummy Read or Dummy Clock
IO_OPT2[7:6]=
>SDI
GET_PANEL
1
1
It is for internal
use, not open.
TS[6:0]
Note: (1) Undefined commands are treated as NOP (00H) command.
(2) B0 to D9 and DE to FF are for factory use of display module supplier. User can decide if these commands are available
or they are treated as NOP (00H) commands before shipped to User. Default value is NOP(00H). If pin EXTC is tied to
high, B0 to D9 and DE to FF extended command sets are accepted, other extended command sets are discarded.
(3) Commands 10H, 12H, 13H, 20H, 21H, 26H, 28H, 29H, 30H, 36H (Bit B4 only), 38H and 39H are updated during V-sync
when Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are
updated immediately. Read status (09H), Read Display Power Mode (0AH), Read Display MADCTL (0BH), Read Display
Pixel Format (0CH), Read Display Image Mode (0DH), Read Display Signal Mode (0EH) and Read Display Self
Diagnostic Result (0FH) of these commands is updated immediately both in Sleep In Mode and Sleep Out Mode.
(4) SETGAMMA and GETGAMMA can’t be set at the same time.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.120February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3 Command Description
6.3.1 NOP
00 H
Command
Parameter
Description
NOP (No Operation)
DNC NWR NRD D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
0
0
0
0
0
0
00
NO PARAMETER
This command is an empty command; it does not have any effect on the display
module.
However it can be used to terminate Frame Memory Write or Read as described
in RAMWR (Memory Write) and RAMRD (Memory Read) Commands.
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
N/A
N/A
N/A
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.121February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.2 Software Reset (01h)
01 H
Command
Parameter
Description
Restriction
Register
Availability
Default
SWRESET (Software Reset)
DNC NWR NRD D7 D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
0
0
0
0
0
1
01
NO PARAMETER
When the Software Reset command is written, it causes a software reset. It
resets the commands and parameters to their S/W Reset default values. (See
default tables in each command description.) Note: The Frame Memory
contents are unaffected by this command
It will be necessary to wait 5msec before sending new command following
software reset.
The display module loads all display supplier’s factory default values to the
registers during this 5msec. If Software Reset is applied during Sleep Out mode,
it will be necessary to wait 120msec before sending Sleep out command.
Software Reset Command cannot be sent during Sleep Out sequence.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
N/A
N/A
N/A
Legend
Red and Blue
Parameter
Flow Chart
Display
Action
Mode
Sequential
transfer
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.122February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.3 Read Display Identification Information (04h)
04 H
Command
1st parameter
nd
2 parameter
rd
3 parameter
Description
RDDIDIF (Read Display Identification Information)
DNC NWR NRD
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
0
0
0
1
0
0
04
1
1
↑
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10
1
1
↑
ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20
1
1
↑
ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30
This read byte returns 24-bit display identification information.
The 1st Parameter is dummy read. The 2nd Parameter identifies the LCD module’s
manufacturer. It is specified by Nokia and for xx is defined as xxHEX.
The 3rd Parameter has 2 purposes. Bit7 (MSB) defines the type of panel. 0=Driver
(STN B/W), 1=Module (Color). Bits 6...0 are used to track the LCD module/driver
version. It is defined by display supplier (with Nokia’s agreement) and it changes
each time a revision is made to the display, material or construction specifications.
See Table:
ID Byte Value V[7:0]
Version
Changes
80h
81h
82h
83h
84h
85h
The 4th parameter identifies the LCD module/driver. It is specified by Nokia and for
this LCD project module is defined as xxHEX.
Restriction
Register
Availability
Default
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Status
Power On Sequence
S/W Reset
Availability
Yes
Yes
Yes
Yes
Default Value
See Description
See Description
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.123February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.4 Read Display Status (09h)
09 H
Command
1st parameter
nd
2 parameter
rd
3 parameter
th
4 parameter
th
5 parameter
Description
RDDST (Read Display Status)
DNC NWR NRD
D7
D6
D5
D4
D3
D2
D1
D0
0
↑
1
0
0
0
0
1
0
0
1
1
1
↑
1
1
↑
D31
D30
D29
D28
D27
D26
D25
D24
1
1
↑
D23
D22
D21
D20
D19
D18
D17
D16
1
1
↑
D15
D14
D13
D12
D11
D10
D9
D8
1
1
↑
D7
D6
D5
D4
D3
D2
D1
D0
This command indicates the current status of the display as described in the table
below:
Bit
Description
Comment
D31
Booster Voltage Status
D30
Page Address Order
D29
Column Address Order
D28
Page/Column Order
D27
Vertical Order
D26
RGB/BGR Order
D25
Horizontal Order
D24
Switching between Segment outputs and RAM
Set to ‘0’
D23
Switching between Common outputs and RAM
Set to ‘0’
D22
Set to ‘1’
D21
Interface Color Pixel Format Definition
Set to ‘1’
D20
Set to ‘0’
D19
Idle Mode On/Off
D18
Partial Mode On/Off
D17
Sleep In/Out
D16
Display Normal Mode On/Off
D15
Vertical Scrolling Status
D14
Horizontal Scrolling Status
Set to ‘0’
D13
Inversion Status
D12
All Pixels On
Set to ‘0’
D11
All Pixels Off
Set to ‘0’
D10
Display On/Off
D9
Tearing Effect Line On/Off
D8
D7
Gamma Curve Selection
D6
D5
Tearing Effect Output Line Mode
D4
For Future Use
Set to ‘0’
D3
For Future Use
Set to ‘0’
D2
For Future Use
Set to ‘0’
D1
For Future Use
Set to ‘0’
D0
For Future Use
Set to ‘0’
HEX
09
-
Bit Values are explained overleaf.

Bit D31 – Booster Voltage Status
‘0’= Booster Off.
‘1’= Booster On.
Bit D30 – Page Address Order

‘0’= Top to Bottom (When MADCTL B7=’0’).
‘1’= Bottom to Top (When MADCTL B7=’1’).
Bit D29 – Column Address Order
‘0’= Left to Right (When MADCTL B6=’0’).
‘1’= Right to Left (When MADCTL B6=’1’).
Bit D28 - Page/Column Order

‘0’= Normal Mode (When MADCTL B5=’0’).
Himax Confidential
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HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
 it D27 – Line Address Order
B
‘0’= LCD Refresh Top to Bottom (When MADCTL B4=’0’).
‘1’= LCD Refresh Bottom to Top (When MADCTL B4=’1’).
Bit D26 – RGB/BGR Order
‘0’= RGB (When MADCTL B3=’0’).
‘1’= BGR (When MADCTL B3=’1’).
Note: For Bits D27, D26, also refer to Section 9.3.23.
Bit D25 – Display Data Latch Data Order (if this bit is not available, so it is set to ‘0’)
‘0’= LCD Refresh Left to Right (When MADCTL B2=’0’).
‘1’= LCD Refresh Right to Left (When MADCTL B2=’1’).
Bit D24 – Switching Between Segment Outputs and RAM

This bit is not applicable for this project, so it is set to ‘0’
Bit D23 – Switching Between Common Outputs and RAM

‘This bit is not applicable for this project, so it is set to ‘0’
Bits D22, D21, D20 – Interface Color Pixel Format Definition
Bit D19 – Idle Mode On/Off
‘0’= Idle Mode Off.
‘1’= Idle Mode On.
Bit D18 – Partial Mode On/Off

‘0’= Partial Mode Off.
‘1’= Partial Mode On.
Bit D17 – Sleep In/Out
‘0’= Sleep In Mode.
‘1’= Sleep Out Mode.
Bit D16 – Display Normal Mode On/Off

‘0’= Display Normal Mode Off.
‘1’= Display Normal Mode On.
Bit D15 – Vertical Scrolling On/Off

‘0’= Vertical Scrolling is Off.
‘1’= Vertical Scrolling is On.
Bit D14 – Horizontal Scrolling Status

This bit is not applicable for this project, so it is set to ‘0’
Bit D13 – Inversion On/Off
‘0’= Inversion is Off.
‘1’= Inversion is On.
Bit D12 – All Pixels On
This bit is not applicable for this project, so it is set to ‘0’
Bit D11 – All Pixels Off
This bit is not applicable for this project, so it is set to ‘0’
Bit D10 – Display On/Off

‘0’= Display is Off.
‘1’= Display is On.
Bit D9 – Tearing Effect Line On/Off
‘0’=Tearing Effect Line Off.
‘1’= Tearing Effect On.
Bits D8, D7, D6 – Gamma Curve Selection
Gamma Curve Selected
Gamma Curve 1
Gamma Curve 2
Gamma Curve 3
Gamma Curve 4
Not Defined
Not Defined
Not Defined
Not Defined
B8
B7
B6
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Gamma Set (26h)
Parameter
GC0
GC1
GC2
GC3
Not Defined
Not Defined
Not Defined
Not Defined
 it D5 – Tearing Effect Line Output Mode.
B
‘0’= Mode 1, V-Blanking only.
‘1’= Mode 2, both H-Blanking and V-Blanking.
Restriction
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.125February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Register
Availability
Default
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Status
Power On Sequence
S/W Reset
Availability
Yes
Yes
Yes
Yes
Default Value
See Description
See Description
Flow Chart
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-P.126February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.5 Read Display Power Mode (0Ah)
0A H
Command
1st parameter
nd
2 parameter
Description
RDDPM (Read Display Power Mode)
DNC
NWR
NRD
D7
D6
D5
D4
D3
D2
D1
0
↑
1
0
0
0
0
1
0
1
1
1
↑
1
1
↑
D7
D6
D5
D4
D3
D2
D1
This command indicates the current status of the display as described in the table
below:
Bit
Description
Comment
D7
Booster Voltage Status
D6
Idle Mode On/Off
D5
Partial Mode On/Off
D4
Sleep In/Out
D3
Display Normal Mode On/Off
D2
Display On/Off
D1
Not Defined
Set to ‘0’
D0
Not Defined
Set to ‘0’
Bit D7 – Booster Voltage Status
‘0’= Booster Off or has a fault.
‘1’= Booster On and working OK (Meets Nokia’s optical requirements).
Bit D6 - Idle Mode On/Off

‘0’= Idle Mode Off.
‘1’= Idle Mode On.
Bit D5 – Partial Mode On/Off

‘0’= Partial Mode Off.
‘1’= Partial Mode On.
Bit D4 – Sleep In/Out

‘0’= Sleep In Mode.
‘1’= Sleep Out Mode.
Bit D3 – Display Normal Mode On/Off

‘0’= Display Normal Mode Off.
‘1’= Display Normal Mode On.
Bit D2 – Display On/Off

‘0’= Display is Off.
‘1’= Display is On.
D0
0
D0
HEX
0A
-
Restrictions
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
08HEX
08HEX
08HEX
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-P.127February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Flow Chart
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.128February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.6 Read Display MADCTL (0Bh)
0B H
Command
1st parameter
2nd parameter
Description
RDDMADCTL (Read Display MADCTL)
DNC
0
1
1
NWR
↑
1
1
NRD
1
↑
↑
D7
0
xx
D7
D6
0
xx
D6
D5
0
xx
D5
D4
0
xx
D4
D3
1
xx
D3
D2
0
xx
D2
D1
1
xx
0
D0
1
xx
0
HEX
0B
xx
xx
This command indicates the current status of the display as described in the table
below:
Bit
Description
Comment
D7
Page Address Order
D6
Column Address Order
D5
Page/Column Order
D4
Line Address Order
D3
RGB/BGR Order
D2
Display Data Latch Order
D1
Switching between Segment outputs and RAM
Set to ‘0’
D0
Switching between Common outputs and RAM
Set to ‘0’
Bit D7 – Page Address Order
‘0’= Top to Bottom (When MADCTL B7=’0’).
‘1’= Bottom to Top (When MADCTL B7=’1’).
Bit D6 – Column Address Order
‘0’= Left to Right (When MADCTL B6=’0’).
‘1’= Right to Left (When MADCTL B6=’1’).
Bit D5 - Page/Column Order
‘0’= Normal Mode (When MADCTL B5=’0’).
‘1’= Reverse Mode (When MADCTL B5=’1’).
Note: For Bits D7 to D5, also refer to Section 8.2.3 MCU to memory write/read direction.
Bit D4 – Line Address Order

‘0’= LCD Refresh Top to Bottom (When MADCTL B4=’0’).
‘1’= LCD Refresh Bottom to Top (When MADCTL B4=’1’).
Bit D3 – RGB/BGR Order
‘0’= RGB (When MADCTL B3=’0’).
‘1’= BGR (When MADCTL B3=’1’).
Note: For Bits D4 and D3 also refer to 9.2.29 Memory Access Control (36h).
Bit D2 – Display Data Latch Data Order
‘0’= LCD Refresh Left to Right (When MADCTL B2=’0’).
‘1’= LCD Refresh Right to Left (When MADCTL B2=’1’).
Bit D1 – Switching Between Segment Outputs and RAM
This bit is not applicable for this project, so it is set to ‘0’
Bit D0 – Switching Between Common Outputs and RAM

Restrictions
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
00HEX
No Change
00HEX
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in whole or in part without prior written permission of Himax.
-P.129February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.130February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.7 Read Display Pixel Format (0Ch)
0C H
Command
1st parameter
2nd parameter
Description
RDDCOLMOD (Read Display COLMOD)
DNC
0
1
1
NWR
↑
1
1
NRD
1
↑
↑
D7
0
D7
D6
0
D6
D5
0
D5
D4
0
D4
D3
1
D3
D2
1
D2
D1
0
D1
D0
0
D0
HEX
0C
-
This command indicates the current status of the display as described in the table below:
Bit
Description
Comment
D7
Set to ‘0’
D6
Set to ‘0’
RGB Interface Colour Format
D5
Set to ‘0’
D4
Set to ‘0’
D3
D2
Control Interface Colour Format
D1
D0
Bit D7 – RGB Interface Colour Format Selection
This bit is not applicable for this project, so it is set to ‘0’.
Bits D6, D5, D4 – RGB Interface Colour Pixel Format Definition
These bits are not applicable for this project, so they are set to ‘0’s.
Bit D3 – Control Interface Colour Format Selection
This bit is not applicable for this project, so it is set to ‘0’.
Bit D2, D1, D0 – Control Interface Colour Pixel Format Definition.
These bits are not applicable for this project, so they are set to ‘110’.
Restrictions
Register
Availability
Default
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Status
Power On Sequence
S/W Reset
Availability
Yes
Yes
Yes
Yes
Default Value
16 bit/pixel
No Change
Flow Chart
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-P.131February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.8 Read Display Image Mode (0Dh)
0D H
Command
1st parameter
2nd parameter
Description
RDDIM (Read Display Image Mode)
DNC
0
1
1
NWR
↑
1
1
NRD
1
↑
↑
D7
0
D7
D6
0
D6
D5
0
D5
D4
0
D4
D3
1
D3
D2
1
D2
D1
0
D1
D0
1
D0
HEX
0D
-
This command indicates the current status of the display as described in the table
below:
Bit D7 – Vertical Scrolling On/Off

‘0’= Vertical Scrolling is Off.
‘1’= Vertical Scrolling is On.
Bit D6 – Horizontal Scrolling Status

This bit is not applicable for this project, so it is set to ‘0’
Bit D5 – Inversion On/Off

‘0’= Inversion is Off.
‘1’= Inversion is On.
Bit D4 – All Pixels On

This bit is not applicable for this project, so it is set to ‘0’
Bit D3 – All Pixels Off

This bit is not applicable for this project, so it is set to ‘0’
Bits D2, D1, D0 – Gamma Curve Selection

Gamma Set
Gamma Curve Selected D2
D1
D0
(26h) Parameter
Gamma Curve 1
0
0
0
GC0
Gamma Curve 2
0
0
1
GC1
Gamma Curve 3
0
1
0
GC2
Gamma Curve 4
0
1
1
GC3
Not Defined
1
0
0
Not Defined
Not Defined
1
0
1
Not Defined
Not Defined
1
1
0
Not Defined
Restrictions
Register
Availability
Default
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Status
Power On Sequence
S/W Reset
Availability
Yes
Yes
Yes
Yes
Default Value
00HEX
00HEX
Flow Chart
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-P.132February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.9 Read Display Signal Mode (0Eh)
0E H
Command
1st parameter
2nd parameter
Description
RDDSM (Read Display Signal Mode)
DNC
0
1
1
NWR
↑
1
1
NRD
1
↑
↑
D7
0
D7
D6
0
D6
D5
0
D5
D4
0
D4
D3
1
D3
D2
1
D2
D1
1
D1
D0
0
D0
HEX
0E
-
This command indicates the current status of the display as described in the table
below:
Bit D7 – Tearing Effect Line On/Off

‘0’= Tearing Effect Line Off.
‘1’= Tearing Effect On.
Bit D6 – Tearing Effect Line Output Mode, see section 8.3 for mode definitions.

‘0’= Mode 1.
‘1’= Mode 2.
Bit D5 – Horizontal Sync. (RGB I/F) On/Off

This bit is not applicable for this project, so it is set to ‘0’
Bit D4 – Vertical Sync. (RGB I/F) On/Off

This bit is not applicable for this project, so it is set to ‘0’
Bit D3 – Pixel Clock (PCLK, RGB I/F) On/Off

This bit is not applicable for this project, so it is set to ‘0’
Bit D2 – Data Enable (DE, RGB I/F)) On/Off

This bit is not applicable for this project, so it is set to ‘0’
D1 are D0 - are for future use and are set to ‘0’.

Restrictions
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Default
Status
Power On Sequence
S/W Reset
Availability
Yes
Yes
Yes
Yes
Default Value
00HEX
00HEX
Flow Chart
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in whole or in part without prior written permission of Himax.
-P.133February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.10 Read Display Self-Diagnostic Result (0Fh)
0F H
Command
1st parameter
2nd parameter
Description
RDDSDR (Read Display Self-Diagnostic Result)
DNC
0
1
1
NWR
1
↑
↑
NRD
↑
1
1
D7
0
D7
D6
0
D6
D5
0
D5
D4
0
D4
D3
1
D3
D2
1
D2
D1
1
D1
D0
1
D0
HEX
0F
-
This command indicates the status of the display self-diagnostic results after Sleep Out -command
as described in the table below:
 Bit D7 – Register Loading Detection See section 5.17.1
 Bit D6 – Functionality Detection See section 5.17.2.
 Bit D5 – Chip Attachment Detection Set bit D5 to ‘0’, if this function is not implemented.
 Bit D4 – Display Glass Break Detection. Set bit D4 to ‘0’, if this function is not implemented.
 Bits D3, D2, D1 and D0 are for future use and are set to ‘0’.
Restrictions
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
00HEX
00HEX
00HEX
Flow Chart
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.134February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.11 Sleep In (10h)
10 H
Command
Parameter
SLPIN (Sleep In)
DNC
0
NWR
↑
NRD
1
D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
0
D0
0
HEX
10
NO PARAMETER
This command causes the LCD module to enter the minimum power consumption
mode. In this mode the DC/DC converter is stopped, Internal oscillator is stopped,
and panel scanning is stopped.
Description
Restriction
Register
Availability
Default
MCU interface and memory are still working and the memory keeps its contents.
See also section 5.13.
This command has no effect when module is already in sleep in mode. Sleep In
Mode can only be left by the Sleep Out Command (11h).
It will be necessary to wait 5msec before sending next command, this is to allow time
for the supply voltages and clock circuits to stabilize.
It will be necessary to wait 120msec after sending Sleep Out command (when in
Sleep In Mode) before Sleep In command can be sent.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default Value
Power On Sequence
Sleep in mode
S/W Reset
Sleep in mode
H/W Reset
Sleep in mode
It takes 120msec to get into Sleep In mode after SLPIN command issued.
Flow Chart
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in whole or in part without prior written permission of Himax.
-P.135February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.12 Sleep Out (11h)
11 H
Command
Parameter
SLPOUT (Sleep Out)
DNC
0
NWR
↑
NRD
1
D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
0
D0
1
HEX
11
NO PARAMETER
This command turns off sleep mode.
In this mode the DC/DC converter is enabled, Internal oscillator is started, and panel
scanning is started.
Description
Restriction
Register
Availability
Default
Flow Chart
See also section 5.13
This command has no effect when module is already in sleep out mode. Sleep Out
Mode can only be left by the Sleep In Command (10h).
It will be necessary to wait 5msec before sending next command, this is to allow time
for the supply voltages and clock circuits to stabilize.
The display module loads all display supplier’s factory default values to the registers
during this 5msec and there cannot be any abnormal visual effect on the display
image if factory default and register values are same when this load is done and
when the display module is already Sleep Out –mode.
The display module is doing self-diagnostic functions during this 5msec. See also
section 8.10.
It will be necessary to wait 120msec after sending Sleep In command (when in Sleep
Out mode) before Sleep Out command can be sent.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Status
Power On Sequence
S/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Sleep In Mode
Sleep In Mode
It takes 120msec to become Sleep Out mode after SLPOUT command issued.
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.136February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.137February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.13 Partial Mode On (12h)
12 H
Command
Parameter
Description
Restrictions
Register
Availability
Default
Flow Chart
PTLON (Partial Mode On)
DNC
0
NWR
↑
NRD
1
D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
1
D0
0
HEX
12
NO PARAMETER
This command turns on partial mode The partial mode window is described by the
Partial Area command (30H). To leave Partial mode, the Normal Display Mode On
command (13H) should be written.
See also section 8.6.2.
This command has no effect when Partial mode is active.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Status
Power On Sequence
S/W Reset
Default Value
Normal Mode On
Normal Mode On
See Partial Area (30h)
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in whole or in part without prior written permission of Himax.
-P.138February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.14 Normal Display Mode On (13h)
13 H
NORON (Normal Display Mode On)
Command
DNC
0
Parameter
Description
Restriction
Register
Availability
Default
Flow Chart
NWR
↑
NRD
1
D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
1
D0
1
HEX
13
NO PARAMETER
This command returns the display to normal mode. Normal display mode on means
Partial mode off, Scroll mode Off.
This command has no effect when Normal Display mode is active.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Status
Power On Sequence
S/W Reset
Default Value
Normal Mode On
Normal Mode On
See Partial Area and Vertical Scrolling Definition Descriptions for details of when to
use this command.
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.139February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.15 Display Inversion Off (20h)
20 H
Command
Parameter
INVOFF (Display Inversion Off)
DNC
0
NRD
1
NWR
↑
D7
0
D6
0
D5
D4
D3
1
0
0
NO PARAMETER
D2
0
D1
0
D0
0
HEX
20
This command is used to recover from display inversion mode.
This command makes no change of contents of frame memory.
This command does not change any other status.
Description
Restriction
Register
Availability
Default
This command has no effect when module is already in inversion off mode.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
Status
Default Value
Power On Sequence
Display Inversion off
S/W Reset
Display Inversion off
H/W Reset
Display Inversion off
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.140February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.16 Display Inversion On (21h)
21 H
Command
Parameter
INVON (Display Inversion On)
DNC
0
NRD
1
NWR
↑
D7
0
D6
0
D5
D4
D3
1
0
0
NO PARAMETER
D2
0
D1
0
D0
1
HEX
21
This command is used to enter into display inversion mode.
This command makes no change of contents of frame memory. Every bit is inverted
from the frame memory to the display.
This command does not change any other status.
Description
Restriction
Register
Availability
Default
Memory
(Example)
Display
This command has no effect when module is already in inversion on mode.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Display Inversion off
Display Inversion off
Display Inversion off
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.141February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.17 Gamma Set (26h)
26 H
Command
Parameter
Description
Restriction
Register
Availability
Default
GAMSET (Gamma Set)
DNC
0
1
NWR
↑
↑
NRD
1
1
D7
0
GC7
D6
0
GC6
D5
1
GC5
D4
0
GC4
D3
0
GC3
D2
1
GC2
D1
1
GC1
D0
0
GC0
HEX
26
-
This command is used to select the desired Gamma curve for the current display. A
maximum of 4 fixed gamma curves can be selected. The curve is selected by setting
the appropriate bit in the parameter as described in the Table:
GC[7..0]
Parameter Curve Selected
01h
GC0
Gamma Curve 1
02h
GC1
Gamma Curve 2
04h
GC2
Gamma Curve 3
08h
GC3
Gamma Curve 4
Values of GC[7..0] not shown in table above are invalid and will not change the
current selected Gamma curve until valid value is received.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
Status
Default Value
Power On Sequence
01h
S/W Reset
01h
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.142February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.18 Display Off(28h)
Command
Parameter
DNC NWR NRD
0
↑
1
NO PARAMETER
D7
0
D6
0
D5
1
D4
0
D3
1
D2
0
D1
0
D0
0
HEX
28
This command is used to enter into DISPLAY OFF mode. In this mode, the output
from Frame Memory is disabled and blank page inserted. This command makes
no change of contents of frame memory. This command does not change any
other status. There will be no abnormal visible effect on the display.
Description
Restriction
This command has no effect when module is already in display off mode.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Display off
Display off
Display off
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.143February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.19 Display On (29h)
29 H
Command
Parameter
DISPON (Display On)
DNC
0
NWR
↑
NRD
1
D7
0
D6
0
D5
D4
D3
1
0
1
NO PARAMETER
D2
0
D1
0
D0
1
HEX
29
This command is used to recover from DISPLAY OFF mode. Output from the Frame
Memory is enabled. This command makes no change of contents of frame memory.
This command does not change any other status.
Description
Restriction
This command has no effect when module is already in display on mode.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Display off
Display off
Display off
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.144February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.20 Column Address Set (2Ah)
2A H
Command
parameter 1st
parameter
2nd
parameter3rd
parameter4th
CASET (Column Address Set)
DNC
0
1
NWR
↑
↑
NRD
1
1
D7
0
SC15
D6
0
SC14
D5
1
SC13
D4
0
SC12
1
↑
1
SC7
SC6
SC5
SC4
1
1
↑
↑
1
1
EC15
EC7
EC14
EC6
EC13
EC5
EC12
EC4
D3
1
SC11
D2
0
SC10
D1
1
SC9
D0
0
SC8
HEX
2A
-
SC3
SC2
SC1
SC0
-
EC11
EC3
EC10
EC2
EC9
EC1
EC8
EC0
-
This command is used to define area of frame memory where MCU can access. This
command makes no change on the other driver status. The values of SC[15:0] and
EC[15:0] are referred when RAMWR command comes. Each value represents one
column line in the Frame Memory.
(Example)
(Example)
Description
Restriction
Register
Availability
Default
SC[15:0]
EC[15:0]
SC[15:0] always must be equal to or less than EC[15:0]
Note 1: When SC[15:0] or EC[15:0] is greater than 83h (when MADCTL’s B5=0) or A1h
(when MADCTL’s B5=1), data of out of range will be ignored
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
Status
Default Value
Power On Sequence
SC[15:0]=0000
EC[15:0]=0083
S/W Reset
When MADCTL’s B5=0:
When MADCTL’s B5=0:
SC[15:0]=0000
EC[15:0]=0083
When MADCTL’s B5=1:
When MADCTL’s B5=1:
SC[15:0]=0000
EC[15:0]=00A1
H/W Reset
SC[15:0]=0000
EC[15:0]=0083
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.145February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.146February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.21 Page Address Set (2Bh)
2B H
PASET (Page Address Set)
Command
parameter 1st
parameter 2nd
parameter3rd
parameter4th
DNC
0
1
1
1
1
NWR
↑
↑
↑
↑
↑
NRD
1
1
1
1
1
D7
0
SP15
SP7
EP15
EP7
D6
0
SP14
SP6
EP14
EP6
D5
1
SP13
SP5
EP13
EP5
D4
0
SP12
SP4
EP12
EP4
D3
1
SP11
SP3
EP11
EP3
D2
0
SP10
SP2
EP10
EP2
D1
1
SP9
SP1
EP9
EP1
D0
1
SP8
SP0
EP8
EP0
HEX
2B
00..
Note 1
00.. Note 1
This command is used to define area of frame memory where MCU can access. This
command makes no change on the other driver status. The values of SP[15:0] and EP[15:0]
are referred when RAMWR command comes. Each value represents one Page line in the
Frame Memory.
Description
Restriction
Register
Availability
Default
SP[15:0] always must be equal to or less than EP[15:0]
Note 1: When SP[15:0] or EP[15:0] is greater than A1h (When MADCTL’s B5=0) or 83h (When
MADCTL’s B5=1), data of out of range will be ignored.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
SP[15:0]=0000
EP[15:0]=00A1
When MADCTL’s B5=0:
When MADCTL’s B5=0:
SP[15:0]=0000
EP[15:0]=00A1
When MADCTL’s B5=1:
When MADCTL’s B5=1:
SP[15:0]=0000
EP[15:0]=0083
SP[15:0]=0000
EP[15:0]=00A1
IF Needed
Flow Chart
IF Needed
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.147February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.22 Memory Write (2Ch)
2C H
RAMWR (Memory Write)
Command
1st parameter
DNC
0
1
NWR
↑
↑
NRD
1
1
D7
0
D15
D6
0
D14
D5
1
D13
D4
0
D12
D3
1
D11
D2
1
D10
D1
0
D9
D0
0
D8
HEX
2C
00..FF
This command is used to transfer data from MCU to frame memory. This command
makes no change to the other driver status. When this command is accepted, the
column register and the page register are reset to the Start Column/Start Page
positions. The Start Column/Start Page positions are different in accordance with
MADCTL setting. (See follow table) Then D[7:0] is stored in frame memory and the
column register and the page register incremented as follow table.
Description
Restriction
Register
Availability
Default
Condition
When RAMWR/RAMRD command is
accepted
Complete Pixel Read/Write action
The Column counter value is larger
than “End column”
The Page counter value is larger than
“End page”
Column Counter
Return to “Start
Column”
Increment by 1
Return to “Start
Column”
Return to “Start
Column”
Page Counter
Return to
“Start Page”
No change
Increment by 1
Return to
“Start Page”
In all color modes, there is no restriction on length of parameters.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Status
Power On Sequence
S/W Reset
Default Value
Contents of memory is set randomly
Contents of memory is not cleared
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.148February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.23 Colour Set (2Dh)
2D H
Command
1st parameter
:
16th parameter
17th parameter
33rd parameter
..
96th parameter
97th parameter
128th parameter
Description
RGBSET (Color Set)
DNC
DNC
0
1
1
1
1
1
1
1
1
NRD
NRD
1
1
1
1
1
1
1
1
1
NWR
NWR
↑
↑
↑
↑
↑
↑
↑
↑
↑
D7
D7
0
X
X
X
X
X
X
X
X
D6
D6
0
X
X
X
X
X
X
X
X
D5
D5
1
R005
Rnn5
R315
G005
Gnn5
G635
B005
B315
D4
D4
0
R004
Rnn4
R314
G004
Gnn4
G634
B004
B314
D3
D3
1
R003
Rnn3
R313
G003
Gnn3
G633
B003
B313
D2
D2
1
R002
Rnn2
R312
G002
Gnn2
G632
B002
B312
D1
D1
0
R001
Rnn1
R311
G001
Gnn1
G631
B001
B311
D0
D0
1
R000
Rnn0
R310
G000
Gnn0
G630
B000
B310
HEX
HEX
2D
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
This command is used to define the LUT for 12bit-to-18bit/16bit-to-18bit color depth
conversions. (See also section 8.9) 128 bytes must be written to the LUT regardless
of the color mode. Only the values in Section 8.9 are referred. This command has no
effect on other commands/parameters and Contents of frame memory. Visible change
takes effect next time the Frame Memory is written to.
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Default Value
Random values
Contents of the look-up table protected
Random values
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.149February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.24 Memory Read (2Eh)
2E H
RAMRD (Memory Read)
Command
1st parameter
2nd parameter
DNC
0
1
1
NWR
↑
1
1
NRD
1
↑
↑
D7
0
D15
D6
0
D14
D5
1
D13
D4
0
D12
D3
1
D11
D2
1
D10
D1
1
D9
D0
0
D8
HEX
2E
-
This command is used to transfer data from frame memory to MCU. See section 9.1
This command makes no change to the other driver status. When this command is
accepted, the column register and the page register are reset to the Start Column/Start
Page positions. The Start Column/Start Page positions are different in accordance
with MADCTL setting. (See follow table) Then D[7:0] is read back from the frame
memory and the column register and the page register incremented as follow table.
Description
Condition
When RAMWR/RAMRD command is
accepted
Complete Pixel Read/Write action
The Column counter value is larger
than “End column”
The Page counter value is larger than
“End page”
Column Counter
Return to “Start
Column”
Increment by 1
Return to “Start
Column”
Return to “Start
Column”
Page Counter
Return to
“Start Page”
No change
Increment by 1
Return to
“Start Page”
Frame Read can be stopped by sending any other command.
In all color modes, the Frame Read is always like figure below. There is no restriction
on length of parameters. Note – Memory Read is only possible via the Parallel
Interface.
NCS
NRESET
DNC_SCL
NWR_DNC
NRD_E
Restriction
D7
0
X
R1
Bit5
G1
Bit5
B1
Bit5
R2
Bit5
D6
0
X
R1
Bit4
G1
Bit4
B1
Bit4
R2
Bit4
D5
1
X
R1
Bit3
G1
Bit3
B1
Bit3
R2
Bit3
D4
1
X
R1
Bit2
G1
Bit2
B1
Bit2
R2
Bit2
1
X
R1
Bit1
G1
Bit1
B1
Bit1
R2
Bit1
D2
1
X
R1
Bit0
G1
Bit0
B1
Bit0
R2
Bit0
D1
0
X
X
X
X
X
D0
0
X
X
X
X
X
D3
Register
Availability
Default
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Status
Power On Sequence
S/W Reset
Availability
Yes
Yes
Yes
Yes
Default Value
Contents of memory is set randomly
Contents of memory is not cleared
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.150February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.151February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.25 Partial Area (30h)
30 H
PLTAR (Partial Area)
Command
1st Parameter
2nd Parameter
3rd Parameter
4th Parameter
DNC
0
1
1
1
1
NWR
↑
↑
↑
↑
↑
NRD
1
1
1
1
1
D7
0
PSL15
PSL7
PEL15
PEL7
D6
0
PSL14
PSL6
PEL14
PEL6
D5
1
PSL13
PSL5
PEL13
PEL5
D4
1
PSL12
PSL4
PEL12
PEL4
D3
0
PSL11
PSL3
PEL11
PEL3
D2
0
PSL10
PSL2
PEL10
PEL2
D1
0
PSL9
PSL1
PEL9
PEL1
D0
0
PSL8
PSL0
PEL8
PEL0
HEX
30
00 … A1
00 ...A1
This command defines the partial mode’s display area. There are 4 parameters associated with this
command, the first defines the Start Row (SR) and the second the End Row (ER), as illustrated in
the figures below. SR and ER refer to the Frame Memory Line Pointer.
If End Row>Start Row when MADCTL B4=0:Start Row
PSL [15:0]
Partial Display Area
PEL[15:0]
End Row
If End Row>Start Row when MADCTL B4=1:End Row
PEL [15:0]
Description
Partial Display Area
PSL [15:0]
Start Row
If End Row<Start Row when MADCTL B4=0:End Row
PEL [15:0]
Partial Display Area
PSL [15:0]
Start Row
Restriction
Register
Availability
Default
Flow Chart
If End Row = Start Row then the Partial Area will be one row deep.
SR[15...0] and ER[15...0] cannot be greater than A1h.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Status
Power On Sequence
S/W Reset
Default Value
SR[15..0]=00
SR[15..0]=00
ER[15..0]=A1
ER[15..0]=A1
1. To Enter Partial Mode:-
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.152February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
2. To Leave Partial Mode
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.153February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.26 Vertical Scrolling Definition (33h)
33 H
Command
1st
parameter
2nd
parameter
3rd
parameter
4th
parameter
5th
parameter
6th
parameter
VSCRDEF (Vertical Scrolling Definition)
DNC
0
NRD
1
NWR
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
D7
0
TFA
15
TFA
7
VSA
15
VSA
7
BFA
15
BFA
7
D6
0
TFA
14
TFA
6
VSA
14
VSA
6
BFA
14
BFA
6
D5
1
TFA
13
TFA
5
VSA
13
VSA
5
BFA
13
BFA
5
D4
1
TFA
12
TFA
4
VSA
12
VSA
4
BFA
12
BFA
4
D3
0
TFA
11
TFA
3
VSA
11
VSA
3
BFA
11
BFA
3
D2
0
TFA
10
TFA
2
VSA
10
VSA
2
BFA
10
BFA
2
D1
1
TFA
9
TFA
1
VSA
9
VSA
1
BFA
9
BFA
1
D0
1
TFA
8
TFA
0
VSA
8
VSA
0
BFA
8
BFA
0
HEX
33
00..A2
00..A2
00..A2
This command defines the Vertical Scrolling Area of the display.
When MADCTL B4=0
The 1st & 2nd parameter TFA[15..0] describes the Top Fixed Area (in No. of lines from
Top of the Frame Memory and Display).
The 3rd & 4th parameter VSA[15..0] describes the height of the Vertical Scrolling Area
(in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start
Address). The first line read from Frame Memory appears immediately after the bottom
most line of the Top Fixed Area.
The 5th & 6th parameter BFA[15..0] describes the Bottom Fixed Area (in No. of lines
from Bottom of the Frame Memory and Display).
TFA, VSA and BFA refer to the Frame Memory Line Pointer.
Top Fixed Area
(0 ,0 )
TFA [ 15:0 ]
First line read from
frame memory
Scroll Area
BFA [15:0]
Bottom Fixed Area
Description
When MADCTL B4=1
The 1st & 2nd parameter TFA[15..0] describes the Top Fixed Area (in No. of lines from
Bottom of the Frame Memory and Display).
The 3rd & 4th parameter VSA[15..0] describes the height of the Vertical Scrolling Area
(in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start
Address). The first line read from Frame Memory appears immediately after the top
most line of the Top Fixed Area.
The 5th & 6th parameter BFA[15..0] describes the Bottom Fixed Area (in No. of lines
from Top of the Frame Memory and Display).
Bottom Fixed Area
(0 ,0 )
BFA [15:0]
Scroll Area
TFA [ 15:0 ]
Top Fixed Area
First line read from
frame memory
See also Section 8.2.2.2 for details of the Memory to Display mappings.
Restriction
The condition is (TFA+VSA+BFA)=162, otherwise Scrolling mode is undefined.
In Vertical Scroll Mode, MADCTL B5 should be set to ‘0’– this only affects the Frame
Memory Write.
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.154February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
TFA[15..0]=0000
TFA[15..0]=0000
TFA[15..0]=0000
Availability
Yes
Yes
Yes
Yes
Yes
VSA[15..0]=00A2
VSA[15..0]=00A2
VSA[15..0]=00A2
BFA[15..0]=0000
BFA[15..0]=0000
BFA[15..0]=0000
Flow
Charts
Note
The Frame Memory Window size must be defined correctly otherwise undesirable image
will be displayed.
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.155February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
2. Continuous Scroll:
3. To Leave Vertical Scroll Mode:
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.156February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.27 Tearing Effect Line Off (34h)
34 H
TEOFF (Tearing Effect Line OFF)
Command
DNC
0
Description
Restriction
Register
Availability
Default
NWR
↑
NRD
1
D7
0
D6
0
D5
1
D4
1
D3
0
D2
1
D1
0
D0
0
HEX
34
This command is used to turn OFF (Active Low) the Tearing Effect output signal from
the TE signal line.
This command has no effect when Tearing Effect output is already OFF.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Status
Power On Sequence
S/W Reset
Default Value
Off
Off
Flow Chart
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.157February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.28 Tearing Effect Line On (35h)
35 H
Command
Parameter
TEON (Tearing Effect Line ON)
DNC
0
1
NWR
↑
↑
NRD
1
1
D7
0
-
D6
0
-
D5
1
-
D4
1
-
D3
0
-
D2
1
-
D1
0
-
D0
1
M
HEX
35
-
This command is used to turn ON the Tearing Effect output signal from the TE signal
line. This output is not affected by changing MADCTL bit B4. The Tearing Effect Line
On has one parameter which describes the mode of the Tearing Effect Output Line.
(X=Don’t Care).
When M=0:
The Tearing Effect Output line consists of V-Blanking information only:
Description
When M=1:
The Tearing Effect Output Line consists of both V-Blanking and H-Blanking
information:
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin
will be active Low.
Restriction
Register
Availability
Default
This command has no effect when Tearing Effect output is already ON.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Status
Power On Sequence
S/W Reset
Default Value
Off
Off
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.158February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.29 Memory Access Control (36h)
36 H
MADCTL (Memory Access Control)
DNC
0
1
Command
1st parameter
NWR
↑
↑
NRD
1
1
D7
0
MY
D6
0
MX
D5
1
MV
D4
1
ML
D3
0
BGR
D2
1
SS
D1
1
-
D0
0
-
HEX
36
XX
This command defines read/write scanning direction of frame memory.
This command makes no change on the other driver status.
Bit Assignment
BIT
MY
MX
MV
ML
NAME
PAGE ADDRESS ORDER
COLUMN ADDRESS ORDER
PAGE/COLUMN SELECTION
Vertical ORDER
BGR
RGB-BGR ORDER
SS
Horizontal ORDER
DESCRIPTION
These 3 bits controls MCU to memory write/read direction.
LCD vertical refresh direction control
Color selector switch control
(0=RGB color filter panel, 1=BGR color filter panel)
LCD horizontal refresh direction control
Description
Sent First (1)
Sent 2nd
Sent 3rd
Sent last (128)
Sent last (128)
Sent 2nd
Register
Availability
Sent 3rd
Sent First (1)
Restriction
D1 and D0 are set to ‘00’internally. D2 is implemented if the LCD is updating pixel-by pixel.
D2 is set to ‘0’internally if the LCD is updating line-by-line.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.159February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
Yes
Default Value
MY=0,MX=0,MV=0,ML=0,BGR=0,SS=0,B1=0,B0=0
No Change
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.160February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.30 Vertical Scrolling Start Address (37h)
37 H
Command
st
1 parameter
nd
2
parameter
VSCRSADD (Vertical Scrolling Start Address)
NRD
DNC
10
NWR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
↑
0
VSP
15
VSP 7
0
VSP
14
VSP 6
1
VSP
13
VSP 5
1
VSP
12
VSP 4
0
VSP
11
VSP 3
1
VSP
10
VSP 2
1
1
37
VSP 9
VSP 8
VSP 1
VSP 0
11
↑
11
↑
00 .. A1
This command is used together with Vertical Scrolling Definition (33h). These two
commands describe the scrolling area and the scrolling mode.
The Vertical Scrolling Start Address command has one parameter which describes the
address of the line in the Frame Memory that will be written as the first line after the
last line of the Top Fixed Area on the display as illustrated below:When MADCTL B4=0
Example:
When Top Fixed Area = Bottom Fixed Area = 00, Vertical Scrolling Area = 162 and
Description
When MADCTL B4=1
Example:
When Top Fixed Area = Bottom Fixed Area = 00, Vertical Scrolling Area = 162 and

W hen new Pointer position and Picture Data are sent, the result on the display will
happen at the next Panel Scan to avoid tearing effect.

VSP refers to the Frame Memory line Pointer.
Restriction
Register
Availability
Default
Flow Chart
Since the value of the Vertical Scrolling Start Address is absolute (with reference to the
Frame Memory), it must not enter the fixed area (defined by Vertical Scrolling
Definition (33h) – otherwise undesirable image will be displayed on the Panel.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
No
No
Yes
Default Value
0000
0000
0000
See Vertical Scrolling Definition (33h) description.
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.161February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.31 Idle Mode Off (38h)
38 H
IDMOFF (Idle mode off)
Command
DNC
0
Parameter
Description
Restriction
Register
Availability
Default
NWR
↑
NRD
1
D7
0
D6
0
D5
1
D4
1
D3
1
D2
0
D1
0
D0
0
HEX
38
NO PARAMETER
This command is used to recover from Idle mode on.
In the idle off mode, LCD can display maximum 262,144 colors. See also section
8.6.2.
This command has no effect when module is already in idle off mode.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Status
Power On Sequence
S/W Reset
Default Value
Idle off mode
Idle off mode
Flow Chart
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.162February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.32 Idle Mode On (39h)
39 H
IDMON (Idle mode on)
Command
DNC
0
Parameter
Description
Restriction
Register
Availability
Default
NWR
↑
NRD
1
D7
0
D6
0
D5
1
D4
1
D3
1
D2
0
D1
0
D0
1
HEX
39
NO PARAMETER
This command is used to enter into Idle mode on. In the idle on mode, color
expression is reduced. The primary and the secondary colors using MSB of each
R, G and B in the Frame Memory, 8 color depth data is displayed.
Memory contents vs. Display Color
R4 R3 R2 R1 R0
G5 G4 G3 G2 G1 G0
B4 B3 B2 B1 B0
Black
0XXXX
0XXXXX
0XXXX
Blue
0XXXX
0XXXXX
1XXXX
Red
1XXXX
0XXXXX
0XXXX
Magenta
1XXXX
0XXXXX
1XXXX
Green
0XXXX
1XXXXX
0XXXX
Cyan
0XXXX
1XXXXX
1XXXX
Yellow
1XXXX
1XXXXX
0XXXX
White
1XXXX
1XXXXX
1XXXX
X=don’t care
See also section 8.6.2.
This command has no effect when module is already in idle on mode.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
Status
Default Value
Power On Sequence
Idle off mode
S/W Reset
Idle off mode
H/W Reset
Idle off mode
Flow Chart
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.163February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.33 Interface Pixel Format (3Ah)
3A H
Command
1st
parameter
Description
Restriction
Register
Availability
Default
COLMOD (Interface Pixel Format)
DNC
0
NRD
1
NWR
↑
D7
0
D6
0
D5
1
D4
1
D3
1
D2
0
D1
1
D0
0
HEX
3A
1
1
↑
XX
XX
XX
XX
XX
CSEL2
CSEL1
CSEL0
011,101
This command is used to define the format of RGB picture data, which is to be
transferred via the MCU Interface. The formats are shown in the table:Interface Format (system
CSEL2 CSEL1 CSEL0
interface)
Not Defined
0
0
0
Not Defined
0
0
1
Not Defined
0
1
0
12 Bit/Pixel
0
1
1
Not Defined
1
0
0
16 Bit/Pixel
1
0
1
18 Bit/Pixel
1
1
0
Not Defined
1
1
1
Note: In 8, 12, 16 &18 Bit/Pixel mode, the LUT is applied to transfer data into the
Frame Memory.
There is no visible effect until the Frame Memory is written to.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
18 Bit/Pixel
No Change
18 Bit/Pixel
Example:
16Bit/Pixel Mode
Legend
Command
Parameter
COLMOD
Display
Flow Chart
Action
011
12Bit/Pixel Mode
Mode
Sequential
transfer
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.164February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.34 Read ID1 (DAh)
DA H
Command
1st parameter
2nd parameter
Description
RDID1 (Read ID1)
DNC
0
1
1
NWR
↑
1
1
NRD
1
↑
↑
D7
1
-
D6
1
-
D5
D4
D3
D2
0
1
1
0
Module’s manufacturer[7:0]
D1
1
-
D0
0
-
HEX
DA
xx
This read byte identifies the LCD module’s manufacturer. It is specified by Nokia and
for xx is defined as xxHEX.
Restriction
Register
Availability
Default
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Status
Power On Sequence
S/W Reset
Availability
Yes
Yes
Yes
Yes
Default Value
xxHEX
xxHEX
Flow Chart
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.165February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.35 Read ID2 (DBh)
DB H
Command
1st parameter
2nd parameter
Description
RDID2 (Read ID2)
DNC
0
1
1
NWR
↑
1
1
NRD
1
↑
↑
D7
1
-
D6
1
V6
D5
0
V5
D4
1
V4
D3
1
V3
D2
0
V2
D1
1
V1
D0
1
V0
HEX
DB
-
This read byte is used to track the LCD module/driver version. It is defined by
display supplier (with Nokia’s agreement) and changes each time a revision is made
to the display, material or construction specifications. See Table:
ID Byte Value V[7:0]
Version
Changes
80h
81h
82h
83h
84h
85h
Restrictions
Register
Availability
Default
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Status
Power On Sequence
S/W Reset
Serial I/F Mode
(P/SX=Low)
Availability
Yes
Yes
Yes
Yes
Default Value
See Description
See Description
Parallel I/F Mode
(P/SX=High)
Legend
Command
Read ID2
Flow Chart
Send 2 nd p arameter
Read ID2
Dummy Read
Host
Display
Parameter
Display
Action
Mode
Send 2
nd
parameter
Sequential
transfer
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.166February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.36 Read ID3 (DCh)
DC H
Command
1st parameter
2nd parameter
Description
RDID3 (Read ID3)
DNC
0
1
1
NWR
↑
1
1
NRD
1
↑
↑
D7
1
-
D6
1
-
D5
D4
D3
D2
0
1
1
1
LCD module/driver ID [7:0]
D1
0
-
D0
0
-
HEX
DC
-
This read byte identifies the LCD module/driver. It is specified by Nokia and for this
LCD project module is defined as xxHEX.
Restrictions
Register
Availability
Default
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Status
Power On Sequence
S/W Reset
Availability
Yes
Yes
Yes
Yes
Default Value
TBDHEX
TBDHEX
Flow Chart
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.167February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4 Himax Command
6.4.1 SETOSC: Set Internal Oscillator (B0h)
B0 H
SETOSC( Set Internal Oscillator)
DNC
NWR
NRD
D15-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
↑
1
--
1
0
1
1
0
0
0
0
B0
1st parameter
1
↑
1
--
-
--
2nd parameter
1
↑
1
--
--
--
--
1
↑
1
--
--
--
--
rd
3 parameter
CADJ[3:0]
UADJ[2:0]
-OSC_
EN_C
ON(0)
---
RADJ[2:0]
--
OSC_
EN(1)
---
--
This command is used to set internal oscillator related setting.
OSC_EN: Enable internal oscillator, High active
CADJ[3:0], RADJ[3:0]: for Internal test.
UADJ[2:0]: Internal oscillator frequency, default is 1.5MHz.
UADJ2
Description
Restrictions
Register
Availability
UADJ1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
frequency
0
1
0
1
0
1
0
1
128%
119%
110%
100%
91%
81%
71%
61%
OSC_EN_CON: OSC_EN status control bit,1: OSC_EN in fix state,0: OSC_EN in changed state
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
Default
UADJ0
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
OSC_TEST=0; OSC_EN=0, CADJ[3:0]=OTP value, RADJ=OTP value,
UADJ[2:0]=3’b011.
OSC_EN=0h, if OPT is programmed, CADJ[3:0] =OTP value, RADJ=OTP value,
else no change
OSC_TEST=0; OSC_EN=0, CADJ[3:0] =OTP value, RADJ=OTP value,
UADJ[2:0]=3’b011
Flow Chart
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.168February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.2 SETPOWER: Set Power (B1h)
B1 H
SETPOWER( Set power related setting)
DNC NWR NRD D15-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
1
--
--
1
PON(0
)
DK(1)
--
--
0
STB(0
)
B1
--
--
--
--
--
--
AP[2:0](000)
--
--
--
--
--
--
VC1[2:0](110)
1
--
--
--
--
--
↑
↑
1
1
---
--
1
↑
1
--
N_DC[7:0]
th
1
↑
1
--
E_DC[7:0]
th
1
↑
1
--
0
↑
1
--
st
1
↑
1
--
nd
1
↑
1
--
rd
1
↑
1
th
1
↑
1
1
th
Command
1 parameter
2 parameter
3 parameter
4 parameter
th
5 parameter
th
6 parameter
7 parameter
8 parameter
9 parameter
1
GASE
NB(0)
--
BT[3:0](0011)
-FS11
--
--
FS10
--
--
--
VRH[3:0](0100)
---
--
---
-FS01
--
-FS00
-----
--
--
DCCL
K_SY
NC(1)
--
Description
GASENB: This stands for abnormal power-off supervise function when the power is off. It’s for
monitoring power status by NISD pad when GASENB is set to 0.
PON: Specify on/off control of step-up circuit 2 for VGH, VGL voltage generation.
For detail, see the Power Supply Setting Sequence.
PON
0
1
Operation of step-up circuit 2
OFF
ON
DK: Specify on/off control of step-up circuit 1 for VLCD voltage generation. For detail, see the Power
Supply Setting Sequence.
DK
0
1
Operation of step-up circuit 1
ON
OFF
STB: When STB = “1”, the HX8353-C into the standby mode, where all display operation stops,
suspend all the internal operations including the internal R-C oscillator. During the standby
mode, only the following process can be executed.
a. Exit the Standby mode (STB = “0”) ,
b. Start the oscillation
In the standby mode, the GRAM data and register content may be lost. For preventing this, they
have to reset again after the standby mode cancel.
AP(2-0):
Adjust the amount of current driving for the operational amplifier in the power supply circuit. When the
amount of fixed current is increased, the LCD driving capacity and the display quality are high, but the
current consumption is increased. This is a tradeoff, Adjust the fixed current by considering both the
display quality and the current consumption. AP(2-0) can be set as “000” when display is off, the
current consumption can be reduced by stopping the operations of operational amplifier and step-up
circuit.
AP2
AP1
AP0
Constant Current of Operational Amplifier
0
0
0
0
0
0
1
1
0
1
0
1
Power Circuit Off
Ignore
Ignore
Ignore
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.169February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
1
1
1
1
0
0
1
1
0
1
0
1
1
1.25
1.5
Ignore
VC1(2-0):
Specify the ratio for VLCD voltage adjusting.
VC12 VC11 VC10
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
VLCD
5.47
5.29
5.12
4.95
4.76
4.59
4.46
4.23
VRH(3-0):
Set the magnification of amplification for VREG1 voltage for gamma voltage setting. It allows magnify
the amplification of VREF from 2.8 to 4.8 times.
VRH3
VRH2
VRH1
VRH0
VREG1
0
0
0
0
VREFx 1.87
0
0
0
1
VREF x 2.00
0
0
1
0
VREF x 2.13
0
0
1
1
VREF x 2.20
0
1
0
0
VREF x 2.27
0
1
0
1
VREF x 2.33
0
1
1
0
VREF x 2.4
0
1
1
1
VREF x 2.47
1
0
0
0
VREF x 2.53
1
0
0
1
VREF x2.6
1
0
1
0
VREF x 2.67
1
0
1
1
VREF x 2.8
1
1
0
0
VREF x 2.93
1
1
0
1
VREF x 3.07
1
1
1
1
0
VREF x 3.2
Inhibited
1
1
1
Note: VREF is the internal reference voltage equals to 1.8V.
BT(3-0):
Switch the output factor of step-up circuit 2 for VGH and VGL voltage generation. The LCD
drive voltage level can be selected according to the characteristic of liquid crystal which panel
used. Lower amplification of the step-up circuit consumes less current and then the power
consumption can be reduced.
BT3
BT2
BT1
BT0
VCL
VGL
VGH
Capacitor Connection Pin
VCOMG=1
VCOMG=0
0
0
0
0
-1x VDD
VLCD x 3
[x 6]
-(VLCDx2)+VCL
[x -5]
-(VLCDX2)
[x -4]
VCL, VGH, VGL
C11 A/B, C21 A/B, C22A/B
0
0
0
1
-1x VDD
VLCD x 3
[x 6]
-(VLCDX2)
[x -4]
-(VLCDX2)
[x -4]
VCL, VGH, VGL
C11 A/B, C21 A/B, C22A/B
0
0
1
0
-1x VDD
VLCD x 3
[x 6]
-(VLCDx2)+VDD
[x -3]
-(VLCDx2)+VDD
[x -3]
VCL, VGH, VGL
C11 A/B, C21 A/B, C22A/B
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.170February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
0
0
1
1
-1x VDD
VLCD x 3+VDD
[x 5]
-(VLCDX2)+VCL
[x -5]
-(VLCDX2)
[x -4]
VCL, VGH, VGL
C11 A/B, C21 A/B, C22A/B
0
1
0
0
-1x VDD
VLCD x 3+VDD
[x 5]
-(VLCDX2)
[x -4]
-(VLCDX2)
[x -4]
VCL, VGH, VGL
C11 A/B, C21 A/B, C22A/B
0
1
0
1
-1x VDD
VLCD x 3+VDD
[x 5]
-(VLCDx2)+VDD
[x -3]
-(VLCDx2)+VDD
[x -3]
VCL, VGH, VGL
C11 A/B, C21 A/B, C22A/B
0
1
1
0
-1x VDD
VLCD X 2
[x 4]
-(VLCDX2)
[x -4]
-(VLCDX2)
[x -4]
VCL, VGH, VGL
C11 A/B, C21 A/B, C22A/B
0
1
1
1
-1x VDD
1
0
0
0
-1x VDD
VLCD X 2
[x 4]
-(VLCDX1)+VCL
[x-3]
-(VLCDX1)
[x-2]
VCL, VGH, VGL
C11 A/B, C21 A/B,
1
0
0
1
-1x VDD
VLCD X 2
[x 4]
-(VLCDX1)
[x-2]
-(VLCDX1)
[x-2]
VCL, VGH, VGL
C11 A/B, C21 A/B,
1
0
1
0
-1x VDD
-(VLCDX1)+VDD
[x-1]
-(VLCDX1)+VDD
[x-1]
VCL, VGH, VGL
C11 A/B, C21 A/B,
1
0
1
1
-1x VDD
-(VLCDX1)
[x-2]
VCL, VGH, VGL
C11 A/B, C21 A/B,
1
1
0
0
-1x VDD
-(VLCDX1)
[x-2]
VCL, VGH, VGL
C11 A/B, C21 A/B,
1
1
0
1
-1x VDD
VLCD X 2
[x 4]
VLCD X 2
+VDD
[x3]
VLCD X1 +
VDD
[x3]
VLCDX1+
VDD
[x3]
-(VLCDX1)+VDD
[x-1]
VCL, VGH, VGL
C11 A/B, C21 A/B,
1
1
1
0
-1x VDD
VLCDX1
[x2]
-(VLCDX1)
[x-2]
-(VLCDX1)
[x-2]
VCL, VGH, VGL
C11 A/B, C21 A/B,
1
1
1
1
Inhibited
-(VLCDX1)+VCL
[x-3]
-(VLCDX1)
[x-2]
-(VLCDX1)+VDD
[x-1]
Inhibited
Note: 1. The conditions of VLCD ≦ 6V, VCL ≦ -3.3V, VGH-VGL ≦ 32V must be satisfied.
2. If VCOMG=0, VCL output is floating.
3. C22 option : VGH and VGL can share the same pump capacitor when operate on special
pumping condition BT[3:0]=1XXX (On this condition, C22 can be removed).
FS0(1-0):
Set the operating frequency of the step-up circuit 1 and extra step-up circuit 1 for VLCD voltage
generation. When using the higher frequency, the driving ability of the step-up circuit and the display
quality are high, but the current consumption is increased. The tradeoff is between the display quality
and the current consumption.
DCDCf = DC / DC converter operating frequency
FS01
FS0
Operation Frequency of Step-up Circuit 1 and Extra Step-up circuit 1
0
0
DCDCf / 1
0
1
DCDCf / 2
1
0
DCDCf / 4
1
1
DCDCf / 8
FS1(1-0):
Set the operating frequency of the step-up circuit 2 and 3 for VGH, VGL and VCL voltage generation.
When using the higher frequency, the driving ability of the step-up circuit and the display quality are
high, but the current consumption is increased. The tradeoff is between the display quality and the
current consumption.
DCDCf = DC / DC converter operating frequency
FS11
FS10
Operation Frequency of Step-up Circuit 2 , Step-up Circuit 3
0
0
DCDCf / 1
0
1
DCDCf / 2
1
0
DCDCf / 4
1
1
DCDCf / 8
Note: Ensure that the operation frequency of step-up circuit 1 ≧ step-up circuit 2
N_DC: Normal mode
E_DC: Idle mode
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.171February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Restrictions
Register
Availability
DCCLK_SYNC: Internal use, not open.
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
GASENB=1’b0, PON=1’b0, XDK=1’b0, VLCD_TRI=1’b0, STB=1’b1,
AP[2:0]=3’b000, VC1[2:0]=3’b110, VC3[2:0]=3’b110, VRH[3:0]=4’b0010,
BT[3:0]=4’b0011, FS1[1:0]=2’b01, FS0[1:0]=2’b00,
N_DC[7:0]=8’b0110_1110, PE_DC[7:0]=8’b0110_1110,
E_DC[7:0]=8’b0110_1110, PI_PRE_REFRESH[1:0]=2’b00,
BLANK_DIV[3:0]=4’b0000, DCCLK_SYNC=1’b1
GASENB=1’b0, PON=1’b0, XDK=1’b0, VLCD_TRI=1’b0, STB=1’b1,
AP[2:0]=3’b000, VC1[2:0]=3’b110, VC3[2:0]=3’b110, VRH[3:0]=4’b0010,
BT[3:0]=4’b0011, FS1[1:0]=2’b01, FS0[1:0]=2’b00,
N_DC[7:0]=8’b0110_1110, PE_DC[7:0]=8’b0110_1110,
E_DC[7:0]=8’b0110_1110, PI_PRE_REFRESH[1:0]=2’b00,
BLANK_DIV[3:0]=4’b0000, DCCLK_SYNC=1’b1
GASENB=1’b0, PON=1’b0, XDK=1’b0, VLCD_TRI=1’b0, STB=1’b1,
AP[2:0]=3’b000, VC1[2:0]=3’b110, VC3[2:0]=3’b110, VRH[3:0]=4’b0010,
BT[3:0]=4’b0011, FS1[1:0]=2’b01, FS0[1:0]=2’b00,
N_DC[7:0]=8’b0110_1110, PE_DC[7:0]=8’b0110_1110,
E_DC[7:0]=8’b0110_1110, PI_PRE_REFRESH[1:0]=2’b00,
BLANK_DIV[3:0]=4’b0000, DCCLK_SYNC=1’b1
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.172February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.3 SETDISP: Set Display Related Register (B2h)
B2 H
Command
st
1
parameter
nd
2
parameter
rd
3
parameter
th
4
parameter
th
5
parameter
th
6
parameter
th
7
parameter
th
8
parameter
th
9
parameter
SETDISP( Set display related register)
DNC NWR NRD D15-8
D7
↑
0
1
-1
D6
0
D5
1
D4
1
GON
DTE
D3
0
D2
0
D1
1
D0
0
HEX
B2
--
--
--
1
↑
1
--
1
↑
1
--
--
--
--
--
N_BP[3:0]
--
1
↑
1
--
--
--
--
--
N_FP[3:0]
--
1
↑
1
SAP[7:0]
--
1
↑
1
EQS[7:0]
--
1
↑
1
EQP[7:0]
--
1
↑
1
--
--
--
--
1
↑
1
--
--
--
PTG[1:0]
1
↑
1
1
↑
1
PT[1:0]
D[1:0]
--
GEN_OFF[3:0]
--
ISC[3:0]
--
SAP_I[7:0]
--
th
10
parameter
--
--
--
--
--
--
--
--
OPTIO
N_DIS
P(0)
--
This command is used to set display related register
D1–0: When D1 = 1, display is on; when D1 = 0, display is off. When display is off, the display data is
retained in the GRAM, and can be instantly displayed by setting D1 = 1. When D1= 0, the display is
off with the entire source outputs are set to the VSSD level. Because of this, the HX8353-C can
control the charging current for the LCD with AC driving. Control the display on/off while control GON
and DTE. When D1–0 = 01, the internal display of the HX8353-C is performed although the actual
display is off. When D1-0 = 00, the internal display operation halts and the display is off.
VSSD
VSSD
HX8353-C Internal
Display Operations
Halt
Operate
Gate-Driver Control Signals
(CPV, FLM, M)
Halt
Operate
0
Non-lit display
Operate
Operate
1
Display
Operate
Operate
D1
D0
Source Output
0
0
0
1
1
1
Description
GON, DTE:
GON
DTE
0
X
1
0
1
1
Gate Output
VGH
VGL
VGH/VGL
PT[1:0] : Non-display area source output control
Source Output Level
REV
Himax Confidential
GRAM
Data
Display area
Non-display Area
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.173February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Data
0
1
18’h00000
.
.
18’h3FFFF
18’h00000
.
.
18’h3FFFF
PT1-0=(0,*)
VCOM = VCOM =
“L”
“H”
V63
V0
.
.
.
.
V0
V63
V0
V63
.
.
.
.
V63
V0
PT1-0=(1,0)
VCOM = VCOM =
“L”
“H”
PT1-0=(1,1)
VCOM =
“L”
VCOM =
“H”
VCOM VCOM =
= “L”
“H”
V63
V0
VSSD
VSSD
Hi-z
Hi-z
V63
V0
VSSD
VSSD
Hi-z
Hi-z
FP[3:0]: Specify the amount of scan line for front porch (FP).
BP[3:0]: Specify the amount of scan line for back porch(BP).
N_FP[3:0], N_BP[3:0]: Normal mode
FP3
FP2
FP1
FP0
BP3
BP2
BP1
BP0
0
0
0
0
0
0
0
1
Ignore
0
0
1
0
2 lines
0
0
1
1
3 lines
0
1
0
0
4 lines
0
1
0
1
5 lines
0
1
1
0
6 lines
0
1
1
1
7 lines
1
0
0
0
8 lines
1
0
0
1
9 lines
1
0
1
0
10 lines
1
0
1
1
11 lines
1
1
0
0
12 lines
1
1
0
1
13 lines
1
1
1
0
14 lines
1
1
1
1
Ignore
Operation Mode
System Interface
BP
≥2 lines
Number of FP
Line
Number of BP
Line
Ignore
FP
≥2 lines
EQS[7:0]: Internal use, not open.
EQP[7:0]: Internal use, not open.
GEN_OFF: Internal use, not open.
PTG[1:0]: Specify the scan mode of gate driver in non-display area.
PTG1
PTG0
Gate Outputs in Non-display Area
0
0
1
0
1
0
Normal Drive
Fixed VGL
Interval scan
1
1
Ignore
ISC[3:0]: Specify the scan cycle of gate driver when PTG1-0=10 in non-display area. Then scan
cycle is set to an odd number from 0~31.The polarity is inverted every scan cycle.
ISC3
0
ISC2
0
ISC1
0
ISC0
0
Scan Cycle
0 frame
fFLM = 60Hz
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.174February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3 frames
5 frames
7 frames
9 frames
11 frames
13 frames
15 frames
17 frames
19 frames
21 frames
23 frames
25 frames
27 frames
29 frames
31 frames
50 ms
84 ms
117 ms
150 ms
184 ms
217 ms
251 ms
284 ms
317 ms
351 ms
384 ms
418 ms
451 ms
484 ms
518 ms
SAP[7-0]: Normal mode, Internal use, not open.
SAP_I[7-0]: Idle mode, Internal use, not open.
Restrictions
Register
Availability
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
PT[1:0]=2’b00, GON=1, DTE=0, D1-0=2’b00, N_FP[3:0]=4’b1101,
N_BP[3:0]=4’b1010, PE_FP[3:0]=4’b1101, PE_BP[3:0]=4’b1010,
E_FP[3:0]=4’b1101, E_BP[3:0]=4’b1010, SAP[7:0]=8’b0001_0100,
EQS=8’b0001_1001, EQP=8’b0001_1001, GEN_OFF=8’b0001_0100,
PTG[1:0]=2’b10, ISC[3:0]=4’b010, SAP_I[7:0]= 8’b0000_1010,, PTG[1:0]=2’b10
PT[1:0]=2’b00, GON=1, DTE=0, D1-0=2’b00, N_FP[3:0]=4’b1101,
N_BP[3:0]=4’b1010, PE_FP[3:0]=4’b1101, PE_BP[3:0]=4’b1010,
E_FP[3:0]=4’b1101, E_BP[3:0]=4’b1010, SAP[7:0]=8’b0001_0100,
EQS=8’b0001_1001, EQP=8’b0001_1001, GEN_OFF=8’b0001_0100,
PTG[1:0]=2’b10, ISC[3:0]=4’b010, SAP_I[7:0]= 8’b0000_1010,, PTG[1:0]=2’b10
PT[1:0]=2’b00, GON=1, DTE=0, D1-0=2’b00, N_FP[3:0]=4’b1101,
N_BP[3:0]=4’b1010, PE_FP[3:0]=4’b1101, PE_BP[3:0]=4’b1010,
E_FP[3:0]=4’b1101, E_BP[3:0]=4’b1010, SAP[7:0]=8’b0001_0100,
EQS=8’b0001_1001, EQP=8’b0001_1001, GEN_OFF=8’b0001_0100,
PTG[1:0]=2’b10, ISC[3:0]=4’b010, SAP_I[7:0]= 8’b0000_1010,, PTG[1:0]=2’b10
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.175February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.4 SETLUT: Set LUT Enable Related Register (B3h)
B3 H
Command
st
1
parameter
SETLUT(Set LUT Enable Related Register)
DNC NWR NRD D15-8 D7 D6
↑
0
1
-1
0
1
↑
1
--
--
--
D5
1
D4
1
D3
0
D2
1
D1
0
D0
1
HEX
B3
LUT_ENB
--
--
--
--
--
--
This command is used to set LUTenable related register
Description
Restrictions
Register
Availability
Default
LUT_ENB: Enable/Disable the look up table.
0: Enable the look up table.
1: Disable the look up table.
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
LUT_EN=OTP value,
LUT_EN= No change ,
LUT_EN=OTP value,
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.176February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.5 SETCYC: Set Display Waveform Cycles (B4h)
B4H
SETCYC( Set display waveform cycles)
Command
st
1 parameter
nd
2 parameter
rd
3 parameter
th
4 parameter
th
5 parameter
th
6 parameter
DNC
0
1
1
1
1
1
1
NWR
↑
↑
↑
↑
↑
↑
↑
NRD
1
1
1
1
1
1
1
D15-8
--------
D7
1
--
D6
D5
D4
D3
0
1
1
0
N_RTN[3:0]
-E_RTN[3:0]
--DIV_E[1:0]
-SON[7:0]
GDON[7:0]
GDOF[7:0]
D2
1
--
D1
D0
1
1
N_NW[2:0]
E_NW[2:0]
---
HEX
B4
-------
This command is used to set display waveform cycles
NW[2:0]: Frame Inversion and N-line inversion control
NW[2:0]
Inversion Type
0
Frame inversion
1
1-line inversion
2
2-line inversion
3
3-line inversion
..
..
7
7-line inversion
RTN[3:0]: Set the 1-line period in a clock unit.
Clock cycles=1/internal operation clock frequency
RTN[3:0]
4’b0000
4’b0001
4’b0010
4’b0011
… .
4’b1110
4’b1111
Description
Clock Cycles per Line
138
139
140
141
… .
153
154
DIV_E[1:0]:The division ratio of clocks for internal operation (DIV1-0). Internal operations are base on
the clocks which are frequency divided according to the value of DIV1-0. Frame frequency can be
adjusted along with the 1H period (RTN3-0). When the drive line count is changed, the frame
frequency must be also adjusted.
fosc = R-C oscillation frequency
DIV_E1
0
0
1
1
DIV_E0
0
1
0
1
Division Ratio
1
2
4
8
Internal Operation Clock Frequency
fosc / 1
fosc / 2
fosc / 4
fosc / 8
Formula for the Frame Frequency:
Frame frequency = fosc/( RTN × DIV × (NL+BP+FP) ) [HZ]
fosc: RC oscillation frequency
RTN bit: Clocks per line
DIV bit: Division ratio
NL: The number of lines
FP: Number of lines for front porch
BP: Number of lines for back porch
BP+FP≦16
The HX8353-C can control the display operation period time for LCD panel driving as follow:
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.177February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
1-Line Period
SON
S1 - S720
Hi-z
GDON
Source Output Period
Hi-z
GDOF
Gate Output Period
G(N)
Nth Gate Output Period
G(N+1)
N+1th Gate Output Period
SON7-0: Specify the valid source output start time in 1-line driving period. The period time is defined
as SYSCLK clock number. (Please note that the setting “00h” and “01h” is inhibited).
GDON7-0: Specify the valid gate output start time in 1-line driving period. The period time is defined
as SYSCLK clock number in internal clock display mode. The period time is defined as
setting value x 8 DOTCLK clock number in external clock display mode. (Please note that
the setting “00h”, “01h”, “02h” is inhibited).
GDOF7-0: Specify the gate output end time in 1-line driving period. The period time is defined as
SYSCLK clock number in internal clock display mode. The period time is defined as setting
value x 8 DOTCLK clock number in external clock display mode. (Please note that the
GDOF7-0  HCK-1).
Restrictions
Register
Availability
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
N_NW[3:0]=3’b001, N_RTN[3:0]=4’b1101, PE_NW[3:0]=3’b000,
E_NW[3:0]=3’b000, E_RTN[3:0]=4’b1101, DIV_E[1:0]=OTP
Value, DIV_PE[1:0]=OTP Value , DIV_N[1:0]=OTP Value,
SON[7:0]=8’h19, GDON[7:0]=8’h1E, GDOF[7:0]=8’h78.
N_NW[3:0]=3’b001, N_RTN[3:0]=4’b1101, PE_NW[3:0]=3’b000,
E_NW[3:0]=3’b000, E_RTN[3:0]=4’b1101, DIV_E[1:0]= No
change, DIV_PE[1:0]= No change , DIV_N[1:0]=No change,
SON[7:0]=8’h19, GDON[7:0]=8’h1E, GDOF[7:0]=8’h78.
N_NW[3:0]=3’b001, N_RTN[3:0]=4’b1101, PE_NW[3:0]=3’b000,
E_NW[3:0]=3’b000, E_RTN[3:0]=4’b1101, DIV_E[1:0]=OTP
Value, DIV_PE[1:0]=OTP Value , DIV_N[1:0]=OTP Value,
SON[7:0]=8’h19, GDON[7:0]=8’h1E, GDOF[7:0]=8’h78.
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.178February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.6 SETBGP: Set BGP Voltage (B5h)
B5 H
Command
1st
parameter
SETBGP( Set Band Gap Voltage)
DNC NWR NRD D15-8
D7
↑
0
1
-1
1
↑
1
--
--
D6
0
D5
1
D4
1
--
--
--
D3
1
D2
0
D1
0
D0
1
HEX
B5
BGP[3:0]
-
This command is used to set BandGap Voltage
BGP[3:0]: band gap voltage control
BGP[3:0]
4’b0000
4’b0001
4’b0010
4’b0011
4’b0100
4’b0101
4’b0110
4’b0111
4’b1000
4’b1001
4’b1010
4’b1011
4’b1100
4’b1101
4’b1110
4’b1111
Description
Restrictions
Register
Availability
Default
VREF output
X 0.936
X 0.944
X 0.952
X 0.96
X 0.968
X 0.976
X 0.984
X 0.992
X 1.000
X 1.008
X 1.016
X 1.024
X 1.032
X 1.040
X 1.048
X 1.056
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
BGP[3:0]=OTP value
BGP[3:0]=No Change
BGP[3:0]=OTP value
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.179February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.7 SETVCOM: Set VCOM Voltage (B6h)
B6 H
Command
st
1
parameter
nd
2
parameter
rd
3
parameter
SETVCOM( Set VCOM Voltage)
DNC
NWR
NRD
D15-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
--
0
1
1
0
1
1
0
B6
1
↑
1
--
1
VCO
MG
--
--
--
--
--
--
--
--
1
↑
1
--
--
1
↑
1
--
--
VCMN[6:0]
--
--
--
VDV[4:0]
--
This command is used to set VCOM Voltage include VCOM Low and VCOM High Voltage
VCOMG: When VCOMG = 1, VCOML voltage can output to negative voltage (1.0V ~ -VDD +0.5V ).
When VCOMG = 0, VCOML voltage becomes VSSD and stops the amplifier of the negative
voltage. Therefore, low power consumption is accomplished.
VDV(4-0): Specify the VCOM amplitude factors for panel common driving (VCOML = VCOMH – VCOM
amplitude). It is possible to setup from 0.6 to 1.23 times of VREG1. When VCOMG0 = 0, the
VDV(4-0) setup is invalid and VCOML is output VSSA.
Description
VDV4
VDV3
VDV2
VDV1
VDV0
VCOM Amplitude
0
0
0
0
0
VREG1*0.6
0
0
0
0
1
VREG1*0.63
0
0
0
1
0
VREG1*0.66
0
0
0
1
1
VREG1*0.69
0
0
1
0
0
VREG1*0.72
0
0
1
0
1
VREG1*0.75
0
0
1
1
0
VREG1*0.78
0
0
1
1
1
VREG1*0.81
0
1
0
0
0
VREG1*0.84
0
1
0
0
1
VREG1*0.87
0
1
0
1
0
VREG1*0.9
0
1
0
1
1
VREG1*0.93
0
1
1
0
0
VREG1*0.96
0
1
1
0
1
VREG1*0.99
0
1
1
1
0
VREG1*1.02
0
1
1
1
1
Inhibit
1
0
0
0
0
VREG1*1.05
1
0
0
0
1
VREG1*1.08
1
0
0
1
0
VREG1*1.11
1
0
0
1
1
VREG1*1.14
1
0
1
0
0
VREG1*1.17
1
0
1
0
1
VREG1*1.2
1
0
1
1
0
VREG1*1.23
1
0
1
1
1
Inhibit
1
1
0
0
0
Inhibit
1
1
0
0
1
Inhibit
1
1
0
1
0
Inhibit
1
1
0
1
1
Inhibit
1
1
1
0
0
Inhibit
1
1
1
0
1
Inhibit
1
1
1
1
0
Inhibit
1
1
1
1
1
Inhibit
Note: VCOML >= (VCL + 0.3), VCOMH <= (VLCD - 0.3) when set VDV[4:0]
VCMN(6-0): Set the VCOMH voltage on normal mode. It is possible to amplify from 0.4 to 0.98 times of
VREG1 voltage.
VCMN6
VCMN5
VCMN4
VCMN3
VCMN2
VCMN1
VCMN0
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
VCOMH
-P.180February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
VREG1 * 0.4
VREG1 * 0.405
VREG1 * 0.41
VREG1 * 0.415
VREG1 * 0.42
VREG1 * 0.425
VREG1 * 0.43
VREG1 * 0.435
VREG1 * 0.44
VREG1 * 0.445
VREG1 * 0.45
VREG1 * 0.455
VREG1 * 0.46
VREG1 * 0.465
VREG1 * 0.47
VREG1 * 0.475
VREG1 * 0.48
VREG1 * 0.485
VREG1 * 0.49
VREG1 * 0.495
VREG1 * 0.5
VREG1 * 0.505
VREG1 * 0.51
VREG1 * 0.515
VREG1 * 0.52
VREG1 * 0.525
VREG1 * 0.53
VREG1 * 0.535
VREG1 * 0.54
VREG1 * 0.545
VREG1 * 0.55
VREG1 * 0.555
VREG1 * 0.56
VREG1 * 0.565
VREG1 * 0.57
VREG1 * 0.575
VREG1 * 0.58
VREG1 * 0.585
VREG1 * 0.59
VREG1 * 0.595
VREG1 * 0.6
VREG1 * 0.605
VREG1 * 0.61
VREG1 * 0.615
VREG1 * 0.62
VREG1 * 0.625
VREG1 * 0.63
VREG1 * 0.635
VREG1 * 0.64
VREG1 * 0.645
VREG1 * 0.65
VREG1 * 0.655
VREG1 * 0.66
VREG1 * 0.665
VREG1 * 0.67
VREG1 * 0.675
VREG1 * 0.68
VREG1 * 0.685
VREG1 * 0.69
VREG1 * 0.695
VREG1 * 0.7
VREG1 * 0.705
VREG1 * 0.71
inhibit
VREG1 * 0.715
VREG1 * 0.72
VREG1 * 0.725
VREG1 * 0.73
VREG1 * 0.735
VREG1 * 0.74
-P.181February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Restrictions
Register
Availability
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VREG1 * 0.745
VREG1 * 0.75
VREG1 * 0.755
VREG1 * 0.76
VREG1 * 0.765
VREG1 * 0.77
VREG1 * 0.775
VREG1 * 0.78
VREG1 * 0.785
VREG1 * 0.79
VREG1 * 0.795
VREG1 * 0.8
VREG1 * 0.805
VREG1 * 0.81
VREG1 * 0.815
VREG1 * 0.82
VREG1 * 0.825
VREG1 * 0.83
VREG1 * 0.835
VREG1 * 0.84
VREG1 * 0.845
VREG1 * 0.85
VREG1 * 0.855
VREG1 * 0.86
VREG1 * 0.865
VREG1 * 0.87
VREG1 * 0.875
VREG1 * 0.88
VREG1 * 0.885
VREG1 * 0.89
VREG1 * 0.895
VREG1 * 0.9
VREG1 * 0.905
VREG1 * 0.91
VREG1 * 0.915
VREG1 * 0.92
VREG1 * 0.925
VREG1 * 0.93
VREG1 * 0.935
VREG1 * 0.94
VREG1 * 0.945
VREG1 * 0.95
VREG1 * 0.955
VREG1 * 0.96
VREG1 * 0.965
VREG1 * 0.97
VREG1 * 0.975
VREG1 * 0.98
inhibit
inhibit
inhibit
inhibit
inhibit
inhibit
inhibit
inhibit
inhibit
inhibit
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Availability
Yes
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.182February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Yes
Yes
Yes
Default Value
VCOMG=1’b0, VDV[4:0]=OTP value, VCMN[5:0]=OTP value,
VCME[5:0]=OTP value, VCMPE[5:0]=OTP value
VCOMG=1’b0, VDV[4:0]= OTP value, VCMN[5:0]= OTP value,
VCME[5:0]= OTP value, VCMPE[5:0]= OTP value
VCOMG=1’b0, VDV[4:0]= OTP value, VCMN[5:0]= OTP value,
VCME[5:0]= OTP value, VCMPE[5:0]= OTP value
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.183February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.8 SETGAMMA: Set Gamma Curve Related Setting (B7)
B7H
Command
st
1 parameter
nd
2 parameter
rd
3 parameter
th
4 parameter
th
5 parameter
th
6 parameter
th
7 parameter
th
8 parameter
th
9 parameter
th
10 parameter
th
11 parameter
th
12 parameter
th
13 parameter
th
14 parameter
th
15 parameter
th
16 parameter
th
17 parameter
th
18 parameter
th
19 parameter
SETGAMMA1( Set Gamma Curve1 Related Setting)
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
0
D5
1
D4
1
1
↑
1
--
1
↑
1
--
1
↑
1
--
↑
1
--
1
↑
1
--
1
↑
1
--
1
↑
1
--
1
↑
1
--
1
↑
1
--
1
↑
1
--
1
↑
1
--
1
↑
1
--
1
↑
1
--
1
↑
1
--
1
↑
1
--
1
↑
1
--
1
↑
1
--
1
↑
1
--
1
↑
1
--
MP12
MP32
MP52
-CP22
-----MN12
MN32
MN52
-CN22
-----
MP11
MP31
MP51
-CP21
-----MN11
MN31
MN51
-CN21
-----
MP10
MP30
MP50
1
----CP23
---------CN23
-----
--
CP20
---
-OP14
-MN10
MN30
MN50
--
CN20
----
ON14
D3
0
D2
1
-MP02
-MP22
-MP42
CP03 CP02
CP13 CP12
CP33 CP32
CP43 CP42
OP03 OP02
OP13 OP12
CGM1[1:0]
-MN02
-MN22
-MN42
CN03 CN02
CN13 CN12
CN33 CN32
CN43 CN42
ON03 ON02
ON13 ON12
D1
1
D0
1
MP01
MP00
MP21
MP20
MP41
MP40
CP01
CP00
CP11
CP10
CP31
CP30
CP41
CP40
OP01
OP00
OP11
OP10
CGM0[1:0]
MN01 MN00
MN21 MN20
MN41 MN40
CN01
CN00
CN11
CN10
CN31
CN30
CN41
CN40
ON01
ON00
ON11
ON10
HEX
B7
-------------
This command is used to set Gamma Curve 1 Related Setting
Register
Groups
Center
Adjustment
Description
Macro
Adjustment
Offset
Adjustment
Restrictions
Register
Availability
Default
Positive
Polarity
CP/N0 3-0
CP/N1 3-0
CP/N2 3-0
CP/N3 3-0
CP/N4 3-0
MP/N0 2-0
MP/N1 2-0
MP/N2 2-0
MP/N3 2-0
MP/N4 2-0
MP/N5 2-0
OP/N0 3-0
OP/N1 4-0
Description
Variable resistor (VRTP/N) for center adjustment
Variable resistor (VRCP/N0)for center adjustment
Variable resistor (VRMP/N) for center adjustment
Variable resistor (VRCP/N1)for center adjustment
Variable resistor (VRBP/N)for center adjustment
8-to-1 selector (reference voltage level of grayscale 1)
8-to-1 selector (reference voltage level of grayscale 8)
8-to-1 selector (reference voltage level of grayscale 20)
8-to-1 selector (reference voltage level of grayscale 43)
8-to-1 selector (reference voltage level of grayscale 55)
8-to-1 selector (reference voltage level of grayscale 62)
Variable resistor (VROP/N0)for offset adjustment
Variable resistor (VROP/N1)for offset adjustment
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
OTP value
No change
OTP value
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.184February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.9 PASSWDEN: Set Password enable command (B9h)
B9 H
PASSWDEN( Set Password enable command)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
↑
Command
0
1
-1
0
1
1
1
0
st
↑
1 parameter
1
1
-0
0
0
1
0
1
nd
↑
2 parameter
1
1
-1
1
0
0
1
1
This command is used to set extended command set access enable.
D1
0
1
0
D0
1
1
0
HEX
B9
17h
CCh
Command description
After command (B9h), must write 2 parameters (17h,
Enable
CCh) by order, then can enable the extended command
(Himax command)
After command(BAh), the extended command (Himax
Disable(default)
command) can not be accessed
As PASSWDEN command has been written, the external pin EXTC control is invalid, and
extended command can access.
Extend cmd
Description
Restrictions
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Availability
Yes
Yes
Yes
Yes
“HW or SW RESET” and EXTC=“L”
“User Define Command”
No Operation(NOP)
MPU Interface Command set
(Standard Command set)
Operation
“PASSWD＿Enable Command” issue
Flow Chart
“User Define Command”
Operation
“PASSWD＿Disable Command” issue
“User Define Command”
No Operation(NOP)
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.185February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.10 PASSWDDISAB: Password Disable command (BAh)
BAH
Command
PASSWDDISAB(Password Disable command)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
↑
0
1
-1
0
1
1
1
0
This command is used to set extended command set access enable.
Extend cmd
Enable
Description
Disable(default)
D1
1
D0
0
HEX
BA
Command description
After command (B9h), must write 2 parameters (17h, CCh) by order,
then can enable the extended command (Himax command)
After command(BAh), the extended command (Himax command)
can not be accessed
As PASSWDDISAB command has been written, it will be disable PASSWDEN command and
the extended command can not be accessed.
Restrictions
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Availability
Yes
Yes
Yes
Yes
Yes
“HW or SW RESET” and EXTC=“L”
“User Define Command”
No Operation(NOP)
MPU Interface Command set
(Standard Command set)
Operation
“PASSWD＿Enable Command” issue
Flow Chart
“User Define Command”
Operation
“PASSWD＿Disable Command” issue
“User Define Command”
No Operation(NOP)
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.186February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.11 SETOTP: Set OTP Related Setting (BBh)
BB H
Command
st
1
parameter
nd
2
parameter
rd
3
parameter
4th
parameter
Description
Restrictions
Register
Availability
SETOTP( Set OTP Related Setting)
DNC
0
NWR
↑
NRD
1
D15-8
--
1
↑
1
--
OTP_MASK[7:0]
--
1
↑
1
--
OTP_INDEX[7:0]
--
1
↑
1
--
OTP_LO
AD_DISA
BLE
DCCL
K_DIS
ABLE
OTP_
POR
OTP_
PWE
1
↑
1
--
--
--
--
--
D6
0
D5
1
D4
1
D3
1
OTP_
EN
D2
0
OTPTE
ST_EN
D1
1
VPP_
SEL
OTP_PTM[1:0]
D0
1
HEX
BB
OTP_P
ROG
--
OTP_VRADJ[1:0]
--
This command is used to set OTP Related Setting
OTP_MASK7~OTP_MASK0: Bit programming mask, if 1, means don’t programming this bit
OTP_INDEX7~OTP_INDEX0: Set location of OTP to be programmed
OTP_EN: When written to 1, internal register begin written to OTP
VPP_SEL: When written to 1, PVSS voltage is fed to OTP
OTP_LOAD_DISABLE: When written to 1, auto load from OTP to internal register when SLPOUT
command received is disabled, this is used when OTP is not yet programmed
DCCLK_DISABLE: Disable Pumping Clock
OTPEST_EN:
0 : normal mode, automatic OTP programming mode (by internal state machine)
1 : manual mode
0 is the default value
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
Default
D7
1
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
OTP_MASK[7:0]=8’h00, OTP_INDEX[7:0]=8’hff, OTP_LOAD_DISABLE=0,
DCCLK_DISABLE=0, VPP_SEL=0, OTP_PROG=0, OTPEST_EN=0,
OTP_EN=0, OTP_PTM[1:0]=2’b00, OTP_VRADJ[1:0] =2’b00
OTP_MASK[7:0]=8’h00, OTP_INDEX[7:0]=8’hff, OTP_LOAD_DISABLE=0,
DCCLK_DISABLE=0, VPP_SEL=0, OTP_PROG=0, OTPEST_EN=0,
OTP_EN=0, OTP_PTM[1:0]=2’b00, OTP_VRADJ[1:0] =2’b00
OTP_MASK[7:0]=8’h00, OTP_INDEX[7:0]=8’hff, OTP_LOAD_DISABLE=0,
DCCLK_DISABLE=0, VPP_SEL=0, OTP_PROG=0, OTPEST_EN=0,
OTP_EN=0, OTP_PTM[1:0]=2’b00, OTP_VRADJ[1:0] =2’b00
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.187February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.12 SETVDC: Set Internal Digital Voltage (BCh)
BC H
Command
st
1
parameter
Description
Restrictions
Register
Availability
Default
SETVDC( Set internal digital voltage)
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
0
D5
1
D4
1
D3
1
1
↑
1
--
--
--
--
--
--
D2
1
D1
0
D0
0
HEX
BC
VDC_SEL[2:0]
--
This command is used to set internal digital voltage for digital circuit and GRAM
VDC_SEL[1:0]: Not open
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
VDC_SEL[2:0]=3’b110
VDC_SEL[2:0]=3’b110
VDC_SEL[2:0]=3’b110
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.188February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.13 SETSPULSE: Set Arbiter Pulse Width (BDh)
BD H
Command
st
1 parameter
nd
2 parameter
SETSPULSE( Set Arbiter Pulse Width)
DN
C
0
1
1
NRD
NWR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
1
↑
1
0
1
1
1
1
0
1
BD
1
1
↑
↑
RTBA[13:8]
--
RTBA[7:0]
--
This command is used to set GRAM arbiter pulse width, it is for internal use.
Description
Restrictions
Register
Availability
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
SPULSE_ERD[2:0]=3’b100, SPULSE_EWR[2:0]=3’b100,
SPULSE_IRD[2:0]=3’b100, ARBMODE_SEL=0, LPLW_EN =0,
REFBL_EN[1:0]=2’b00, RPULSE [2:0]=3’b100, DPULSE [2:0]=3’b000
No change
SPULSE_ERD[2:0]=3’b100, SPULSE_EWR[2:0]=3’b100,
SPULSE_IRD[2:0]=3’b100, ARBMODE_SEL=0, LPLW_EN =0,
REFBL_EN[1:0]=2’b00, RPULSE [2:0]=3’b100, DPULSE [2:0]=3’b000
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.189February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.14 SETPROBE: Set Probe Signal Group (BEh)
BE H
Command
1st
parameter
nd
2
parameter
SETPROBE ( Set Probe Signal Group)
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
0
D5
1
D4
1
D3
1
D2
1
D1
1
D0
0
HEX
BE
1
↑
1
--
--
--
--
--
--
--
TEST_M
ODE(0)
TEST_O
E(0)
--
1
↑
1
--
PROB[7:0]
--
This command is used to set which group of signals to be observed
Description
Restrictions
Register
Availability
Default
PROBE[7:0]: Internal use
TEST_MODE: Internal use
TEST_OE: Internal use
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
PROBE[7:0]=8’h00, TEST_MODE =0, TEST_OE=0
PROBE[7:0]=8’h00, TEST_MODE =0, TEST_OE=0
PROBE[7:0]=8’h00, TEST_MODE =0, TEST_OE=0
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.190February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.15 SETPTBA: Set Power Option (BFh)
BF H
Command
st
1 parameter
nd
2
parameter
Description
Restrictions
SETPTBA ( Set Power Option)
DNC
0
1
NWR
↑
↑
NRD
1
1
D15-8
---
1
↑
1
--
D7
1
D6
0
D5
1
D4
D3
1
1
PTBA[15:8]
D2
1
D1
1
D0
1
HEX
BF
-
PTBA[7:0]
-
This command is used to set power circuit option
PTBA[15:0]: Internal use
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
PTBA[15:0]=16’h0000
PTBA[15:0]=16’h0000
PTBA[15:0]=16’h0000
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.191February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.16 SETSTBA: Set Source Option (C0h)
C0 H
Command
1st
parameter
2nd
parameter
rd
3
parameter
SETSTBA ( Set Source Option)
DNC
NWR
NRD
0
↑
1
D158
--
0
↑
1
--
1
↑
1
--
1
↑
1
--
D7
D6
D5
D4
D3
D2
D1
D0
HEX
1
1
0
0
0
0
0
C0
--
--
--
--
--
--
--
0
STB
A[8]
STBA[7:0]
VTESTSEL[3:0]
STESTOE[1:0]
---
--
--
--
This command is used to set source circuit option
Description
STBA[8:0]: Not open
VTESTSEL[3:0]: Not open
STESTOE: Not open
Restrictions
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Default
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
STBA[15:0]=16’h0149; VTESTSEL[3:0]=4’b0000;
Power On Sequence
STESTOE1=1’b0, STESTOE0=1’b0, GAOE=1’b0; GMA=1’b0;
TLADD[7:0]=8’b0000_0000
STBA[15:0]=16’h0149; VTESTSEL[3:0]=4’b0000;
S/W Reset
STESTOE1=1’b0, STESTOE0=1’b0, GAOE=1’b0; GMA=1’b0;
TLADD[7:0]=8’b0000_0000
STBA[15:0]=16’h0149; VTESTSEL[3:0]=4’b0000;
H/W Reset
STESTOE1=1’b0, STESTOE0=1’b0, GAOE=1’b0; GMA=1’b0;
TLADD[7:0]=8’b0000_0000
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.192February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.17 SETID: Set ID (C4h)
C4 H
Command
st
1
parameter
nd
2
parameter
rd
3
parameter
Description
Restrictions
SETID ( Set ID)
DNC
0
NWR
↑
NRD
1
D15-8
--
1
↑
1
--
1
↑
1
--
1
↑
1
--
D7
1
D6
1
D5
0
--
D4
0
D3
0
D2
1
D1
0
D0
0
HEX
C4
ID1[7:0]
--
ID2[6:0]
--
ID3[7:0]
--
This command is used to timing controller internal test
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
OTP value
No Change
OTP value
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.193February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.18 SETECO: Set ECO (C6h)
C6 H
Command
st
1
parameter
nd
2
parameter
Description
Restrictions
SETROMT ( Set ECO)
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
1
D5
0
D4
0
D3
0
1
↑
1
--
ECO0[7:0] (8'b0)
1
↑
1
--
ECO1[7:0] (8'b0)
D2
1
D1
1
D0
0
HEX
C6
This command is used for internal test
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Default
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.194February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.19 SETMREV: Set Free Running Mode (CAh)
CA H
Command
st
1
parameter
Description
Restrictions
SETMREV ( Set Free Running Mode)
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
1
D5
0
D4
0
D3
1
D2
0
D1
1
D0
0
HEX
CA
1
↑
1
--
--
--
--
--
--
--
SFULL
--
--
The command is internal use, not open.
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
SFULL=1’b0
SFULL=1’b0
SFULL=1’b0
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.195February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.20 SETIOOPT: Set IO_OPT (CBh)
CB H
Command
st
1
parameter
nd
2
parameter
Description
Restrictions
SETIOOPT ( Set IO_OPT)
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
1
D5
0
D4
0
D3
1
1
↑
1
--
IO_OPT[7:0]
1
↑
1
--
IO_OPT2[7:0]
D2
0
D1
1
D0
1
HEX
CB
--
This command is used for internal test
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
IO_OPT[7:0]=8b’01010101
IO_OPT[7:0]=8b’01010101
IO_OPT[7:0]=8b’01010101
Flow Chart
6.4.21 SETPANEL: Set PANEL (CCh)
CC H
Command
st
1
parameter
Description
Restrictions
SETPANEL ( Set PANEL)
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
1
D5
0
D4
0
D3
1
D2
1
D1
0
D0
0
HEX
CC
1
↑
1
--
--
--
--
SM_PA
NEL
SS_P
ANEL
--
--
--
--
Compensate for Panel type, layout and color filter order.
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
SM_PANEL=0, SS_PANEL=0,
SM_PANEL=0, SS_PANEL=0,
SM_PANEL=0, SS_PANEL=0,
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.196February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.22 GETOSC: Read Internal Oscillator (E0h)
E0 H
Command
st
1
parameter
nd
2
parameter
rd
3
parameter
GETOSC( Read Internal oscillator setting)
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
HEX
E0
xx
1
↑
--
--
--
--
--
--
--
--
--
--
1
1
↑
--
CADJ[3:0]
--
--
1
1
↑
--
--
--
th
4
parameter
Description
Restrictions
Register
Availability
1
1
↑
--
--
--
OSC_
EN_C
ON(0)
--
--
RADJ[2:0]
--
OSC_
EN(0)
--
This command is used to read internal oscillator related setting
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
Default
--
UADJ[2:0]
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
OSC_TEST=0; OSC_EN=0, CADJ[3:0]=OTP value,
RADJ=OTP value, UADJ[2:0]=3’b011.
OSC_EN=0h, if OPT is programmed, CADJ[3:0] =OTP
value, RADJ=OTP value, else no change
OSC_TEST=0; OSC_EN=0, CADJ[3:0] =OTP value,
RADJ=OTP value, UADJ[2:0]=3’b011
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.197February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.23 GETPOWER: Read Power (E1h)
E1 H
Command
st
1 parameter
nd
2
parameter
rd
3
parameter
th
4
parameter
th
5
parameter
th
6
parameter
th
7
parameter
th
8
parameter
th
9
parameter
th
10
parameter
Description
Restrictions
Register
Availability
GETPOWER( Read power related setting)
DNC
0
1
NWR
↑
1
NRD
1
↑
D7
1
--
D6
1
--
D5
1
--
D4
0
--
D3
0
--
D2
0
--
D1
0
--
D0
1
--
HEX
E1
--
1
1
↑
GASENB
--
--
PON
DK
--
--
STB
--
1
1
↑
--
--
--
--
--
AP[2:0]
--
1
1
↑
--
--
VC1[2:0]
--
1
1
↑
--
1
1
↑
1
1
↑
1
1
↑
N_DC[7:0]
--
1
1
↑
E_DC[7:0]
--
1
1
↑
--
--
--
BT[3:0]
--
--
--
--
FS1[1:0]
--
--
VRH[3:0]
--
--
--
--
--
--
--
--
--
FS0[1:0]
--
---
DCCLK_
SYNC
This command is used to read power related register.
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
PON=1’b0, DK=1’b0, STB=1’b0, AP[2:0]=3’b000, VR2[2:0]=3’b000, V
RH[3:0]=4’b0000, BT[3:0]=4’b0000, VDV[4:0]=5’b00000, VCM[5:0]=6’
b000000, FS0[1:0]=2’b00, FS1[1:0]=2’b00, DC[7:0]=8’b00000000
PON=1’b0, DK=1’b0, STB=1’b0, AP[2:0]=3’b000, VR2[2:0]=3’b000, V
RH[3:0]=4’b0000, BT[3:0]=4’b0000, VDV[4:0]=5’b00000, VCM[5:0]=6’
b000000, FS0[1:0]=2’b00, FS1[1:0]=2’b00, DC[7:0]=8’b00000000
PON=1’b0, DK=1’b0, STB=1’b0, AP[2:0]=3’b000, VR2[2:0]=3’b000, V
RH[3:0]=4’b0000, BT[3:0]=4’b0000, VDV[4:0]=5’b00000, VCM[5:0]=6’
b000000, FS0[1:0]=2’b00, FS1[1:0]=2’b00, DC[7:0]=8’b00000000
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.198February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.24 GETDISP: Read Display Related Register (E2h)
E2 H
Command
st
1
parameter
nd
2 paramete
r
rd
3
parameter
th
4
parameter
th
5
parameter
th
6
parameter
th
7
parameter
th
8
parameter
th
9
parameter
th
10
parameter
GETDISP( Read display related register)
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
1
D0
0
HEX
E2
1
1
↑
--
--
--
--
--
--
--
--
--
--
1
1
↑
--
GON
DTE
--
--
--
1
1
↑
--
--
--
--
--
N_BP[3:0]
--
1
1
↑
--
--
--
--
--
N_FP[3:0]
--
1
1
↑
--
SAP[7:0]
--
1
1
↑
--
EQS[7:0]
--
1
1
↑
--
EQP[7:0]
--
1
1
↑
--
--
--
--
1
1
↑
--
--
--
PTG[1:0]
1
1
↑
--
1
1
↑
--
PT[1:0]
D[1:0]
--
GEN_OFF[3:0]
--
ISC[3:0]
--
SAP_I[7:0]
--
th
11
parameter
Description
Restrictions
Register
Availability
--
--
--
--
--
--
TION
_DIS
P(0)
This command is used to read display related register
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
Default
--
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
D1-0=2’b00, GON=0, DTE=0, PT[1:0]=2’b00, P[3:0]=4’b1000,
BP[3:0]=4’b1000, ISC[3:0]=4’b000, SAP[7:0]=8’h04, SAP2[7:0]=8’h04,
PTG[1:0]=2’b00
D1-0=2’b00, GON=0, DTE=0, PT[1:0]=No change, FP[3:0]=No change,
BP[3:0]= No change, ISC[3:0]= No change, SAP[7:0]= No change,
SAP2[7:0]= No change, PTG[1:0]= No change
D1-0=2’b00, GON=0, DTE=0, PT[1:0]=2’b00, FP[3:0]=4’b1000,
BP[3:0]=4’b1000, ISC[3:0]=4’b000, SAP[7:0]=8’h04, SAP2[7:0]=8’h04,
PTG[1:0]=2’b00
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.199February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.25 GETLUT: ReadLUT Enable Related Register (E3h)
E3 H
Command
st
1
parameter
nd
2
parameter
Description
Restrictions
GETRGBIF( Read RGB interface related register)
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
1
D0
1
HEX
E3
1
1
↑
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
LUT_
ENB
This command is used to read RGB interface related register
1
1
↑
--
--
--
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
LUT_EN=OTP value,
LUT_EN= No change ,
LUT_EN=OTP value,
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.200February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.26 GETCYC: Read Display Waveform Cycle(E4h)
E4H
Command
st
1 paramet
er
nd
2 paramet
er
th
3 paramet
er
th
4 paramet
er
th
5 paramet
er
th
6 paramet
er
th
7 paramet
er
Description
Restrictions
Register
Availability
GETCYC( Read display waveform cycles)
DNC
NWR NRD D15-8
D7
D6
↑
0
1
-1
1
D4
0
D3
0
D2
1
D1
0
D0
0
HEX
E47
--
--
--
--
--
--
--
1
1
↑
--
1
1
↑
--
N_RTN[3:0]
--
N_NW[2:0]
--
1
1
↑
--
E_RTN[3:0]
--
E_NW[2:0]
--
1
1
↑
--
1
1
↑
--
SON[7:0]
--
1
1
↑
--
GDON[7:0]
--
1
1
↑
--
GDOF[7:0]
--
--
--
--
--
DIV_E[1:0]
--
--
--
--
--
This command is used to read display waveform cycles
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
Default
D5
1
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
NW[3:0]=4’b0000, RTN[3:0]=4’b0000, DIV_N[1:0]=2’b00,
DIV_PE=2’b00, DIV_E=2’b00, SON[7:0]=8’h00, GON[7:0]=8’h00
NW[3:0]=No change, RTN[3:0]= No change, DIV_N[1:0]= No change,
SON [7:0]= No change, GON [7:0]= No change, GOF [7:0]= No change
NW[3:0]=4’b0000, RTN[3:0]=4’b0000, DIV[1:0]=2’b00, DIV_PE=2’b00,
DIV_E=2’b00, SON[7:0]=8’h00, GON[7:0]=8’h00
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.201February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.27 GETBGP: Read BGP Voltage Setting (E5h)
E5 H
Command
1st
parameter
nd
2
parameter
Description
Restrictions
GETBGP( Get BandGap Voltage Setting)
DNC NWR NRD D15-8
D7
D6
↑
0
1
-1
1
D5
1
D4
0
D3
0
D2
1
D1
0
D0
1
HEX
E5
--
--
--
--
--
1
1
↑
--
--
--
--
--
1
1
↑
--
--
--
--
--
BGP[3:0]
--
This command is used to read BandGap Voltage setting
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
BGP[3:0]=OTP value
BGP[3:0]=No Change
BGP[3:0]= OTP value
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.202February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.28 GETVCOM: Read VCOM Voltage Setting (E6h)
E6 H
Command
st
1
parameter
nd
2
parameter
rd
3
parameter
th
4
parameter
Description
Restrictions
Register
Availability
GETVCOM( Read VCOM Voltage)
DN
NWR NRD D15-8
D7
C
↑
0
1
-1
D6
D5
D4
D3
D2
D1
D0
HEX
1
1
0
0
1
1
0
E6
1
1
↑
--
--
--
--
--
--
--
--
--
--
1
1
↑
--
VCO
MG
--
--
--
--
--
--
--
--
1
1
↑
--
--
1
1
↑
--
--
--
VDV[4:0]
--
This command is used to read VCOM Low and VCOM High Voltage setting
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
Default
VCMN[6:0]
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
VCOMG=1’b0, VDV[4:0]= OTP value, VCMN[5:0]= OTP value,
VCME[5:0]= OTP value, VCMPE[5:0]= OTP value
VCOMG=1’b0, VDV[4:0]= OTP value, VCMN[5:0]= OTP value,
VCME[5:0]= OTP value, VCMPE[5:0]= OTP value
VCOMG=1’b0, VDV[4:0]= OTP value, VCMN[5:0]= OTP value,
VCME[5:0]= OTP value, VCMPE[5:0]= OTP value
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.203February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.29 GETGAMMA: Read Gamma Curve Related Setting (E7h)
E7 H
Command
1st parameter
2nd
parameter
3rd
parameter
4th
parameter
5th
parameter
6th
parameter
7th
parameter
8th
parameter
9th
parameter
10th
parameter
11th
parameter
12th
parameter
13th
parameter
14th
parameter
15th
parameter
16th
parameter
17th
parameter
18th
parameter
19th
parameter
20th
parameter
Description
Restrictions
GETGAMMA1( Read Gamma Curve1 Related Setting)
DNC
0
1
NWR
↑
1
NRD
1
↑
D15-8
---
D7
1
--
D6
1
--
D5
1
--
D4
0
--
D3
0
--
D2
1
--
D1
1
--
D0
1
--
HEX
E7
--
1
1
↑
--
--
MP12
MP11
MP10
--
MP02
MP01
MP00
--
1
1
↑
--
--
MP32
MP31
MP30
--
MP22
MP21
MP20
--
1
1
↑
--
--
MP52
MP51
MP50
--
MP42
MP41
MP40
--
1
1
↑
--
--
--
--
--
CP03
CP02
CP01
CP00
--
1
1
↑
--
CP23
CP22
CP21
CP20
CP13
CP12
CP11
CP10
--
1
1
↑
--
--
--
--
--
CP33
CP32
CP31
CP30
--
1
1
↑
--
--
--
--
--
CP43
CP42
CP41
CP40
--
1
1
↑
--
--
--
--
--
OP03
OP02
OP01
OP00
--
1
1
↑
--
--
--
--
OP14
OP13
OP12
OP11
OP10
1
1
↑
--
--
--
--
--
1
1
↑
--
--
MN12
MN11
MN10
--
MN02
MN01
MN00
--
1
1
↑
--
--
MN32
MN31
MN30
--
MN22
MN21
MN20
--
1
1
↑
--
--
MN52
MN51
MN50
--
MN42
MN41
MN40
--
1
1
↑
--
--
--
--
--
CN03
CN02
CN01
CN00
1
1
↑
--
CN23
CN22
CN21
CN20
CN13
CN12
CN11
CN10
1
1
↑
--
--
--
--
--
CN33
CN32
CN31
CN30
1
1
↑
--
--
--
--
--
CN43
CN42
CN41
CN40
1
1
↑
--
--
--
--
--
ON03
ON02
ON01
ON00
1
1
↑
--
--
--
--
ON14
ON13
ON12
ON11
ON10
Default
CGM0[1:0]
--
This command is used to read Gamma Curve Related Setting
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Register
Availability
CGM1[1:0]
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Default Value
Power On Sequence
OTP value
S/W Reset
No change
H/W Reset
OTP value
Availability
Yes
Yes
Yes
Yes
Yes
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.204February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.30 GETOTP: Read OTP Related Setting (EBh)
EB H
Command
1st
parameter
2nd
parameter
3rd
parameter
4th
parameter
5th
parameter
6th
parameter
Description
Restrictions
Register
Availability
GETOTP( Read OTP Related Setting)
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
1
D5
1
D4
0
D3
1
D2
0
D1
1
D0
1
HEX
EB
1
1
↑
--
--
--
--
--
--
--
--
--
--
1
1
↑
--
OTP_MASK[7:0]
--
1
1
↑
--
OTP_INDEX[7:0]
---
1
1
↑
--
OTP_LO
AD_DIS
ABLE
DCCLK
_DISA
BLE
OTP
_PO
R
OTP_
PWE-
1
1
↑
--
--
--
--
--
1
1
↑
--
OTPES
T_EN
OTP_PTM[1:0]
VPP_
SEL
OTP_
PROG
---
OTP_VRADJ[1:0]
---
OTP_DATA[7:0]
This command is used to set OTP Related Setting
OTP_MASK7~OTP_MASK0: Bit programming mask, if 1, means don’t programming this bit
OTP_INDEX7~OTP_INDEX0: Set location of OTP to be programmed
OTP_EN: When written to 1, internal register begin written to OTP
VPP_SEL: When written to 1, PVSS voltage is fed to OTP
OTP_LOAD_DISABLE: When written to 1, auto load from OTP to internal register when SLPOUT
command received is disabled, this is used when OTP is not yet programmed
DCCLK_DISABLE: Disable Pumping Clock
OTPEST_EN:
0 : normal mode, automatical OTP programming mode (by internal state machine)
1 : manual mode
0 is the default value
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
Default
OTP_
PTM
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
OTP_MASK[7:0]=8’h00, OTP_INDEX[7:0]=8’hff, OTP_LOAD_DISABLE=0,
DCCLK_DISABLE=0, VPP_SEL=0, OTP_PROG=0, OTPEST_EN=0,
OTP_EN=0, OTP_PTM[1:0]=2’b00, OTP_VRADJ[1:0] =2’b00
OTP_MASK[7:0]=8’h00, OTP_INDEX[7:0]=8’hff, OTP_LOAD_DISABLE=0,
DCCLK_DISABLE=0, VPP_SEL=0, OTP_PROG=0, OTPEST_EN=0,
OTP_EN=0, OTP_PTM[1:0]=2’b00, OTP_VRADJ[1:0] =2’b00
OTP_MASK[7:0]=8’h00, OTP_INDEX[7:0]=8’hff, OTP_LOAD_DISABLE=0,
DCCLK_DISABLE=0, VPP_SEL=0, OTP_PROG=0, OTPEST_EN=0,
OTP_EN=0, OTP_PTM[1:0]=2’b00, OTP_VRADJ[1:0] =2’b00
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.205February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.31 GETVDC: Read Internal Digital Voltage Setting (ECh)
EC H
Command
1st
parameter
2nd
parameter
Description
Restrictions
GETVDC( Read internal digital voltage)
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
1
D5
1
D4
0
D3
1
D2
1
D1
0
D0
0
HEX
EC
1
1
↑
--
--
--
--
--
--
--
--
--
--
1
1
↑
--
--
--
--
--
--
VDC_SEL[2:0]
--
This command is used to read internal digital voltage setting
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
VDC_SEL[1:0]=2’b00
VDC_SEL[1:0]=2’b00
VDC_SEL[1:0]=2’b00
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.206February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.32 GETSPULSE: Read Arbiter Pulse Width (EDh)
ED H
Command
st
1 parameter
nd
2 parameter
Description
Restrictions
Register
Availability
GETSPULSE( Get Arbiter Pulse Width)
DN
C
0
NRD
NWR
D7
D6
D5
1
↑
1
1
1
1
1
↑
↑
D4
D3
D2
D1
D0
HEX
0
1
1
0
1
ED
RTBA[13:8]
RTBA[7:0]
This command is used to get GRAM arbiter pulse width, it is for internal use.
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
1
1
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
Default
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
SPULSE_ERD[2:0]=3’b011, SPULSE_EWR[2:0]=3’b001,
SPULSE_IRD[2:0]=3’b011, ARBMODE_SEL=0, LPLW_EN =0,
REFBL_EN[1:0]=2’b00 RPULSE [2:0]=3’b011, DPULSE [2:0]=3’b001
S/W Reset
No change
H/W Reset
SPULSE_ERD[2:0]=3’b011, SPULSE_EWR[2:0]=3’b001,
SPULSE_IRD[2:0]=3’b011, ARBMODE_SEL=0, LPLW_EN =0,
REFBL_EN[1:0]=2’b00, RPULSE [2:0]=3’b011, DPULSE [2:0]=3’b001
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.207February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.33 GETPROBE: Read Probe Signal Group (EEh)
EE H
Command
1st
parameter
2nd
parameter
3rd
parameter
Description
Restrictions
GETPROBE ( Read Probe Signal Group)
DNC
NWR
NRD
D15-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
--
1
1
1
0
1
1
1
0
EE
1
1
↑
--
--
--
--
--
--
--
--
--
--
1
1
↑
--
--
--
--
--
--
--
TEST_
MODE
TEST_
OE
--
1
1
↑
--
PROB[7:0]
--
This command is used to read which group of signals to be observed
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
PROBE[7:0]=8’h00, TEST_MODE=1’b0, TEST_OE=1’b0
PROBE[7:0]=8’h00, TEST_MODE=1’b0, TEST_OE=1’b0
PROBE[7:0]=8’h00, TEST_MODE=1’b0, TEST_OE=1’b0
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.208February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.34 GETPTBA: Read Power Option (EFh)
EF H
Command
1st
parameter
2nd
parameter
3rd
parameter
Description
Restrictions
GETPTBA ( Read Power Option)
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
1
D5
1
D4
0
D3
1
D2
1
D1
1
D0
1
HEX
EF
1
1
↑
--
--
--
--
--
--
--
--
--
--
1
1
↑
--
PTBA[15:8]
--
1
1
↑
--
PTBA[7:0]
--
This command is used to read power circuit option setting
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
PTBA[15:0]=16’h0000;
PTBA[15:0]=16’h0000;
PTBA[15:0]=16’h0000;
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.209February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.35 GETSTBA: Read Source Option (F0h)
F0 H
Command
1st parameter
2nd parameter
3rd parameter
4th parameter
Description
Restrictions
Register
Availability
GETSTBA ( Read Source Option)
DNC NWR NRD D15-8
D7
↑
0
1
-1
↑
1
1
--1
↑
--
1
1
↑
--
1
1
↑
--
1
D5
1
--
D4
1
--
D3
0
--
D2
0
--
D1
0
--
D0
0
--
HEX
F0
--
STBA
[8]
--
STBA[7:0]
VTESTSEL[3:0]
--
STESTOE[1:0]
--
This command is used to read source circuit option setting
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Power On Sequence
Default
D6
1
--
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
STBA[15:0]=16’h0081; VTESTSEL[3:0]=4’b0000; STESTOE1=1’b0,
STESTOE0=1’b0, GAOE=1’b0; GMA=1’b0;
STBA[15:0]=16’h0081; VTESTSEL[3:0]=4’b0000; STESTOE1=1’b0,
STESTOE0=1’b0, GAOE=1’b0; GMA=1’b0;
STBA[15:0]=16’h0081; VTESTSEL[3:0]=4’b0000; STESTOE1=1’b0,
STESTOE0=1’b0, GAOE=1’b0; GMA=1’b0;
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.210February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.36 GETPFUSE: Get Internal OTP (F1h)
F1 H
Command
1st
parameter
Description
Restrictions
Register
Availability
Default
GETPFUSE ( Set internal Efuse)
DNC
NWR
NRD
0
↑
1
D158
--
1
↑
1
--
D7
D6
D5
D4
D3
D2
D1
D0
HEX
1
1
1
1
0
0
0
1
F1
-
-
-
-
-
-
-
PFUSE
This command is used to set source circuit option
PFUSE: Internal use for OTP programming. This pad is only for internal use, not open.
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Default Value
Power On Sequence
PFUSE=0
PFUSE=0
S/W Reset
PFUSE=0
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.211February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.37 GETHXID: Read Himax ID (F4h)
F4 H
Command
1st
parameter
2nd
parameter
3rd
parameter
4rd
parameter
Description
Restrictions
GETHXID ( Read)
DNC NWR NRD
↑
0
1
D15-8
--
D7
1
D6
1
D5
1
D4
1
D3
0
D2
1
D1
0
D0
0
HEX
F4
--
--
--
--
--
--
--
--
--
1
1
↑
--
1
1
↑
--
ID_version[7:0](8’h53)
1
1
↑
--
ID2_version [7:0](0Ch)
1
1
↑
--
VersionID[7:0](00h)
--
--
It is for internal use, not open.
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Default Value
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.212February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.38 GETECO: Read ECO(F6h)
F6H
Command
1st
parameter
2nd
parameter
3rd
parameter
Description
Restrictions
GETECO ( Read )
DNC NWR NRD
↑
0
1
D15-8
--
D7
1
D6
1
D5
1
D4
1
D3
0
D2
1
D1
1
D0
0
HEX
F6
--
--
--
--
--
--
--
--
--
1
1
↑
--
1
1
↑
--
ECO0[7:0]
--
1
1
↑
--
ECO1[7:0]
--
It is for internal use, not open.
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Default Value
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.213February, 2008
HX8353-C
162RGB x 132 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.39 GETMREV: Get Free Running Mode (FAh)
FA H
Command
1st
parameter
2nd
parameter
Description
Restrictions
GETMREV ( Get Free Running Mode)
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
1
D5
1
D4
1
D3
1
D2
0
D1
1
D0
0
HEX
FA
1
1
↑
--
--
--
--
--
--
--
--
--
--
1
1
↑
--
--
--
--
--
--
--
SFULL
--
--
It is for internal use, not open.
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Default Value
SFULL=0
SFULL=0
SFULL=0
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.214February, 2008
HX8353-C(N)
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4.40 GETIOOPT: Get IO_OPT (FBh)
FB H
Command
1st
parameter
2nd
parameter
3rd
parameter
Description
Restrictions
GETIOOPT ( Get IO_OPT)
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
1
D5
0
D4
0
D3
1
D2
0
D1
1
D0
1
HEX
FB
1
1
↑
--
--
--
--
--
--
--
--
--
--
1
1
↑
--
IO_OPT[7:0](0101_0101)
1
1
↑
--
IO_OPT2[7:0] (0000_0000)
--
It is for internal use, not open.
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Default Value
IO_OPT[7:0]=8b’00000000
IO_OPT[7:0]=8b’00000000
IO_OPT[7:0]=8b’00000000
Flow Chart
6.4.41 GETPANEL: Get PANEL (FCh)
FC H
SETPANEL ( Set PANEL)
Command
DNC
0
NWR
↑
NRD
1
D15-8
--
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
0
D0
0
HEX
FC
1
1
↑
--
--
--
--
--
--
--
--
--
--
1
1
↑
--
--
--
--
SM_PA
NEL
SS_PA
NEL
--
--
--
--
1st
parameter
2nd
parameter
Description
Restrictions
Compensate for Panel type, layout and color filter order.
If EXTC is high or enable PASSWDEN command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Default Value
SM_PANEL=0, SS_PANEL=0,
SM_PANEL=0, SS_PANEL=0,
SM_PANEL=0, SS_PANEL=0,
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.215February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
7. Electrical Characteristic
7.1 Absolute Maximum Ratings
Item
Symbol
Value
Supply voltage 1
VDD
- 0.3 ~ + 3.7
Supply voltage 2
VDDI
- 0.3 ~ + 3.7
Drive Supply Voltage
VGH – VGL
- 0.3 ~ + 32.0
Input voltage range
VIN
- 0.3 ~ VDDI + 0.3
Output voltage range
VO
- 0.3 ~ VDDI+ 0.3
Operating temperature range
TOPR
- 40 ~ + 85
Storage temperature range
TSTG
- 55 ~ + 125
Table 7. 1 Absolute Maximum Ratings
(VSS = 0V)
Unit
V
V
V
V
V
°C
°C
7.2 ESD Protection Level
Mode
Human Body Model
Machine Model
Test Condition
Protection Level
C=100 pF, R=1.5kΩ
> 3000
C=200 pF, R=0.0Ω
> 300
Table 7. 2 ESD Protection Level
Unit
V
V
7.3 Maximum Series Resistance
Name
Type
VDD
VDDI
VSSA
VSSD
OSC
EXTC
P68, BS2, BS1, BS0
STE_SEL, GC_SEL, SPI_SEL
RSO0, RSO1, RSO2
LC_SEL0, LC_SEL1, BURN
NRESET, NCS, DNC_SCL
NWR_RNW, NRD_E
TEST[3:1], VDC_ENB
SS_PANEL, GS_PANEL, REV_PANEL,
BGR_PANEL
DUMMYR1,DummyR2,
DB0_SDA, DB17 ~ DB1
VGH
VGL
C11A, C11B
C22A, C22B
C21A, C21B
VDDD
VLCD
VCL
TE
VCOMH, VCOML
VREGIOUT
VREF
VTESTOUT
VCOM
Power supply
Power supply
Power supply
Power supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Maximum Series
Resistance
10
10
10
10
100
100
100
100
100
100
100
100
100
Input
100
Ω
100
100
10
10
10
10
10
20
10
10
100
50
50
50
50
50
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Input
Input / Output
Capacitor connection
Capacitor connection
Capacitor connection
Capacitor connection
Capacitor connection
Capacitor connection
Capacitor connection
Capacitor connection
Output
Output
Output
Output
Output
Output
Table 7. 3
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
Unit
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
-P.216February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
7.4 DC Characteristics
7.4.1 DC Characteristics List
Parameter
Symbol
Power & Operating Voltages
IO Operating voltage
VDDI
Analog & Logic Operating
VDD,VDDI
voltage
Source Drive Voltage
VS
Gate Drive High Voltage
VGH
Drive Supply Voltage
VGH-VGL
Input / Output
High level input voltage
VIH
Low level input voltage
VIL
High level output voltage
VOH
Low level output voltage
VOL
Input leakage current
IIL
Conditions
Related Pins
-
VDDI
-
(2)
VDD,VDDI
Min.
Typ.
Max.
1.65
1.8
1.95
2.3
2.5/2.75
2.9
3.0
9.0
15.0
4.5
14.0
27.0
5.0
16.
30
0.7VDDI
VSSA
0.8VDDI
VSSA
-1.0
-
VDDI
0.3VDDI
VDDI
0.2VDDI
+1.0
(2)
(3)
-
VS
(3)
VGH
(3)
VGH, VGL
IOH = -1.0mA
IOL = +1.0mA
VIN = VDDI or VSSA
Note
(1),(2)
Note
DB17 to DB0,
(2)
TE, TEST1
(1),(2)
Note
(1),(2)
Unit
V
V
µA
Note: (1) OSC, P68, BS1, BS0, NRESET, DNC_SCL, NWR_RNW, NRD_E, and DB17 to DB0 pins
(2), (3) When the measurement are performed with LCD module, Measurement Points are like below
Measurement point for *3)
FPC
Measurement point for *2)
LCD Panel
Connector pin or flex side
Table 7. 4 DC Characteristics 1
Parameter
VCOM Generator
Symbol
VCOM amplitude
VCOMA
VCOM output high
resistance
VCOM output low
resistance
Source Driver
RVCOMH
RVCOML
Gray scale resistance
(1),(2)
Rgray
IVOSH
Drive output current
IVOSL
Conditions
No load
VCOM output = High
IVCOM = 1mA
VCOM output = Low
IVCOM = 1mA
Rap~Rjp, Ran~Rjn,
R0~R62 of gray voltage
generator
VS=4.25V, VSO=V0 at
positive, VOUT=V0-2V
VS=4.25V, VSO=V0 at
negative, VOUT=V0-2V
VSSD+1.0 ~ VS-1.0
VSSD+0.1V ~ VSSD+1.0
VS-1.0 ~ VS-0.1V
Related Pins
Min.
Typ.
Max.
Unit
2.5
--
5
V
VCOM
-
100
-
VCOM
-
100
-
S1 to S396
0.7*Rx
Rx
1.3*Rx
Ω
S1 to S396
-
-200
-100
µA
S1 to S396
100
200
-
µA
S1 to 396
-
±10
±20
mV
S1 to 396
-
±30
±50
mV
0.1
-
VS-0.1
V
-
2
3
kΩ
VCOMH
VCOML
Ω
Output voltage deviation
DVOS
Output voltage range
Gate Driver
(3)
Output ON resistance
VOS
-
S1 to 396
RONG
Ta = 25°C
G1 to G162
Note: (1) VSO is the output voltage of source output pins S1 to S396.
(2) VOUT is the applied voltage to source output pins S1 to S396.
(3) Resistance value when -0.1[mA] is applied during the ON status of the gate output pin G0 to G160.
RON [ ] = V [V] / 0.1[mA] ( V: Voltage change when –0.1[mA] is applied in the on status.)
Table 7. 5 DC Characteristics 2
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.217February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
7.4.2 Current Consumption
Host
I/F
Mode of
operation
Host interface NOT active
- Normal Mode On
- Partial Mode Off
- Idle Mode Off
- Sleep Out Mode
- Normal Mode On
- Partial Mode Off
- Idle Mode On
- Sleep Out Mode
- Normal Mode Off
- Partial Mode On
(32 lines)
- Idle Mode Off
- Sleep Out Mode
- Normal Mode Off
- Partial Mode On
(32 lines)
- Idle Mode On
- Sleep Out Mode
- Sleep In Mode
Frame
Frequency
Inversion
Mode
Image
Memory Data
Access
Control
(MY:MX:MV)
60Hz
TBD
TBD
TBD
TBD
TBD
Note(1)
Note(2)
Note(3)
Note(4)
Note(5)
X;X;X
X;X;X
X;X;X
X;X;X
X;X;X
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
60Hz
TBD
Note(5)
X;X;X
TBD
TBD
TBD
TBD
60Hz
TBD
Grey
Levels
X;X;X
TBD
TBD
TBD
TBD
TBD
Note(6)
X;X;X
TBD
TBD
TBD
TBD
TBD
Note(7)
X;X;X
TBD
TBD
TBD
TBD
N/A
N/A
X;X;X
0;0;0
0;0;1
0;1;0
0;1;1
1;0;0
1;0;1
1;1;0
1;1;1
0;0;0
0;0;1
0;1;0
0;1;1
1;0;0
1;0;1
1;1;0
1;1;1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
60Hz
N/A
Host interface active
262k Colors(8)
CPU Access
@ 15fps
- Normal Mode On
- Partial Mode Off
- Idle Mode Off
- Sleep Out Mode
Current consumption
Typical
Worst case
VDD
VDDI
VDD
VDDI
(mA)
(mA)
(mA)
(mA)
60Hz
TBD
262k Colors(8)
CPU Access
@ 25fps
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Typical Case:
TA = 25oC
Note: X Do not care
VDD2 = 2.75V
(1) All pixels black
VDD1 = 1.8V
(2) Checker board one by one
(3) Checker board 4 by 4
Worst Case:
(4) Grey-scale from top to bottom
TA = -30 to70oC
(5) 20% Black, 80%White
VDD2 = 2.5V to 2.9V
(6) Black & White Checker board 8 by 8.
VDD1 = 1.65V to 2.5V
(7) Absolute Worst Case Patterns: Defined by Display Supplier
Includes Process Variance.
(8) Absolute Worst Case Patterns and Sequences: Defined by Display Supplier
(9) Absolute worst case VDD current is less than TBD mA in the case of CPU access is inactive, Normal Mode On,
Partial Mode Off, Idle Mode Off, Sleep Out mode.
(10) Absolute worst case VDDI current is less than TBD mA in the case of CPU access is inactive, Normal Mode
On, Partial Mode Off, Idle Mode Off, Sleep Out mode.
(11) Inrush currents are not included in current consumption values
Table 7. 6 Current Consumption
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.218February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
7.5 AC CHARACTERISTICS
7.5.1 Parallel Interface Characteristics (8080-series MPU)
tCHW
tCHW
VIH
V IL
NCS
t CS
t CSH
t CSF
VIH
VIL
DNC_RS_SCL
t AHT
tAST
tWC
t WRL
VIH
V IL
NWR_RNW
tWRH
t AHT
tRCS/tRCSFM
tRC/tRCFM
t CSF
tRDL/tRDLFM
V IH
NRD_E
t DST
DB17~DB0
VIH
V IL
tRDH/tRDHFM
V IL
tRAT/tTRATFM
t DHT
V IH
VIL
t ODH
VOH
VOL
VOH
VOL
Figure 7. 1 Parallel Interface characteristics (8080-series MPU)
(VSSA=0V, VDDI=1.65V to 2.50V, VDD=2.3V to 2.9V,Ta = -30 to 70°C)
Signal
DNC_RS_SCL
NCS
NWR_RNW
NRD_E (ID)
NRD_E (FM)
DB17 to DB0
Symbol
tAST
tAHT
tCHW
tCS
tRCS
tRCSFM
tCSF
tWC
tWRH
tWRL
tRC
tRDH
tRDL
tRCFM
tRDHFM
tRDLFM
tDST
tDHT
tRAT
tRATFM
tODH
Parameter
Address setup time
Address hold time (Write/Read)
Chip select “H” pulse width
Chip select setup time (Write)
Chip select setup time (Read ID)
Chip select setup time (Read FM)
Chip select wait time (Write/Read)
Write cycle
Control pulse “H” duration
Control pulse “L” duration
Read cycle (ID)
Control pulse “H” duration (ID)
Control pulse “L” duration (ID)
Read cycle (FM)
Control pulse “H” duration (FM)
Control pulse “L” duration (FM)
Data setup time
Data hold time
Read access time (ID)
Read access time (FM)
Output disable time
Min.
0
10
0
15
45
355
10
66
15
15
160
90
45
450
90
355
10
10
20
Max.
40
340
80
Unit
Description
ns
-
ns
-
ns
-
ns
When read ID data
ns
When read from frame
memory
ns
For maximum CL=30pF
For minimum CL=8pF
Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals.
Input Signal Slope
tr
VIH=0.7*VDDI
VIL=0.3*VDDI
Output Signal Slope
tf
tr
tf
VOH=0.8*VDDI
VOL=0.2*VDDI
Table 7. 7 Parallel Interface characteristics (8080-series MPU)
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.219February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Figure 7. 2 Chip select timing
Figure 7. 3 Write to read and read to write timing
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.220February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
7.5.2 Serial Interface Characteristics
Figure 7. 4 Serial Interface Characteristics
(VSSA=0V, VDDI=1.65V to 2.50V, VDD=2.5V to 2.9V,Ta = -30 to 70°C)
Parameter
Serial clock cycle (Write)
SCL ”H” pulse width (Write)
SCL ”L” pulse width (Write)
Data setup time (Write)
Data hold time (Write)
Serial clock cycle (Read)
SCL ”H” pulse width (Read)
SCL ”L” pulse width (Read)
Symbol
tSCYCW
tSHW
tSLW
tSDS
tSDH
tSCYCR
tSHR
tSLR
Access Time
tACC
Output disable time
tOH
NCS “H” pulse width
NCS-SCL time (write)
NCS-SCL time (write)
NCS-SCL time (Read)
NCS-SCL time (Read)
tCHW
tCSS
tCSH
tCSS
tCSH
Conditions
SCL
SDA
SCL
Min.
66
15
15
10
10
150
60
60
Typ.
-
Max.
-
Unit
10
-
50
ns
15
-
50
ns
40
15
15
60
65
-
-
ns
SDA For maximum
CL=30pF
For maximum CL=8pF
SDA For maximum
CL=30pF
For maximum CL=8pF
NCS
NCS
NCS
ns
ns
ns
ns
ns
Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals. For output, see Section 7.7.6.2
Input Signal Slope
Output Signal Slope
tr
tf
VIH=0.7*VDDI
VIL=0.3*VDDI
tr
tf
VOH=0.8*VDDI
VOL=0.2*VDDI
Table 7. 8 Serial Interface Characteristics
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.221February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
7.5.3 Reset Input Timing
Shorter than 5μs
tRESW
NRESET
tREST
Internal Status
Normal Operation
Initial Condition
(Default for H/W reset)
Resetting
Figure 7. 5 Reset input timing
Symbol
tRESW
tREST
Parameter
(1)
Reset low pulse width
(2)
Related Pins
NRESET
-
Min.
10
Typ.
-
Max.
-
-
-
5
-
120
Reset complete time
-
Note
Unit
µs
When reset applied during
Sleep In mode
When reset applied during
Sleep Out mode
ms
ms
Note: (1) Spike due to an electrostatic discharge on NRESET line does not cause irregular system reset according to the table below.
NRESET Pulse
Shorter than 5µ s
Longer than 10µ s
Between 5 µ s and 10µ s
Action
Reset Rejected
Reset
Reset Start
(2) During the resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms,
when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In –mode) and then return to Default condition
for H/W reset.
(3) During Reset Complete Time, ID2 value in OTP will be latched to internal register during this period. This loading is done every time
when there is H/W reset complete time (tREST) within 5ms after a rising edge of NRESET.
(4) Spike Rejection also applies during a valid reset pulse as shown below:
(5) It is necessary to wait 5msec after releasing NRESET before sending commands. Also Sleep Out command cannot be sent for
120msec.
Table 7. 9
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.222February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
7.5.4 Measurement Conditions
7.5.4.1 tRATFM, tODH Measurement Condition
Measurement Condition Set-up
Oscilloscope
See “NOTE”
Data Generator
Connector
LCD Panel
FPC
External components for test condition
(pull-down and pull-up cases) which are
removed after test:
Resistor: 3kOhm ± 5%
Capacitor: 8 or 30pF ± 10%
Connector Pin / Measurement Point
See “NOTE”
Note: Capacitances and resistances of the oscilloscope’s probe must be included externals components in these
Measurements
Figure 7. 6
Minimum Value Measurement
70%
NRD_E
tODH
DB(n) [n=0..17]
(pulled up)
0%
100%
DB(n) [n=0..17]
(pulled down)
Measurement circuit pulled down
Measurement circuit pulled up
VCC
External components
on the connector pin
3kOhm
DB(n) [n=0..17]
(pulled down)
Measurement point on
the connector pin
3kOhm
8pF
External
components on
the connector pin
DB(n) [n=0..17]
(pulled up)
Measurement point on
the connector pin
8pF
Figure 7. 7
Himax Confidential
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-P.223February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Maximum Value Measurement
70%
NRD_E
30%
tODH
DB(n) [n=0..17]
(pulled up)
20%
0%
100%
80%
DB(n) [n=0..17]
(pulled down)
Measurement circuit pulled up
Measurement circuit pulled down
VCC
External components
on the connector pin
3kOhm
DB(n) [n=0..17]
(pulled down)
Measurement point on
the connector pin
External
components on
the connector pin
DB(n) [n=0..17]
(pulled up)
3kOhm
30pF
Measurement point on
the connector pin
30pF
Figure 7. 8
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.224February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
7.5.4.2 tACC, tOH Measurement Condition
Measurement Condition Set-up
Oscilloscope
See “NOTE”
Data Generator
Connector
LCD Panel
FPC
External components for test condition
(pull-down and pull-up cases) which are
removed after test:
Resistor: 3kOhm ± 5%
Capacitor: 8 or 30pF ± 10%
Connector Pin / Measurement Point
See “NOTE”
Note: Capacitances and resistances of the oscilloscope’s probe must be included externals components in these
Measurements
Figure 7. 9
Minimum Value Measurement
Figure 7. 10
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.225February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Maximum Value Measurement
70%
NRD_E
t OH
t ACC
DB0
(pulled up)
20%
DB0
(pulled down)
0%
100%
80%
Measurement circuit pulled up
Measurement circuit pulled down
VCC
External components
on the connector pin
3kOhm
External
components on
the connector pin
DB0(DOUT)
DB0 (DOUT)
Measurement point on
the connector pin
3kOhm
30pF
Measurement point on
the connector pin
30pF
Figure 7. 11
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-P.226February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8. Reference Application
8.1 Example Connection with Panel
(0,0)
Frame Memory
(1, 1)
132 x 162 Panel Viewing Area
(131,161)
GODD - - - G1
S1 --- - - - S396
G2 - - - GEVEN
HX8353-C Bumps Down
Bumps Down
IC
LCD (Front Side)
GLASS
BACK LIGHT
Bumps up
LCD (Front Side)
GLASS
IC
Figure 8. 1
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-P.227February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2 Connection Example with External Components
VDDI
VDD
VDDI
VDD
VLCD
C11A
C11B
C22A
C22B
C21A
C21B
VDDD
C1 = 1.0 uF~ 2.2 uF(Typical:1uF )
C2 = 1.0 uF~ 2.2uF(Typical:2.2uF)
C2
C2
C1
C1
C1
VGH
VCL
C1
C1
VGL
C1
VCOMH
VCOML
VSSA
Note1: C22 option : VGH and VGL can share the same pump capacitor when operate
on special pumping condition  VGH<4xVDD, VGL>-3xVDD (On this condition, C22
can be removed).
Note2: If need to remove capacitor of VDDD connection : when VDDI = 1.65~1.95v,
VDDD can connect to VDDI on FPC directly
Figure 8. 2 Example connection with external components
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-P.228February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.3 External Components
Pad Name
VGL
VCL
VDDD
VGH
C21A, C21B
C22A, C22B
C11A, C11B
VLCD
VDD
VSSD
VDDI
VSSD
Typical
capacitance value
Connection
Connect to Capacitor (Max 16V): VGL ---(-)----| |--- (+)----- VSSA
Connect to Capacitor (Max 5V): VCL ---(-)----| |--- (+)----- VSSA
Connect to Capacitor (Max 5V): VDDD ---(+)----| |--- (-)----- VSSA
Connect to Capacitor (Max 21V): VGH ---(+)----| |--- (-)----- VSSA
Connect to Capacitor (Max 7V): C21A ---(+)----| |--- (-)-----C21B
Connect to Capacitor (Max 7V): C22A,---(+)----| |--- (-)----C22B
Connect to Capacitor (Max 5V): C11A ---(+)----| |--- (-)-----C11B
Connect to Capacitor (Max 6V): VLCD ---(+)----| |--- (-)-----VSSA
VDD (Analogue Power)
Connect to VSSD
VDDI (Digital Power)
VSSA (Ground)
Table 8. 1 Example capacitor connection
Pins connection
Recommended voltage
VDD, VDDI, VCL, C11A/B, VDDD
6V
VLCD, C21A/B, C22A/B,
VGH, VGL
10V
25V
1.0µF
1.0µF
1.0µF
1.0µF
1.0µF
1.0µF
2.2µF
1.0µF
Optional
Optional
-
Capacity
1 µFor 2.2uF
(B characteristics)
1 µF
1 µF
Table 8. 2 Adoptability of Capacitor
Reusable
> 200 kΩ
Pins to connect
VcomR
Table 8. 3 Adoptability of Variable resistor
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in whole or in part without prior written permission of Himax.
-P.229February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
9. Layout Recommedacation
TBD
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in whole or in part without prior written permission of Himax.
-P.230February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
10. Ordering Information
Part No.
HX8353-C000PDxxx
Package
TBD.
11. Revision History
Version
Date
2008/02/25
2008/4/17
2008/4/21
2008/4/22
2008/4/25
01
2008/4/29
2008/4/30
2008/5/07
Description of Changes
New setup
1. Modify the 8.2 Connection Example with External
Components (page 231)
2. Modify the 7.3 Maximum Series Resistance (page
219)
3. Mody the setting of VC1[2:0] and BT[3:0] (page
171 and page 172)
1. Modify the 7.3 Maximum Series Resistance (page
219)
2. Add the voltage range of VCOMH, VCOML
(page10)
1. Modify the 4.5 Bump arrangement (page 22)
2. Modify the seal-ing =15um * 2 (page 16)
1. Modify the Pin Coordinate,add description of input
and output pin (page 18~21)
2. Modify the Bump arrangement,add pin number of
input and output pin (page 23)
1. Modify Fig.5.53 BT[2:0] to BT[3:0] (page 85)
2. Modify table5.33 Master clock Frequency 10M to
1.5M (page 113)
3. Modify B2H(ISC) fFLM =70Hz to fFLM =60Hz (page
176)
4. Modify B4H(RTN,clock cycles perline) (page 179)
5. Modify address and resolution unmatch
5.3.1 SA,ML=1(page 52)
5.3.2 SA,RA(page 53)
5.3.6 SA,RA(page 57)
5.3.7 SA,RA(page 58)
6. Modify Alignment mark A1 and A2
(page17,page21)
7. Modify table 6.2 E7 and 6.4.29 E7 parameter
(page 121, page206)
1. Add description of input PIN (page 13 ,page 14)
2. Add description of BURN (page15)
1. Modify VRH[3:0] setting (page 171, page 172)
2. Modify “Serial interface”(5.12) , when SPI_SEL
pin high is 4 wire (page 40)
3. Modify Fig5.55 (page 86)
4. Modify Fig5.57 gamma stream,Table5.22, Table
5.23 and Table5.24 (page 90, page91)
5. Add 2nd parametet of C6h(page118, page196)
6. Modify register of B2h and E2h (page 175, page
201)
7. Remove bit5 function in B5h,E5h(page 181,page
204)
8. Remove E8h and F5h(page 199)
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-P.231February, 2008
HX8353-C
132RGB x 162 dot, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
9. Modify parameter4 of E0h
10. Modify table6.2 (page117~page122)
2008/5/16
1. Modify 8.1Example Connection with Panel(page
228)
2. Modify “Voltage Calculation Formula”,
SumRP(SumRN)=124+… .(page 92)
2008/5/20
1. Modify “Page top” 132RGBx162 dot
2008/5/21
1. 5.18 OTP Programming, in note2 ”,… . NAVILD bit
will be changed to 1 “ (page 106)
2. Programming seruence step9,modify “Specify
OTP_index” read and write (page 109)
3. Modify B9H and BAH flow chart (page 186 and
page187)
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in whole or in part without prior written permission of Himax.
-P.232February, 2008