NT7605 - NewHaven Display

NT7605
Single-chip 20C X 2L Dot-Matrix LCD Controller / Driver
Features
! 2 kinds of LCD pads sequence
! Character Generator ROM (CG ROM):
2 kinds of CG ROM sizes:
192 characters:
160 5 X 8 dot patterns
32 5 X 10 dot patterns
240 characters:
192 5 X 8 dot patterns
48 5 X 10 dot patterns
Custom CG ROM is also available
! Built-in power-on reset function
! Logic power supply: 2.8V ~ 5.5V
! LCD driver power supply: V1 ~ V5
divided by Built-in LCD power division resister.
! Two oscillator operations
(Freq. = 500KHz - 540KHz):
• Built-in RC oscillation
• External clock
! CMOS Process
! Available in COG FORM
! Internal LCD drivers
16 common signal drivers
100 segment signal drivers
! Maximum display dimensions
20 characters * 2 lines or
40 characters * 1 line
! Interfaces with 4-bit or 8-bit MPU
! Versatile display functions provided on chip:
Display Clear, Cursor Home, Display ON/OFF,
Cursor ON/OFF, Character Blinking, Cursor
Shift, and Display Shift
! Three duty factors, selected by PROGRAM:
1/8, 1/11, and 1/16
! Displays Data RAM (DD RAM): 80 X 8 bits
(Displays up to 80 characters)
! Character Generator RAM (CG RAM):
64 X 8 bits for general data,
8 5 X 8 programmable dot patterns, or
4 5 X 10 programmable dot patterns
! Low voltage reset
! ITO option for A-type and B-type LCD waveform
General Description
The NT7605 also contains Character Generator RAM where
the user can store 8 different character patterns at run time.
These memory features make the character display flexible.
NT7605 also provides many display instructions to achieve
versatile LCD display functions. The NT7605 is fabricated on
a single LSI chip using the CMOS process, resulting in very
low power requirements.
The NT7605 is a dot matrix LCD controller and driver LSI that
can operate with either a 4-bit or an 8-bit microprocessor
(MPU). NT7605 receives control character codes from the
MPU, stores them in an internal RAM (up to 80 characters),
transforms each character code into a 5 X 7, 5 X 8, or 5 X 10
dot matrix character pattern, and then displays the codes on
the LCD panel. The built-in Character Generator ROM
consists of 256 different character patterns.
1
V2.1
NT7605
Pad Configuration
5600µm
162
83
163
82
NT7605
1230µm
180
65
1
11
12 13
14
26
Item
Pad No.
Chip size
-
Pad pitch
1 - 180
27
29
30
38
39
44
Size
X
Y
1230
5600
65
2
45
64
Unit
µm
NT7605
Block Diagram
V1
V2
V3
V4
V5
OPT_UD
OPT_R0
OPT_R1
OPT_LCD
VDD
GND
8
OSC1
OSC2
INSTRUCTION
DECODE
TEST
TIMING
GENERATOR
7
8
INSTRUCTION
REGISTER
(IR)
ADDRESS
COUNTER
TESTM
LCD DRIVER
VOLTAGE
GENERATOR
7
RS
7
7
R/W
7
CURSOR
ADDRESS
COUNTER
E
7
DISPLAY
DATA
RAM
(DD RAM)
80 X 8 BITS
I/O
BUFFER
4
16
COMMON
SIGNAL
DRIVER
16
COM1
I
COM16
100-BIT
LATCH
CIRCUIT
100
SEGMENT
SIGNAL
DRIVER
100
SEG1
I
SEG100
8
8
DB7 ~ DB4
16-BIT
SHIFT
REGISTER
DATA
REGISTER
(DR)
DB3 ~ DB0
4
BUSY
FLAG
(BF)
8
CURSOR
/BLINK
CONTROLLER
8
7
CHARACTER
GENERATOR
RAM
(CG RAM)
64 X 8 BITS
CHARACTER
GENERATOR
ROM (CG ROM)
5
5
PARALLER - TO - SERIAL
CONVERTER
3
TESTD
NT7605
Pad Description (Total 180 pads for COG type)
Pad No.
Designation
I/O
External
Connection
1
TEST
I
Test pin
2
TESTM
O
Test output
3 - 11
GND
P
Power supply
12
OSC1
I
Description
Test pin internally pull-down. (No connect for user)
LCD driver clock output. (No connect for user)
GND: 0V
For external clock operation, clock inputs to OSC1
Clock output
13
OSC2
O
14, 15
V1
P
Power supply
Power supply for LCD driver. VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 ≥ GND
16, 17
V2
P
Power supply
Power supply for LCD driver
18, 19
V3
P
Power supply
Power supply for LCD driver
20, 21
V4
P
Power supply
Power supply for LCD driver
22 - 26
V5
P
Power supply
Power supply for LCD driver
27, 29
OPT_R0,
OPT_R1
I
ITO Option
30 - 38
VDD
P
Power supply
30, 40
RS
I
MPU
41, 42
R/W
I
MPU
43, 44
E
I
MPU
Read/Write start signal (Schmitt trigger input)
45, 46
DB0
47, 48
DB1
49, 50
DB2
I/O
MPU
Lower 4 tri-state bi-directional data bus for transmitting data
between MPU and NT7605. Not used during 4-bit operation
51, 52
DB3
53, 54
DB4
55, 56
DB5
57, 58
DB6
I/O
MPU
Higher 4 tri-state bi-directional data bus for transmitting data between
MPU and NT7605. DB7 is also used as busy flag
59, 60
DB7
61
OPT_LCD
I
ITO Option
63
OPT_UD
I
ITO Option
The built-in bias resister select:
OPT_R1, OPT_R0: No ITO = 1. ITO on = 0
1, 1:
2.2KΩ;
1, 0:
4KΩ;
0, 1:
6.8KΩ;
0, 0: No built-in bias resister:
VDD: +5V
Register select signal
0: Instruction register (write), Busy flag, address counter (read)
1: Data register (write, read)
Read/Write control signal
0: Write
1: Read
No ITO. (Option = 1): B-Type waveform
ITO On. (Option = 0): A-Type waveform
No ITO. (Option = 1): COM1→COM8→COM9→COM16;
SEG1→SEG100
ITO On. (Option = 0): COM9→COM16→COM1→ COM8;
SEG100→SEG1
64
TESTD
O
Test output
Test data output. (No connect for user)
180 - 173
COM1 - 8
O
LCD panel
65 - 72
COM9 - 16
O
LCD panel
Common signal output pins, for place on the upper glass
(OPT_UD=1)
65 - 72
COM1 - 8
O
LCD panel
180 - 173
COM9 - 16
O
LCD panel
Common signal output pins, for place on the lower glass
(OPT_UD=0)
172 - 73
SEG1 - 100
O
LCD panel
Segment signal output pins (OPT_UD = 1)
73 - 172
SEG1 - 100
O
LCD panel
Segment signal output pins (OPT_UD = 0)
28, 62
GND_OUT
P
GND output pin, use for pull-down ITO option
4
NT7605
Functional Description
1. 192 Characters:
The CG ROM contains 160 5 X 8 dot character patterns and
32 5 X 10 dot character patterns. The relation between the
character codes and character patterns is shown in Table 1.
The character codes from 00H to 0FH are used to get
character patterns from the CG RAM. The character codes
10H to 1FH, 80H to 9FH and 20H all map to null character
patterns. The character codes from E0H to FFH are
assigned to generate 5 X 10 dot character patterns, and
other codes are used to generate 5x8 dot character patterns.
The NT7605 is a dot-matrix LCD controller and driver LSI. It
operates with either a 4-bit or an 8-bit microprocessor (MPU).
The NT7605 receives both instructions and data from the
MPU. Some instructions set operation modes, such as the
function mode, data entry mode, and display mode; as well
as some control LCD display functions, such as clear display,
restore display, shift display as well as controlling the cursor.
Other instructions include reading and writing both data and
addresses. All the instructions allow users convenient and
powerful functions to control the LCD dot-matrix displays.
Data is written into and read from the Data Display RAM (DD
RAM) or the Character Generator RAM (CG RAM). As
display character codes, the data stored in the DD RAM
decodes a set of dot-matrix character patterns that are built
into the Character Generator ROM (CG ROM). The CG
ROM, with many character patterns (up to 256 patterns),
defines the character pattern fonts. The NT7605 regularly
scans the character patterns through the segment drivers.
The CG RAM stores character pattern fonts at run time if
users intend to show character patterns that are not defined
in the CG ROM. This feature makes character display
flexible. Other unused bytes can be used as general-purpose
data storage.
2. 240 Characters:
The CG ROM contains 192 5 X 8 dot character patterns and
48 5 X 10 dot character patterns. The relation between the
character codes and character patterns is shown in Table 2.
The character codes from 00H to 0FH are used to get
character patterns from the CG RAM. The character codes
from 10H to 1FH and from E0H to FFH are assigned to
generate 5 X 10 dot character patterns, and other codes to
generate 5 X 8 dot character patterns. Only one null
character pattern exists in this type. Note that the underlined
cursor, displayed on the 8th duty may be obscure if the 8th
row of a dot character pattern is coded. We recommend that
users display the cursor in the blinking mode if coding 5 X 8
dot character patterns is their custom CG ROM.
The LCD driver circuit consists of 16 common signal drivers
and 100 segment signal drivers allowing a variety of
application configurations to be implemented.
Custom
character
patterns
are
available
by
mask-programming the ROM. For convenience of character
pattern development, NOVATEK has developed a
user-friendly editor program for the NT7605 to help
determine the character patterns users prefer. By executing
the program on the computer, users can easily create and
modify their character patterns. By transferring the resulting
files generated by the program through a modem or some
other communication method, the user and NOVATEK can
establish a reliable, fast link for programming the CG ROM.
Character Generator ROM (CG ROM)
The character generator ROM generates LCD dot character
patterns from the 8-bit character pattern codes. The NT7605
provides 2 CG ROM configurations:
5
NT7605
Absolute Maximum Ratings*
*Comments
Power Supply Voltage (VDD) . . . . . . . . . . -0.3V to +7.0V
Power Supply Voltage (V1 to V5) . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VDD + 0.3V
Input Voltage (VI) . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
Operating Temperature (TOPR) . . . . . . .-20°C to +70°C
Storage Temperature (TSTG) . . . . . . . .-55°C to +125°C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those indicated
in the operational sections of this specification is not implied
or intended. Exposure to the absolute maximum rating
conditions for extended periods may affect device reliability.
! All voltage values are referenced to GND = 0V
! V1 to V5, must maintain VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 ≥ GND
DC Electrical Characteristics (VDD = 4.5V~5.5V, GND = 0V, TA = 25°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
-
VDD
V
0.2 VDD
V
Conditions
Applicable
Pin
VDD
Operating Voltage
VIH1
"H" Level Input Voltage
0.8 VDD
VIL1
"L" Level Input Voltage
-0.3
VOH1
"H" Level Output Voltage
VDD - 0.6
-
-
V
IOH = -1.2mA
DB0 - DB7
VOL1
"L" Level Output Voltage
-
-
GND + 0.6
V
IOL = 1.2mA
(CMOS)
VCOMD
Driver Voltage Descending (COM)
-
-
0.3
V
ID = 5µA
COM1 - 16
VSEGD
Driver Voltage Descending (SEG)
-
-
0.3
V
ID = 5µA
SEG1 - 100
IIL
Input Leakage Current
-1
-
1
µA
VIN = 0 to VDD
-IP
Pull-up MOS Current
50
125
250
µA
VDD = 5V
RS, R/W,
DB0 - DB7
mA
Rf oscillation,
from external
clock VDD = 5V,
fOSC = fCP =
540KHz,
include LCD bias
current
VDD
IOP
Power Supply Current
-
-
1
1.5
DB0 - DB7,
RS, R/W,
E, OSC1
External Clock Operation
fCP
External Clock Operating
Frequency
380
540
750
KHz
tDUTY
External Clock Duty Cycle
45
50
55
%
tRCP
External Clock Rise Time
0.1
-
0.5
µs
tFCP
External Clock Fall Time
0.1
-
0.5
µs
Internal Clock Operation (Built-in RC Oscillator)
fOSC
Oscillator Frequency
380
540
750
KHz
VLCD
LCD Driving Voltage
3.0
-
VDD
V
6
Rf = 50KΩ (reference only)
VDD = 2 .8V ~ 5.5V
VDD - V5
NT7605
DC Electrical Characteristics (continued) (VDD = 2.8V~4.5V, GND = 0V, TA = 25°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
2.8
3.0
4.5
V
Conditions
Applicable
Pin
VDD
Operating Voltage
VIH1
"H" Level Input Voltage
0.8 VDD
-
VDD
V
VIL1
"L" Level Input Voltage
-0.3
-
0.2 VDD
V
VOH1
"H" Level Output Voltage
VDD - 0.4
-
-
V
IOH = -0.8mA
DB0 - DB7
VOL1
"L" Level Output Voltage
-
-
GND + 0.4
V
IOL = 0.8mA
(CMOS)
VCOMD
Driver Voltage Descending (COM)
-
-
0.3
V
ID = 5µA
COM1 - 16
VSEGD
Driver Voltage Descending (SEG)
-
-
0.3
V
ID = 5µA
SEG1 - 100
IIL
Input Leakage Current
-1
-
1
µA
VIN = 0 to VDD
-IP
Pull-up MOS Current
30
75
150
µA
VDD = 3V
RS, R/W,
DB0 - DB7
Rf oscillation,
from external
clock VDD = 3V,
fOSC = fCP =
540KHz,
include LCD
bias current
VDD
IOP
Supply Current Power Supply
Current
-
1
1.5
mA
DB0 - DB7,
RS, R/W,
E, OSC1
External Clock Operation
fCP
External Clock Operating
Frequency
380
540
750
KHz
tDUTY
External Clock Duty Cycle
45
50
55
%
tRCP
External Clock Rise Time
0.1
-
0.5
µs
tFCP
External Clock Fall Time
0.1
-
0.5
µs
Internal Clock Operation (Built-in RC Oscillator)
fOSC
Oscillator Frequency
380
540
750
KHz
VLCD
LCD Driving Voltage
2.5
-
VDD
V
7
Rf = 50KΩ (reference only)
VDD = 2 .8V ~ 5.5V
VDD - V5
NT7605
AC Characteristics
Read Cycle (VDD = 4.5V~5.5V, GND = 0V, TA = 25°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
tCYCE
Enable Cycle Time
500
-
-
ns
Figure 1
tWHE
Enable "H" Level Pulse Width
300
-
-
ns
Figure 1
-
-
25
ns
Figure 1
-
-
ns
Figure 1
10
-
-
ns
Figure 1
-
-
190
ns
Figure 1
20
-
-
ns
Figure 1
Min.
Typ.
Max.
Unit
Conditions
tRE, tFE
Enable Rise/Fall Time
1
tAS
RS, R/W Setup Time
tAH
RS, R/W Address Hold Time
tRD
Read Data Output Delay
tDHR
Read Data Hold Time
60
2
100
Write Cycle (VDD = 4.5V~5.5V, GND = 0V, TA = 25°C)
Symbol
Parameter
tCYCE
Enable Cycle Time
500
-
-
ns
Figure 2
tWHE
Enable "H" Level Pulse Width
300
-
-
ns
Figure 2
-
-
25
ns
Figure 2
-
-
ns
Figure 2
tRE, tFE
Enable Rise/Fall Time
1
60
tAS
RS, R/W Setup Time
tAH
RS, R/W Address Hold Time
10
-
-
ns
Figure 2
tDS
Data Output Delay
100
-
-
ns
Figure 2
Data Hold Time
10
-
-
ns
Figure 2
tDHW
1002
Notes: 1: 8-bit operation mode
2: 4-bit operation mode
Power Supply Conditions Using Internal Reset Circuit
(VDD = 4.5V~5.5V, GND = 0V, TA = 25°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
tRON
Power Supply Rise Time
0.1
-
10
ms
Figure 3
tOFF
Power Supply OFF Time
1
-
-
ms
Figure 3
8
NT7605
AC Characteristics (continued)
Read Cycle (VDD = 2.8V~4.5V, GND = 0V, TA = 25°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
tCYCE
Enable Cycle Time
500
-
-
ns
Figure 1
tWHE
Enable "H" Level Pulse Width
300
-
-
ns
Figure 1
-
-
25
ns
Figure 1
-
-
ns
Figure 1
10
-
-
ns
Figure 1
-
-
190
ns
Figure 1
20
-
-
ns
Figure 1
Min.
Typ.
Max.
Unit
Conditions
tRE, tFE
Enable Rise/Fall Time
1
tAS
RS, R/W Setup Time
tAH
RS, R/W Address Hold Time
tRD
Read Data Output Delay
tDHR
Read Data Hold Time
60
2
100
Write Cycle (VDD = 2.8V~4.5V, GND = 0V, TA = 25°C)
Symbol
Parameter
tCYCE
Enable Cycle Time
500
-
-
ns
Figure 2
tWHE
Enable "H" Level Pulse Width
300
-
-
ns
Figure 2
-
-
25
ns
Figure 2
-
-
ns
Figure 2
tRE, tFE
Enable Rise/Fall Time
1
60
tAS
RS, R/W Setup Time
tAH
RS, R/W Address Hold Time
10
-
-
ns
Figure 2
tDS
Data Output Delay
150
-
-
ns
Figure 2
Data Hold Time
10
-
-
ns
Figure 2
tDHW
2
100
Notes: 1: 8-bit operation mode
2: 4-bit operation mode
Power Supply Conditions Using Internal Reset Circuit
(VDD = 2.8V~4.5V, GND = 0V, TA = 25°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
tRON
Power Supply Rise Time
0.1
-
10
ms
Figure 3
tOFF
Power Supply OFF Time
1
-
-
ms
Figure 3
9
NT7605
Timing Waveforms
Read Operation
VIH1
VIL1
tAS
RS
VIH1
VIL1
tAH
R/W
tWHE
VIH1
VIL1
E
tFE
VIL1
tDHR
tRE
tRD
VOH1
VOL1
DB0 ~ DB7
VIL1
VOH1
VOL1
VAILD DATA
tCYCE
Figure 1. Bus Read Operation Sequence
(Reading out data from NT7605 to MPU)
Write Operation
VIH1
VIL1
tAS
RS
R/W
VIH1
VIL1
tAH
VIL1
tWHE
tFE
VIH1
VIL1
E
VIL1
tDHW
tRE
tDS
VIH1
VIL1
DB0 ~ DB7
VAILD DATA
VIL1
VIH1
VIL1
tCYCE
Figure 2. Bus Write Operation Sequence
(Writing data from MPU to NT7605)
Interface Signals with Segment Driver LSI
4.5V
VDD
0.2V
0.1ms > tRON > 10ms
0.2V
0.2V
tOFF > 1ms
tRON
tOFF
Figure 3. tOFF stipulates the time of power off for instantaneous
Power supply to or when power supply repeats ON and OFF.
10
NT7605
Note 1: The NT7605 has two clock options:
A. Internal Oscillator (Built-in RC)
OSC1
OSC2
OPEN
OPEN
B. External Clock Operation
OSC1
OSC2
PULSE INPUT
OPEN
Note 2: Input/Output Terminals:
A. Input Terminal
Applicable Terminal: E (No Pull Up MOS)
VDD
PMOS
NMOS
Applicable Terminal: RS, R/W (with Pull Up MOS)
VDD
VDD
Pull Up MOS
PMOS
PMOS
NMOS
11
NT7605
B. Output Terminal
Applicable Terminal: TESTM
VDD
PMOS
NMOS
C. I/O Terminal
Applicable Terminal: DB0 to DB7
VDD
VDD
Pull Up MOS
PMOS
PMOS
VDD
ENABLE
PMOS
NMOS
DATA
NMOS
(OUTPUT CIRCUIT)
(TRISTATE)
Note 3: ITO Options:
Set Option = 0: Place ITO on the Option Pad.
Set Option = 1: No ITO on the Option Pad.
No ITO:
ITO On:
GND OUTPUT
PAD
GND_OUT
OPTION PAD
GND OUTPUT
PAD
OPTION
OPTION PAD
OPTION
GND_OUT
(Internal
pull up)
(Internal
pull up)
ITO
Option = 1
Option = 0
12
NT7605
Table 1. NT7605H-BDT01 Correspondence between Character Codes and Character Patterns
(NOVATEK Standard 192 Character CG ROM)
13
NT7605
Instruction Set
Code
Instruction
Function
Execution
time (max)
(fOSC =
540KHz)
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Display Clear
0
0
0
0
0
0
0
0
0
1
Display/
Cursor Home
0
0
0
0
0
0
0
0
1
*
Entry Mode
Set
0
0
0
0
0
0
0
1
I/D
S
Display
ON/OFF
0
0
0
0
0
0
1
D
C
B
Display/
Cursor Shift
0
0
0
0
0
1
S/C
R/L
*
*
Function Set
0
0
0
0
1
DL
N
F
*
*
RAM Address
Set
0
0
0
1
DD RAM
Address Set
0
0
1
ADD
0
1
BF
AC
Read Busy Flag (BF) and
contents of Address Counter
(AC)
1µs
1
0
Write data
Write data to CG RAM or DD
RAM
40µs
1
1
Read data
Read data from CG RAM or DD
RAM
40µs
Busy Flag/
Address
Counter
Read
CG RAM/
DD RAM
Data Write
CG RAM/
DD RAM
Data Read
I/D = 1 : Increment
S = 1 : Display Shift On
D = 1 : Display On
C = 1 : Cursor Display On
B = 1 : Cursor Blink On
S/C = 1 : Shift Display
R/L = 1 : Shift Right
DL = 1 : 8-Bit
N = 1 : Dual Line
F = 1 : 5x10 dots
BF = 1 : Internal Operation
BF = 0 : Ready for Instruction
ACG
Clear entire display area,
Restore display from shift, and
load address counter with DD
RAM address 00H
Restore display from shift and
load address counter with DD
RAM address 00H
Specify direction of cursor
movement and display shift
mode. This operation takes
place after each data transfer
(read/write)
Specify activation of display (D)
cursor (C) and blinking of
character at cursor position (B)
Shift display or move cursor
Set interface data length (DL),
number of the display line (N),
and character font (F)
Load the address counter with
a CG RAM address
Subsequent data access is for
CG RAM data
Load the address counter with
a DD RAM address
Subsequent data access is for
DD RAM data
I/D = 0 : Decrement
DD RAM : Display Data RAM
S/C
R/L
DL
N
F
= 0 : Move Cursor
= 0 : Shift Left
= 0 : 4-Bit
= 0 : Signal Line
= 0 : 5x8 dots
CG RAM : Character Generator
RAM
ACG :
Character Generator
RAM Address
ADD :
Display Data RAM
Address
AC :
Address Counter
Note 1: Symbol " * " signifies an insignificant bit (disregard).
Note 2: Correct input value for "N" is predetermined for each model.
Note 3: The variation of execution time depends on the change of oscillator frequency; for example:
if fOSC = 380KHz, then execution time = 40µs× (540KHz / 380KHz) = 57µs
14
1.64ms
1.64ms
40µs
40µs
40µs
40µs
40µs
40µs
NT7605
Interface to LCD
(1) Character Font and Number of Lines
The NT7605 provides a 5 X 7 dot character font 1-line mode, a 5 X 10 dot character font 1-line mode and a
5 X 7 dot character font 2-line mode, as shown in the table below.
Three types of common signals are available as displayed in the table. The number of lines and the font type can be selected by
the program.
Number of Lines
Character Font
Number of Common Signals
Duty Factor
Bias
1
5 X 7 dots + Cursor
(or 5 X 8 dots)
8
1/8
1/4
1
5 X 10 dots + Cursor
11
1/11
1/4
2
5 X 7 dots + Cursor
(or 5 X 8 dots)
16
1/16
1/5
(2) Connection to LCD
The following 4 LCD connection examples show the various combinations between characters and lines.
NT7605 can directly drive the following combinations:
(a) 5 X 8 Font – 20 characters X 1 line (1/8 duty cycle, 1/4 bias)
LCD PANEL
COM1
COM8
SEG1
NT7605
SEG100
15
NT7605
(b) 5 X 10 Font - 20 characters X 1 line (1/11 duty cycle, 1/4 bias)
LCD PANEL
COM1
COM8
SEG1
NT7605
SEG100
COM11
COM9
(c) 5 X 8 Font - 20 characters X 2 line (1/16 duty cycle, 1/5 bias)
LCD PANEL
COM1
COM8
NT7605
SEG1
SEG100
COM16
COM9
16
NT7605
(d) 5 X 8 Font - 40 characters X 1 line (1/16 duty cycle, 1/5bias)
LCD PANEL
COM1
COM8
SEG1
NT7605
SEG100
COM16
COM9
17
NT7605
(3) Orientation Type of NT7605:
C1, S1
Type1: Place the chip on the
upper glass(IC face up)
OPT_UD = 1 (NO ITO)
C8, S1
C1, S1
C8, S1
LCD PANEL
Type2: Place the chip on the
lower glass(IC face down)
OPT_UD = 0 ( ITO ON)
LCD PANEL
C9, S100
C9, S100
1
NT7605
C16, S100
Type3: Place the chip on the
lower glass(IC face down)
OPT_UD = 1 (NO ITO)
C1, S1
1
1
Type4: Place the chip on the
upper glass(IC face up)
OPT_UD = 0 ( ITO ON)
NT7605
C1, S1
C8, S1
NT7605
1
C8, S1
LCD PANEL
C9, S100
C16, S100
Note:
1. Dot line:
2. Dash line:
C16, S100
NT7605
ITO layout on lower glass.
ITO layout on upper glass.
18
LCD PANEL
C9, S100
C16, S100
NT7605
(3) Bias Power Connection
NT7605 provides 1/4 or 1/5 bias for various duty cycle applications. The built-in power division resister divide voltage is
described in the following table. The connection of NT7605, power supply, and resistors are also shown as follows:
Power Division
1/8, 1/11 Duty Cycle - 1/4 Bias
1/16 Duty Cycle - 1/5 Bias
V1
VDD - 1/4 VLCD
VDD - 1/5 VLCD
V2
VDD - 1/2 VLCD
VDD - 2/5 VLCD
V3
VDD - 1/2 VLCD
VDD - 3/5 VLCD
V4
VDD - 3/4 VLCD
VDD - 4/5 VLCD
V5
VDD - VLCD
VDD - VLCD
The bias is auto selected by the duty cycle. When the LCD is set to 1/16 duty, the bias is set to 1/5. Otherwise, the bias is set to
1/4.
The ITO Option can select the division resister value:
VDD
VDD
OPT_R1
OPT_R0
Division Resister
No ITO (1)
No ITO (1)
2.2KΩ
No ITO (1)
ITO On (0)
4KΩ
ITO On (0)
No ITO (1)
6.8KΩ
V4
No ITO (0)
No built-in resister
(external input)
V5
ITO On (0)
V1
NT7605 V2
VLCD
Built-in bias resister
2.2K, 4K or 6.8K ohm
V3
VR
GND
VDD
VDD
VDD
VDD
R
R
V1
V1
R
R
V2
V2
NT7605
NT7605
VLCD
V3
R
VLCD
V3
R
R
V4
V4
R
R
V5
V5
VR
VR
GND
GND
Exit Power division. (The resistance value depends on the LCD panel size)
19
NT7605
(4) LCD Waveform
A-type, 1/8 Duty Cycle, 1/4 Bias
800 CLOCKS
COM1
1
2
3
4
5
8
1
2
VDD
V1
V2 (V3)
V4
V5
1 Frame
1sec
1 Frame =
× 800 × 8 = 11.9ms
540K
Frame Frequency =
1
= 84 .3Hz
11 .9ms
A-type, 1/11 Duty Cycle, 1/4 Bias
800 CLOCKS
COM1
1
2
3
4
5
11
1
2
VDD
V1
V2 (V3)
V4
V5
1 Frame
1 Frame =
1sec
× 800 × 11 = 16.3ms
540K
Frame Frequency =
1
= 61.4Hz
16.3ms
A-type, 1/16 Duty Cycle, 1/5 Bias
400 CLOCKS
COM1
1
2
3
4
5
16
1
2
VDD
V1
V2
V3
V4
V5
1 Frame
1 Frame =
1sec
× 400 × 16 = 11.9ms
540K
Frame Frequency =
20
1
= 84.3Hz
11.9ms
NT7605
B-type, 1/8 Duty Cycle, 1/4 Bias
800 CLOCKS
COM1
1
2
3
4
5
6
7
8
9
16 1
2
VDD
V1
V2 (V3)
V4
V5
1 Frame
1sec
× 800 × 8 = 11.9ms
540K
1 Frame =
Frame Frequency =
1
= 84.3Hz
11.9ms
B-type, 1/11 Duty Cycle, 1/4 Bias
800 CLOCKS
COM1
1
2
3
4
5
6
7
8
9 10 11 12
21 22 1
2
VDD
V1
V2 (V3)
V4
V5
1 Frame
1Frame =
1sec
× 800 × 11 = 16.3ms
540K
Frame Frequency =
1
= 61.4Hz
16.3ms
B-type, 1/16 Duty Cycle, 1/5 Bias
400 CLOCKS
COM1
1
2
3
4
5
13 14 15 16 17
31 32 1
2
VDD
V1
V2
V3
V4
V5
1 Frame
1Frame =
1sec
× 400 ×16 = 11.9ms
540K
Frame Frequency =
21
1
= 84.3Hz
11.9ms
NT7605
Low Voltage Reset
The Low voltage reset function is used to monitor the supply voltage and applies an internal reset at the time when a low voltage
is detected.
Functions of the Low Voltage Reset Circuit
The Low voltage reset circuit has the following functions:
# Generates an internal reset signal when VDD ≤ VLVR.
# Cancels the internal reset signal when VDD > VLVR.
Here, VDD: power supply voltage, VLVR: Low voltage reset detection voltage, about 2.0V.
Application Circuit (for reference only)
VDD
LCD PANEL
COM1 ~ 16
NT7605
SEG1 ~ 100
DB0 ~ 7
MPU
E, R/W, RS
V5
VR
GND
22
NT7605
Example (for reference only)
Interface with 8-bit MPU
RS
R/W
E
Internal
signal
Internal operation
DB7
DATA
BUSY
BUSY
Instruction
NO
BUSY
DATA
Busy flag check
Instruction
Interface with 4-bit MPU
RS
R/W
E
Internal
signal
DB7
Internal operation
D7
Instruction
D3
BUSY
NO
BUSY
AC3
Busy flag check
23
AC3
D7
D3
Instruction
NT7605
Initializing by Instruction
1. 8-bit Interface
Power On
Wait for more than 30 ms
after VDD on
Function set
RS
RW
0
0
N
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
1
N
F
X
X
F
0
1-line mode
1
2-line mode
0
5 x 7 dots
1
5 x 10 dots
0
display off
1
display on
0
cursor off
1
cursor on
0
blink off
1
blink on
0
decrement mode
1
increment mode
0
entire shift off
1
entire shift on
Wait for more than 40 μs
D
Display ON/OFF Control
RS
RW
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
D
C
B
C
B
Wait for more than 40 μs
Clear Display
RS
RW
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
Wait for more than 1.64ms
Entry Mode Set
RS
RW
0
0
I/D
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
1
I/D
S
Initialization end
Write date to DDRAM: Write N
RS
RW
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
0
1
1
1
..........
24
0
S
NT7605
2. 4-bit Interface
Power On
Wait for more than 30 ms
after VDD on
Function set
RS
RW
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
0
X
X
X
X
0
0
0
0
1
0
X
X
X
X
0
0
N
F
X
X
X
X
X
X
N
F
0
1-line mode
1
2-line mode
0
5 x 7 dots
1
5 x 10 dots
0
display off
1
display on
0
cursor off
1
cursor on
0
blink off
1
blink on
0
decrement mode
1
increment mode
0
entire shift off
1
entire shift on
Wait for more than 40 μs
D
Display ON/OFF Control
RS
RW
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
X
X
X
X
0
0
1
D
C
B
X
X
X
X
C
B
Wait for more than 40 μs
Clear Display
RS
RW
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
X
X
X
X
0
0
0
0
0
1
X
X
X
X
Wait for more than 1.64ms
Entry Mode Set
I/D
RS
RW
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
X
X
X
X
0
0
0
0
I/D
S
X
X
X
X
S
Initialization end
Write date to DDRAM: Write N
RS
RW
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
0
X
X
X
X
1
0
1
1
1
0
X
X
X
X
..........
’
25
NT7605
Ordering Information
Part No.
CG ROM
Package
Shipment Style
NT7605H-BDB01
192 CGROM (ref P13)
COG CHIP FORM
Bumped Die on Blue tape
NT7605H-BDT01
192 CGROM (ref P13)
COG CHIP FORM
Bumped Die on chip Tray
NT7605-BDW01
192 CGROM (ref P13)
COG CHIP FORM
Bumped Die on Wafer
26
NT7605
Bonding Diagram
5600µm
162
83
163
82
Y
NT7605
1230µm
X
(0,0)
180
65
1
Pad No.
11
12 13
Designation
14
26
X
27
29
30
38
Y
Pad No.
39
44
45
64
Designation
X
Y
1
TEST
-2567.5
-546.25
31
VDD
-357.5
-546.25
2
TESTM
-2502.5
-546.25
32
VDD
-292.5
-546.25
3
GND
-2437.5
-546.25
33
VDD
-227.5
-546.25
4
GND
-2372.5
-546.25
34
VDD
-162.5
-546.25
5
GND
-2307.5
-546.25
35
VDD
-97.5
-546.25
6
GND
-2242.5
-546.25
36
VDD
-32.5
-546.25
7
GND
-2177.5
-546.25
37
VDD
32.5
-546.25
8
GND
-2112.5
-546.25
38
VDD
97.5
-546.25
9
GND
-2047.5
-546.25
39
RS
552.5
-546.25
10
GND
-1982.5
-546.25
40
RS
617.5
-546.25
11
GND
-1917.5
-546.25
41
RW
682.5
-546.25
12
OSC1
-1787.5
-546.25
42
RW
747.5
-546.25
13
OSC2
-1722.5
-546.25
43
E
812.5
-546.25
14
V1
-1592.5
-546.25
44
E
877.5
-546.25
15
V1
-1527.5
-546.25
45
DB0
1332.5
-546.25
16
V2
-1462.5
-546.25
46
DB0
1397.5
-546.25
17
V2
-1397.5
-546.25
47
DB1
1462.5
-546.25
18
V3
-1332.5
-546.25
48
DB1
1527.5
-546.25
19
V3
-1267.5
-546.25
49
DB2
1592.5
-546.25
20
V4
-1202.5
-546.25
50
DB2
1657.5
-546.25
21
V4
-1137.5
-546.25
51
DB3
1722.5
-546.25
22
V5
-1072.5
-546.25
52
DB3
1787.5
-546.25
23
V5
-1007.5
-546.25
53
DB4
1852.5
-546.25
24
V5
-942.5
-546.25
54
DB4
1917.5
-546.25
25
V5
-877.5
-546.25
55
DB5
1982.5
-546.25
26
V5
-812.5
-546.25
56
DB5
2047.5
-546.25
27
OPT_R0
-682.5
-546.25
57
DB6
2112.5
-546.25
28
GND_OUT
-617.5
-546.25
58
DB6
2177.5
-546.25
29
OPT_R1
-552.5
-546.25
59
DB7
2242.5
-546.25
30
VDD
-422.5
-546.25
60
DB7
2307.5
-546.25
27
NT7605
Bonding Diagram (continued)
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
61
OPT_LCD
2372.5
-546.25
101
SEG72
1397.5
546.25
62
GND_OUT
2437.5
-546.25
102
SEG71
1332.5
546.25
63
OPT_UD
2502.5
-546.25
103
SEG70
1267.5
546.25
64
TESTD
2567.5
-546.25
104
SEG69
1202.5
546.25
65
COM9
2731.5
-552.5
105
SEG68
1137.5
546.25
66
COM10
2731.5
-487.5
106
SEG67
1072.5
546.25
67
COM11
2731.5
-422.5
107
SEG66
1007.5
546.25
68
COM12
2731.5
-357.5
108
SEG65
942.5
546.25
69
COM13
2731.5
-292.5
109
SEG64
877.5
546.25
70
COM14
2731.5
-227.5
110
SEG63
812.5
546.25
71
COM15
2731.5
-162.5
111
SEG62
747.5
546.25
72
COM16
2731.5
-97.5
112
SEG61
682.5
546.25
73
SEG100
2731.5
-32.5
113
SEG60
617.5
546.25
74
SEG99
2731.5
32.5
114
SEG59
552.5
546.25
75
SEG98
2731.5
97.5
115
SEG58
487.5
546.25
76
SEG97
2731.5
162.5
116
SEG57
422.5
546.25
77
SEG96
2731.5
227.5
117
SEG56
357.5
546.25
78
SEG95
2731.5
292.5
118
SEG55
292.5
546.25
79
SEG94
2731.5
357.5
119
SEG54
227.5
546.25
80
SEG93
2731.5
422.5
120
SEG53
162.5
546.25
81
SEG92
2731.5
487.5
121
SEG52
97.5
546.25
82
SEG91
2731.5
552.5
122
SEG51
32.5
546.25
83
SEG90
2567.5
546.25
123
SEG50
-32.5
546.25
84
SEG89
2502.5
546.25
124
SEG49
-97.5
546.25
85
SEG88
2437.5
546.25
125
SEG48
-162.5
546.25
86
SEG87
2372.5
546.25
126
SEG47
-227.5
546.25
87
SEG86
2307.5
546.25
127
SEG46
-292.5
546.25
88
SEG85
2242.5
546.25
128
SEG45
-357.5
546.25
89
SEG84
2177.5
546.25
129
SEG44
-422.5
546.25
90
SEG83
2112.5
546.25
130
SEG43
-487.5
546.25
91
SEG82
2047.5
546.25
131
SEG42
-552.5
546.25
92
SEG81
1982.5
546.25
132
SEG41
-617.5
546.25
93
SEG80
1917.5
546.25
133
SEG40
-682.5
546.25
94
SEG79
1852.5
546.25
134
SEG39
-747.5
546.25
95
SEG78
1787.5
546.25
135
SEG38
-812.5
546.25
96
SEG77
1722.5
546.25
136
SEG37
-877.5
546.25
97
SEG76
1657.5
546.25
137
SEG36
-942.5
546.25
98
SEG75
1592.5
546.25
139
SEG35
-1007.5
546.25
99
SEG74
1527.5
546.25
139
SEG34
-1072.5
546.25
100
SEG73
1462.5
546.25
140
SEG33
-1137.5
546.25
28
NT7605
Bonding Diagram (continued)
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
141
SEG32
-1202.5
546.25
162
SEG11
-2567.5
546.25
142
SEG31
-1267.5
546.25
163
SEG10
-2731.5
552.5
143
SEG30
-1332.5
546.25
164
SEG9
-2731.5
487.5
144
SEG29
-1397.5
546.25
165
SEG8
-2731.5
422.5
145
SEG28
-1462.5
546.25
166
SEG7
-2731.5
357.5
146
SEG27
-1527.5
546.25
167
SEG6
-2731.5
292.5
147
SEG26
-1592.5
546.25
168
SEG5
-2731.5
227.5
148
SEG25
-1657.5
546.25
169
SEG4
-2731.5
162.5
149
SEG24
-1722.5
546.25
170
SEG3
-2731.5
97.5
150
SEG23
-1787.5
546.25
171
SEG2
-2731.5
32.5
151
SEG22
-1852.5
546.25
172
SEG1
-2731.5
-32.5
152
SEG21
-1917.5
546.25
173
COM8
-2731.5
-97.5
153
SEG20
-1982.5
546.25
174
COM7
-2731.5
-162.5
154
SEG19
-2047.5
546.25
175
COM6
-2731.5
-227.5
155
SEG18
-2112.5
546.25
176
COM5
-2731.5
-292.5
156
SEG17
-2177.5
546.25
177
COM4
-2731.5
-357.5
157
SEG16
-2242.5
546.25
178
COM3
-2731.5
-422.5
158
SEG15
-2307.5
546.25
179
COM2
-2731.5
-487.5
159
SEG14
-2372.5
546.25
180
COM1
-2731.5
-552.5
160
SEG13
-2437.5
546.25
ALK_L
-2230.95
95
161
SEG12
-2502.5
546.25
ALK_R
2230.95
95
29
NT7605
Package Information
Chip Outline Dimensions
unit: µm
A1
A1
A2
g
m
C1
g
f
g
m
r (Metal 2)
m
m
m
m
m
m
m
A2
A1
B1
B1
m
m
g
D
m
f
g
m
f
f
C1
m
r (Metal 2)
X
(0,0)
m
C2
E
Y
NT7605
D
f
A2
f
E
m
g
m
g
B1
B1
B2
C2
g
B2
Symbol
Dimensions in µm
Symbol
Dimensions in µm
A1
232.5
D
569.05
A2
164
E
520
B1
130
g
42
B2
455
f
90
C1
62.5
m
65
C2
68.75
r
35
30
A2
A1
NT7605
Tray Information
f
Y
e
H30-230*60-33
10*31
X
X
W1
W2
T2 T1
SECTION Y-Y
c
d
Y
g
h
W1
W2
g
a
b
e
f
h
T2
T1
SECTION X-X
Tray Outline Dimensions
unit: mm
Symbol
Dimensions in mm
Symbol
Dimensions in mm
a
1.54
g
0.84
b
2.12
h
4.20
c
5.84
W1
76.0
d
6.14
W2
68.0
e
1.60
T1
71.0
f
1.40
T2
68.3
31
NT7605
Product Spec. Change Notice
NT7605 Specification Revision History
Version
2.1
Content
Adding Note 3 and modified fosc from 270KHz to 540KHz
(Page 14 , Document mistake corrected)
Modify the number of clock in single duty from 400 to 800 (1/8
duty and 1/11 duty),200 to 400(1/16 duty) and fosc from 270K
to 540K(Page 21) ( Document mistake corrected)
Date
Jul.2002
ROM Table deleted(Page 14)
2.0
B-type waveform modified(Page 21 , Document mistake
corrected)
Apr.2002
1.0
Add new orientation type of NT7605 (page 19)
Correct 4-bit interface Initializing sample. (page 26)
VDD conditions in Electrical Characteristics changed.(page
6~9)
Add more description for OPT_UD option. (page 4)
Nov.2001
0.4
Original
Feb.2001
32