NTE74175 Integrated Circuit TTL − Quad D−Type Flip−Flop with Clear Description: The NTE74175 is a monolithic, positive−edge−triggered flip−flop in a 16−Lead plastic DIP type package that utilizes TTL circuitry to implement D−type flip−flop logic. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive−going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive−going pulse. When the clock input is at either the high or low level, the D input signal ha no effect at the output. Features: D Contains Four Flip−Flops with Double Rail Outputs D Buffered Clock and Direct Clear Inputs D Individual Data Input to Each Flip−Flop Applications: D Buffer/Storage Register D Shift Register D Pattern Generator Absolute Maximum Ratings: (Note 1) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V DC Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38mW Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 05C to +705C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −655C to +1505C Note 1. Unless otherwise specified, all voltages are referenced to GND. Recommended Operating Conditions: Parameter Symbol Min Typ Max Unit Supply Voltage VCC 4.75 5.0 5.25 V High−Level Output Current IOH − − −800 =A Low−Level Output Current IOL − − 16 mA fclock 0 − 25 MHz Width of Clock or Clear Pulse tw 20 − − ns Setup Time Data Input tsu 20 − − ns 25 − − ns Clock Frequency Clear Inactive State Data Hold Time th 5 − − ns Operating Temperature Range TA 0 − +70 5C Min Typ Max Unit Electrical Characteristics: (Note 2, Note 3) Parameter Symbol Test Conditions High−Level Input Voltage VIH 2 − − V Low−Level Input Voltage VIL − − 0.8 V Input Clamp Voltage VIK VCC = MIN, II = −12mA − − −1.5 V High Level Output Voltage VOH VCC = MIN, VIH = 2V, VIL = 0.8V, IOH = −800=A 2.4 3.4 − V Low Level Output Voltage VOL VCC = MIN, VIH = 2V, VIL = 0.8V, IOL = 16mA − 0.2 0.4 V Input Current II VCC = MAX, VI = 5.5V − − 1 mA High Level Input Current IIH VCC = MAX, VI = 2.4V − − 40 =A Low Level Input Current IIL VCC = MAX, VI = 0.4V − − −1.6 mA Short−Circuit Output Current IOS VCC = MAX, Note 4 −18 − −57 mA Supply Current ICC VCC = MAX, Note 5 − 30 45 mA Note 2. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended Operation Conditions”. Note 3. All typical values are at VCC = 5V, TA = +255C. Note 4. Not more than one output should be shorted at a time. Note 5. With all outputs open and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V is applied to clock. Switching Characteristics: (VCC = 5V, TA = +255C unless otherwise specified) Parameter Maximum Clock Frequency Propagation Delay Time, from Clear Input Propagation Delay Time, from Clock Input Symbol fmax Min Typ Max Unit 25 35 − MHz − 16 25 ns tPHL − 23 35 ns tPLH − 20 30 ns tPHL − 24 35 ns tPLH Test Conditions RL = 4005 , CL = 15pF Function Table (Each Flip−Flop): Inputs Outputs Clear Clock D Q Q L X X L H H = H H L H = L L H H L X Qo Qo H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Irrelevant = = Transition from LOW to HIGH Level Q0 = The level of Q before the indicated steady state input conditions were established Pin Connection Diagram CLR 1 16 VCC 1Q 2 1Q 3 15 4Q 14 4Q 1D 4 13 4D 2D 5 12 3D 2Q 6 11 3Q 10 3Q 2Q 7 GND 8 9 CLK 16 9 1 8 .870 (22.0) Max .260 (6.6) Max .200 (5.08) Max .100 (2.54) .700 (17.78) .099 (2.5) Min