datasheet: pdf

NTE74221
Integrated Circuit
TTL − Dual Monostable Multivibrator
Description:
The NTE74221 is a monolithic dual multivibrator in a 16−Lead plastic DIP type package with performance characteristics virtually identical to those of the NTE74121. Each multivibrator features a negative−transition−triggered input and a positive−transition−triggered input either of which can be used
as an inhibit input.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of
the input pulse. Schmitt−trigger input circuitry (TTL hysteresis) for B input allows jitter−free triggering
from inputs with transition rates as slow as 1 volt/second, providing the circuit with excellent noise
immunity of typically 1.2 volts. A high immunity to VCC noise of typically 1.5V is also provided by internal latching circuitry.
Once fired, the outputs are independent o further transitions of the A an B inputs and are a function of the
timing components, or the output pulses can be terminated by the overriding clear. Input pulses may be of
any duration relative to the output pulse. Output pulse length may be varied from 35ns to the maximum pulse
length of 70 seconds by choosing appropriate timing components. With Rext = 2k and Cext = 0, and output
pulse of typically 30ns is achieved which may be used as a DC triggered reset signal. Output rise and fall
times are TTL compatible and independent of pulse length.
Pulse width stability is achieved through internal compensation and is virtually independent of VCC
and temperature. In most applications, pulse stability will only be limited by the accuracy of external
timing components.
Jitter−free operation is maintained over the full temperature and VCC ranges for more than six decades
of timing capacitance (10pF to 10F) and more than one decade of timing resistance (2k to
40k).Throughout these ranges, pulse width is defined by the relationship: tw(out) = CextRext In2 [ 0.7
CextRext. In circuits where the pulse cutoff is not critical, timing capacitance up to 1000F and timing resistance as low as 1.4k may be used. Also, the range of jitter−free output pulse widths is extended if VCC
is held to 5V and free−air temperature is +25C. Duty cycles as high as 90% are achieved when using
maximum recommended RT. Higher duty cycles are available if a certain amount of pulse−width jitter is
allowed.
Features:
D Overriding Clear Terminates Output Pulse
Recommended Operating Conditions:
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
4.75
5.0
5.25
V
High−Level Output Current
IOH
−
−
−800
A
Low−Level Output Current
IOL
−
−
16
mA
dv/dt
1
−
−
V/s
1
−
−
V/s
Rate of Rise or Fall of Input Pulse
Schmitt, B
Logic Input, A
Input Pulse Width
A or B
tw(in)
50
−
−
ns
Clear
tw(clear)
20
−
−
ns
tsu
15
−
−
ns
External Timing Resistance
Rext
1.4
−
40
k
External Timing Capacitance
Cext
0
−
1000
F
RT = 2k
−
−
67
%
RT = MAX Rext
−
−
90
%
0
−
+70
C
Min
Typ
Max
Unit
−
1.4
2.0
V
Clear Inactive−State Setup Time
Output Duty Cycle
Operating Temperature Range
TA
Electrical Characteristics: (Note 1, Note 2)
Parameter
Symbol
Threshold Voltage at A Input
VT+
Threshold Voltage at B Input
VT+
Test Conditions
VCC = MIN
VT−
VCC = MIN
VT−
0.8
1.4
−
V
−
1.55
2.0
V
0.8
1.35
−
V
−
−
−1.5
V
2.4
3.4
−
V
Input Clamp Voltage
VIK
VCC = MIN, II = −12mA
High Level Output Voltage
VOH
VCC = MIN, IOH = −800A
Low Level Output Voltage
VOL
VCC = MIN, IOL = 16mA
−
0.2
0.4
V
Input Current
II
VCC = MAX, VI = 5.5V
−
−
1
mA
High Level Input Current
IIH
VCC = MAX, VI = 2.4V
Input A
−
−
40
A
Input B, Clear
−
−
80
A
Input A
−
−
−1.6
mA
Input B, Clear
−
−
−3.2
mA
−18
−
−55
mA
Quiescent
−
26
50
mA
Triggered
−
46
80
mA
Low Level Input Current
IIL
VCC = MAX, VI = 0.4V
Short−Circuit Output Current
IOS
VCC = MAX, Note 3
Supply Current
ICC
VCC = MAX
Note 1. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended
Operation Conditions”.
Note 2. All typical values are at VCC = 5V, TA = +25C.
Note 3. Not more than one output should be shorted at a time.
Switching Characteristics: (VCC = 5V, TA = +25C unless otherwise specified)
Parameter
Propagation Delay Time
(From A Input to Q Output)
Symbol
tPLH
Propagation Delay Time
(From B Input to Q Output)
Test Conditions
Min
Typ
Max
Unit
−
45
70
ns
tPLH
−
35
55
ns
Propagation Delay Time
(From A Input to Q Output)
tPHL
−
50
80
ns
Propagation Delay Time
(From B Input to Q Output)
tPHL
−
40
65
ns
Propagation Delay Time
(From Clear Input to Q Output)
tPHL
−
−
27
ns
Propagation Delay Time
(From Clear Input to Q Output)
tPHL
−
−
40
ns
Output Pulse Width
(From A or B Input to Q or Q Output)
tw(out)
Cext = 80pF, Rext = 2k
70
110
150
ns
Cext = 0pF, Rext = 2k
20
30
50
ns
Cext = 100pF, Rext = 10k
650
700
750
ns
Cext = 1F, Rext = 10k
6.5
7.0
7.5
ns
CL = 15pF, Cext = 80pF, Rext = 2k
RL = 400
Function Table:
Truth Table:
Clear
Inputs
A
B
L
X
X
H
H
*
X
H
X
L

L
X
X
L

H
H
Outputs
Q
Q
L
L
L
H
H
H
H = High Level
L = Low Level
X = Irrelavent
 = Transition from LOW−to−HIGH
 = Transition from HIGH−to−LOW
= One HIGH Level Pulse
= One LOW Level Pulse
* This condition is true only if the output of the latch
formed by the two NAND gates has been conditioned
to the logical “1” state prior to CLR going high. This
latch is conditioned by taking either A or B low which
CLR is in the inactive state.
Pin Connection Diagram
16 VCC
1A 1
15 1 REXT/CEXT
14 1 CEXT
1B 2
1 CLR 3
1Q 4
13 1 Q
2Q 5
12 2 Q
11 2 CLR
2 CEXT 6
2 REXT/CEXT 7
10 2 B
GND 8
9 2A
16
9
1
8
.870 (22.0) Max
.260 (6.6) Max
.200 (5.08)
Max
.100 (2.54)
.700 (17.78)
.099 (2.5) Min