L6560 L6560A POWER FACTOR CORRECTOR VERY PRECISE ADJUSTABLE INTERNAL OUTPUT OVERVOLTAGE PROTECTION HYSTERETIC START-UP (ISTART-UP < 0.5mA) VERY LOW QUIESCENT CURRENT (< 3.5mA) INTERNAL START-UP TIMER TRANSITION MODE OPERATING TOTEM POLE OUTPUT CURRENT: ±400mA DIP8/SO8 PACKAGES DESCRIPTION The L6560/A is a monolithic integrated circuit in Minidip and SO8 packages, designed as a controller and driver of a discrete power MOS transistor for the implementation of active power factor correction, for sinusoidal line current consumption. Realized in mixed BCD technology, the chip integrates: - An undervoltage lockout with micropower startup and hysteresis. - An internal temperature compensated precise band gap reference. - A stable error amplifier. MULTIPOWER BCD TECHNOLOGY Minidip SO8 ORDERING NUMBERS: L6560 L6560D L6560A L6560AD - One quadrant multiplier. - Current sense comparator. - An output overvoltage protection circuit. - A totem-pole output stage able to drive a POWER MOS or IGBT devices with source and sink current of 400mA. The chip works in transition mode and is particularly intended for lamp ballast applications and for low power SMPS. BLOCK DIAGRAM June 2000 1/11 L6560 - L6560A ABSOLUTE MAXIMUM RATINGS Symbol Pin IVcc 8 ICC + IZ Parameter IGD 7 Output Totem Pole Peak Current (2µs) INV, COMP MULT 1, 2, 3 CS 4 Current Sense Input ZCD 5 Zero Current Detector Analog Inputs & Outputs Tj Tstg Unit 30 mA ±700 -0.3 to 7 mA V -0.3 to 7 V 5 (source) 10 (sink) mA mA 1 0.65 W Junction Temperature Operating Range -25 to 150 °C Storage Temperature -55 to 150 °C Power Dissipation @Tamb = 50 °C Ptot Value (Minidip) (SO8) PIN CONNECTION THERMAL DATA Symbol Parameter Rth j-amb Thermal Resistance Junction-ambient SO 8 MINIDIP Unit 150 100 °C/W PIN FUNCTIONS N. Name Function 1 INV Inverting input of the error amplifier. A resistive divider is connected between output regulated voltage and this point, to provide the voltage feedback. 2 COMP Output of error amplifier. A feedback compensation network is placed between this pin and the INV pin. 3 MULT Input of the multipler stage. A resistive divider connects to this pin the rectified mains. A voltage signal, proportional to the rectified mains, appears on this pin. 4 CS Input to the comparator of the control loop. The current is sensed by a resistor and the resulting voltage is applied to this pin. 5 ZCD 6 GND 7 GD Gate driver output. A push pull output stage is able to drive the Power MOS with peak current of 400mA (source and sink). 8 VCC Supply voltage of driver and control circuits. 2/11 Zero current detection input. Ground of the control section. L6560 - L6560A ELECTRICAL CHARACTERISTICS (VCC = 14.5V; Tj = 25°C unless otherwise specified) SUPPLY VOLTAGE SECTION Symbol Pin VCC 8 Operating Range Parameter Test Condition Min. VCC ON 8 Turn-on Threshold L6560 L6560A 13.5 11 VCC OFF 8 Turn-off Threshold L6560 L6560A Hys 8 Hysteresis L6560 L6560A after turn-on Typ. 11 Max. Unit 18 V 14.5 12 15.5 13 V v 9 8.7 10 9.6 11 10.5 V V 4.3 2.5 4.7 2.8 5.1 3.1 V V Min. SUPPLY CURRENT SECTION Symbol Pin Typ. Max. Unit ISTART-U 8 Start-up Current before turn-on at: VCC = 13V (L6560) VCC = 10.5V (L6560A) 0.3 0.5 mA ICC 8 Operating Supply Current CL = 0nF @ 70KHz 2.5 3.5 mA CL = 1nF @ 70KHz 3.2 4 mA in OVP condition Vpin1 = 2.7V 0.9 1.3 mA 18 20 22 V Min. Typ. Max. Unit 2.46 2.5 2.54 V VZ 8 Parameter Zener Voltage Test Condition ICC = 25mA ERROR AMPLIFIER SECTION Symbol Pin VINV 1 Parameter Voltage Feedback Input Threshold Test Condition –25 ≤ TJ ≤ 85°C; 12V < VCC < 18V TS Temperature Stability Tamb = -25 to 85°C RL Line Regulation VCC = 11 to 18V IINV 1 GV ICOMP 2 2.43 2.56 0.5 Input Bias Current % 1 4 mV 0.1 1 µA Voltage Gain Open loop 60 80 dB Source Current (V1 < Vref) VCOMP = 5V 0.14 0.2 mA 0.5 1 mA Min. Typ. Sink Current (V1 > Vref) MULTIPLIER SECTION Symbol Pin VMULT 3 ∆VCS ∆Vmult K Parameter Test Condition Operating Voltage Max. 0 to 2.5 0 to 4.2 Unit V Output Max. Slope VMULT = from 0V to 1V VCOMP = 6V 0.9 1.25 1.6 Gain VMULT = 1V VCOMP = 5V 0.45 0.65 0.85 1/V Min. Typ. Max. Unit 1.9 V 5 µA 400 ns CURRENT SENSE COMPARATOR Symbol Pin VCS 4 Voltage Threshold Parameter ICS 4 Input Bias Current td (H-L) 4 Delay to Output Test Condition VMULT = 2.5V VCOMP = 6V 1.6 200 3/11 L6560 - L6560A ELECTRICAL CHARACTERISTICS (continued) ZERO CURRENT DETECTOR Symbol Pin Parameter VZCD 5 Input Threshold Voltage Rising Edge Test Condition Min. Typ. 0.3 0.5 0.7 V VZCD 5 Clamp Voltage IZCD = 3mA 5 5.7 6.4 V VZCD 5 Clamp Voltage IZCD = –3mA 0.4 0.7 1 V Min. Unit 1.8 Hysteresis Max. Unit 2.3 V OUTPUT SECTION Symbol Pin VGD 7 Parameter Dropout Voltage Typ. Max. IGDsource = 200mA Test Condition 1.2 2 V IGDsource = 20mA 0.7 1 V IGDsink = 200mA 1.5 V IGDsink = 20mA 0.3 V tr 7 Output Voltage Rise Time CL = 1nF 50 120 ns tf 7 Output Voltage Fall Time CL = 1nF 40 100 ns Min. Typ. Max. Unit 36 40 44 µA Min. Typ. Max. Unit 45 60 OUTPUT OVERVOLTAGE SECTION Symbol Pin IOVP 2 Parameter Test Condition OVP Triggering Current RESTART TIMER Symbol tSTART Pin Parameter OVER VOLTAGE PROTECTION OVP The output voltage is expected to be kept by the operation of the PFC circuits close to its reference value that is set by the ratio of the two external resistors R1 and R2 (see fig. 2), taking into consideration that the non inverting input of the error amplifier is biased inside the L6560 at 2.5V. In steady state conditions, the current through R1 and R2 is: ∆Voutsc − 2.5 R1 2.5 or ISC = R2 ISC = and, if the external compensation network is made only with a capacitor C, the current through C is equal zero. When the output voltage increases abruptly the current through R1 becomes: IR1 = 4/11 Test Condition Start Timer Vout − 2.5 R1 IR1 = µs Voutsc + ∆VOUT − 2.5 = Isc + ∆I. R1 Since the current through R2 doesn’t change, the ∆I current must flow through the capacitor C and enter in the error amplifier. This current is mirrored inside the L6560, and compared with a precise internal reference of 40µA. Whenever such 40µA limit is exceed, the OVP protection is triggered (Dynamic OVP), and the external power transistor is switched off, until the overvoltage situation disappears. However if the overvoltage persists, before that the transient condition of dynamic circuit exhausts, an internal comparator (Static OVP) latches the OVP condition keeping the external power switch turned off (see fig. 1). The OVP value is threfore set by the equation OVP = ∆Vout = R1 ⋅ 40µA. Typical values for R1, R2 and C are reported in the application circuit. The overvoltage can be set independently from the average output voltage. The precision in setting the overvoltage threshold is 7% of the overvoltage value (for instance ∆V = 60V ± 4.2V). L6560 - L6560A Figure 1. OVER VOLTAGE VOUT nominal 40µA ISC E/A OUTPUT 3.1V DYNAMIC OVP STATIC OVP D95IN219A Figure 2: Overvoltage Protection Circuit Ccomp. +Vo ∆I R1 1 2 - X E/A + R2 PWM DRIVER 2.5V 3.1V + ∆I 40µA D93IN035B 5/11 L6560 - L6560A Figure 3: Typical Application Circuit (100W) D1 BYT03-400 R3 D3 1N4150 68K 5% BRIDGE + 4 x BY255 FUSE 4A/250V 100 5% D2 1N5248B C1 1µF 250V R2 C6 R7 1.5M 1% 10nF Vo=240V Po=100W C3 330nF 5 8 2 1 L6560 Vac (85V to 135V) 3 C2 22µF 25V + R1 68K 5% R9 1.5M 1% R10 16K 1% T 7 6 R5 10 MOS IRF740 C5 150µF 315V 4 R4 330 C7 10nF R6 0.33 1W C4 1nF R8 16K 1% - D94IN050B TRANSFORMER T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT primary 90T of Litz wire 10 x 0.2mm secondary 11T of #27 AWG (0.15mm) gap 1.9mm for a total primary inductance of 0.6mH Figure 4: Typical Application Circuit (120W) D1 BYT13-600 R3 D3 1N4150 220K 5% BRIDGE + 4 x BY255 FUSE 4A/250V 100 5% D2 1N5248B C1 1µF 400V R2 C6 R7 1M 1% 4.7nF 2 1 L6560 Vac (175V to 265V) 3 7 6 R5 10 MOS STP8NA50 C5 47µF 450V 4 R4 330 C7 10nF C4 1nF TRANSFORMER T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT primary 90T of Litz wire 10 x 0.2mm secondary 7T of #27 AWG (0.15mm) gap 1.25mm for a total primary inductance of 0.8mH 6/11 Vo=400V Po=120W C3 1µF 5 8 C2 22µF 25V + R1 68K 5% R9 1.8M 1% R10 6.2K 1% T R6 0.4 1W R8 6.34K 1% D94IN049A - L6560 - L6560A Figure 5: P.C. Board and Component Layout of the Figg. 3 and 4 (1:1.25 scale) Figure 6: OVPCurrent Threshold vs. Temperature D94IN047 IOVP (mA) Figure 7: Undervoltage Lockout Threshold vs. Temperature VCC-TH-ON (V) D94IN044 14 42 13 41 12 VCC-TH-OFF (V) 10 40 9 -25 39 -50 -25 0 25 50 75 100 125 T (°C) 0 25 50 T (°C) 75 100 125 7/11 L6560 - L6560A Figure 9: Voltage Feedback Input Threshold vs. Temperature Figure 8: Supply Current vs. Supply Voltage ICC (mA) VREF (V) D94IN045 D94IN048 CL = 1nF f = 70KHz TA = 25°C 4 2.50 3 2 2.48 1 0 2.46 -5 0 5 10 15 20 VCC(V) Figure 10: Output Saturation Voltage vs. Sink Current VPIN7 (V) 50 T (°C) 100 Figure 11: Output Saturation Voltage vs. Source Current D94IN053 VCC = 14.5V SINK 2.0 VCC -0.5 1.5 VCC -1.0 1.0 VCC -1.5 0.5 VCC -2.0 0 SOURCE 0 0 100 200 300 400 IGD (mA) Figure 12: Multiplier Characteristics Family D94IN042 VCS(pin4) (V) 1.8 0 100 200 300 400 IGD (mA) Figure 13: Multiplier Characteristics Family VCOMP(pin2) (V) 5.7 5.1 4.7 4.3 4.1 1.6 VCS (pin4) (mV) 550 VCOMP D94IN043 5.7 500 450 1.4 5.1 400 1.2 3.9 350 4.7 1.0 300 0.8 250 4.3 200 4.1 3.7 0.6 150 0.4 3.6 0.2 3.9 100 3.7 3.6 50 0 0.0 -1.0 8/11 0 VPIN7 (V) D94IN046 VCC = 14.5V -50 0.0 1.0 2.0 3.0 VMULT(pin3) (V) 4.0 5.0 -200 -100 0 100 200 VMULT (pin3) (mV) 300 400 L6560 - L6560A mm DIM. MIN. A TYP. inch MAX. MIN. 3.32 TYP. MAX. 0.131 a1 0.51 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 0.020 D E 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L Z 3.18 OUTLINE AND MECHANICAL DATA 3.81 1.52 0.125 0.150 Minidip 0.060 9/11 L6560 - L6560A mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.25 a2 MAX. 0.069 0.004 0.010 1.65 0.065 a3 0.65 0.85 0.026 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.020 c1 45° (typ.) D (1) 4.8 5.0 0.189 0.197 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 F (1) 3.8 4.0 0.15 0.157 L 0.4 1.27 0.016 0.050 M S 0.6 0.024 8 ° (max.) (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 10/11 OUTLINE AND MECHANICAL DATA SO8 L6560 - L6560A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 11/11