Preliminary 10 NJU6627 3 LCD NJU6627 LCD 10 3 LCD 1 ROM/RAM / 5V 10V 5V NJU6627C CPU 1MHz CPU ROM 7,840 5X7 224 23 2 50 10 3 COMMK1 COMMK2 100 21 NJU6627 NJU6627 10 3 5 7 ( 100 RAM:30 8 ROM RAM RAM 3 ) : 10 3 :7,840 : :1,120 : :100 : 23 / :1/23 1/16Duty /2 : :4 6 5 7 5 7 224 32 50 / / :24 :16 ( ) CR VDD = 4.5 ~ 5.5V CMOS Ver.2011-09-17 -1- NJU6627 Preliminary PAD 75 51 76 50 TOP VIEW Y X 100 26 1 PAD PAD -2- 25 : X=0µm, Y=0µm : X= 4.50 mm, Y= 4.61 mm : 400µm ± 25 µm : 90.0 µm x 90.0 µm : 134µm (Min.) :P Ver.2011-09-17 Preliminary NJU6627 PAD PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Ver.2011-09-17 V4 V3 V2 V1 VLCD VOUT C1+ C1VCI VDD OSC1 REQ DATA SCL CSb RESETb VSS K1 K2 K3 K4 K5 K6 S1 S2 S3 S4 COMMK1 COM8 COM9 COM10 COM11 COM12 COM13 COM14 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 X= µm -2007.3 -1862.5 -1717.7 -1572.9 -1428.1 -1158.4 -1018.4 -878.4 -738.4 -497.6 -345.8 -204.0 -17.2 142.6 286.6 430.6 596.8 817.4 951.4 1098.6 1232.6 1379.8 1513.8 1743.2 1923.2 1978.6 1978.6 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 2088.0 Y= µm -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -2038.5 -1656.2 -1476.2 -1205.0 -1060.0 -915.0 -770.0 -625.0 -480.0 -335.0 -191.0 -45.0 100.0 245.0 390.0 535.0 680.0 825.0 970.0 1115.0 1260.0 1405.0 1550.0 1695.0 1840.0 1985.0 4.50 x 4.61 mm( PAD No. 51 SEG16 52 SEG17 53 SEG18 54 SEG19 55 SEG20 56 SEG21 57 SEG22 58 SEG23 59 SEG24 60 SEG25 61 SEG26 62 SEG27 63 SEG28 64 SEG29 65 SEG30 66 SEG31 67 SEG32 68 SEG33 69 SEG34 70 SEG35 71 SEG36 72 SEG37 73 SEG38 74 SEG39 75 SEG40 76 SEG41 77 SEG42 78 SEG43 79 SEG44 80 SEG45 81 SEG46 82 SEG47 83 SEG48 84 SEG49 85 SEG50 86 COMMK2 87 COM21 88 COM20 89 COM19 90 COM18 91 COM17 92 COM16 93 COM15 94 COM7 95 COM6 96 COM5 97 COM4 98 COM3 99 COM2 100 COM1 X=0µm, Y=0µm) X= µm Y= µm 1930.0 2143.0 1785.0 2143.0 1640.0 2143.0 1495.0 2143.0 1350.0 2143.0 1205.0 2143.0 1060.0 2143.0 915.0 2143.0 770.0 2143.0 625.0 2143.0 480.0 2143.0 335.0 2143.0 190.0 2143.0 -335.0 2143.0 -480.0 2143.0 -625.0 2143.0 -770.0 2143.0 -915.0 2143.0 -1060.0 2143.0 -1205.0 2143.0 -1350.0 2143.0 -1495.0 2143.0 -1640.0 2143.0 -1785.0 2143.0 -1930.0 2143.0 -2088.0 1999.0 -2088.0 1854.0 -2088.0 1709.0 -2088.0 1564.0 -2088.0 1419.0 -2088.0 1274.0 -2088.0 1129.0 -2088.0 984.0 -2088.0 839.0 -2088.0 694.0 -2088.0 549.0 -2088.0 404.0 -2088.0 259.0 -2088.0 114.0 -2088.0 -31.0 -2088.0 -176.0 -2088.0 -321.0 -2088.0 -466.0 -2088.0 -611.0 -2088.0 -756.0 -2088.0 -901.0 -2088.0 -1046.0 -2088.0 -1191.0 -2088.0 -1336.0 -2088.0 -1481.0 -3- Preliminary NJU6627 C1+ VCI C1- VOUT VLCD RB V1 V2 RB RB V4 V3 RB RB 2 S1 – S4 K1 – K6 CR (IR) OSC1 (ID) RAM(DD RAM) 30 x8(CG)+30x6(MK) DATA RAM (MK RAM) 20x5 RAM (CG RAM) 5x7x32 ROM (CG ROM) 7,840 SEG1-SEG50 71bit CSb (DR) SCL COM1-COM21 COMMK1 COMMK2 ↔ REQ 8bit RESETb VSS -4- Ver.2011-09-17 Preliminary NJU6627 No. 10 17 VDD VSS 9 VCI 6 VOUT 5 4 3 2 1 VLCD V1 V2 V3 V4 7 8 C1+ C1- 11 OSC1 15 CSb 14 SCL 13 DATA 16 RESETb 12 REQ 18-23 K1-K6 24-27 S1-S4 36-85 SEG1-SEG50 94-100 29-35 87-93 COM1-COM21 28 86 Ver.2011-09-17 - : VDD=+5V, GND : VSS=0V VSS :0.1uF / 900us ”L” (fOSC=200KHz) ”H” COMMK1 COMMK2 -5- Preliminary NJU6627 (1) (1-1) NJU6627 (IR) IR RAM(MK RAM) DR DD RAM CG RAM MK RAM (1-2) - RAM(DD RAM) - RAM(DD RAM) 30 DD RAM DD RAM AC RAM(CG RAM) DD RAM CG RAM MK RAM (AC) (AC) DD RAM CG RAM IR AC RAM DD RAM CG RAM MK RAM (1-3) (DR) 2 8 RAM(DD RAM) CPU MK RAM IR MK RAM DD RAM CG RAM (AC) 8 - - DR +1( RAM -1) 30 8 (AC) (ADD) 16 AD5 AD4 AD3 AD2 AD1 AD0 2 ) DD RAM 0 1 0 0H 4 ”08”H 0 0 0 8H (1-3-1) DD RAM 1 00 10 20 2 01 11 21 3 02 12 22 4 03 13 23 5 04 14 24 6 05 15 25 7 06 16 26 8 07 17 27 9 08 18 28 ← ←DD RAM 10 09 19 29 (16 ) DD RAM (00) ← (10) ← (20) ← 01 11 21 02 12 22 03 13 23 04 14 24 05 15 25 06 16 26 07 17 27 08 18 28 09 19 29 00 10 20 09 19 29 00 10 20 01 11 21 02 12 22 03 13 23 04 14 24 05 15 25 06 16 26 07 17 27 08 18 28 ROM (CG ROM) - ROM(CG ROM) 224 5 7 8 (1-4) ROM 1 (20)H -6- 5 →(09) →(19) →(29) 7 ROM NJU6627 - ) - ROM ( Ver.2011-09-17 Preliminary 1 Ver.2011-09-17 CG RAM (01) (17) (02) (18) (03) (19) (04) (20) (05) (21) (06) (22) (07) (23) (08) (24) (09) (25) (10) (26) (11) (27) (12) (28) (13) (29) (14) (30) (15) (31) (16) (32) - - (ROM - NJU6627 02) -7- Preliminary NJU6627 2 -8- CG RAM (01) (17) (02) (18) (03) (19) (04) (20) (05) (21) (06) (22) (07) (23) (08) (24) (09) (25) (10) (26) (11) (27) (12) (28) (13) (29) (14) (30) (15) (31) (16) (32) - - (ROM - 03) Ver.2011-09-17 Preliminary (1-5) RAM (CG RAM) RAM(CG RAM) 32 5 7 CG RAM RAM 1 (00)H CG RAM - ← (DD RAM) - (CG RAM CG RAM (DD RAM ) 76543210 DD RAM ← → 00000000 00000 00000001 00001 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 y y y y y 000 001 010 011 100 101 110 111 y y y y y 11111 - ) (CG RAM ) 43210 ← → 76543210 → y y y y y 00011111 11110 10001 10001 11110 10100 10010 10001 * * * * * 10001 01010 11111 00100 11111 00100 00100 * * * * * (1) (2) y y y y y (32) (Don’t Care) ) 1. 0 4 CG RAM 2. CG RAM 0 2 CG RAM 3. CG RAM 4. 1,2 CG RAM 5. CG RAM - "1" ,"0" Ver.2011-09-17 (1F)H 2 2 CG RAM * NJU6627 3 7 0 4 - (5 8 :32 ( - 5 7 ) 4 ) "0" -9- Preliminary NJU6627 (1-6) RAM(MK RAM) RAM(MK RAM) 100 RAM / MK RAM 3 COMMK1 1 50 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COMMK2 100 51 1 2 3 4 5 6 7 8 9 10 SEG 46 47 48 49 50 3 MK RAM MK RAM (40H 53H) 100 0000 100 0001 100 0010 100 0011 : 101 0011 40H 41H 42H 43H : 53H D7 0 0 0 0 D6 0 0 0 0 D5 0 0 0 0 D4 “1” “6” “11” “16” 0 0 0 “96” D3 “2” “7” “12” “17” D2 “3” “8” “13” “18” D1 “4” “9” “14” “19” D0 “5” “10” “15” “20” “97” “98” “99” “100” : ) MK RAM MK RAM (1-7) DD RAM,CG RAM,MK RAM,CG ROM RAM CPU DD RAM - (1-8) 23 - - 10 - - 50 - - Ver.2011-09-17 Preliminary NJU6627 (1-9) 4 6 24key NJU6627 S4 S3 S2 S1 K6 K5 K4 K3 K2 K1 ON OFF (1-9-1) 64 128 T[s](T=1/fosc) T[s] / CPU REQ ”H” 64 T[s] S1 S2 S3 S4 REQ T=1/ fosc 128 T [s] (1-9-2) REQ "H" "L" (1-9-3) REQ ”L” REQ ”H” "1" S3 Ver.2011-09-17 ”L” "0" K2 S3 (D1) "1" S1 S4 K2 K1 K6 "0" - 11 - Preliminary NJU6627 NJU6627 S4 S3 S2 S1 K6 K5 K4 K3 K2 K1 ON OFF S3 K2 ”1” D5 D4 D3 D2 D1 D0 K6 K6 K6 K6 K5 K5 K5 K5 K4 K4 K4 K4 K3 K3 K3 K3 K2 K2 K2 K2 K1 K1 K1 K1 S1 S2 S3 S4 (1-9-4) 6 D15 1 D14 0 D13 1 D12 0 D11 0 D10 1 SX1 0 0 1 1 D9 D8 SX1 SX0 SX0 0 1 0 1 D7 * SX(X=1 4) D6 * D5 K6 D4 K5 D3 K4 D2 K3 D1 K2 D0 K1 S1 S2 S3 S4 (1-9-5) / REQ REQ ”H” REQ - 12 - ”L” Ver.2011-09-17 Preliminary NJU6627 (1-9-6) S1 S4 K1 K6 K1 K6 2 “L” ”H” L” (1-9-1) 2 2 CPU REQ “H” CPU REQ “L” REQ CPU “L” T=1/ fosc 1 2 128 T[s] 128 T[s] 128 T[s] REQ CSb SCL DATA S1 S2 S3 S1 Ver.2011-09-17 S4 S4 S1 S2 S3 S1 S4 S4 S1 S2 S3 S1 S4 S4 - 13 - NJU6627 Preliminary • REQ No REQ =”H” Yes CSb S1 1 T [s] REQ =”H” REQ 127 T [s] No Yes REQ S2 T=1/ fosc REQ =”H” No fosc=200KHz Yes REQ = 127 5 s = 635 s S3 REQ =”H” No Yes S4 No Yes (1-9-7) 3 ( 4 ) S1 S2 S3 S4 K1 S3 3 ”L” K2 K3 K4 K5 K6 - 14 - Ver.2011-09-17 Preliminary (1-10) (1-10-1) NJU6627 ( NJU6627 ) (fosc=200KHz ) VDD 2.4V 1.45ms D=0 M=0 B=0 / I/D=1 S=0 V=0 DU=1 K=1 PD=0 +1( ) =0000 VLCD 1/23Duty(3 AC=00H DD RAM ) 00H 20H ) CPU (1-10-2) 900us 550us fosc=200KHz ) "L" ( • 900us 550us Ver.2011-09-17 - 15 - NJU6627 Preliminary (2) NJU6627 (IR) IC CPU (DR) 2 4 MSB RAM 4 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 *1 (a) 1 0 0 1 1 1 1 1 (b) 1 0 0 1 1 0 0 1 * * * * * * * * 550us (c) 1 0 0 1 0 0 0 1 * * * * * * * * 0us (d) 1 0 0 0 1 0 0 0 * * * * * * I/D S 0us 1 0 0 0 1 0 0 1 * * * * * D M B 0us (f) 1 0 0 1 0 0 1 0 * * * * * * * ARL 0us (g) 1 0 0 0 1 0 1 0 * * * * * * * DRL 0us (h) 1 0 0 0 1 1 0 0 * * * * (i) 1 0 0 0 1 1 1 0 * * * * 1 0 0 1 0 0 1 1 * 1 0 0 1 0 0 0 0 CG RAM (00-FE)H 0us 1 0 0 1 1 0 0 0 Write data (DD RAM) 35us 1 0 0 1 1 0 0 0 * * * Write data (MK RAM) 35us 1 0 0 1 1 0 0 0 * * * Write data (CG RAM) 35us 1 0 1 0 0 1 * * (e) (j) (k) / DD/MK RAM CG RAM DD RAM (l) MK RAM CG RAM (m) SX - * 0us V DU K DD RAM (00-29)H MK RAM (40-53)H PD 0us (PD:35us) 0us 0us *1 fOSC=200KHz - 16 - Ver.2011-09-17 Preliminary (2-1) (a) NJU6627 (Maker Test) D15 1 D14 0 D13 0 D12 1 D11 1 D10 1 D9 1 D8 1 D7 * D6 * D5 * D4 * D3 * D2 * *= (b) D1 * D0 * (Don’t care) (Clear Display) D15 1 D14 0 D13 0 D12 1 D11 1 D10 0 D9 0 D8 1 D7 * D6 * DD RAM RAM 00 ) ROM (c) D5 * D4 * D3 * D2 * D1 * D0 * (20)H DD I/D MK/CG RAM (20)H (Return Home) D15 1 D14 0 D13 0 D12 1 D11 0 D10 0 D9 0 D8 1 D7 * DD RAM (d) D6 * D5 * D4 * D3 * 00 D2 * D1 * D0 * I/D MK/CG RAM (Entry Mode Set) D15 1 D14 0 D13 0 D12 0 D11 1 I/D D10 0 D9 0 S I/D 1 0 D8 0 D7 * D6 * D5 * D4 * D3 * D2 * D1 I/D D0 S DD RAM DD RAM MK RAM CG RAM DD RAM MK RAM CG RAM +1 -1 S 1 I/D I/D=1 I/D=0 CG RAM MK RAM 0 Ver.2011-09-17 - 17 - Preliminary NJU6627 (e) / (Display ON/OFF Control) D15 1 D14 0 D13 0 D12 0 D11 1 D10 0 D9 0 D8 1 D7 * D6 * D5 * D4 * D3 * D2 D D1 M D0 B D4 * D3 * D2 * D1 * ARL / D 1 0 DD RAM D=1 M 1 0 B DD RAM 1 ( fOSC=200KHz ) 500ms 0 5x7 (1) (f) (2) (Address Shift) D15 1 D14 0 D13 0 D12 1 D11 0 D10 0 D9 1 D8 0 D7 * D6 * D5 * D0 ARL 0 1 - 18 - ( ( -1 +1 ) ) Ver.2011-09-17 Preliminary (g) NJU6627 (Display Shift) D15 1 D14 0 D13 0 D12 0 D11 1 D10 0 D9 1 D8 0 D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 DRL (AC) DRL 0 1 ( ( (h) ) ) (Set Electronic Volume Register) D15 1 D14 0 D13 0 D12 0 D11 1 D10 1 D9 0 D8 0 D7 * D6 * D5 * D4 * D3 C3 D0,D1,D2,D3 VLCD D2 C2 D1 C1 D0 C0 C0,C1,C2,C3 16 1 (1,1,1,1) C3 C2 C1 C0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Ver.2011-09-17 VLCD VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT ) 80/95 80/94 80/93 80/92 80/91 80/90 80/89 80/88 80/87 80/86 80/85 80/84 80/83 80/82 80/81 80/80 VOUT=8.4(V) VLCD (V) 7.074 7.149 7.226 7.304 7.385 7.467 7.551 7.636 7.724 7.814 7.906 8.000 8.096 8.195 8.296 8.400 - 19 - Preliminary NJU6627 (i) (Set Display Mode) D15 1 D14 0 D13 0 D12 0 D11 1 D10 1 D9 1 D8 0 D7 * D6 * D5 * D4 * D3 V D2 DU D1 K D0 PD V 1 0 VOUT DU 1 0 1/23Duty 1/16Duty K 1 0 S1 S4 VSS PD 1 COM SEG VSS 0 • REQ REQ - 20 - H H Ver.2011-09-17 Preliminary (j) DD/MK RAM D15 1 D14 0 (Set DD/MK RAM Address) D13 0 DD/MK RAM D12 1 D11 0 D10 0 DD RAM D9 1 D8 1 D7 * D6 D5 D4 D3 D2 D1 D0 AD6 AD5 AD4 AD3 AD2 AD1 AD0 MK RAM CPU DD RAM / MK RAM RAM RAM (00)H (10)H (20)H (40)H DD RAM 1 DD RAM 2 DD RAM 3 MK RAM (k) CG RAM D15 1 CG RAM NJU6627 (09)H (19)H (29)H (53)H (Set CG RAM Address) D14 0 D13 0 D12 1 D11 0 D10 0 D9 0 D8 0 D7 D6 D5 D4 D3 D2 D1 D0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 CG RAM CG RAM CPU CG RAM CG RAM Ver.2011-09-17 RAM (00)H (FE)H - 21 - Preliminary NJU6627 (l) RAM (Write Data to CG, DD or MK RAM) • DD RAM D15 1 D14 0 D13 0 D12 1 D11 1 D10 0 D9 0 D8 0 D7 D6 D5 D4 D3 D2 D1 D0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 D13 0 D12 1 D11 1 D10 0 D9 0 D8 0 D7 * D6 * D5 * D4 D3 D2 D1 D0 DM4 DM3 DM2 DM1 DM0 D13 0 D12 1 D11 1 D10 0 D9 0 D8 0 D7 * D6 * D5 * D4 D3 D2 D1 D0 DC4 DC3 DC2 DC1 DC0 D3 K4 D2 K3 D1 K2 D0 K1 • MK RAM D15 1 D14 0 • CG RAM D15 1 D14 0 DD RAM MK RAM CG RAM DD, CG, MK RAM +1 (m) (Read Data Key) D15 1 D14 0 D13 1 D12 0 SX1 0 0 1 1 D15 D8 - 22 - -1 D11 0 D10 1 D9 D8 SX1 SX0 SX0 0 1 0 1 D7 * D6 * D5 K6 D4 K5 S1 S2 S3 S4 8 8 Ver.2011-09-17 Preliminary NJU6627 (2-2) VDD 2.4V 1.45ms 1 0 0 0 1 0 0 0 * * * * * * I/D S 1 0 0 0 1 1 0 0 * * * * C3 C2 C1 C0 1 0 0 0 1 1 1 0 * * * * V DU K PD 1 0 0 1 1 0 0 1 * * * * * * * * D0 ) CG RAM/DD RAM/MK RAM MK RAM / Ver.2011-09-17 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 1 0 0 0 1 0 0 1 * * * * * 0 (D) 0 (M) 0 (V) - 23 - Preliminary NJU6627 (3) (3-1) VCI D3 = "1" : VCI 2 D3 = "0" : VOUT NJU6627 VOUT Cout C1+ * Cout=C1=1.0 uF C1 C1- VCI - 24 - Ver.2011-09-17 Preliminary NJU6627 (3-2) V1,V2,V3,V4 VOUT IC 16 VLCD,V1,V2,V3,V4 1/16 1/23 1/5 VLCD - VSS VLCD VLCD NJU6627 VOUT (16 + ) 3.75K VLCD VLCD + 4K V1 V1 + 4K V2 V2 + 4K V3 V3 + VLCD 4K V4 V4 + 4K VSS VSS (3-3) OSC1 OSC1 VDD NJU6627 120kΩ (fOSC=200kHz TYP.) OSC1 33pF Ver.2011-09-17 - 25 - Preliminary NJU6627 (3-4) 200kHz TYP.( =5.0us) 2 23 110 23 1 2 3 4 23 1 3 4 1 2 3 VLCD V1 V2 COMMK1 V3 V4 VSS 1 1 1 = 5.0 (us) 110 23 = 12.65 (ms) = 1 / 12.65 (ms) = 79 (Hz) (4) CPU 1 16 - CSb SCL DATA CSb "L" 16 (CSb) (SCL) (CSb) 16 16 16 16 CSb RAM +1( -1) MSB D15 D8 8 - 26 - 8 DATA Ver.2011-09-17 Preliminary NJU6627 (Ta=25 (1) VDD -0.3 +7.0 V (2) VCI VOUT, VLCD, V1 V4 Vt Topr Tstg -0.3 +7.0 V VCI V VOUT, VLCD,V1 V OSC1,SCL,DATA,CSb,RESETb,K1-K6 (3) 1) VSS+0.3 VSS+10.5 -0.3 VDD+0.3 -40 +85 -55 +125 LSI ) V4 LSI LSI LSI 2) LSI VDD-VSS,VCI-VSS,VOUT-VSS VSS=0V 3) Ver.2011-09-17 VOUT VCI VLCD VDD VSS VSS=0V VOUT - 27 - NJU6627 Preliminary VDD=4.5V 5.5V VSS=0.0V VDD (1) (2) VCI (3) VOUT VIH1 VIL1 VIH2 VIL2 VOH1 (1) (2) (1) VOL1 VDD VCI VOUT OSC1,SCL, DATA, CSb, RESETb K1-K6 IOH1=-2mA,VDD=5.0V REQ,DATA IOL1=1mA,VDD=5.0V IOH=-20 A ,VDD=5.0V IOL2=500 A , VDD=5.0V VOH2 (2) S1-S4 VOL2 ON (COM) RCOM COM1-COM21 COMMK1, COMMK2 ON (SEG) RSEG SEG1-SEG50 MOS MOS 1 2 -Ip1 -Ip2 ILI IDD1 Ta= -40 +85 ( DATA K1-K6 SCL, CSb, RESETb VDD IDD2 ) Id 1uA(COM VO=VLCD,VSS,V1,V4 ) MIN TYP MAX 4.5 - 5.5 V 3.0 - 5.0 V VDD 0.8VDD VSS 0.8VDD VSS 4.0 - 10.0 VDD 0.2VDD VDD 0.4VDD - V - - 0.5 0.8VDD VDD VSS 0.2VDD 4 V V V V - - 40 kΩ 5 - - 40 kΩ 5 5 10 25 25 50 50 A A -1.0 - 1.0 A VDD=5V, fOSC=200 kHz, , - 120 300 A 6 VDD=5V, - 5 10 A 6 1.1 1.6 mA 6.2 4.6 3.0 1.4 6.4 4.8 3.2 1.6 6.6 5.0 3.4 1.8 V 14.0 20.0 26.0 KΩ 9.0 9.8 160 200 240 kHz 280 45 400 50 520 55 kHz % - 0.4 1.0 mA ) Id 1uA(SEG VO=VLCD,VSS,V2,V3 VDD=5V, VIN =VSS VDD=5V, VIN =VSS VIN 0 VDD VCI=5V, fOSC=200 kHz, ICI VCI "1111" RB=VLCD/IB RB: 5 IB: V1 V2 V3 V4 V1 V2 V3 V4 RB VLCD Vout VOUT "1111" VLCD 8.0V "1111" VOUT=8.0V, Ta=25 VCI=5V, fOSC=200 kHz, fOSC OSC1 fCP Duty OSC1 OSC1 IOUT VOUT Ta=25 , VDD=5V, Ta=25 Rosc=120k , Cosc=33pF V VOUT=8.0V VOUT ”1111” Ta=25 - 28 - Ver.2011-09-17 7 Preliminary 4 5 COM,SEG Id (COM1 COM21/COMMK1/COMMK2) (SEG1 SEG50) (VLCD,V1-V4) ±0.15V VSS VLCD V1 V4 VSS VLCD NJU6627 V2 V3 • 5V NJU6627 A VDD VSS 6 CMOS ”H”/”L” DATA 7 Ver.2011-09-17 VDD 1/2 - 29 - Preliminary NJU6627 • (VDD=4.5V 5.5V Ta= -40 +85 ) tCYCE tSC PWCS tCSU tCHI tSISU tSIH tKDD tSRWD tCRWD tCH2 tR tF 1 SCL CS 2 8 9 RAM 10 8,9 MIN MAX 1 300 800 50 1 300 300 300 300 1 - - s ns s 300 300 300 15 15 8 9 10 ns ns ns ns ns ns ns s ns ns 4 4 4 1 tR tF tCSU CSb tCYCE tR tSC PWCS tF F ••••• SCL tSC tCH1 tR/tF ••••• DATA tSISU tSIH tCH2 2 CSb 8 9 10 15 16 ••••• SCL tKDD ••••• DATA tCRWD tSRWD DATA DATA - 30 - DATA DATA Ver.2011-09-17 Preliminary NJU6627 • (Ta=25 ) ”L” (fOSC=200KHz ) tRSL MIN TYP. MAX 900 - - s tRSL RESET VIL • (Ta=25 MIN TYP. MAX trDD 0.1 - 5 ms tOFF 1 - - ms ) 2.2V 0.2V VDD 0.1ms 0.2V trDD trDD 0.2V tOFF tOFF 5ms 1ms • (fOSC=200KHz) MIN TYP. MAX tKS - 320 - us tKP - 80 - us VDD S1 VSS VDD S2 VSS tKP VDD S4 VSS tKS Ver.2011-09-17 - 31 - NJU6627 Preliminary LCD COMMK1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COMMK2 SEG MK 1 COMMK1 COM1 COM2 COMMK2 SEG1 SEG2 - 32 - 1 1 2 3 4 5 2 3 21 MK MK 2 1 1 2 3 21 MK MK 2 1 1 2 VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS • • • • • • • • VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS Ver.2011-09-17 Preliminary NJU6627 OSC1 COMMK1 COM1 CPU •••• RESETb REQ SCL CSb DATA COM21 COMMK2 LCD 10 3 VDD SEG1 NJU6627 VLCD V1 V2 V3 V4 + + + + + SEG50 + VSS Ver.2011-09-17 + ••••••••• + VCI C1+ C1VOUT S4 S3 S2 S1 K6 K5 K4 K3 K2 K1 - 33 -