New Product R2A20152NS/SP 8-bit 2ch D/A Converter with Buffer Amplifiers for I2C BUS (Corresponds to Fast mode) R03DS0013EJ0100 Rev.1.00 2011.09.05 Description The R2A20152 is an integrated circuit semiconductor of CMOS structure with 2 channels of built in D/A converters with output buffer operational amplifiers. It is the characteristic improvement version of M62332. The input interface is I2C Bus serial data method, and connects with a microcomputer with minimum wiring. It conforms FAST-MODE of I2C BUS Specifications. The output circuit is composed of buffer operational amplifier with sync and source drive capacity of 1.0 mA or more, and it operates in the whole voltage range from VCC to ground. Features • Guarantee Differential nonlinearity error : +/-0.7LSB, Nonlinearity error : +/-1.0LSB • Digital data transfer format: I2C BUS serial data method (Corresponds to Fast mode: 400kHz) • Output buffer operational amplifier: It operates in the whole voltage range from VCC to ground. • High output current drive capacity: +/-1.0 mA over • Very small size SON-8 package Application Conversion from digital data to analog control data for home-use and industrial equipment. Signal gain control or automatic adjustment of LCD-TV, PDP-TV, LCD-monitor, or etc. Blurring correction control or various control of the interchangeable lens of digital camera. Block Diagram Vcc SCL SDA GND 8 7 6 5 I2C BUS TRANCEIVER Power on reset Channel decoder 8-bit latch 8-bit latch 8-bit upper segment R-2R 8-bit upper segment R-2R + R03DS0013EJ0100 Rev.1.00 2011.09.05 + 1 2 3 4 Ao1 Ao2 N.C. N.C Page 1 of 8 New Product R2A20152NS/SP Pin Arrangement R2A20152SP R2A20152NS Ao1 1 8 Vcc Ao1 1 8 Vcc Ao2 2 7 SCL Ao2 2 7 SCL N.C. 3 6 SDA N.C. 3 6 SDA N.C. 4 5 GND N.C. 4 5 GND (Top view) (Top view) N.C. : Not connected Outline: PWSN0008KA-A (SON-8) [NS] N.C. : Not connected Outline: PRSP0008DE-C (SOP-8) [SP] Pin Description Pin No. Pin Name 1 Ao1 8-bit resolution D-A converter output terminal 2 Ao2 (After power on, analog output of every channel is set in DAC data "00h") 3 N.C. 4 N.C. 5 GND GND terminal 6 SDA Serial data input terminal 7 SCL Serial clock input terminal 8 Vcc Power supply terminal R03DS0013EJ0100 Rev.1.00 2011.09.05 Function Not connected Page 2 of 8 New Product R2A20152NS/SP Absolute Maximum Ratings Item Ta= 25deg, unless otherwise noted) Ratings Unit Supply Voltage Symbol Vcc Condition -0.3 to +6.5 V Input Voltage Vin -0.3 to Vcc+0.3 < +6.5 V Output Voltage Vo -0.3 to Vcc+0.3 < +6.5 V Buffer amp. Output current IAO Continuous -2.0 to +2.0 mA Power dissipation Pd Ta = +85deg 270(NS) / 272(SP) mW Ta > +25deg Thermal derating factor K theta 6.75(NS) / 6.8(SP) mW/deg Operating temperature Topr -30 to +85 deg Storage temperature Tstg -40 to +125 deg Electrical Characteristics Item (Vcc= +5V +/-10%, GND=0V, Ta= -30 to +85deg, unless otherwise noted) Symbol Supply voltage Vcc Supply current Icc Rise time of supply voltage *1 Ratings Test Condition Unit Min. Typ. Max. 2.7 5.0 5.5 V CLK = 500kHz, IAO = 0µA, DATA: 6Ah (at maximum current) 0 0.5 1.5 mA SDA = SCL = GND, IAO = 0µA 0 0.3 1.0 mA trVcc Vcc = 0 to 2.7V 100 - - µs VccPOR Vcc = 0 to 2.7V - 1.5 1.9 V tPOR Vcc < 0.1V 1 - - ms Input leak current IILK VIN = 0 to Vcc -10 - 10 µA Input low voltage VIL 0 - 0.2Vcc V Input high voltage VIH 0.8Vcc - Vcc V Vhys 0.5 0.8 - V Internal reset operating voltage *1 Power supply restart interval (Power supply OFF ON) *1 Hysteresis of Schmitt trigger input (SDA, SCL) Output low voltage (SDA) VOL Pulse width of spike noise tSP Buffer amplifier output voltage range VAO Buffer amplifier output Drive range IAO Differential nonlinearity SDL -0.7 - 0.7 LSB Nonlinearity SL -1.0 - 1.0 LSB -2.0 - 2.0 LSB -2.0 - 2.0 LSB Zero code error SZERO Full scale error SFULL Isink =3mA - - 0.4 V 0 - 50 ns IAO = 100µA 0.1 - Vcc – 0.1 IAO = 500µA 0.2 - Vcc – 0.2 Upper side saturation voltage = 0.3V, Lower side saturation voltage = 0.2V -1.0 - 1.0 Vcc = 5.12V (20mV/LSB), without load ( IAO = 0µA ) V mA Output capacitate load CO - - 0.1 µF Buffer amplifier output impedance RO - 5.0 - ohm *1 : When power supply is turned on, internal circuit is initialized by power on reset circuit. But, if re-powered on quickly, initialize is not operate. So, keep the time period of re-powered on (tPOR). trVcc Vcc tPOR (equivalent to trVcc) VccPOR GND Internal reset signal GND < 0.1V Resetting period R03DS0013EJ0100 Rev.1.00 2011.09.05 Resetting period Page 3 of 8 New Product R2A20152NS/SP I2C BUS Line Characteristics Item Symbol STANDARD MODE FAST MODE Min. Max. Min. Max. Unit SCL clock frequency fSCL 0 100 0 400 kHz Time the bus must be free before a new transmission can start tBUF 4.7 - 1.3 - µs tHD:STA 4.0 - 0.6 - µs LOW period of the SCL clock tLOW 4.7 - 1.3 - µs HIGH period of the SCL clock tHIGH 4.0 - 0.6 - µs Set-up time for a repeated START condition tSU:STA 4.7 - 0.6 - µs Data hold time tHD:DAT 0 3.45 0 0.9 µs Data set-up time tSU:DAT 250 - 100 - ns Rise time of both SDA and SCL signals tR - 1000 - 300 ns Fall time of both SDA and SCL signals tF - 300 - 300 ns tSU:STO 4.0 - 0.6 - µs Cb - 400 - 400 pF Hold time (repeated) START condition After this period, the first clock pulse is generated. Set-up time for STOP condition Capacitive load of bus line Above values correspond with input level (VIHmin / VILmax). Timing Chart tR, tF tBUF VIH SDA VIL tHD:STA tSU:DAT tHD:DAT tSU:STA tSU:STO VIH SCL VIL tLOW Start R03DS0013EJ0100 Rev.1.00 2011.09.05 tHIGH Start Stop Start Page 4 of 8 New Product R2A20152NS/SP I2C BUS Format STA W Slave address A A Sub address DAC data A STP Note: STA: START condition, W: write (SDA = Low), A: acknowledge bit, STP: STOP condition Slave address First 1 Last 0 0 1 1 1 0 Sub address First X Last X X X X X X Channel select data S0 S0 Channel Selection 0 1 Don’t care ch1 selection ch2 selection Channel Select data DAC data First MSB D7 Last LSB D6 D5 D4 D3 D2 D1 D0 First MSB Last LSB D7 D6 D5 D4 D3 D2 D1 D0 DAC output 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 Vcc / 256 X 1 Vcc / 256 X 2 Vcc / 256 X 3 Vcc / 256 X 4 : : : : : : : : : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 Vcc / 256 X 255 Vcc R03DS0013EJ0100 Rev.1.00 2011.09.05 Page 5 of 8 New Product R2A20152NS/SP Data Timing Chart SCL and SDA (Model) < START condition to sleve address bit > SDA 1 2 3 4 5 6 7 W A 2 3 4 5 6 7 8 A SCL START condition D/A output < Sub address bit > SDA 1 SCL D/A output < DAC data bit to STOP condition > SDA 1 2 3 4 5 6 7 8 A SCL D/A output STOP condition START condition With SCL at High, SDA goes from High to Low. STOP condition With SCL at High, SDA goes from Low to High. ( Under normal condition, SDA must be changed, when SCL is Low. ) Acknowledge bit The receiving IC has to pull down SDA line whenever receive slave data (Transmitting IC releases the SDA line just then transmit 8-bit data.) R03DS0013EJ0100 Rev.1.00 2011.09.05 Page 6 of 8 New Product R2A20152NS/SP Digital Data Formats STA Slave address Sub address 2 A W A DAC data 2 Sub address 1 A A DAC data 1 Sub address n A A DAC data n A STP Note: After START condition, the master IC (MCU etc.) accesses the slave IC by slave address, and transmits the data to each channel by two bytes (sub address and DAC data). Precaution for Use 1. Supply voltage terminal (VCC) is also used for D/A converter upper reference voltage setting. If ripple or spike is input this terminal, accuracy of D/A conversion is down. So, when use this device, please connect capacitor among VCC to GND for stable D/A conversion. 2. This IC’s output amplifier has an advantage to capacitive load. So it’s no problem at device action when the capacitor (0.1µF Max) is connected among output to GND for every noise elimination. Standard Application Circuit Analog output terminals 2 Ao2 3 N.C 4 Vcc Ao1 R2A20152NS/SP 1 N.C 8 + 10F 5V 5V SCL 7 MCU SDA 6 GND 5 Ordering Information Order part No. Package Name Package Code Package type No. Packing/Quantity R2A20152SP SOP-8 PRSP0008DE-C SP Embossed Taping/2,500 pcs. R2A20152NS SON-8 PWSN0008KA-A NS Embossed Taping/5,000 pcs. R03DS0013EJ0100 Rev.1.00 2011.09.05 Page 7 of 8 R2A20152NS/SP New Product Package Dimensions PRSP0008DE-C [SP] PWSN0008KA-A [NS] R03DS0013EJ0100 Rev.1.00 2011.09.05 Page 8 of 8 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. 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