PO54G00A, PO74G00A

PO54G00A, PO74G00A
www.potatosemi.com
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
54, 74 Series Noise Cancellation GHz Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Specified From –40°C to 85°C, –40°C to 125°C,
and –55°C to 125°C
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 750MHz with 5pf load
. Operating frequency up to 350MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Latch-Up Performance Exceeds 250 mA Per
JESD 17
. ESD Protection Exceeds JESD 22
. 5000-VHuman-BodyModel (A114-A)
. 200-VMachineModel (A115-A)
. Available in 14pin 150mil wide SOIC package
. Available in 14pin Ceramic Dual Flatpack
. Available in 20pin Leadless Ceramic Chip Carrier
Potato Semiconductor’s PO74G00A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL/CMOS output
frequency with less than 1.5ns propagation delay.
This quadruple 2-input positive-NAND gate is
designed for 1.65-V to 3.6-V VCC operation.
The PO74G00A performs the Boolean function
Y= A B or Y= A + B in positive logic.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
1
14
2
13
1Y
3
12
2A
4A
4
11
4Y
5
10
3B
6
9
3A
7
8
3Y
1B
2B
2Y
GND
V CC
4B
Pin Description
INPUTS
B
OUTPUT
Y
H
H
L
L
X
H
Potato Semiconductor Corporation
L
4
3 2 1 20 19
18
6
16
5
7
8
17
15
14
9 10 11 12 13
4A
NC
4Y
NC
3B
Logic Block Diagram
A
X
1Y
NC
2A
NC
2B
2Y
GND
NC
3Y
3A
1A
1B
1A
NC
VCC
4B
Pin Configuration
A
B
Y
H
1
01/01/10
PO54G00A, PO74G00A
www.potatosemi.com
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
54, 74 Series Noise Cancellation GHz Logic
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-55 to 125
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
5.5
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = 5.5V
-
-
5
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-5
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Potato Semiconductor Corporation
2
01/01/10
PO54G00A, PO74G00A
www.potatosemi.com
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
54, 74 Series Noise Cancellation GHz Logic
Power Supply Characteristics
Symbol
IccQ
Description
Quiescent Power Supply Current
Test Conditions (1)
Min
Typ
Max
Unit
Vcc=Max, Vin=Vcc or GND
-
0.1
40
uA
Notes:
1.
2.
3.
4.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
Capacitance
Parameters (1)
Description
Cin
Cout
Test Conditions
Typ
Unit
Input Capacitance
Vin = 0V
4
pF
Output Capacitance
Vout = 0V
6
pF
Test Conditions (1)
M ax
Unit
Notes:
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
tPLH
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tPHL
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tr/tf
Rise/Fall Time
0.8V – 2.0V
0.8
ns
fmax
Input Frequency
CL =15pF
350
MHz
fmax
Input Frequency
CL = 5pF
750
MHz
fmax
Input Frequency
CL = 2pF
1125
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
Potato Semiconductor Corporation
3
01/01/10
PO54G00A, PO74G00A
www.potatosemi.com
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
54, 74 Series Noise Cancellation GHz Logic
Test Waveforms
Propagation Delay
3V
1.5V
Input
0V
tPHL
tPLH
VoH
2.0V
1.5V
0.8V
VoL
Output
tf
tR
Test Circuit
Vcc
Pulse
Generator
50Ohm
Potato Semiconductor Corporation
D.U.T.
15pF
to
2pF
4
01/01/10
PO54G00A, PO74G00A
www.potatosemi.com
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
54, 74 Series Noise Cancellation GHz Logic
Packaging Mechanical Drawing: 14 pin 150mil SOIC
0.244 6.20
0.228 5.80
0.010
0.007
0.050 1.27
0.016 0.40
0.25
0.17
X.XX Denotes dimensions in inches
X.XX
X.XX
Denotes dimensions in millimenters
X.XX
Packaging Mechanical Drawing: 14pin Leadless Ceramic Chip Carrier
X.XX Denotes dimensions in inches
X.XX
X.XX
Denotes dimensions in millimenters
X.XX
Potato Semiconductor Corporation
5
01/01/10
PO54G00A, PO74G00A
www.potatosemi.com
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
54, 74 Series Noise Cancellation GHz Logic
Packaging Mechanical Drawing: 20pin Ceramic Dual Flatpack
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
3
0.358 (9,09)
0.342 (8,69)
2
1
13
12
4
18
5
17
6
16
0.358 (9,09)
7
0.307 (7,80)
15
8
14
9
10
11
12
X.XX Denotes dimensions in inches
X.XX
X.XX
Denotes dimensions in millimenters
X.XX
13
IC Ordering Information
Ordering Code
Package
Top-Marking
TA
PO74G00ASU for Tube
14pin SOIC
Pb-free & Green
POTATO74G00AS
-40 C to 125 C
PO74G00ASR for Tape & Reel
14pin SOIC
Pb-free & Green
POTATO74G00AS
-40 C to 125 C
PO54G00ALU for Tube
14pin Leadless
Ceramic Chip Carrier
Pb-free & Green
POTATO54G00AL
-55 C to 125 C
PO54G00AFU for Tube
20pin Ceramic
Dual Flatpack
Pb-free & Green
POTATO54G00AF
-55 C to 125 C
IC Package Information
PACKAGE
TYPE
TAPE
WIDTH
(mm)
TAPE
PITCH
(mm)
PIN 1 LOCATION
TAPE TRAILER
LENGTH
QTY
PER REEL
TAPE LEADER
LENGTH
QTY
PER
TUBE
S
SOIC 14
16
8
Top Left Corner
39 (12”)
3000
64 (20”)
55
L
LCCC 20
N/A
N/A
N/A
N/A
N/A
N/A
55
F
CFP 14
N/A
N/A
N/A
N/A
N/A
N/A
150
PACKAGE
CODE
Potato Semiconductor Corporation
6
01/01/10