Data Sheet(eng)

EM78F
648/644/642/641N
548/544/542/541N
Flash Series 8-Bit
Microcontroller
Product
Specification
DOC. VERSION 1.2
ELAN MICROELECTRONICS CORP.
March 2013
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2010~2013 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
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other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall
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NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
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Tel: +886 3 563-9977
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Elan (HK) Microelectronics
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Fax: +1 408 366-8225
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Shenzhen:
Shanghai:
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Company, Ltd.
Elan Microelectronics
Shenzhen, Ltd.
Elan Microelectronics
Shanghai, Ltd.
301 Dong-A Building
632 Kojan-Dong, Namdong-ku
Incheon City, KOREA
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[email protected]
Headquarters:
st
Contents
Contents
1
General Description .................................................................................................. 1
2
Features ..................................................................................................................... 1
2.1
3
4
Features Selection Guide................................................................................... 2
Pin Assignment ......................................................................................................... 3
3.1
EM78F648N / 548N Pin Assignment.................................................................. 3
3.2
EM78F644N / 544N Pin Assignment.................................................................. 4
3.3
EM78F642N / 542N Pin Assignment.................................................................. 4
3.4
EM78F641N / 541N Pin Assignment.................................................................. 5
Pin Description.......................................................................................................... 5
4.1
EM78F648N / 548N Pin Description .................................................................. 5
4.2
EM78F644N / 544N Pin Description .................................................................. 8
4.3
EM78F642N / 542N Pin Description ................................................................ 10
4.4
EM78F641N / 541N Pin Description ................................................................ 11
5
Block Diagram ......................................................................................................... 12
6
Functional Description ........................................................................................... 13
6.1
Operational Registers (for EM78F644/642/641/544/542/541N Series only) .... 13
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
6.1.13
6.1.14
6.1.15
6.1.16
6.1.17
6.1.18
6.1.19
6.1.20
R0 (Indirect Addressing Register) .....................................................................13
R1 (Timer Clock/Counter) .................................................................................13
R2 (Program Counter and Stack)......................................................................13
R3 (Status Register)..........................................................................................16
R4 (RAM Select Register).................................................................................16
Bank 0 R5 (Port 5) ............................................................................................16
Bank 0 R6 (Port 6) ............................................................................................17
Bank 0 R7 (Port 7) ............................................................................................17
Bank 0 R8 (Port 8) ............................................................................................17
Bank 0 R9 (TBLP: Table Point Register for Instruction TBRD).........................17
Bank 0 RA (Wake-up Control Register) ............................................................18
Bank 0 RB (EEPROM Control Register)...........................................................18
Bank 0 RC (256 Bytes EEPROM Address) ......................................................19
Bank 0 RD (256 Bytes EEPROM Data) ............................................................19
Bank 0 RE (Mode Select Register) ...................................................................20
Bank 0 RF (Interrupt Status Register 1)............................................................21
R10 ~ R3F.........................................................................................................22
Bank 1 R5 TC1CR (Timer 1 Control) ................................................................22
Bank 1 R6 TCR1DA (Timer 1 Data Buffer A) ....................................................24
Bank 1 R7 TCR1DB (Timer 1 Data Buffer B)....................................................24
Product Specification (V1.2) 03.15.2013
• iii
Contents
6.1.21
6.1.22
6.1.23
6.1.24
6.1.25
6.1.26
6.1.27
6.1.28
6.1.29
6.1.30
6.1.31
6.1.32
6.1.33
6.1.34
6.1.35
6.1.36
6.1.37
6.1.38
6.1.39
6.1.40
6.1.41
6.1.42
6.1.43
6.1.44
6.1.45
6.2
Special Function Registers (EM78F644/642/641/544/542/541N Series only) . 42
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
6.2.12
6.2.13
iv •
Bank 1 R8 TC2CR (Timer 2 Control) ................................................................25
Bank 1 R9 TC2DH (Timer 2 High Byte Data Buffer).........................................29
Bank 1 RA TC2DL (Timer 2 Low Byte Data Buffer) ..........................................29
Bank 1 RB SPIS (SPI Status Register) .............................................................29
Bank 1 RC SPIC (SPI Control Register) ...........................................................30
Bank 1 RD SPIRB (SPI Read Buffer) ...............................................................31
Bank 1 RE SPIWB (SPI Write Data Buffer) ......................................................32
Bank 1 RF (Interrupt Status Register 2)............................................................32
Bank 2 RA URC1 (UART Control 1) .................................................................32
Bank 2 RB URC2 (UART Control 2) .................................................................33
Bank 2 RC URS (UART Status) ........................................................................34
Bank 2 RD URRD (UART_RD Data Buffer)......................................................35
Bank 2 RE URTD (UART_TD Data Buffer).......................................................35
Bank 2 RF (Pull-high Control Register 1) .........................................................35
Bank 3 R5 (TMRCON: Timer A and Timer B Control Register) ........................36
Bank 3 R6 (TBHP: Table Pointer Register for Instruction TBRD) .....................36
Bank 3 R7 (CMPCON: Comparator 2 Control Register
and PWMA/B Control Register) ........................................................................37
Bank 3 R8 (PWMCON: PWMA/B Lower 2 Bits of the Period
and Duty Control Register) ...............................................................................37
Bank 3 R9 (PRDAH: Most Significant Byte of PWMA) .....................................38
Bank 3 RA (DTAH: Most Significant Byte of PWMA Duty Cycle)......................38
Bank 3 RB (PRDBH: Most Significant Byte of PWMB).....................................38
Bank 3 RC (DTBH: Least Significant Byte of PWMB Duty Cycle)....................38
Bank 3 RD TC3CR (Timer 3 Control)................................................................39
Bank 3 RE TC3D (Timer 3 Data Buffer)............................................................41
Bank 3 RF (Pull-Down Control Register 1) .......................................................41
A (Accumulator).................................................................................................42
CONT (Control Register)...................................................................................42
IOC5 (I/O Port 5 Control Register)....................................................................43
IOC6 (I/O Port 6 Control Register)....................................................................43
IOC7 (I/O Port 7 Control Register)....................................................................44
IOC8 (I/O Port 8 Control Register)....................................................................44
IOC9..................................................................................................................44
IOCA (WDT Control Register)...........................................................................44
IOCB (Pull-Down Control Register 2) ...............................................................45
IOCC (Open-Drain Control Register) ................................................................46
IOCD (Pull-High Control Register 2) .................................................................46
IOCE (Interrupt Mask Register 2) .....................................................................47
IOCF (Interrupt Mask Register 1)......................................................................48
Product Specification (V1.2) 03.15.2013
Contents
6.3
Operational Registers for EM78F648/548N ..................................................... 49
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.3.13
6.3.14
6.3.15
6.3.16
6.3.17
6.3.18
6.3.19
6.3.20
6.3.21
6.3.22
6.3.23
6.3.24
6.3.25
6.3.26
6.3.27
6.3.28
6.3.29
6.3.30
6.3.31
6.3.32
6.3.33
6.3.34
6.3.35
6.3.36
6.3.37
6.3.38
6.3.39
6.3.40
6.3.41
R0: IAR (Indirect Addressing Register) .............................................................49
R1: BSR (Bank Selection Control Register) .....................................................49
R2: PC (Program Counter) ...............................................................................49
R3: SR (Status Register)...................................................................................53
R4: RSR (RAM Select Register) .......................................................................54
Bank 0 R5 ~ R9 (Port 5 ~ Port 9)......................................................................54
Bank 0 RA (Not Used).......................................................................................54
Bank 0 RB OMCR (Operating Mode Control Register) ....................................54
Bank 0 RC: ISR1 (Interrupt Status Register 1) .................................................56
Bank 0 RD: ISR2 (Interrupt Status Register 2) .................................................57
Bank 0 RE: ISR3 (Interrupt Status Register 3) .................................................57
Bank 0 RF .........................................................................................................58
Bank 0 R10: EIESCR (External Interrupt Edge Select Control Register) .........58
Bank 0 R11: WDTCR ........................................................................................58
Bank 0 R12: LVDCR (Low Voltage Detector Control Register) ........................59
Bank 0 R13: TCCCR (TCC Control Register)...................................................59
Bank 0 R14: TCCDATA (TCC Data Register) ...................................................60
Bank 0 R15~R19 (IOCR5~IOCR9) ...................................................................60
Bank 0 R1A~R1B..............................................................................................60
Bank 0 R1C: IMR1 (Interrupt Mask Register 1) ................................................60
Bank 0 R1D: IMR2 (Interrupt Mask Register 2) ................................................61
Bank 0 R1E: IMR3 (Interrupt Mask Register 3) ................................................62
Bank 0 R1F .......................................................................................................62
Bank 0 R20: P5WUCR (Port 5 Wake Up Control Register)..............................63
Bank 0 R21: P5WUECR (Port 5 Wake-up Edge Control Register) ..................63
Bank 0 R22: P7WUCR (Port 7 Wake-up Control Register) ..............................63
Bank 0 R23: P7WUECR (Port 7 Wake-up Edge Control Register) ..................63
Bank 0 R24~R2A ..............................................................................................63
Bank 0 R2B: SPICR (SPI Control Register) .....................................................64
Bank0 R2C: SPIS (SPI Status Register)...........................................................65
Bank 0 R2D: SPIR (SPI Read Buffer Register) ................................................65
Bank 0 R2E: SPIR (SPI Write Buffer Register).................................................65
Bank 0 R2F: WUCR1 (Wake-up Control Register 1) ........................................66
Bank 0 R30~R31...............................................................................................66
Bank 0 R32: URCR1 (UART Control Register 1)..............................................67
Bank 0 R33: URCR2 (UART Control Register 2)..............................................67
Bank 0 R34: URS (UART Status Register) .......................................................68
Bank 0 R35: URRD (UART Receive Data Buffer Register) ..............................69
Bank 0 R36: URTD (UART Transmit Data Buffer Register)..............................69
Bank 0 R37: TBPTL (Table Pointer Low Register)............................................69
Bank 0 R38: TBPTH (Table Pointer High Register) ..........................................69
Product Specification (V1.2) 03.15.2013
•v
Contents
6.3.42
6.3.43
6.3.44
6.3.45
6.3.46
6.3.47
6.3.48
6.3.49
6.3.50
6.3.51
6.3.52
6.3.53
6.3.54
6.3.55
6.3.56
6.3.57
6.3.58
6.3.59
6.3.60
6.3.61
6.3.62
6.3.63
6.3.64
6.3.65
6.3.66
6.3.67
6.3.68
6.3.69
6.3.70
6.3.71
6.3.72
6.3.73
6.3.74
6.3.75
6.3.76
6.3.77
6.3.78
6.3.79
6.3.80
6.3.81
6.3.82
vi •
Bank 0 R39: CMP1CR (Comparator 1 Control Register) .................................69
Bank 0 R3A~R3B..............................................................................................70
Bank 0 R3C: CMP2CR (Comparator 2 Control Register).................................71
Bank 0 R3D~R42 ..............................................................................................72
Bank 0 R43: CPIRLCON (Comparator Internal Reference Level
Control Register)...............................................................................................72
Bank 0 R44~R47...............................................................................................72
Bank 0 R48: TC1CR (Timer 1 Control Register)...............................................72
Bank 0 R49: TCR1DA (Timer 1 Data Buffer A) .................................................75
Bank 0 R4A: TCR1DB (Timer 1 Data Buffer B) ................................................75
Bank 0 R4B: TC2CR (Timer 2 Control Register) ..............................................75
Bank 0 R4C: TCR2DH (Timer 2 High Byte Data Buffer Register) ....................77
Bank 0 R4D: TCR2DL (Timer 2 Low Byte Data Buffer Register)......................78
Bank 0 R4E: TC3CR (Timer 3 Control Register) ..............................................78
Bank 0 R4F: TCR3D (Timer 3 Duty Buffer Register) ........................................80
Bank 1 R5: P5PHCR (Port 5 Pull High Control Register).................................80
Bank 1 R6: P6PHCR (Port 6 Pull High Control Register).................................81
Bank 1 R7: P7PHCR (Port 7 Pull High Control Register).................................81
Bank 1 R8: P8PHCR (Port 8 Pull High Control Register).................................81
Bank 1 R9: P9PHCR (Port 9 Pull High Control Register).................................82
Bank 1 RA .........................................................................................................82
Bank 1 RB: P5PLCR (Port 5 Pull Low Control Register) ..................................82
Bank 1 RC: P6PLCR (Port 6 Pull Low Control Register)..................................83
Bank 1 RD: P7PLCR (Port 7 Pull Low Control Register)..................................83
Bank 1 RE: P8PLCR (Port 8 Pull Low Control Register) ..................................84
Bank 1 RF: P9PLCR (Port 9 Pull Low Control Register) ..................................84
Bank 1 R10 .......................................................................................................84
Bank 1 R11: P5HD/SCR (Port 5 High Drive/Sink Control Register) .................84
Bank 1 R12: P6HD/SCR (Port 6 High Drive/Sink Control Register).................85
Bank 1 R13: P7HD/SCR (Port 7 High Drive/Sink Control Register).................85
Bank 1 R14: P8HD/SCR (Port 8 High Drive/Sink Control Register).................85
Bank 1 R15: P9HD/SCR (Port 9 High Drive/Sink Control Register).................85
Bank 1 R16 .......................................................................................................85
Bank 1 R17: P5ODCR (Port 5 Open Drain Control Register) ..........................86
Bank 1 R18: P6ODCR (Port 6 Open Drain Control Register) ..........................86
Bank 1 R19: P7ODCR (Port 7 Open Drain Control Register) ..........................86
Bank 1 R1A: P8ODCR (Port 8 Open Drain Control Register) ..........................86
Bank 1 R1B: P9ODCR (Port 9 Open Drain Control Register) ..........................86
Bank 1 R1C.......................................................................................................87
Bank 1 R1D: IRCS (IRC Frequency Selection Register) ..................................87
Bank 1 R1E .......................................................................................................87
Bank 1 R1F: EEPROM Control.........................................................................87
Product Specification (V1.2) 03.15.2013
Contents
6.3.83
6.3.84
6.3.85
6.3.86
6.3.87
6.3.88
6.3.89
6.3.90
6.3.91
6.3.92
6.3.93
6.3.94
6.3.95
6.3.96
6.3.97
6.3.98
6.3.99
6.3.100
6.3.101
6.3.102
6.3.103
6.3.104
6.3.105
6.3.106
6.3.107
6.3.108
6.3.109
6.3.110
6.3.111
Bank 1 R20: EEPROM ADDR........................................................................88
Bank 1 R21: EEPROM DATA.........................................................................88
Bank1 R22......................................................................................................88
Bank1 R23: I2CCR1 (I2C Status and Control Register 1) .............................88
Bank 1 R24: I2CCR2 (I2C Status and Control Register2) .............................89
Bank 1 R25: I2CSA (I2C Slave Address Register).........................................90
Bank 1 R26: I2CDA (I2C Device Address Register) ......................................90
Bank 1 R27: I2CDB (I2C Data Buffer Register) .............................................91
Bank 1 R28: I2CA (I2C Data Buffer Register) ................................................91
Bank 1 R29.....................................................................................................91
Bank 1 R2A: PWMER (PWM Enable Control Register).................................91
Bank 1 R2B: TIMEN (Timer/PWM Enable Control Register) .........................91
Bank 1 R2C~R2E...........................................................................................92
Bank 1 R2F: PWMACR (PWM A Control Register) .......................................92
Bank 1 R30: PWMBCR (PWM B Control Register) .......................................92
Bank 1 R31.....................................................................................................92
Bank 1 R32: TACR (Timer A Control Register) ..............................................92
Bank1 R33: TBCR (Timer B Control Register)...............................................93
Bank 1 R34.....................................................................................................93
Bank 1 R35: TAPRDH (Timer A Period Buffer Register) ................................93
Bank 1 R36: TBPRDH (Timer B Period Buffer Register) ...............................93
Bank 1 R37.....................................................................................................93
Bank 1 R38: TADTH (Timer A Duty Buffer Register)......................................93
Bank 1 R39: TBDTH (Timer B Duty Buffer Register) .....................................93
Bank1 R3A .....................................................................................................93
Bank 1 R3B: PRDxL (PWM A/B/C Period Buffer Low Bits Register) .............94
Bank 1 R3C: DTxL (PWM1/2 Duty Buffer Low Bits Register) ........................94
Bank 1 R3D~R4F ...........................................................................................94
Bank 0 R50~R7F, Bank0~1 R80~RFF...........................................................94
6.4
TCC/WDT and Prescaler.................................................................................. 94
6.5
I/O Ports ........................................................................................................... 95
6.5.1
6.5.2
6.6
I/O for EM78F644N/642/641/544/542/541N .....................................................95
I/O for EM78F648/548N....................................................................................96
UART (Universal Asynchronous Receiver/Transmitter).................................... 97
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
UART Mode.......................................................................................................98
Transmitting.......................................................................................................98
Receiving .........................................................................................................99
Baud Rate Generator........................................................................................99
UART Timing .....................................................................................................99
Product Specification (V1.2) 03.15.2013
• vii
Contents
6.7
SPI Function................................................................................................... 100
6.7.1
6.7.2
6.7.3
6.7.4
6.8
I2C Function ................................................................................................... 106
6.8.1
6.8.2
6.8.3
6.8.2
6.9
Overview and Features...................................................................................100
6.7.1.1 Overview ......................................................................................... 100
6.7.1.2 Features .......................................................................................... 100
SPI Function Description ................................................................................102
SPI Signal and Pin Description .......................................................................103
SPI Mode Timing.............................................................................................105
7-Bit Slave Address.........................................................................................108
10-Bit Slave Address.......................................................................................108
6.8.2.1 Master-Transmitter Transmits to Slave-Receiver
with a 10-bit Slave Address .......................................................................... 109
6.8.2.2 Master-Receiver Reads from Slave-Transmitter
with a 10-bit Slave Address .......................................................................... 109
6.8.2.3 Master Transmits and Receives Data to and from
the Same Slave Device with 10-Bit Addresses ............................................ 110
6.8.2.4 Master Device Transmits Data to Two or More
Slave Devices with 10 and 7 Bits Slave Address ......................................... 110
Master Mode I2C Transmit.............................................................................. 112
Slave Mode I2C Transmit................................................................................ 112
Dual Set of PWM (Pulse Width Modulation)................................................... 112
6.9.1
6.9.2
6.9.3
6.9.4
Overview ......................................................................................................... 112
Increment Timer Counter (TMRX: TMRAH/L or TMRBH/L)............................ 113
PWM Period (PRDX: PRDA or PRDB) ........................................................... 114
PWM Duty Cycle (DTX: DTA or DTB) ............................................................. 114
6.10 Comparator .................................................................................................... 115
6.10.1
6.10.2
6.10.3
6.10.4
6.10.5
External Reference Signal .............................................................................. 115
Internal Reference Signal ............................................................................... 115
Comparator Outputs........................................................................................ 116
Interrupt........................................................................................................... 116
Wake-up from Sleep Mode ............................................................................. 117
6.11 Reset and Wake-up........................................................................................ 117
6.11.1 Reset and Wake-up for EM78F644/642/641/544/542/541N........................... 117
6.11.2 Reset and Wake-up for EM78F648/548N.......................................................128
6.11.3 The Status of RST, T, and P of STATUS Register...........................................143
6.12 Interrupt .......................................................................................................... 144
6.12.1 Interrupt for EM78F644/642/641/544/542/541N ..............................................144
6.12.2 Interrupt for EM78F648/548N .........................................................................146
6.13 LVD (Low Voltage Detector) for EM78F648/548N.......................................... 147
6.13.1 LVD Level Control ...........................................................................................147
6.13.2 LVD Interrupt ...................................................................................................148
6.13.3 LVD Function Setup ........................................................................................148
viii •
Product Specification (V1.2) 03.15.2013
Contents
6.14 Data EEPROM ............................................................................................... 150
6.15 Oscillator ........................................................................................................ 150
6.15.1
6.15.2
6.15.3
6.15.4
Oscillator Modes .............................................................................................150
Crystal Oscillator/Ceramic Resonators (XTAL)...............................................151
External RC Oscillator Mode...........................................................................152
Internal RC Oscillator Mode............................................................................153
6.16 Power-on Considerations ............................................................................... 154
6.17 External Power-on Reset Circuit .................................................................... 154
6.18 Residue-Voltage Protection ............................................................................ 155
6.19 Code Option Register..................................................................................... 156
6.19.1 Code Option Register (Word 0) ......................................................................156
6.19.1.1 EM78F644/642/641/544/542/541N Code Option Word 0............... 156
6.19.1.1 EM78F648/548 Code Option Word 0 ............................................. 158
6.19.2 Code Option Register (Word 1) ......................................................................159
6.19.2.1 EM78F644/642/641/544/542/541N Code Option Word 1............... 159
6.19.2.2 EM78F648/548N Code Option Word 1........................................... 160
6.19.3 Customer ID Register (Word 2) ......................................................................161
6.19.3.1 EM78F644/642/641/544/542/541N Code Option Word 2............... 161
6.19.3.2 EM78F648/548N Code Option Word 2........................................... 161
6.20 Instruction Set ................................................................................................ 161
6.20.1 Instruction Set Table........................................................................................162
7
8
Timing Diagram ..................................................................................................... 166
7.1
AC Test Input/Output Waveform ..................................................................... 166
7.2
Reset Timing (CLK1:0 = "01") ........................................................................ 166
Absolute Maximum Ratings ................................................................................. 167
8.1
9
For EM78F648/548N...................................................................................... 167
DC Electrical Characteristics ............................................................................... 167
9.1
For EM78F648/548N...................................................................................... 167
9.1.1
9.1.2
9.1.3
9.2
For EM78F644/544N...................................................................................... 170
9.2.1
9.2.2
9.2.3
9.3
Program Flash Memory Electrical Characteristics..........................................169
Data EEPROM Electrical Characteristics (for EM78F648N only)..................169
Comparator Electrical Characteristics.............................................................169
Program Flash Memory Electrical Characteristics..........................................172
Data EEPROM Electrical Characteristics (for EM78F644N only)..................172
Comparator Electrical Characteristics.............................................................172
EM78F642/542N ............................................................................................ 173
9.3.1
9.3.2
9.3.3
Program Flash Memory Electrical Characteristics..........................................175
Data EEPROM Electrical Characteristics (for EM78F642N only)..................175
Comparator Electrical Characteristics.............................................................175
Product Specification (V1.2) 03.15.2013
• ix
Contents
9.4 EM78F641/541N .............................................................................................. 176
9.4.1
9.4.2
9.4.3
10
Program Flash Memory Electrical Characteristics..........................................178
Data EEPROM Electrical Characteristics (for EM78F641N only)..................178
Comparator Electrical Characteristics.............................................................178
AC Electrical Characteristics ............................................................................... 179
10.1 EM78F648/548N ............................................................................................ 179
10.2 EM78F644/642/641/544/542/541N ................................................................ 179
APPENDIX
A
Package Type......................................................................................................... 180
A.1 Green Products Compliance .......................................................................... 180
B
Packaging Configuration...................................................................................... 181
B.1 EM78F648/548N ............................................................................................ 181
B.1.1
B.1.2
B.1.3
B.1.4
B.1.5
44-Pin QFP Package ......................................................................................181
40-Pin DIP Package........................................................................................182
28-Pin Skinny DIP Package............................................................................183
28-Pin DIP Package........................................................................................184
28-Pin SOP Package ......................................................................................185
B.2 EM78F644/544N ............................................................................................ 186
B.2.1
B.2.2
B.2.3
B.2.4
28-Pin Skinny DIP Package............................................................................186
28-Pin SOP Package ......................................................................................187
24-Pin Skinny DIP Package............................................................................188
24-Pin SOP Package ......................................................................................189
B.3 EM78F642/542N ............................................................................................ 190
B.3.1
B.3.2
B.3.3
B.3.4
B.3.5
20-Pin DIP Package........................................................................................190
20-Pin SOP Package ......................................................................................191
20-Pin SSOP Package....................................................................................192
18-Pin DIP Package........................................................................................193
18-Pin SOP Package ......................................................................................194
B.4 EM78F641/541N ............................................................................................ 195
B.4.1
B.4.2
B.4.3
C
16-Pin DIP Package........................................................................................195
16-Pin SOP Package ......................................................................................196
10-Pin MSOP Package ...................................................................................197
Quality Assurance and Reliability ....................................................................... 198
C.1 Address Trap Detect....................................................................................... 198
x•
Product Specification (V1.2) 03.15.2013
Contents
Specification Revision History
Doc. Version
1.0
Revision Description
Initial release version
Date
2010/05/05
1. Modified the contents of the Operating Frequency
Range vs. Operating Voltage in Section 2 Features
2. Modified the description of the Control-bit TS.
1.1
3. Modified the descriptions in the Section TCC/WDT and
Prescaler.
2012/07/17
4. Modfied Figure 6-11 TCC and WDT Block Diagram.
5. Modified the maximum supportable baud rate of the
SPI function.
1.2
1. Modified the pin number of EM78F641/541N in
Figure 3-4
2. Added LVR specification in the DC Electrical
Characteristics section.
Product Specification (V1.2) 03.15.2013
2013/03/15
• xi
Contents
xii •
Product Specification (V1.2) 03.15.2013
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
1
General Description
The EM78F64xN/54xN Series are 8-bit microprocessors designed and developed with low-power, highspeed CMOS technology, and high noise immunity. Each of these MUCs are equipped with on-chip
1/2/4K×13-bit and 8Kx15-bit Electrical Flash Memory, but only the EM78F64xN are embedded with 256 or
128×8-bit in-system programmable EEPROM. Each provides three protection bits to prevent intrusion of
user’s Flash memory code. Twelve Code option bits are also available to meet user’s requirements.
With its enhanced Flash-ROM features, the EM78F64xN/54xN MUCs provide a convenient way of
developing and verifying user’s programs. Moreover, the Flash-ROM device offers the advantages of easy
and effective program updates with development and programming tools. Users can take advantage of
ELAN’s Writer to easily program their development codes.
2
Features

CPU Configuration

EM78F648N EM78F644N EM78F642N EM78F641N
CPU
EM78F548N EM78F544N EM78F542N EM78F541N
ROM
8K × 15 bits
4K × 13 bits
2K × 13 bits
1K × 13 bits
SRAM
304 × 8 bits
144 × 8 bits
80 × 8 bits
48 × 8 bits
256 bytes
256 bytes
128 bytes
128 bytes
(648N only)
(644N only)
(642N only)
(641N only)
8-Level
8-Level
8-Level
8-Level
EEPROM
STACK
LVR
Operating EM78F648N EM78F644N EM78F642N EM78F641N
Frequency EM78F548N EM78F544N EM78F542N EM78F541N
2.3 / 3.3 / 4.0
x
/ 4.5 V
x
x
• In-system programmable EEPROM
IRC Mode
•
•
•
•

DC ~ 20 MHz DC ~ 16 MHz DC ~ 16 MHz DC ~ 16 MHz
5 ~ 5.5V
4.5 ~ 5.5V
4.5 ~ 5.5V
4.5 ~ 5.5V
Available Interrupts
EM78F648N EM78F644N EM78F642N EM78F641N
EM78F548N EM78F544N EM78F542N EM78F541N
15
10
4
2
External
4
3
3
3
Peripheral Configuration
Function
I/O
EM78F648N EM78F644N EM78F642N EM78F641N
Port
EM78F548N EM78F544N EM78F542N EM78F541N
DC ~ 4 MHz
2.2 ~ 5.5V
Internal

I/O Port Configuration
DC~ 4 MHz
2.2 ~ 5.5V
DC ~ 8 MHz DC ~ 8 MHz DC ~ 8 MHz DC ~ 8 MHz
3 ~ 5.5V
3 ~ 5.5V
3 ~ 5.5V
3 ~ 5.5V
ERC Mode
Interrupt
Endurance: 1,000,000 write/erase cycles
More than 10 years data retention
Less than 1.5 mA at 5V / 4 MHz
Typically 20 μA, at 3V / 32kHz
Typically 1.5 μA, during Sleep mode
DC ~ 4 MHz DC ~ 4 MHz
2.4 ~ 5.5V
2.3 ~ 5.5V
Crystal Mode
4.2, 3.7, 2.7V 4.0, 3.5, 2.7V 4.0, 3.5, 2.7V 4.0, 3.5, 2.7V
LVD

Operating Frequency Range
(Base On Two Clocks)
EM78F648NEM78F644NEM78F642NEM78F641N
EM78F548NEM78F544NEM78F542NEM78F541N
Two channel
PWM
10-bit
resolution
10-bit
resolution
x
x
One 8-bit
Timer/counter
(TC1)
Timer
Counter
Capture
Timer
Counter
Capture
Timer
Counter
Capture
x
One 16-bit
Timer/counter
(TC2)
Timer
Counter
Window
Timer
Counter
Window
Timer
only
x
I/O
P5, P6, P7,
P8, P9
P5, P6,
P7, P8
P5, P6,
P7, P8
P5, P6,
P8
PullHigh
40
14
10
6
PullDown
40
14
7
5
Opendrain
40
8
8
6
Timer
Timer
Timer
Timer
One 8-bit
Counter
Counter
Counter
Counter
Timer/counter
PWM / PDO PWM / PDO PWM / PDO PWM / PDO
(TC3)
High
Sink
40
x
x
x
One-set
Comparator
High
Sink
40
x
x
x
• Wake-up port: P6
• External interrupt with Wake-up: P60
10mv
10mv
5mv
5mv
offset voltage offset voltage offset voltage offset voltage
• 8-bit real time clock/counter (TCC) with selective
signal sources, trigger edges, and overflow
interrupt
• External interrupt input pin
• 2-/4-/8-/16 clocks per instruction cycle selected
by code option
Product Specification (V1.2) 03.15.2013
•1
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
• Power down (Sleep) mode
• High EFT immunity
Operating Voltage Range

Operating EM78F648N EM78F644N EM78F642N EM78F641N
Voltage
Commercial
0°C~70°C
Industrial
-40°C~85°C
EM78F548N EM78F544N EM78F542N EM78F541N
2.4 ~ 5.5V
2.2 ~ 5.5V
2.2 ~ 5.5V
2.2 ~ 5.5V
2.6 ~ 5.5V
2.4 ~ 5.5V
2.4 ~ 5.5V
2.4 ~ 5.5V
Communciation Peripheral Configuration

Function
SPI
Special Features
• Programmable free running Watchdog Timer
• Power-on voltage detector available
(2.0V ~ 2.1V)

EM78F648N/548N Package Types
• 44-pin QFP 10x10 mm : EM78Fx48NQ44J/S
• 40-pin DIP 600 mil
:
EM78Fx48ND40J/S
• 28-pin SKDIP 300 mil : EM78Fx48NK28J/S
• 28-pin SOP 300 mil : EM78Fx48NSO28J/S

EM78F644N/544N Package Types
• 28-pin SKDIP 300 mil : EM78Fx44NK28J/S
• 28-pin SOP 300 mil : EM78Fx44NSO28J/S
• 24-pin SKDIP 300 mil : EM78Fx44NK24J/S
• 24-pin SOP 300 mil : EM78Fx44NSO24J/S

EM78F642N/542N Package Types
• 20-pin DIP 300 mil
:
EM78Fx42ND20J/S
• 20-pin SOP 300 mil : EM78Fx42NSO20J/S
• 20-pin SSOP 209 mil : EM78Fx42NSS20J/S
• 18-pin DIP 300 mil
:
EM78Fx42ND18J/S
• 18-pin SOP 300 mil : EM78Fx42NSO20J/S

EM78F641N/541N Package Types
• 16-pin DIP 300 mil
:
EM78Fx41NAD16J/S
• 16-pin SOP 150 mil :
EM78Fx41NASO16J/S
• 10-pin MSOP 118 mil : EM78Fx41NMS10J/S
EM78F648N EM78F644N EM78F642NEM78F641N
EM78F548N EM78F544N EM78F542NEM78F541N
Three wire
Three wire
synchronous
synchronous
x
x
communication communication
Two wire
UART

Two wire
Asynchronous Asynchronous
x
x
x
x
Process
Total
communication communication
7 / 10 bits
Address &
I2C
x
8 bits data
Internal RC Drift Rate

Drift Rate
Internal RC
Frequency
4 MHz
Temperature
Voltage
(-40°C~85°C) (2.2V~5.5V)
± 3%
± 5%
± 2.5%
± 10.5%
16 MHz
± 3%
± 5%
± 2.5%
± 10.5%
8 MHz
± 3%
± 5%
± 2.5%
± 10.5%
*455kHz
± 3%
± 5%
± 2.5%
± 10.5%
*NOT applicable to EM78F541N and EM78F641N
NOTE
These are Green Products which do not contain
hazardous substances.
2.1 Features Selection Guide
Timer
Program Data
I/O 8- 16- PWM
Memory Memory
bit bit
Part No.
VDD
EM78Fx48N
2.4 ~
5.5V
8K x 15
bits
304 x
8 bits
40
2.2 ~
5.5V
4K x 13
bits
144 x
8 bits
25
EM78Fx42N
2.2 ~
5.5V
2K x 13
bits
80 x 8
bits
18
2
EM78Fx41N
2.2 ~
5.5V
1K x 13
bits
48 x 8
bits
14
1
EM78Fx44N
2•
2
2
1
2 ch x
10
bits
UART
SPI
I2C
Package
Type
44 QFP
Two wire
Three wire
7 / 10 bits
synchronous
Asynchronous
Address &
40 DIP
communication
communication
8 bits data
28 SKDIP/SOP
2 ch x
10
bits
Two wire
Three wire
synchronous
Asynchronous
communication
communication
1
x
x
x
x
0
x
x
x
x
1
x
28 SKDIP/SOP
24 SKDIP/SOP
20 DIP/SOP
18 DIP/SOP
16 DIP/SOP
10 MSOP
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
3
Pin Assignment
3.1 EM78F648N / 548N Pin Assignment
28 Pin SKDIP/SOP
40-Pin DIP
44-Pin QFP
Figure 3-1 EM78F648N / 548N Pin Assignment
Product Specification (V1.2) 03.15.2013
•3
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
3.2 EM78F644N / 544N Pin Assignment
24-Pin SKDIP/SOP
28-Pin SKDIP/SOP
Figure 3-2 EM78F644N / 544N Pin Assignment
3.3 EM78F642N / 542N Pin Assignment
18-Pin DIP/SOP
20-Pin DIP/SOP/SSOP
Figure 3-3 EM78F642N / 542N Pin Assignment
4•
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
3.4 EM78F641N / 541N Pin Assignment
10-Pin DIP/SOP
16-Pin DIP/SOP/SSOP
Figure 3-4 EM78F641N / 541N Pin Assignment
4
Pin Description
4.1 EM78F648N / 548N Pin Description
Name
P50//SS
Function
Input
Type
P50
ST
/SS
ST
P51
P51/SDA/TX/SO
TX
ST
SO
P52/RX/SI
P53/SCK/SCL
Output
Type
CMOS
Description
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
SPI slave select pin
CMOS
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
CMOS
UART TX output
CMOS
SPI serial data output
CMOS
I2C serial data (open-drain)
SDA
ST
P52
ST
RX
ST
SI
ST
P53
ST
CMOS
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
SCK
ST
CMOS
SPI serial clock input/output
SCL
ST
CMOS
I2C serial clock (open-drain)
Product Specification (V1.2) 03.15.2013
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
CMOS
UART RX input
SPI serial data input
•5
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Name
Function
P54
P54/OSCI/RCOUT
P55
P56/TC2
P57/TC3/PDO
P61~P67
P70/CO1
ST
P72/CIN1-
P73
P74/TC1
P75/PWMA
CMOS
XTAL
Clock output of internal RC oscillator
Clock output of external RC oscillator (open-drain)
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
Clock output of crystal/resonator oscillator
P56
ST
TC2
ST
Timer 2 clock input
P57
ST
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
TC3
ST
P60
ST
/INT
ST
P61~P67
ST
P70
ST
CMOS
CMOS
External RC input pin
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
Timer 3 clock input
CMOS
Programmable divider output
CMOS
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink, high drive and pin change wakeup.
External interrupt pin
CMOS
CMOS
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink, high drive and pin change wakeup.
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
CMOS
Output of Comparator 1
CMOS
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
P71
ST
CIN1+
AN
Non-inverting end of Comparator 1
P72
ST
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
CIN1-
AN
P73
ST
P74
ST
CMOS
Inverting end of Comparator 1
CMOS
CMOS
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
TC1
CMOS
Timer 1 clock input
P75
CMOS
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
CMOS
PWMA output
CMOS
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
CMOS
PWMB output
P76
PWMB
6•
CMOS
AN
ST
PWMA
P76/PWMB
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
ERCin
CO1
P71/CIN1+
CMOS
Description
Clock input of crystal/resonator oscillator
XTAL
OSCO
PDO
P60//INT
ST
OSCI
RCOUT
P55/OSCO/ERCin
Input Output
Type
Type
ST
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Name
P77/TCC
P80/CO2
Function
Input
Type
P77
ST
TCC
ST
P80
ST
CO2
(DATA)
Output
Type
CMOS
Description
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
Real Time Clock/Counter clock input
CMOS
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
CMOS
Output of Comparator 2
CMOS
DATA pin for Writer programming
(DATA)
ST
P81
ST
CIN2+
AN
(CLK)
ST
P82
ST
CIN2-
AN
Inverting end of Comparator 2
P83
ST
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
/RESET
ST
(/RESET)
(/RESET)
ST
CMOS
P84~P87
P84~P87
ST
CMOS
P90~P97
P90~P97
ST
CMOS
VDD
VDD
Power
−
Power
VSS
VSS
Power
−
Ground
P81/CIN2+
(CLK)
P82/CIN2-
P83/RESET
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
CMOS
Clock pin for Writer programming
CMOS
CMOS
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
Internal pull-high reset pin
Legend: ST: Schmitt Trigger input
XTAL: oscillation pin for crystal/ resonator
Product Specification (V1.2) 03.15.2013
Non-inverting end of Comparator 2
/RESET pin for Writer programming
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high, high sink and high drive.
AN: analog pin
CMOS: CMOS output
•7
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
4.2 EM78F644N / 544N Pin Description
Name
P50//SS
Function
Input
Type
P50
ST
/SS
ST
P51
P51/TX/SO
TX
ST
SO
P52/RX/SI
P53/SCK
P54/OSCI/RCOUT
P57/TC3/PDO
Bidirectional I/O pin with programmable pull-down
SPI slave select pin
CMOS
Bidirectional I/O pin with programmable pull-down
CMOS
UART TX output
CMOS
SPI serial data output
ST
RX
ST
SI
ST
P53
ST
CMOS
Bidirectional I/O pin with programmable pull-down
SCK
ST
CMOS
SPI serial clock input/output
P54
ST
OSCI
P55
P56/TC2
CMOS
Description
P52
RCOUT
P55/OSCO/ERCin
Output
Type
OSCO
XTAL
ST
ERCin
AN
P56
ST
TC2
ST
P57
ST
TC3
PDO
ST
Bidirectional I/O pin with programmable pull-down
CMOS
UART RX input
SPI serial data input
CMOS
Bidirectional I/O pin
Clock input of crystal/ resonator oscillator
CMOS
Clock output of internal RC oscillator
Clock output of external RC oscillator(open-drain)
CMOS
Bidirectional I/O pin
XTAL
Clock output of crystal/ resonator oscillator
CMOS
External RC input pin
CMOS
CMOS
Bidirectional I/O pin
Timer 2 clock input
Bidirectional I/O pin
Timer 3 clock input
CMOS
Programmable divider output
CMOS
Bidirectional I/O pin with programmable pull-down, open
drain, pull-high and pin change wakeup.
P60
ST
/INT
ST
P61~P63
P61~P63
ST
CMOS
P64~P65
P64~P65
ST
CMOS
P66
ST
(CLK)
ST
P67
ST
CMOS
Bidirectional I/O pin with programmable open-drain, pullhigh and pin change wakeup.
(DATA)
ST
CMOS
Data pin for Writer programming
P60//INT
P66
(CLK)
P67
(DATA)
8•
External interrupt pin
CMOS
Bidirectional I/O pin with programmable pull-down, open
drain, pull-high and pin change wakeup.
Bidirectional I/O pin with programmable open-drain, pullhigh and pin change wakeup.
Bidirectional I/O pin with programmable open-drain, pullhigh and pin change wakeup.
Clock pin for Writer programming
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Name
Function
Input
Type
Output
Type
P72 ~ P73
P72~P73
ST
CMOS
P74/TC1
P75/PWMA
P74
ST
CMOS
Timer 1 clock input
P75
CMOS
Bidirectional I/O pin with programmable pull-down and
pull-high.
CMOS
PWMA output
CMOS
Bidirectional I/O pin with programmable pull-down and
pull-high.
CMOS
PWMB output
CMOS
Bidirectional I/O pin with programmable pull-down and
pull-high.
ST
P76
ST
PWMB
P77/TCC
P77
ST
TCC
ST
P80
P80/CO2
Bidirectional I/O pin with programmable pull-down and
pull-high.
Bidirectional I/O pin with programmable pull-down and
pull-high.
TC1
PWMA
P76/PWMB
CMOS
Description
CO2
ST
Real Time Clock/Counter clock input
CMOS
Bidirectional I/O pin
CMOS
Bidirectional I/O pin with programmable pull-down and
pull-high.
P81
ST
CIN2+
AN
P82
ST
CIN2-
AN
/RESET
ST
(/RESET)
ST
VDD
VDD
Power
−
Power
VSS
VSS
Power
−
Ground
P81/CIN2+
P82/CIN2/RESET
(/RESET)
CMOS
CMOS
CMOS
Legend: ST: Schmitt Trigger input
XTAL: oscillation pin for crystal / resonator
Product Specification (V1.2) 03.15.2013
Bidirectional I/O pin
Non-Inverting end of Comparator 2
Bidirectional I/O pin
Inverting end of Comparator 2
Internal pull-high reset pin
/RESET pin for Writer programming
AN: analog pin
CMOS: CMOS output
•9
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
4.3 EM78F642N / 542N Pin Description
Name
P50
P54/OSCI/RCOUT
Function
Input
Type
Output
Type
P50
ST
CMOS
P54
ST
OSCI
RCOUT
P55
P55/OSCO/ERCin
P57/TC3/PDO
OSCO
XTAL
ST
ERCin
AN
P57
ST
TC3
PDO
ST
CMOS
Description
Bidirectional I/O pin with programmable pull-down
Bidirectional I/O pin
Clock input of crystal/resonator oscillator
CMOS
Clock output of internal RC oscillator
Clock output of external RC oscillator (open-drain)
CMOS
Bidirectional I/O pin
XTAL
Clock output of crystal / resonator oscillator
CMOS
External RC input pin
Bidirectional I/O pin
CMOS
Timer 3 clock input
Programmable divider output
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high and pin change wakeup.
P60
ST
/INT
ST
P61~P63
P61~P63
ST
CMOS
P64~P65
P64~P65
ST
CMOS
P66
ST
(CLK)
ST
Clock pin for Writer programming
P67
ST
CMOS
Bidirectional I/O pin with programmable open-drain and
pull-high.
(DATA)
ST
CMOS
Data pin for Writer programming
CMOS
Bidirectional I/O pin with programmable pull-down and
pull-high.
CMOS
Timer 1 clock input
CMOS
Bidirectional I/O pin with programmable pull-down and
pull-high.
P60//INT
P66
(CLK)
P67
(DATA)
P74/TC1
P74
ST
TC1
P77/TCC
P80/CO2
P81/CIN2+
P82/CIN2-
10 •
P77
ST
TCC
ST
P80
CO2
ST
P81
ST
CIN2+
AN
P82
ST
CIN2-
AN
CMOS
External interrupt pin
CMOS
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high and pin change wakeup.
Bidirectional I/O pin with programmable open-drain, pullhigh and pin change wakeup.
Bidirectional I/O pin with programmable open-drain, pullhigh and pin change wakeup.
Real Time Clock/Counter clock input
CMOS
Bidirectional I/O pin
CMOS
Output of Comparator 2
CMOS
CMOS
Bidirectional I/O pin
Non-inverting end of Comparator 2
Bidirectional I/O pin
Inverting end of Comparator 2
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Function
Input
Type
P83
ST
/RESET
ST
(/RESET)
ST
CMOS
VDD
VDD
Power
−
Power
VSS
VSS
Power
−
Ground
Name
P83/RESET
(/RESET)
Output
Type
CMOS
Legend: ST: Schmitt Trigger input
XTAL: oscillation pin for crystal/ resonator
Description
Bidirectional I/O pin
Internal pull-high reset pin
/RESET pin for Writer programming
AN: analog pin,
CMOS: CMOS output
4.4 EM78F641N / 541N Pin Description
Name
P50
P54/OSCI/RCOUT
Function
Input
Type
Output
Type
P50
ST
CMOS
P54
ST
OSCI
RCOUT
P55
P55/OSCO/ERCin
P57/TC3/PDO
OSCO
XTAL
ST
CMOS
CMOS
Bidirectional I/O pin
XTAL
Clock output of crystal/ resonator oscillator
AN
CMOS
External RC input pin
P57
ST
CMOS
Bidirectional I/O pin
ST
CMOS
TC3
/INT
ST
P61~P63
P61~P63
ST
CMOS
P64~P65
P64~P65
ST
CMOS
(DATA)
Clock input of crystal/ resonator oscillator
CMOS
ST
P81/CIN2+
Bidirectional I/O pin
Clock output of internal RC oscillator
Clock output of external RC oscillator (open-drain)
P60
P80/CO2
Bidirectional I/O pin with programmable pull-down
ERCin
PDO
P60//INT
Description
P80
CO2
ST
P81
ST
CIN2+
AN
(DATA)
ST
Product Specification (V1.2) 03.15.2013
CMOS
Timer 3 clock input
Programmable divider output
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high and pin change wakeup.
External interrupt pin
Bidirectional I/O pin with programmable pull-down, opendrain, pull-high and pin change wakeup.
Bidirectional I/O pin with programmable open-drain, pullhigh and pin change wakeup.
CMOS
Bidirectional I/O pin
CMOS
Output of Comparator 2
Bidirectional I/O pin
CMOS
Non-inverting end of Comparator 2
Data pin for Writer programming
• 11
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Function
Input
Type
P82
ST
CIN2-
AN
(CLK)
ST
P83
ST
/RESET
ST
(/RESET)
ST
CMOS
VDD
VDD
Power
−
Power
VSS
VSS
Power
−
Ground
Name
P82/CIN2(CLK)
P83/RESET
(/RESET)
Output
Type
CMOS
CMOS
CMOS
Description
Bidirectional I/O pin
Inverting end of Comparator 2
Clock pin for Writer programming
Bidirectional I/O pin
Internal pull-high reset pin
/RESET pin for Writer programming
Legend: ST: Schmitt Trigger input
XTAL: oscillation pin for crystal/ resonator
5
AN: analog pin,
CMOS: CMOS output
Block Diagram
Figure 5-1 Functional Block Diagram
12 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6
Functional Description
6.1 Operational Registers (for
EM78F644/642/641/544/542/541N Series only)
6.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as an indirect addressing
pointer. Any instruction that uses R0 as a pointer actually accesses data pointed by
the RAM Select Register (R4).
6.1.2 R1 (Timer Clock/Counter)
R1 is incremented by an external signal edge, which is defined by the TE bit (CONT-4)
through the TCC pin, or by the instruction cycle clock. It is writable and readable as any
other registers. It is defined by resetting PSTE (CONT-3).
The prescaler is assigned to TCC, if the PSTE bit (CONT-3) is reset. The content of
the prescaler counter is cleared only when the TCC register is written with a value.
6.1.3 R2 (Program Counter and Stack)
Depending on the device type, R2 and hardware stack are 12-bit wide. The
structure is depicted in Figure 6-1a.
The configuration structure generates 4K×13 bits on-chip Flash ROM addresses
to the relative programming instruction codes. One program page is 1024 words
long.
R2 is set as all "0"s when under a reset condition.
"JMP" instruction allows direct loading of the lower 10 program counter bits.
Thus, "JMP" allows the PC to go to any location within a page.
"CALL" instruction loads the lower 10 bits of the PC, and PC+1 are pushed onto
the stack. Thus, the subroutine entry address can be located anywhere within a
page.
"LJMP" instruction allows direct loading of the program counter bits (A0~A11).
Therefore, "LJMP" allows the PC to jump to any location within 4K (212).
"LCALL" instruction loads the program counter bits (A0 ~A11), and PC+1 are
pushed onto the stack. Thus, the subroutine entry address can be located
anywhere within 4K (212)
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top-level stack.
Product Specification (V1.2) 03.15.2013
• 13
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
"ADD R2, A" allows a relative address to be added to the current PC, and the
ninth and above bits of the PC will increase progressively.
"MOV R2, A" allows loading an address from the "A" register to the lower 8 bits of
the PC, and the ninth and tenth bits of the PC remain unchanged.
Any instruction except “ADD R2, A” that is written to R2 (e.g., "MOV R2, A", "BC
R2, 6") will cause the ninth bit and the tenth bit (A8~A9) of the PC to remain
unchanged.
All instructions are single instruction cycle (fclk/2, fclk/4, fclk/8 or fclk/16) except
for instructions that would change the contents of R2 and “LCALL”, “LJMP”,
“TBRD” instructions. The “LCALL”, “LJMP” and “TBRD” instructions need two
instructions cycle.
Figure 6-1 Program Counter Organization
14 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Data Memory Configuration
Figure 6-1b Data Memory Configuration
Product Specification (V1.2) 03.15.2013
• 15
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.1.4 R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
T
P
Z
DC
C
Bits 7 ~ 5: Not used, set to “0” all the time.
Bit 4 (T):
Time-out bit
Set to “1” with the "SLEP" and "WDTC" commands, or during power up
and reset to “0” by WDT time-out.
Bit 3 (P):
Power down bit
Set to “1” during power-on or by a "WDTC" command and reset to “0” by
a "SLEP" command.
Bit 2 (Z):
Zero flag
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
6.1.5 R4 (RAM Select Register)
Bits 7 ~ 6: Used to select Bank 0 ~ Bank 3
NOTE
For F642/542N, Bit 7 is unused. Set to “0” all the time.
For F641/541N, Bit 7 ~ Bit 6 are unused. Set to “0” all the time.
Bits 5 ~ 0: Used to select registers (Address: 00~3F) in indirect addressing mode.
See the data Memory Configuration in Figure 6-1b.
6.1.6 Bank 0 R5 (Port 5)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P57
P56
P55
P54
P53
P52
P51
P50
Bit 7 ~ 0 (P57 ~ P50): 8-bit Port 5 I/O data register
NOTE
For F642/542N, Bit 6, Bit 3 ~ Bit 1 are unused. Set to “0” all the time.
For F641/541N, Bit 6, Bit 3 ~ Bit 1 are unused. Set to “0” all the time.
User can use the IOC5 register to define each bit as input or output.
16 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.1.7 Bank 0 R6 (Port 6)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P67
P66
P65
P64
P63
P62
P61
P60
Bit 7 ~ 0 (P67 ~ P60): 8-bit Port 6 I/O data register
NOTE
For F641/541N, Bit 7 and Bit 6 are unused. Set to “0” all the time.
User can use the IOC6 register to define each bit as input or output.
6.1.8 Bank 0 R7 (Port 7)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P77
P76
P75
P74
P73
P72
-
-
Bits 7 ~ 2 (P77 ~ P72): 6-bit Port 7 I/O data register
Bits 1 ~ 0: Not used, set to “0” all the time.
NOTE
For F642/542N, Bit 6 and Bit 5, Bit 3 ~ Bit 0 are unused. Set to “0” all the time.
For F641/541N, Bit 7 ~ Bit 0 are unused. Set to “0” all the time.
User can use the IOC7 register to define each bit as input or output.
6.1.9 Bank 0 R8 (Port 8)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
P83
P82
P81
P80
Bits 3 ~ 0 (P83 ~ P80): 4-bit Port 8 I/O data register
NOTE
For F644/544N, Bit 3 is unused. Set to “0” all the time.
User can use the IOC8 register to define each bit as input or output.
6.1.10
Bank 0 R9 (TBLP: Table Point Register for Instruction TBRD)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RBit7
RBit6
RBit5
RBit4
RBit3
RBit2
RBit1
RBit0
Bits 7 ~ 0: This is the least 8 significant bits of address for program code.
NOTE
Bank 0 R9 overflow will carry to Bank 3 R6.
Bank 0 R9 underflow will borrow from Bank 3 R6.
Product Specification (V1.2) 03.15.2013
• 17
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.1.11 Bank 0 RA (Wake-up Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMP2WE
ICWE
-
EXWE
SPIWE
-
-
-
Bit 7 (CMP2WE): Comparator 2 wake-up enable bit
0: Disable Comparator 2 Wake-up
1: Enable Comparator 2 Wake-up
When the Comparator 2 Output Status Change is used to enter an
interrupt vector or to Wake-up the IC from Sleep, the CMP2WE bit
must be set to “Enable“.
Bit 6 (ICWE): Port 6 input status change wake-up enable bit
0: Disable Port 6 input status change Wake-up
1: Enable Port 6 input status change Wake-up
Bit 5: Not used, set to “0” all the time
Bit 4 (EXWE): External /INT wake-up enable bit
0: Disable External /INT pin Wake-up
1: Enable External /INT pin Wake-up
Bit 3 (SPIWE): SPI Wake-up enable bit when SPI acts as Slave device
0: Disable SPI Wake-up when SPI acts as Slave device
1: Enable SPI Wake-up when SPI acts as Slave device
NOTE
F642/542N, Bit 3 is unused. Set to “0” all the time.
For F641/541N, Bit 3 is unused. Set to “0” all the time.
Bits 2 ~ 0: Not used, set to “0” all the time.
6.1.12 Bank 0 RB (EEPROM Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RD
WR
EEWE
EEDF
EEPC
-
-
-
Bit 7 (RD): Read control register
0: Disable EEPROM read execution
1: Read EEPROM contents (RD can be set by software. RD is
cleared by hardware after Read instruction is completed).
Bit 6 (WR): Write control register
0: Write cycle to the EEPROM is completed.
1: Initiate a write cycle (WR can be set by software. WR is cleared
by hardware after Write cycle is completed).
18 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 5 (EEWE): EEPROM Write Enable bit
0: Prohibit write to the EEPROM
1: Allows EEPROM write cycles
Bit 4 (EEDF): EEPROM Detect Flag
0: Write cycle is completed
1: Write cycle is unfinished
Bit 3 (EEPC): EEPROM power-down control bit
0: Switch OFF the EEPROM
1: Switch ON the EEPROM
Bits 2 ~ 0:
Not used, set to “0” all the time.
NOTE
EM78F548/544/542/541N series ICs do not support EEPROM function. Therefore,
the corresponding control registers (Bank 0 RB~RD) are reserved.
6.1.13 Bank 0 RC (256 Bytes EEPROM Address)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EE_A7
EE_A6
EE_A5
EE_A4
EE_A3
EE_A2
EE_A1
EE_A0
Bits 7 ~ 0:
256 bytes EEPROM address
NOTE
EM78F548/544/542/541N series ICs do not support EEPROM function. Therefore,
the corresponding control registers (Bank 0 RB~RD) are reserved.
For F642/542N, Bit 7 is unused. Set to “0” all the time.
For F641/541N, Bit 7 is unused. Set to “0” all the time.
6.1.14 Bank 0 RD (256 Bytes EEPROM Data)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EE_D7
EE_D6
EE_D5
EE_D4
EE_D3
EE_D2
EE_D1
EE_D0
Bits 7 ~ 0:
256 bytes EEPROM data
NOTE
EM78F548/544/542/541N series ICs do not support EEPROM function. Therefore,
the corresponding control registers (Bank0 RB~RD) are reserved.
Product Specification (V1.2) 03.15.2013
• 19
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.1.15 Bank 0 RE (Mode Select Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
TIMERSC
CPUS
IDLE
-
-
-
-
Bit 7: Not used, set to “0” all the time
Bit 6 (TIMERSC): TCC, TC1, TC2, TC3, Timer A and Timer B clock source select
0: Fs is used as Fc
1: Fm is used as Fc
Bit 5 (CPUS):
CPU Oscillator Source Select.
0: Fs: Sub frequency for WDT internal RC time base
1: Fm: Main-oscillator clock
When CPUS=0, the CPU oscillator selects the Sub-oscillator, and
the Main oscillator is stopped.
Bit 4 (IDLE):
Idle Mode Enable Bit.
0: IDLE=”0” + SLEP instruction Æ Sleep mode
1: IDLE=”1” + SLEP instruction Æ Idle mode
CPU Operation Mode
Wake-up
IDLE = 0
+ SLEP
Sleep mode (*)
Fm : stop
Fs : stop
CPU : stop
RESET
Normal mode
Fm : oscillation
Fs : oscillation
CPU : using Fm
Wake-up
IDLE = 0
+ SLEP
CPUS = 1
CPUS = 0
Green mode
Fm : stop
Fs : oscillation
CPU : using Fs
Wake-up
IDLE = 1
+ SLEP
IDLE = 1
+ SLEP
Wake-up
Idle mode
Fm : stop
Fs : oscillation
CPU : stop
Note: * only when WDT IRC is Fs.
If the watchdog function is enabled before going into sleep mode, Fs does not stop.
Hence, some circuits like timer/counter (of which clock source is Fs) must be disabled before
going into sleep mode, especially when the corresponding interrupt is enabled.
Figure 6-2 CPU Operation Mode Block Diagram
20 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Oscillator
(Normal Mode Source)
CPU Mode Status
Sleep/Idle → Normal
Crystal ;
Green → Normal
1M ~ 16 MHz
Oscillator Stable Time
(S)
Sleep/Idle → Green
455K, 4M, 8M, 16 MHz
2
32 CLK
< 2 µs
Green → Normal
Sleep/Idle → Green
1
32 CLK
< 100 µs
Sleep/Idle → Normal
IRC ;
254 CLK
< 5 µs
Green → Normal
2
254 CLK
< 100 µs
Sleep/Idle → Normal
3.5 MHz
(CLK)
0.5 ms ~ 2 ms
Sleep/Idle → Green
ERC ;
1
Count from
Normal/Green
32 CLK
< 100 µs
The oscillator stable time depends on the oscillator characteristics
After the oscillator has stabilized, the CPU will count 254/32 CLK in Normal/Green mode and
continue to work in Normal/Green mode.
Ex 1: The 4 MHz IRC Wakes-up from Sleep mode to Normal mode. The total Wake-up time
is 2 µs + 32 CLK @ 4 MHz
Ex 2: The 4 MHz IRC Wakes-up from Sleep mode to Green mode. The total wake-up time is
100 µs + 32 CLK @ 16kHz
Bits 3 ~ 0: Not used, set to “0” all the time.
6.1.16 Bank 0 RF (Interrupt Status Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
SPIIF
PWMBIF
PWMAIF
EXIF
ICIF
TCIF
Note: Set to “1” to enable Interrupt Request
“0” to disable interrupt execution
Bits 7 ~ 6: Not used, set to “0” all the time.
Bit 5 (SPIIF):
SPI mode Interrupt flag. Flag is cleared by software.
Bit 4 (PWMBIF): PWMB (Pulse Width Modulation) Interrupt flag
Set when a selected period is reached. Reset by software.
Bit 3 (PWMAIF): PWMA (Pulse Width Modulation) interrupt flag.
Set when a selected period is reached. Reset by software.
NOTE
For F642/542N, Bit 5 ~ Bit 3 are unused. Set to “0” all the time.
For F641/541N, Bit 5 ~ Bit 3 are unused. Set to “0” all the time
Bit 2 (EXIF):
External interrupt flag. Set by a falling edge on /INT pin, reset by
software.
Bit 1 (ICIF):
Port 6 input status change interrupt flag. Set when Port 6 input
changes, reset by software.
Product Specification (V1.2) 03.15.2013
• 21
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 0 (TCIF):
TCC overflow interrupt flag. Set when TCC overflows, reset by
software.
NOTE
RF can be cleared by instruction but cannot be set.
IOCF is the interrupt mask register.
The result of reading RF is the "logic AND" of RF and IOCF.
6.1.17 R10 ~ R3F
These are all 8-bit general-purpose registers.
6.1.18 Bank 1 R5 TC1CR (Timer 1 Control)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1CAP
TC1S
TC1CK1
TC1CK0
TC1M
TC1ES
-
-
NOTE
For F641/541N, this register is reserved.
Bit 7 (TC1CAP): Software capture control
0: Disable software capture
1: Enable software capture
Bit 6 (TC1S):
Timer/Counter 1 start control
0: Stop and clear the counter
1: Start Timer/Counter 1
Bit 5~Bit 4 (TC1CK1~TC1CK0): Timer/Counter 1 clock source selection
TC1CK1 TC1CK0
0
0
0
1
1
0
1
1
Bit 3 (TC1M):
Clock Source
Resolution
(4 MHz)
Max. Time
(4 MHz)
Resolution
(16kHz)
Max. Time
(16kHz)
Normal, Idle
Fc=4M
Fc=4M
Fc=16K
Fc=16K
12
1024 µs
262144 µs
256 ms
65536 ms
10
256 µs
65536 µs
64 ms
16384 ms
7
32 µs
8192 µs
8 ms
2048 ms
-
-
-
-
Fc/2
Fc/2
Fc/2
External clock
(TC1 pin)
Timer/Counter 1 mode select
0: Timer/Counter 1 mode
1: Capture mode
22 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 2 (TC1ES):
TC1 signal edge
0: Increment if the transition from low to high (rising edge) takes
place on the TC1 pin.
1: Increment if the transition from high to low (falling edge) takes
place on TC1 pin.
Bits 1 ~ 0:
Not used, set to “0” all the time.
Timer/Counter 1 Configuration
rising
TC1ES
TC1 pin
inhibit
capture
edge
detector falling control
TC1
interrupt
TC1M
M
12
fc/210
fc/2
7
fc/2
MUX
8-bit up counter
overflow
TC1S
TC1CAP
TC1CK
Comparator
2
capture
TC1CR
TCR1DB
capture
TCR1DA
Figure 6-3a Timer/Counter 1 Configuration Block Diagram
In Timer mode, counting up is performed using the internal clock. When the
contents of the up-counter matched the TCR1DA, then interrupt is generated and the
counter is cleared. Counting up resumes after the counter is cleared. The current
contents of the up-counter are loaded into TCR1DB by setting TC1CAP to “1” and the
TC1CAP is automatically cleared to “0” after capture is completed.
In Counter mode, counting up is performed using the external clock input pin (TC1
pin) and either rising or falling edge can be selected by TC1ES, but both edges
cannot be used. When the contents of the up-counter matched the TCR1DA, then
interrupt is generated and the counter is cleared. Counting up resumes after the
counter is cleared. The current contents of the up-counter are loaded into the
TCR1DB by setting TC1CAP to “1” and the TC1CAP is automatically cleared to “0”
after capture is completed.
Product Specification (V1.2) 03.15.2013
• 23
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
In Capture mode, the pulse width, period and duty of the TC1 input pin are
measured under this mode to decode the remote control signal. The counter is set as
free running by the internal clock. On a rising (falling) edge of TC1 pin input, the
contents of the counter is loaded into TCR1DA, then the counter is cleared and
interrupt is generated. On a falling (rising) edge of the TC1 pin input, the contents of
the counter are loaded into TCR1DB. At the next rising edge of the TC1 pin input
while the counter is still counting, the contents of the counter are loaded into
TCR1DA. Then, the counter is cleared and interrupt is generated again. If an
overflow occurs before an edge is detected, the FFH is loaded into TCR1DA and the
overflow interrupt is generated. During interrupt processing, user can determine
whether an overflow has occurred by checking if the TCR1DA value is FFH. After an
interrupt (capture to TCR1DA or overflow detection) is generated, capture and
overflow detection are halted until TCR1DA is read out.
Capture Mode Timing
Clock source
Up-counter
K-2
K-1 K 0
1
m-1
m m+1
n-1 n 0
1
2
3
FE FF0
1
2
3
TC1 pin input
TCR1DA
K
n
TCR1DB
FF (overflow)
m
FE
capture
TC1 interrupt
overflow
capture
Reading TCR1DA
Figure 6-3b Capture Mode Timing Diagram
6.1.19 Bank 1 R6 TCR1DA (Timer 1 Data Buffer A)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCR1DA7 TCR1DA6 TCR1DA5 TCR1DA4 TCR1DA3 TCR1DA2 TCR1DA1 TCR1DA0
Bit 7 ~ Bit 0 (TCR1DA7 ~ TCR1DA0): Data buffer of 8-bit Timer/Counter 1.
NOTE
For F641/541N, this register is reserved.
6.1.20 Bank 1 R7 TCR1DB (Timer 1 Data Buffer B)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCR1DB7 TCR1DB6 TCR1DB5 TCR1DB4 TCR1DB3 TCR1DB2 TCR1DB1 TCR1DB0
Bit 7 ~ Bit 0 (TCR1DB7 ~ TCR1DB0): Data buffer of 8-bit Timer/Counter 1.
NOTE
For F641/541N, this register is reserved.
24 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.1.21 Bank 1 R8 TC2CR (Timer 2 Control)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCM1
RCM0
TC2ES
TC2M
TC2S
TC2CK2
TC2CK1
TC2CK0
Bits 7 ~ 6 (RCM1 ~ RCM0): IRC mode select bits. The Bank 1 R8<7,6> is enabled
when Word 1<12> COBS0 = ”1”.
Writer Trim IRC
Bank 1 R8<7,6>
Frequency
Operating Voltage
Range
Stable
Time
RCM1
RCM0
0
0
4 MHz ± 2.5%
2.2V ~ 5.5V
< 5 µs
0
1
16 MHz ± 10%
4.5V ~ 5.5V
< 1.5 µs
1
0
8 MHz ± 10%
3.0V ~ 5.5V
< 3 µs
1
1
455kHz ± 10%
2.2V ~ 5.5V
< 50 µs
0
0
4 MHz ± 10%
2.2V ~ 5.5V
< 6 µs
0
1
16 MHz ± 2.5%
4.5V ~ 5.5V
< 1.25 µs
1
0
8 MHz ± 10%
3.0V ~ 5.5V
< 3 µs
1
1
455kHz ± 10%
2.2V ~ 5.5V
< 50 µs
0
0
4 MHz ± 10%
2.2V ~ 5.5V
< 6 µs
0
1
16 MHz ± 10%
4.5V ~ 5.5V
< 1.5 µs
1
0
8 MHz ± 2.5%
3.0V ~ 5.5V
< 2.5 µs
1
1
455kHz ± 10%
2.2V ~ 5.5V
< 50 µs
0
0
4 MHz ± 10%
2.2V ~ 5.5V
< 6 µs
0
1
16 MHz ± 10%
4.5V ~ 5.5V
< 1.5 µs
1
0
8 MHz ± 10%
3.0V ~ 5.5V
< 3 µs
1
1
455kHz ± 2.5%
2.2V ~ 5.5V
< 45 µs
4 MHz
16 MHz
8 MHz
455kHz
NOTE
The initial values of Bank 1 R8<7,6> will be kept the same as Word 1<3,2>.
If the IRC frequency is changed from A-frequency to B-frequency, the MCU needs to
wait for some time for it to work. The waiting time corresponds to the B-frequency.
Example:
1st Step When user selects the 4 MHz at the Writer, the initial values of Bank 1
R8<7,6> would be “00”, the same as the value of Word 1<3,2>. If the MCU
is free-running, it will work at 4 MHz ± 2.5%. Refer to the table below.
Writer Trim IRC
Bank 1 R8<7,6>
Frequency
Operating Voltage
Range
Stable
Time
0
4 MHz ± 2.5%
2.2V ~ 5.5V
< 5 µs
0
1
16 MHz ± 10%
4.5V ~ 5.5V
< 1.5 µs
1
0
8 MHz ± 10%
3.0V ~ 5.5V
< 3 µs
1
1
455kHz ± 10%
2.2V ~ 5.5V
< 50 µs
RCM1
RCM0
0
4 MHz
Product Specification (V1.2) 03.15.2013
• 25
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
2nd Step If it is desired to set Bank 1 R8<7,6> = “01” while the MCU is working at
4 MHz ± 2.5%, the MCU needs to hold for 1.5 µs, then it will continue to
work at 16 MHz ± 10%.
Writer Trim IRC
4 MHz
3rd Step
Frequency
Operating Voltage
Stable Time
Range
RCM1
RCM0
0
0
4 MHz ± 2.5%
2.2V ~ 5.5V
< 5 µs
0
1
16 MHz ± 10%
4.5V ~ 5.5V
< 1.5 µs
1
0
8 MHz ± 10%
3.0V ~ 5.5V
< 3 µs
1
1
455kHz ± 10%
2.2V ~ 5.5V
< 50 µs
If it is desired to set Bank 1 R8<7,6> = “11” while the MCU is working at
16 MHz ± 10%, the MCU needs to hold for 50 µs, then it will continue to
work at 455kHz ± 10%.
Writer Trim IRC
4 MHz
4th Step
Bank 1 R8<7,6>
Bank 1 R8<7,6>
Frequency
Operating Voltage
Stable Time
Range
RCM1
RCM0
0
0
4 MHz ± 2.5%
2.2V ~ 5.5V
< 5 µs
0
1
16 MHz ± 10%
4.5V ~ 5.5V
< 1.5 µs
1
0
8 MHz ± 10%
3.0V ~ 5.5V
< 3 µs
1
1
455kHz ± 10%
2.2V ~ 5.5V
< 50 µs
If it is desired to set Bank 1 R8<7,6> = “00” while the MCU is working at
455kHz ± 10%, the MCU needs to hold for 5 µs, then it will continue to work
at 4 MHz ± 2.5%.
Writer Trim IRC
4 MHz
Bank 1 R8<7,6>
Frequency
Operating Voltage
Stable Time
Range
RCM1
RCM0
0
0
4 MHz ± 2.5%
2.2V ~ 5.5V
< 5 µs
0
1
16 MHz ± 10%
4.5V ~ 5.5V
< 1.5 µs
1
0
8 MHz ± 10%
3.0V ~ 5.5V
< 3 µs
1
1
455kHz ± 10%
2.2V ~ 5.5V
< 50 µs
Bit 5 (TC2ES) TC2 signal edge
0: Increment if a transition from low to high (rising edge) takes place
on the TC2 pin.
1: increment if a transition from high to low (falling edge) takes place
on the TC2 pin.
Bit 4 (TC2M): Timer/Counter 2 mode select
0: Timer/counter mode
1: Window mode
NOTE
For F642/542N, Bit 5 ~ Bit 4 are unused. Set to “0” all the time.
26 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 3 (TC2S):
Timer/Counter 2 start control
0: Stop and clear the counter
1: Start Timer/Counter 2
Bit 2~Bit 0 (TC2CK2~TC2CK0): Timer/Counter 2 clock source select
TC2CK2 TC2CK1 TC2CK0
0
0
0
0
0
1
0
1
0
Clock Source Resolution Max. Time Resolution Max. Time
Normal, Idle
Fc=4M
Fc=4M
Fc=16K
Fc=16K
23
2.1 sec
38.2 hr
524.3 s
9544 hr
13
2.048 ms
134.22 sec
512 ms
33554.432 s
8
64 µs
4.194 sec
16 ms
1048.576 s
3
2 µs
131.072 ms
0.5 ms
32768 ms
250 ns
16.384 ms
0.0625 ms
4096 ms
Fc/2
Fc/2
Fc/2
0
1
1
Fc/2
1
0
0
Fc
1
0
1
−
−
−
−
−
1
1
0
−
−
−
−
−
1
1
1
External clock
(TC2 pin)
−
−
−
−
NOTE
For F641/541N, Bit 7 ~ Bit 6 cannot be set as “11” Bit 5 ~ Bit 0 are unused and set to
“0” all the time.
Figure 6-4a Timer/Counter 2 Configuration Block Diagram
Product Specification (V1.2) 03.15.2013
• 27
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
In Timer mode, counting up is performed using internal clock. When the contents of
the up-counter match the TCR2 (TCR2DH+TCR2DL), interrupt is then generated and
the counter is cleared. Counting up resumes after the counter is cleared.
Clock source
Up-counter
0
TCR2
n
1
2
3
4
5
n-3
n-2
n-1
n 0
2
1
match
3
clear counter
TC2 Interrupt
Figure 6-4b Timer Mode Timing Diagram
In Counter mode, counting up is performed using external clock input pin (TC2) and
either rising or falling can be selected by setting TC2ES. When the contents of the
up-counter match the TCR2 (TCR2DH+TCR2DL), then interrupt is generated and the
counter is cleared. Counting up resumes after the counter is cleared.
TC2 Pin
Up-counter
TCR2
0
1
2
3
4
n-2
n-1
n 0
1
2
3
n
match
clear counter
TC2 Interrupt
Figure 6-4c Counter Mode Timing Diagram
In Window mode, counting up is performed on a rising edge of the pulse that is
logical AND of an internal clock and the TC2 pin (window pulse). When the contents
of up-counter match with the TCR2 (TCR2DH+TCR2DL), then interrupt is generated
and the counter is cleared. The frequency (window pulse) must be slower than
the selected internal clock.
In Writing to the TCR2DL, comparison is inhibited until TCR2DH is written.
28 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
TC2 pin
Clock source
Up-counter
0
TCR2
n
1
2
n-3
n-1
n-2
n 0
match
1
2
3
clear counter
TC2 Interrupt
Figure 6-4d Window Mode Timing Diagram
6.1.22 Bank 1 R9 TC2DH (Timer 2 High Byte Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC2D15
TC2D14
TC2D13
TC2D12
TC2D11
TC2D10
TC2D9
TC2D8
Bit 7 ~ Bit 0 (TCR2D15 ~ TCR2D8): High byte data buffer of 16-bit Timer/Counter 2
NOTE
For F641/541N, this register is reserved.
6.1.23 Bank 1 RA TC2DL (Timer 2 Low Byte Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC2D7
TC2D6
TC2D5
TC2D4
TC2D3
TC2D2
TC2D1
TC2D0
Bit 7 ~ Bit 0 (TC2D7 ~ TC2D0): Low byte data buffer of 16-bit Timer/Counter 2
NOTE
For F641/541N, this register is reserved.
6.1.24 Bank 1 RB SPIS (SPI Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DORD
TD1
TD0
-
OD3
OD4
-
RBF
NOTE
For F642/542N, F641/541N, this register is reserved.
Bit 7 (DORD): Data transmission order
0: Shift left (MSB first)
1: Shift right (LSB first)
Product Specification (V1.2) 03.15.2013
• 29
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 6~Bit 5 (TD1 ~ TD0): SDO status output delay time options
TD1
TD0
Delay Time
0
0
8 CLK
0
1
16 CLK
1
0
24 CLK
1
1
32 CLK
Bit 4: Not used, set to “0” all the time.
Bit 3 (OD3): Open-Drain control bit
0: Open-drain disable for SDO
1: Open-drain enable for SDO
Bit 2 (OD4): Open-Drain control bit
0: Open-drain disable for SCK
1: Open-drain enable for SCK
Bit 1:
Not used, set to “0” all the time
Bit 0 (RBF): Read Buffer Full flag
0: Receiving is not completed. SPIRB has not fully exchanged data.
1: Receiving completed; SPIRB has fully exchanged data.
6.1.25 Bank 1 RC SPIC (SPI Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CES
SPIE
SRO
SSE
SDOC
SBRS2
SBRS1
SBRS0
NOTE
For F642/542N, F641/541N, this register is reserved.
Bit 7 (CES): Clock Edge Select bit
0: Data shifts out on a rising edge, and shifts in on a falling edge. Data
is on hold during low-level.
1: Data shifts out on a falling edge, and shifts in on a rising edge. Data
is on hold during high-level.
Bit 6 (SPIE): SPI Enable bit
0: Disable SPI mode
1: Enable SPI mode
30 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 5 (SRO):
SPI Read Overflow bit
0: No overflow
1: A new data is received while the previous data is still being held in
the SPIRB register. Under this condition, the data in the SPI Shift
register will be destroyed. To avoid setting this bit, users are
required to read the SPIRB register although only transmission is
implemented. This can only occur in Slave mode.
Bit 4 (SSE):
SPI Shift Enable bit
0: Reset as soon as the shifting is completed and the next byte is
ready to shift.
1: Start to shift, and keep at “1” while the current byte is still being
transmitted.
This bit will reset to “0” at every 1-byte transmission by the hardware.
Bit 3 (SDOC): SDO output status control bit
0: After Serial data output, the SDO remains high.
1: After Serial data output, the SDO remains low.
Bit 2 ~ Bit 0 (SBRS2 ~ SBRS0): SPI Baud Rate Select bits
SBRS2 (Bit 2)
SBRS1 (Bit 1)
SBRS0 (Bit 0)
Mode
Baud Rate
0
0
0
Master
Fosc/2
0
0
1
Master
Fosc/4
0
1
0
Master
Fosc/8
0
1
1
Master
Fosc/16
1
0
0
Master
Fosc/32
1
0
1
Master
Fosc/64
1
1
0
Slave
/SS enable
1
1
1
Slave
/SS disable
Note: Up to 2 MHz (maximum) bit frequency. If the system frequency (Fosc) operates at
8 MHz, we recommend choosing Fosc/4 as maximum baud rate option of SPI function
6.1.26 Bank 1 RD SPIRB (SPI Read Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRB7
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB0
Bit 7 ~ Bit 0 (SRB7 ~ SRB0): SPI Read data buffer
NOTE
For F642/542N, F641/541N, this register is reserved.
Product Specification (V1.2) 03.15.2013
• 31
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.1.27 Bank 1 RE SPIWB (SPI Write Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SWB7
SWB6
SWB5
SWB4
SWB3
SWB2
SWB1
SWB0
Bit 7 ~ Bit 0 (SWB7 ~ SWB0): SPI Write data buffer
NOTE
For F642/542N, F641/541N, this register is reserved.
6.1.28 Bank 1 RF (Interrupt Status Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMP2IF
-
TC3IF
TC2IF
TC1IF
UERRIF
RBFF
TBEF
Bit 7 (CMP2IF): Comparator 2 Interrupt flag. Set when a change occurs in the
Comparator 2 output. Reset by software.
Bit 6: Not used, set to ”0” all the time.
Bit 5 (TC3IF):
8-bit Timer/Counter 3 Interrupt flag
Bit 4 (TC2IF):
16-bit Timer/Counter 2 Interrupt flag
Bit 3 (TC1IF):
8-bit Timer/Counter 1 Interrupt flag
Bit 2 (UERRIF): UART Receive Error Interrupt flag
Bit 1 (RBFF):
UART receive mode data buffer full interrupt flag
Bit 0 (TBEF):
UART transmit mode data buffer empty interrupt flag
NOTE
The Interrupt flag is automatically set by hardware. It must be cleared by software.
For F642/542N, Bit 2 ~ Bit 0 are unused. Set to “0” all the time.
For F641/541N, Bit 4 ~ Bit 0 are unused. Set to “0” all the time
6.1.29 Bank 2 RA URC1 (UART Control 1)
Bit 7
URTD8
Bit 6
Bit 5
UMODE1 UMODE0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BRATE2
BRATE1
BRATE0
UTBE
TXE
NOTE
For F642/542N, F641/541N, this register is reserved.
Bit 7 (URTD8): Transmission Data Bit 8
32 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 6 ~ Bit 5 (UMODE1 ~ UMODE0): UART mode select
UMODE1
UMODE0
UART Mode
0
0
Mode 1: 7-bit
0
1
Mode 1: 8-bit
1
0
Mode 1: 9-bit
1
1
Reserved
Bit 4 ~ Bit 2 (BRATE2 ~ BRATE0): Transmit Baud Rate select
BRATE2
BRATE1
BRATE0
Baud Rate
4 MHz
8 MHz
0
0
0
Fc/13
19200
38400
0
0
1
Fc/26
9600
19200
0
1
0
Fc/52
4800
9600
0
1
1
Fc/104
2400
4800
1
0
0
Fc/208
1200
2400
1
0
1
Fc/416
600
1200
1
1
0
TC3
−
−
1
1
1
Reserved
Bit 1 (UTBE): UART transfer buffer empty flag. Set to “1” when transfer buffer is
empty. Automatically reset to “0” when writing to the URTD register.
The UTBE bit will be cleared by hardware when transmission is
enabled. The UTBE bit is read-only. Therefore, writing to the URTD
register is necessary when user wants to start shift transmission.
Bit 0 (TXE):
Enable transmission
0: Disable
1: Enable
6.1.30 Bank 2 RB URC2 (UART Control 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
SBIM1
SBIM0
UINVEN
-
-
-
NOTE
For F642/542N, F641/541N, this register is reserved.
Bits 7 ~ 6: Not used, set to “0” all the time.
Bit 5 ~ Bit 4 (SBIM1 ~ SBIM0): Serial bus interface operating mode select
SBIM1
SBIM0
Operating Mode
0
0
I/O mode
0
1
SPI mode
1
0
UART mode
1
1
Reserved
Product Specification (V1.2) 03.15.2013
• 33
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 3 (UINVEN): Enable UART TXD and RXD port inverse output.
0: Disable TXD and RXD port inverse output
1: Enable TXD and RXD port inverse output
Bits 2 ~ 0: Not used, set to ”0” all the time
6.1.31 Bank 2 RC URS (UART Status)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URRD8
EVEN
PRE
PRERR
OVERR
FMERR
URBF
RXE
NOTE
For F642/542N, F641/541N, this register is reserved.
Bit 7 (URRD8): Receiving Data Bit 8
Bit 6 (EVEN):
Select parity check
0: Odd parity
1: Even parity
Bit 5 (PRE):
Enable parity addition
0: Disable
1: Enable
Bit 4 (PRERR): Parity error flag. Set to “1” when parity error occurred.
Bit 3 (OVERR): Over running error flag. Set to “1” when an overrun error occurred.
Bit 2 (FMERR): Framing error flag. Set to “1” when framing error occurred.
NOTE
The Interrupt flag is automatically set by hardware. It must be cleared by software.
Bit 1 (URBF): UART read buffer full flag. Set to “1” when one character is received.
Reset to 0 automatically when read from URS and URRD register.
The URBF will be cleared by hardware when enabling receiving. The
URBF bit is read-only. Therefore, reading the URS register is
necessary to avoid overrun error.
Bit 0 (RXE): Enable receiving
0: Disable
1: Enable
34 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.1.32 Bank 2 RD URRD (UART_RD Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URRD7
URRD6
URRD5
URRD4
URRD3
URRD2
URRD1
URRD0
Bits 7 ~ 0 (URRD7 ~ URRD0): UART receive data buffer. Read only.
NOTE
For F642/542N, F641/541N, this register is reserved.
6.1.33 Bank 2 RE URTD (UART_TD Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URTD7
URTD6
URTD5
URTD4
URTD3
URTD2
URTD1
URTD0
Bits 7 ~ 0 (URTD7 ~ URTD0): UART transmit data buffer. Write only.
NOTE
For F642/542N, F641/541N, this register is reserved.
6.1.34 Bank 2 RF (Pull-high Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH77
/PH76
/PH75
/PH74
/PH73
/PH72
“1”
“1”
Bit 7 (/PH77): Control bit used to enable pull-high on the P77 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PH76): Control bit used to enable pull-high on the P76 pin.
Bit 5 (/PH75): Control bit used to enable pull-high on the P75 pin.
Bit 4 (/PH74): Control bit used to enable pull-high on the P74 pin.
Bit 3 (/PH73): Control bit used to enable pull-high on the P73 pin.
Bit 2 (/PH72): Control bit used to enable pull-high on the P72 pin.
Bits 1 ~ 0:
Not used, set to “1” all the time.
NOTE
The RF Register is both readable and writable.
For F642/542N, Bit 6 ~ Bit 5, Bit 3 ~ Bit 0 are unused. Set to “1” all the time.
For F641/541N, Bit 7 ~ Bit 0 are unused. Set to “1” all the time.
Product Specification (V1.2) 03.15.2013
• 35
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.1.35 Bank 3 R5 (TMRCON: Timer A and Timer B Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TAEN
TAP2
TAP1
TAP0
TBEN
TBP2
TBP1
TBP0
NOTE
For F642/542N, F641/541N, this register is reserved.
Bit 7 (TAEN): Timer A enable bit
0: Disable Timer A (default)
1: Enable Timer A
Bits 6 ~ 4 (TAP2 ~ TAP0): Timer A clock prescaler option bits.
Bit 3 (TBEN): Timer B enable bit
0: Disable Timer A (default)
1: Enable Timer A
Bits 2 ~ 0 (TBP2 ~ TBP0): Timer B clock prescaler option bits
TAP2/TBP2
TAP1/TBP1
TAP0/TBP0
Prescale
0
0
0
1:2 (Default)
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
6.1.36 Bank 3 R6 (TBHP: Table Pointer Register for Instruction
TBRD)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MLB
-
-
-
RBit11
RBit10
RBit9
RBit8
Bit 7 (MLB):
Select MSB or LSB machine code to be moved to the register.
The machine code is pointed by the TBLP and TBHP registers.
Bits 6 ~ 4:
Not used, set to “0” all the time.
Bits 3 ~ 0:
These are the 4 most significant bits of program code address
NOTE
For F642/542N, Bit 3 is unused. Set to “0” all the time.
For F641/541N, Bit 3 and Bit 2 are unused. Set to “0” all the time.
36 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.1.37 Bank 3 R7 (CMPCON: Comparator 2 Control Register and
PWMA/B Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
CPOUT2
COS21
COS20
PWMAE
PWMBE
Bit 7 ~ Bit 5: Not used, set to “0” all the time
Bit 4 (CPOUT2): The result of Comparator 2 output
Bit 3 ~ Bit 2 (COS21 ~ COS20): Comparator 2 select bits
COS21
COS20
Function Description
0
0
Comparator 2 is not used. P80 acts as normal I/O pin
0
1
Act as a Comparator 2 and P80 acts as normal I/O pin
1
0
Act as a Comparator 2 and P80 acts as Comparator 2 output pin (CO)
1
1
Not used
Bit 1 (PWMAE): PWMA enable bit.
0: PWMA is off and its related pin carries out the P75 function
(default).
1: PWMA is on, and its related pin is automatically set to output.
Bit 0 (PWMBE): PWMB enable bit.
0: PWMB is off and its related pin carries out the P76 function
(default).
1: PWMB is on, and its related pin is automatically set to output.
NOTE
For F642/542N, Bit 1 and Bit 0 are unused. Set to “0” all the time.
For F641/541N, Bit 1 and Bit 0 are unused. Set to “0” all the time.
6.1.38 Bank 3 R8 (PWMCON: PWMA/B Lower 2 Bits of the Period
and Duty Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRDA [1]
PRDA [0]
DTA [1]
DTA [0]
PRDB [1]
PRDB [0]
DTB [1]
DTB [0]
NOTE
For F642/542N, F641/541N, this register is reserved.
Bits 7 ~ 6 (PRDA [1], PRDA [0]): Least Significant Bits of PWMA Period Cycle.
Bits 5 ~ 4 (DTA [1], DTA [0]):
Least Significant Bits of PWMA Duty Cycle.
Bits 3 ~ 2 (PRDB [1], PRDB [0]): Least Significant Bits of PWMB Period Cycle.
Bits 1 ~ 0 (DTB [1], DTB [0]):
Product Specification (V1.2) 03.15.2013
Least Significant Bits of PWMB Duty Cycle.
• 37
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.1.39 Bank 3 R9 (PRDAH: Most Significant Byte (Bit 9 ~ Bit 2) of
PWMA)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRDA[9]
PRDA[8]
PRDA[7]
PRDA[6]
PRDA[5]
PRDA[4]
PRDA[3]
PRDA[2]
The content of Bank 3 of R9 is a period (time base) of PWMA Bit 9 ~ Bit 2. The
frequency of PWMA is the reverse of the period.
NOTE
For F642/542N, F641/541N, this register is reserved.
6.1.40 Bank 3 RA (DTAH: Most Significant Byte (Bit 9 ~ Bit 2) of
PWMA Duty Cycle)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DTA[9]
DTA[8]
DTA[7]
DTA[6]
DTA[5]
DTA[4]
DTA[3]
DTA[2]
A specified value keeps the PWMA output to remain high until the value matches with
TMRA.
NOTE
For F642/542N, F641/541N, this register is reserved.
6.1.41 Bank 3 RB (PRDBH: Most Significant Byte (Bit 9~Bit 2) of
PWMB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRDB[9]
PRDB[8]
PRDB[7]
PRDB[6]
PRDB[5]
PRDB[4]
PRDB[3]
PRDB[2]
The content of Bank 3 of R9 is a period (time base) of PWMB Bit 9~Bit 2. The
frequency of PWMB is the reverse of the period.
NOTE
For F642/542N, F641/541N, this register is reserved.
6.1.42 Bank 3 RC (DTBH: Least Significant Byte (Bit 9 ~ Bit 2) of
PWMB Duty Cycle)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DTB[9]
DTB[8]
DTB[7]
DTB[6]
DTB[5]
DTB[4]
DTB[3]
DTB[2]
A specified value keeps the PWMB output to remain high until the value matches with
TMRB.
NOTE
For F642/542N, F641/541N, this register is reserved.
38 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.1.43 Bank 3 RD TC3CR (Timer 3 Control)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC3FF1
TC3FF0
TC3S
TC3CK2
TC3CK1
TC3CK0
TC3M1
TC3M0
Bits 7 ~ 6 (TC3FF1 ~ TC3FF0): Timer/Counter 3 flip-flop control
TC3FF1
TC3FF0
Operating Mode
0
0
Clear
0
1
Toggle
1
0
Set
1
1
Reserved
Bit 5 (TC3S): Timer/Counter 3 start control
0: Stop and clear the counter
1: Start Timer/Counter 3
Bits 4 ~ 2 (TC3CK2 ~ TC3CK0): Timer/Counter 3 clock source select
TC3CK2 TC3CK1 TC3CK0
0
0
0
0
1
0
0
1
1
0
Clock Source Resolution Max. Time Resolution Max. Time
Normal, Idle
11
0
Fc/2
7
1
Fc/2
5
0
Fc/2
3
1
Fc/2
2
0
Fc/2
1
Fc=4M
Fc=4M
Fc=16K
Fc=16K
512 µs
131072 µs 128 ms
32768 ms
32 µs
8192 µs
8 ms
2048 ms
8 µs
2048 µs
2 ms
512 ms
2 µs
512 µs
500 µs
128 ms
1 µs
256 µs
250 µs
64 ms
1
0
1
Fc/2
500 ns
128 µs
125 µs
32 ms
1
1
0
Fc
250 ns
64 µs
62.5 µs
16 ms
1
1
1
External clock
(TC3 pin)
-
-
-
-
Bits 1 ~ 0 (TC3M1 ~ TC3M0): Timer/Counter 3 operating mode select
TC3M1
TC3M0
0
0
Timer/Counter
0
1
Reserved
1
0
Programmable Divider Output
1
1
Pulse Width Modulation Output
Product Specification (V1.2) 03.15.2013
Operating Mode
• 39
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Figure 6-5a Timer / Counter 3 Configuration
In Timer mode, counting up is performed using the internal clock (rising edge trigger).
When the contents of the up-counter match the TCR3, then interrupt is generated and
the counter is cleared. Counting up resumes after the counter is cleared.
In Counter mode, counting up is performed using an external clock input pin (TC3
pin). When the contents of the up-counter match the TCR3, then interrupt is
generated and the counter is cleared. Counting up resumes after the counter is
cleared.
In Programmable Divider Output (PDO) mode, counting up is performed using the
internal clock. The contents of TCR3 are compared with the contents of the upcounter. The F/F output is toggled and the counter is cleared each time a match is
found. The F/F output is inverted and output to /PDO pin. This mode can generate
50% duty pulse output. The F/F can be initialized by the program and it is
initialized to “0” during reset. A TC3 interrupt is generated each time the /PDO
output is toggled.
Clock source
Up-counter
TCR3
0
1
2
3
n-1
n
0
1
n-1
n
0
1
n-1
n
0
1
2
n
F/F
/PDO Pin
TC3 Interrupt
Figure 6-5b PDO Mode Timing Chart
40 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
In Pulse Width Modulation (PWM) Output Mode, counting up is performed using
the internal clock. The contents of TCR3 are compared with the contents of the upcounter. The F/F is toggled when a match is found. While the counter continues
counting, the F/F is toggled again when the counter overflows, after which the counter
is cleared. The F/F output is inverted and output to /PWM pin. A TC3 interrupt is
generated each time an overflow occurs. TCR3 is configured as a 2-stage shift
register and, during output, will not switch until one output cycle is completed
even if TCR3 is overwritten. Therefore, the output can be changed continuously.
However, only when TC3S is set to “1” will the TCR3 start to shift and allows data to
be loaded into TCR3.
Clock Source
Up-counter
TCR3
0
1
n-1
n
n+1 n+2
FE
FF
n-1
0
n/n
n
n+1 n+2
FE
FF
0
1
n/m
match
overflow
m
m/m
match
overflow
Shift
overwrite
F/F
m-1
/PWM
1 period
TC3 interrupt
Figure 6-5c PWM Mode Timing Chart
6.1.44 Bank 3 RE TC3D (Timer 3 Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC3D7
TC3D6
TC3D5
TC3D4
TC3D3
TC3D2
TC3D1
TC3D0
Bits 7 ~ 0 (TC3D7 ~ TC3D0): Data Buffer of 8-bit Timer/Counter 3.
6.1.45 Bank 3 RF (Pull-Down Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PD77
/PD76
/PD75
/PD74
/PD73
/PD72
”1”
”1”
Bit 7 (/PD77): Control bit used to enable pull-down on P77 pin
0: Enable internal pull-down
1: Disable internal pull-down
Bit 6 (/PD76): Control bit used to enable pull-down of the P76 pin.
Bit 5 (/PD75): Control bit used to enable pull-down of the P75 pin.
Bit 4 (/PD74): Control bit used to enable pull-down of the P74 pin.
Bit 3 (/PD73): Control bit used to enable pull-down of the P73 pin.
Bit 2 (/PD72): Control bit used to enable pull-down of the P72 pin.
Product Specification (V1.2) 03.15.2013
• 41
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bits 1 ~ 0: Not used, set to “1” all the time.
NOTE
The RF register is both readable and writable.
For F642/542N, Bit 6 ~ Bit 5, Bit 3 ~ Bit 0 are unused. Set to “1” all the time.
For F641/541N, Bit 7 ~ Bit 0 are unused. Set to “1” all the time.
6.2 Special Function Registers
(for EM78F644/642/641/544/542/541N Series only)
6.2.1 A (Accumulator)
Internal data transfer operation or instruction operand holding usually involves the
temporary storage function of the Accumulator. The Accumulator is not an
addressable register.
6.2.2 CONT (Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTE
/INT
TS
TE
PSTE
PST2
PST1
PST0
Bit 7 (INTE): INT signal edge
0: Interrupt occurs at a rising edge of the INT pin
1: Interrupt occurs at a falling edge of the INT pin
Bit 6 (/INT): Interrupt Enable Flag
0: Masked by DISI or hardware interrupt
1: Enabled by ENI/RETI instructions
Bit 5 (TS):
TCC signal source
0: Internal oscillator cycle clock. If P77 is used as I/O pin, TS must be 0
1: Transition on the TCC pin
Bit 4 (TE):
TCC signal edge
0: Increment if a transition from low to high takes place on the TCC pin
1: Increment if a transition from high to low takes place on the TCC pin
NOTE
For F641/541N, Bit 5 ~ Bit 4 are unused. Set to “0” all the time.
Bit 3 (PSTE): Prescaler enable bit for TCC
0: Prescaler disable bit, the TCC rate is 1:1
1: Prescaler enable bit, the TCC rate is set as Bit 2 ~ Bit 0
42 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 2 ~ Bit 0 (PST 2 ~ PST0): TCC prescaler bits
PST2
PST1
PST0
TCC Rate
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
NOTE
The CONT register is both readable and writable.
6.2.3 IOC5 (I/O Port 5 Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C57
C56
C55
C54
C53
C52
C51
C50
Bits 7 ~ 0 (C57 ~ C50): 8-bit Port 5 I/O data register
0: Define the I/O pin as output
1: Define the I/O pin as high impedance
User can use the IOC5 register to define each bit as input or output.
NOTE
For F642/542N, Bit 6, Bit 3 ~ Bit 1 are unused. Set to “0” all the time.
For F641/541N, Bit 6, Bit 3 ~ Bit 1 are unused. Set to “0” all the time.
6.2.4 IOC6 (I/O Port 6 Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C67
C66
C65
C64
C63
C62
C61
C60
Bits 7 ~ 0 (C67 ~ C60): 8-bit Port 6 I/O data register
0: Define the I/O pin as output
1: Define the I/O pin as high impedance
User can use the IOC6 register to define each bit as input or output.
NOTE
For F641/541N, Bit 7 ~ Bit 6 are unused. Set to “0” all the time.
Product Specification (V1.2) 03.15.2013
• 43
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.2.5 IOC7 (I/O Port 7 Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C77
C76
C75
C74
C73
C72
-
-
Bits 7 ~ 2 (C77 ~ C72): 6-bit Port 7 I/O data register
0: Define I/O pin as output
1: Define I/O pin as high impedance
Bits 1 ~ 0:
Not used, set to “0” all the time.
User can use the IOC7 register to define each bit as input or output.
NOTE
For F642/542N, Bit 6 ~ Bit 5, Bit 3 ~ Bit 0 are unused. Set to “0” all the time.
For F641/541N, Bit 7 ~ Bit 0 are unused. Set to “0” all the time.
6.2.6 IOC8 (I/O Port 8 Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
C83
C82
C81
C80
Bits 7 ~ 4:
Not used, set to “0” all the time.
Bits 3 ~ 0 (C83 ~ C80): 4-bit Port 8 I/O data register
0: Define I/O pin as output
1: Define I/O pin as high impedance
User can use the IOC8 register to define each bit as input or output.
NOTE
For F644N/544n, Bit 3 is unused. Set to “0” all the time.
6.2.7 IOC9
Reserved registers
6.2.8 IOCA (WDT Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
EIS
-
-
PSWE
PSW2
PSW1
PSW0
Bit 7 (WDTE): Control bit used to enable the Watchdog timer
0: Disable WDT
1: Enable WDT
WDTE is both readable and writable.
44 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 6 (EIS):
Control bit used to define the P60 (/INT) pin function
0: P60, bidirectional I/O pin
1: /INT, external interrupt pin. In this case, the I/O control bit of P60
(Bit 0 of IOC6) must be set to "1".
When EIS is "0", the /INT path is masked. When EIS is "1", the status
of the /INT pin can also be read by way of reading Port 6 (R6).
The EIS is both readable and writable.
Bits 5 ~ 4:
Not used, set to “0” all the time
Bit 3 (PSWE): Prescaler enable bit for WDT
0: Prescaler disable bit. WDT rate is 1:1
1: Prescaler enable bit. WDT rate is set at Bit 0~Bit 2
Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits
PSW2
PSW1
PSW0
WDT Rate
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
6.2.9 IOCB (Pull-Down Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PD63
/PD62
/PD61
/PD60
/PD53
/PD52
/PD51
/PD50
Bit 7 (/PD63): Control bit used to enable pull-down of the P63 pin.
0: Enable internal pull-down
1: Disable internal pull-down
Bit 6 (/PD62): Control bit used to enable pull-down on P62 pin
Bit 5 (/PD61): Control bit used to enable pull-down on P61 pin
Bit 4 (/PD60): Control bit used to enable pull-down on P60 pin
Bit 3 (/PD53): Control bit used to enable pull-down on P53 pin
Bit 2 (/PD52): Control bit used to enable pull-down on P52 pin
Bit 1 (/PD51): Control bit used to enable pull-down on P51 pin
Bit 0 (/PD50): Control bit used to enable pull-down on P50 pin
Product Specification (V1.2) 03.15.2013
• 45
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
The IOCB Register is both readable and writable.
NOTE
For F642/542N, Bit 3 ~ Bit 1 are unused. Set to “1” all the time.
For F641/541N, Bit 3 ~ Bit 1 are unused. Set to “1” all the time.
6.2.10 IOCC (Open-Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD67
OD66
OD65
OD64
OD63
OD62
OD61
OD60
Bit 7 (OD67): Control bit used to enable open-drain output of the P67 pin.
0: Disable open-drain output
1: Enable open-drain output
Bit 6 (OD66): Control bit used to enable open-drain output on P66 pin
Bit 5 (OD65): Control bit used to enable open-drain output on P65 pin
Bit 4 (OD64): Control bit used to enable open-drain output on P64 pin
Bit 3 (OD63): Control bit used to enable open-drain output on P63 pin
Bit 2 (OD62): Control bit used to enable open-drain output on P62 pin
Bit 1 (OD61): Control bit used to enable open-drain output on P61 pin
Bit 0 (OD60): Control bit used to enable open-drain output on P60 pin
The IOCC Register is both readable and writable.
NOTE
For F641/541N, Bit 7 ~ Bit 6 are unused. Set to “0” all the time.
6.2.11 IOCD (Pull-High Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH67
/PH66
/PH65
/PH64
/PH63
/PH62
/PH61
/PH60
Bit 7 (/PH67): Control bit used to enable pull-high of the P67 pin.
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PH66): Control bit used to enable pull-high on P66 pin
Bit 5 (/PH65): Control bit used to enable pull-high on P65 pin
Bit 4 (/PH64): Control bit used to enable pull-high on P64 pin
Bit 3 (/PH63): Control bit used to enable pull-high on P63 pin
Bit 2 (/PH62): Control bit used to enable pull-high on P62 pin
46 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 1 (/PH61): Control bit used to enable pull-high on P61 pin
Bit 0 (/PH60): Control bit used to enable pull-high on P60 pin
The IOCD Register is both readable and writable.
NOTE
For F641/541N, Bit 7 ~ Bit 6 are unused. Set to “1” all the time.
6.2.12 IOCE (Interrupt Mask Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMP2IE
-
TC3IE
TC2IE
TC1IE
UERRIE
URIE
UTIE
Bit 7 (CMP2IE): CMP2IF interrupt enable bit.
0: Disable CMP2IF interrupt
1: Enable CMP2IF interrupt
When the Comparator 2 output status change is used to enter an
interrupt vector or enter the next instruction, the CMP2IE bit must be
set to “Enable“.
Bit 6:
Not used, set to “0” all the time.
Bit 5 (TC3IE): Interrupt enable bit
0: Disable TC3IF interrupt
1: Enable TC3IF interrupt
Bit 4 (TC2IE): Interrupt enable bit
0: Disable TC2IF interrupt
1: Enable TC2IF interrupt
Bit 3 (TC1IE): Interrupt enable bit
0: Disable TC1IF interrupt
1: Enable TC1IF interrupt
Bit 2 (UERRIE): UART receive error interrupt enable bit
0: Disable UERRIF interrupt
1: Enable UERRIF interrupt
Bit 1 (URIE): UART receive mode Interrupt enable bit
0: Disable RBFF interrupt
1: Enable RBFF interrupt
Bit 0 (UTIE): UART transmit mode interrupt enable bit.
0: Disable TBEF interrupt
1: Enable TBEF interrupt
Product Specification (V1.2) 03.15.2013
• 47
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
The IOCE Register is both readable and writable.
NOTE
For F642/542N, Bit 2 ~ Bit 0 are unused. Set to “0” all the time.
For F641/541N, Bit 4 ~ Bit 0 are unused. Set to “0” all the time.
6.2.13 IOCF (Interrupt Mask Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
SPIIE
PWMBIE
PWMAIE
EXIE
ICIE
TCIE
Bits 7 ~ 6:
Not used, set to “0” all the time.
Bit 5 (SPIIE): SPIIF interrupt enable bit.
0: Disable SPIIF interrupt
1: Enable SPIIF interrupt
Bit 4 (PWMBIE): PWMBIF interrupt enable bit
0: Disable PWMBIF interrupt
1: Enable PWMBIF interrupt
Bit 3 (PWMAIE): PWMAIF interrupt enable bit
0: Disable PWMAIF interrupt
1: Enable PWMAIF interrupt
Bit 2 (EXIE): EXIF interrupt enable bit
0: Disable EXIF interrupt
1: Enable EXIF interrupt
Bit 1 (ICIE): ICIF interrupt enable bit
0: Disable ICIF interrupt
1: Enable ICIF interrupt
Bit 0 (TCIE): TCIF interrupt enable bit
0: Disable TCIF interrupt
1: Enable TCIF interrupt
The IOCF Register is both readable and writable.
NOTE
Individual interrupt is enabled by setting its associated control bit in the IOCF to "1".
Global interrupt is enabled by the ENI instruction and disabled by the DISI instruction.
For F642/542N, Bit 5 ~ Bit 3 are unused. Set to “0” all the time.
For F641/541N, Bit 5 ~ Bit 3 are unused. Set to “0” all the time.
48 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3 Operational Registers for EM78F648/548N
6.3.1 R0: IAR (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an
indirect addressing pointer. Any instruction using R0 as a pointer actually accesses
data pointed by the RAM Select Register (R4).
6.3.2 R1: BSR (Bank Selection Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
SBS0
0
0
0
GBS0
Bits 7 ~ 5:
Not used, set to “0” all the time.
Bit 4 (SBS0): Special register bank select bit. It is used to select Bank 0/1 of special
register R5~R4F.
0: Bank 0
1: Bank 1
Bits 3~1:
Not used, set to “0” all the time.
Bit 0 (GBS0): General register bank select bit. It is used to select Bank 0/1of general
register R80~RFF.
0: Bank 0
1: Bank 1
6.3.3 R2: PC (Program Counter)
Depending on the device type, R2 and hardware stack are 12-bit wide. The
program counter structure is depicted in Figure 6-6.
Generates 8K×15 bits on-chip Flash ROM addresses to the relative programming
instruction codes. One program page is 4096 words long.
R2 is set as all "0"s when under RESET condition.
"JMP" instruction allows direct loading of the lower 12 program counter bits.
Thus, "JMP" allows the PC to go to any location within a page.
"CALL" instruction loads the lower 12 bits of the PC, and the present PC value
will add 1 and is pushed into the stack. Thus, the subroutine entry address can
be located anywhere within a page.
"LJMP" instruction allows direct loading of the lower 13 program counter bits.
13
Therefore, "LJMP" allows the PC to jump to any location within 8K (2 ).
"LCALL" instruction loads the lower 13 bits of the PC, and PC+1 are pushed into
the stack. Thus, the subroutine entry address can be located anywhere within 8K
13
(2 ).
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top-level stack.
Product Specification (V1.2) 03.15.2013
• 49
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
"ADD R2, A" allows a relative address to be added to the current PC, and the
ninth and above bits of the PC will be incremented progressively.
"MOV R2, A" allows to load an address from the "A" register to the lower 8 bits of
the PC, and the ninth and above bits of the PC are not changed.
•Any instruction (except “ADD R2,A”) that is written to R2 (e.g., "MOV R2, A", "BC
R2, 6",⋅etc.) will cause the ninth bit and the above bits (A8~A11) of the PC to
remain unchanged.
All instructions are single instruction cycle (fclk/2, fclk/4, fclk/8, fclk/16). The instruction
that would change the contents of R2 will need one more instruction cycle.
User Memory Space
Figure 6-6 Program Counter Structure
50 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Data Memory Configuration
Address
Bank 0
0X00
IAR (Indirect Addressing Register)
0X01
BSR (Bank Selection Control Register)
0X02
PC (Program Counter)
0X03
SR (Status Register)
0X04
RSR (RAM Select Register)
0X05
Port 5
P5PHCR
0X06
Port 6
P6PHCR
0X07
Port 7
P7PHCR
0X08
Port 8
P8PHCR
0X09
Port 9
P9PHCR
0X0A
-
-
0x0B
OMCR (Operating Mode Control Register)
P5PLCR
0X0C
ISR1 (Interrupt Status Register 1)
P6PLCR
0X0D
ISR2 (Interrupt Status Register 2)
P7PLCR
0X0E
ISR3 (Interrupt Status Register 3)
P8PLCR
0X0F
-
P9PLCR
0X10
EIESCR
-
0X11
WDTCR
P5HD/SCR
0X12
LVDCR
P6HD/SCR
0X13
TCCCR
P7HD/SCR
0X14
TCCDATA
P8HD/SCR
0X15
IOCR5
P9HD/SCR
0X16
IOCR6
-
0X17
IOCR7
P5ODCR
0X18
IOCR8
P6ODCR
0X19
IOCR9
P7ODCR
0X1A
-
P8ODCR
0X1B
-
P9ODCR
0X1C
IMR1 (Interrupt Mask Register 1)
-
0X1D
IMR2 (Interrupt Mask Register 2)
IRCS
0X1E
IMR3 (Interrupt Mask Register 3)
-
0X1F
-
EEROM CONTROL
0X20
P5WUCR
EEPROM ADDR
0X21
P5WUECR
EEPROM DATA
Product Specification (V1.2) 03.15.2013
Bank 1
• 51
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address
Bank 0
Bank 1
0X22
P7WUCR
-
0X23
P7WUECR
I2CCR1 (I2C Status and Control Register 1)
0X24
-
I2CCR2 (I2C Status and Control Register 2)
0X25
-
I2CSA (I2C Slave Address Register)
0X26
-
I2CDA (I2C Device Address Register)
0X27
-
I2CDB (I2C Data Buffer)
0X28
-
I2CA
0X29
-
-
0X2A
-
PWMER (PWM Enable Control Register)
0x2B
SPICR (SPI Control Register)
TIMEN (Timer/PWM Enable Control Register)
0X2C
SPIS (SPI Status Register)
-
0X2D
SPIR (SPI Read Buffer)
-
0X2E
SPIW (SPI Write Buffer)
-
0X2F
WUCR1
PWMACR (PWM A Control Register)
0X30
-
PWMBCR (PWM B Control Register)
0X31
-
-
0X32
URCR1 (UART Control Register 1)
TACR (Timer A Control Register)
0X33
URCR2 (UART Control Register 2)
TBCR (Timer B Control Register)
0X34
URS (UART Status Register)
-
0X35
URRD (UART Receive Data Buffer Register)
TAPRD (Timer A Period Buffer)
0X36
URTD (UART Transmit Data Buffer Register)
TBPRD (Timer B Period Buffer)
0X37
TBPTL
-
0X38
TBPTH
TADT (Timer A Duty Buffer)
0X39
CMP1CR (Comparator 1 Control Register)
TBDT (Timer B Duty Buffer)
0X3A
-
-
0x3B
-
PRDxL
0X3C
CMP2CR
DTxL
0X3D
-
-
0X3E
-
-
0X3F
-
-
0X40
-
-
0X41
-
-
0X42
-
-
0X43
CPIRLCON
-
0X44
-
-
52 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address
Bank 0
Bank 1
0X45
-
-
0X46
-
-
0X47
-
-
0X48
TC1CR
-
0X49
TCR1DA
-
0X4A
TCR1DB
-
0x4B
TC2CR
-
0X4C
TCR2DH
-
0X4D
TCR2DL
-
0X4E
TC3CR
-
0X4F
TCR3D
-
0X50
0X51
General Purpose Register
.
.
0X7F
0X80
0X81
.
Bank 1
Bank 0
.
.
0XFE
0XFF
6.3.4 R3: SR (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
T
P
Z
DC
C
Bits 7~5: Not used, set to “0” all the time.
Bit 4 (T): Time-out bit
Set to “1” by "SLEP" and "WDTC" command executions or during power
up. Reset to “0” when WDT time-out occurs.
Product Specification (V1.2) 03.15.2013
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8-Bit Microcontroller
Bit 3 (P): Power down bit
Set to “1” at power on or by "WDTC" command execution. Reset to “0” by
“SLEP” command execution.
Bit 2 (Z): Zero flag
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
6.3.5 R4: RSR (RAM Select Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RSR7
RSR6
RSR5
RSR4
RSR3
RSR2
RSR1
RSR0
Bits 7~0 (RSR7~RSR0): These bits are used to select registers (Address: 00~FF) in
indirect address mode. Refer to the table on Data Memory Configuration
(Section 6.3.3) for more details.
6.3.6 Bank 0 R5 ~ R9 (Port 5 ~ Port 9)
R5, R6, R7, R8, and R9 are I/O data registers.
6.3.7 Bank 0 RA (Not Used)
6.3.8 Bank 0 RB OMCR (Operating Mode Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPUS
IDLE
TC1SS
TC2SS
TC3SS
TASS
TBSS
0
Bit 7 (CPUS): CPU Oscillator Source Select.
0: Fs: sub-oscillator for WDT internal RC time base
1: Fm: main-oscillator
When CPUS=0, the CPU oscillator will select the sub-oscillator, and
the main oscillator is stopped.
Bit 6 (IDLE): Idle mode enable bit. This bit defines and instructs SLEP instruction
which mode to go after the instruction is executed.
0: “IDLE=0”+SLEP instruction → Sleep mode
1: “IDLE=1”+SLEP instruction → Idle mode
54 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
CPU Operation Mode
Figure 6-7 CPU Operation Mode Block Diagram
Oscillator
(Normal Mode Source)
CPU Mode Status
Sleep/Idle → Normal
Crystal ;
1M ~ 16 MHz
Green → Normal
Sleep/Idle → Green
Sleep/Idle → Normal
ERC ;
Green → Normal
3.5 MHz
Sleep/Idle → Green
Sleep/Idle → Normal
IRC ;
455K, 4M, 8M, 16 MHz
Green → Normal
Sleep/Idle → Green
1
2
Oscillator Stable Time
(S)
1
0.5 ms ~ 2 ms
< 100 µs
< 5 µs
Count from
Normal/Green
(CLK)
2
254 CLK
254 CLK
32 CLK
32 CLK
< 100 µs
< 2 µs
32 CLK
< 100 µs
The oscillator stable time depends on the oscillator characteristics
After the oscillator has stabilized, the CPU will count 254/32 CLK in Normal/Green mode and
continue to work in Normal/Green mode.
Ex 1: The 4 MHz IRC wakes-up from Sleep mode to Normal mode. The total wake-up time
is 2 µs + 32 CLK @ 4 MHz
Ex 2: The 4 MHz IRC wakes-up from Sleep mode to Green mode. The total wake-up time is
100 µs + 32 CLK @ 16kHz
Bit 5 (TC1SS): TC1 clock source select bit
0: Fs is used as Fc
1: Fm is used as Fc
Product Specification (V1.2) 03.15.2013
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EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 4 (TC2SS): TC2 clock source select bit
0: Fs is used as Fc
1: Fm is used as Fc
Bit 3 (TC3SS): TC3 clock source select bit
0: Fs is used as Fc
1: Fm is used as Fc
Bit 2 (TASS):
Timer A clock source select bit
0: Fs is used as Fc
1: Fm is used as Fc
Bit 1 (TBSS):
Timer B clock source select bit
0: Fs is used as Fc
1: Fm is used as Fc
Bit 0:
Not used, fixed to “0” all the time.
6.3.9 Bank 0 RC: ISR1 (Interrupt Status Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDIF
0
SPIF
PWMBIF
PWMAIF
EXIF
ICIF
TCIF
Note: Set to “1” to enable Interrupt Request
“0” to disable interrupt execution
Bit 7 (LVDIF): Low voltage detector interrupt flag
When LVD1, LVD0 = “0, 0”, Vdd > 2.3V, LVDIF is “0”,
Vdd<= 2.3V, set LVDIF to “1”. LVDIF reset to “0” by software.
When LVD1, LVD0 = “0, 1”, Vdd > 3.3V, LVDIF is “0”,
Vdd<= 3.3V, set LVDIF to “1”. LVDIF reset to “0” by software.
When LVD1, LVD0 = “1, 0”, Vdd > 4.0V, LVDIF is “0”,
Vdd<= 4.0V, set LVDIF to “1”. LVDIF reset to “0” by software.
When LVD1, LVD0 = “1, 1”, Vdd > 4.5V, LVDIF is “0”,
Vdd<= 4.5V, set LVDIF to “1”. LVDIF reset to “0” by software.
Bit 6: Not used, fixed to “0” all the time.
Bit 5 (SPIF):
SPI mode interrupt flag. Flag is cleared by software.
Bit 4 (PWMBIF): PWMB (Pulse Width Modulation) interrupt flag.
Set when a selected period is reached. Reset by software.
Bit 3 (PWMAIF): PWMA (Pulse Width Modulation) interrupt flag.
Set when a selected period is reached. Reset by software.
Bit 2 (EXIF):
56 •
External interrupt flag.
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 1 (ICIF):
Port 6 input status change interrupt flag.
Set when Port 6 input changes. Reset by software.
Bit 0 (TCIF):
TCC overflow interrupt flag.
Set when TCC overflows. Reset by software.
6.3.10 Bank 0 RD: ISR2 (Interrupt Status Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMP2IF
CMP1IF
TC3IF
TC2IF
TC1IF
UERRIF
RBFF
TBEF
Bit 7 (CMP2IF): Comparator 2 Interrupt Flag. Set when a change occurs in the
output of Comparator 2. Reset by software.
Bit 6 (CMP1IF): Comparator 1 Interrupt Flag. Set when a change occurs in the output
of Comparator 1. Reset by software.
Bit 5 (TC3IF): 8-bit Timer/Counter 3 Interrupt Flag. Flag cleared by software.
Bit 4 (TC2IF): 16-bit Timer/Counter 2 Interrupt Flag. Flag cleared by software.
Bit 3 (TC1IF): 8-bit Timer/Counter 1 Interrupt Flag. Flag cleared by software.
Bit 2 (UERRIF): UART Receiving Error Interrupt. Flag cleared by software or UART
disabled.
Bit 1 (RBFF): UART receive mode data buffer full interrupt flag.
Flag cleared by software.
Bit 0 (TBEF): UART transmit mode data buffer empty interrupt flag.
Flag cleared by software.
6.3.11 Bank 0 RE: ISR3 (Interrupt Status Register 3)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
I2CSTPIF
0
I2CRIF
I2CTIF
Bits 7~4: Not used, fixed to “0” all the time.
Bit 3 (I2CSTPIF): I2C slave receive data stop interrupt flag
Bit 2: Not used, fixed to “0” all the time.
Bit 1 (I2CRIF): I2C receive interrupt flag. Set when I2C receives 1byte data and
responds ACK signal. Reset by firmware or I2C disable.
Bit 0 (I2CTIF): I2C transmit interrupt flag. Set when I2C transmits 1 byte data and
receive handshake signal (ACK or NACK). Reset by firmware or I2C
disable.
Product Specification (V1.2) 03.15.2013
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8-Bit Microcontroller
6.3.12 Bank 0 RF (Not Used)
6.3.13 Bank 0 R10: EIESCR (External Interrupt Edge Select
Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
EIES
Bits 7~1:
Not used, fixed to “0” all the time.
Bit 0 (EIES): External interrupt edge select bit
0: Falling edge interrupt
1: Rising edge interrupt
6.3.14 Bank 0 R11: WDTCR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
EIS
INT
0
PSWE
PSW2
PSW1
PSW0
Bit 7 (WDTE): Watchdog Timer enable bit. WDTE is both readable and writable.
0: Disable WDT
1: Enable WDT
Bit 6 (EIS):
P60/ /INT switch control bit. EIS is both readable and writable.
0: P60
1: /INT, external interrupt pin. In this case, the I/O control bit of P60
must be set to "1". When EIS is "0", the path of /INT is masked.
When EIS is "1", the status of /INT pin can also be read through
reading Port 6 (R6).
Bit 5 (INT):
Interrupt Enable flag
0: Interrupt masked by DISI or hardware interrupt
1: Interrupt enabled by ENI/DISI instructions
Bit 4: Not used, fixed to “0” all the time
Bit 3 (PSWE): Prescaler enable bit for WDT
0: Prescaler disabled, WDT rate is 1:1
1: Prescaler enabled, WDT rate is set from Bits 2~0
Bits 2~0 (PSW2~PSW0): WDT Prescaler bits
PSW2
0
0
0
0
1
1
1
1
58 •
PSW1
0
0
1
1
0
0
1
1
PSW0
0
1
0
1
0
1
0
1
WDT Rate
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.15 Bank 0 R12: LVDCR (Low Voltage Detector Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
LVDEN
/LVD
LVD1
LVD0
Bits 7~4:
Not used, fixed to “0” all the time.
Bit 3 (LVDEN): Low voltage detector enable bit
0: LVD disable
1: LVD enable
Bit 2 (/LVD):
Low voltage detector. This is a read only bit. When the VDD pin
voltage is lower than LVD voltage interrupt level (which is set by
LVD1 and LVD0), this bit will be cleared.
0: The low voltage is detected
1: The low voltage is not detected or LVD function is disabled
Bits1~0 (LVD1~LVD0): Low voltage detector level select bits
LVD1
0
0
1
1
LVD0
0
1
0
1
LVD Voltage Interrupt Level
2.3
3.3
4.0
4.5
6.3.16 Bank 0 R13: TCCCR (TCC Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
TCCS
TS
TE
PSTE
PST2
PST1
PST0
Bit 7: Not used, fixed to “0” all the time.
Bit 6 (TCCS):
TCC Clock Source Select Bit
0: Fs (sub clock)
1: Fm (main clock)
Bit 5 (TS):
TCC Signal Source
0: Internal oscillator cycle clock. If P77 is used as I/O pin,
TS must be “0”.
1: Transition on the TCC pin
Bit 4 (TE):
TCC Signal Edge
0: Increment if the transition from low to high takes place on the
TCC pin;
1: Increment if the transition from high to low takes place on the
TCC pin.
Product Specification (V1.2) 03.15.2013
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8-Bit Microcontroller
Bit 3 (PSTE):
Prescaler enable bit for TCC
0: Prescaler disabled, TCC rate is 1:1
1: Prescaler enabled, TCC rate is set as Bits 2~0.
Bits 2~0 (PST2~PST0): TCC Prescaler bits
PST2
0
0
PST1
0
0
PST0
0
1
TCC Rate
1:2
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
1
1
0
1
1:128
1:256
6.3.17 Bank 0 R14: TCCDATA (TCC Data Register)
Increase by an external signal edge through the TCC pin, or by the instruction cycle
clock. External signal of TCC trigger pulse width must be greater than one instruction.
The signals to increase the counter are determined by Bit 4 and Bit 5 of the TCCCR
register. This register is writable and readable as any other registers.
6.3.18 Bank 0 R15~R19 (IOCR5~IOCR9)
These registers are used to control I/O port direction. They are both readable and
writable.
0: Set the relative I/O pin as output
1: Set the relative I/O pin into high impedance
6.3.19 Bank 0 R1A~R1B (Not Used)
6.3.20 Bank 0 R1C: IMR1 (Interrupt Mask Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDIE
0
SPIE
PWMBIE
PWMAIE
EXIE
ICIE
TCIE
Bits 7 (LVDIE): LVDIF interrupt enable bit
0: Disable LVDIF interrupt
1: Enable LVDIF interrupt
Bit 6: Not used, fixed to “0” all the time.
Bit 5 (SPIE):
Interrupt enable bit
0: Disable SPIF interrupt
1: Enable SPIF interrupt
60 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 4 (PWMBIE): PWMBIF interrupt enable bit
0: Disable PWMB interrupt
1: Enable PWMB interrupt
Bit 3 (PWMAIE): PWMAIF interrupt enable bit
0: Disable PWMA interrupt
1: Enable PWMA interrupt
Bit 2 (EXIE): EXIF interrupt enable bit
0: Disable EXIF interrupt
1: Enable EXIF interrupt
Bit 1 (ICIE): ICIF interrupt enable bit
0: Disable ICIF interrupt
1: Enable ICIF interrupt
Bit 0 (TCIE): TCIF interrupt enable bit
0: Disable TCIF interrupt
1: Enable TCIF interrupt
6.3.21 Bank 0 R1D: IMR2 (Interrupt Mask Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMP2IE
CMP1IE
TC3IE
TC2IE
TC1IE
UERRIE
URIE
UTIE
Bit 7 (CMP2IE): CMP2IF interrupt enable bit
0: Disable CMP2IF interrupt
1: Enable CMP2IF interrupt
When the Comparator output status changeis used to enter interrupt
vector or enter the instruction, the CMP2IE bit must be set to
“Enable“.
Bit 6 (CMP2IE): CMP1IF interrupt enable bit
0: Disable CMP1IF interrupt
1: Enable CMP1IFinterrupt
When the Comparator output status change is used to enter interrupt
vector or enter the next instruction, the CMP1IE bit must be set to
“Enable“.
Bit 5 (TC3IE): Interrupt enable bit.
0: Disable TC3IF interrupt
1: Enable TC3IF interrupt
Product Specification (V1.2) 03.15.2013
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8-Bit Microcontroller
Bit 4 (TC2IE): Interrupt enable bit
0: Disable TC2IF interrupt
1: Enable TC2IF interrupt
Bit 3 (TC1IE): Interrupt enable bit
0: Disable TC1IF interrupt
1: Enable TC1IF interrupt
Bit 2 (UERRIE): UART receive error interrupt enable bit
0: Disable UERRIF interrupt
1: Enable UERRIF interrupt
Bit 1 (URIE):
UART receive mode Interrupt enable bit
0: Disable RBFF interrupt
1: Enable RBFF interrupt
Bit 0 (UTIE):
UART transmit mode interrupt enable bit
0: Disable TBEF interrupt
1: Enable TBEF interrupt
6.3.22 Bank 0 R1E: IMR3 (Interrupt Mask Register 3)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
I2CSTPIE
0
I2CRIE
I2CTIE
Bits 7~3: Not used, fixed to “0” all the time.
Bit 3 (I2CSTPIE): I2CSTPIF interrupt enable bit.
0: Disable I2CSTP interrupt
1: Enable I2CSTP interrupt
Bit 2: Not used, fixed to “0” all the time.
Bit 1 (I2CRIE): I2C Interface Rx interrupt enable bit
0: Disable interrupt
1: Enable interrupt
Bit 2 (I2CTIE): I2C Interface Tx interrupt enable bit
0: Disable interrupt
1: Enable interrupt
6.3.23 Bank 0 R1F (Not Used)
62 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.24 Bank 0 R20: P5WUCR (Port 5 Wake Up Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WU_P57
WU_P56
WU_P55
WU_P54
WU_P53
WU_P52
WU_P51
WU_P50
Bits 7~0 (WU_P57~WU_P50): Wake up function control for Port 5
0: Disable wake up function
1: Enable wake up function
6.3.25 Bank 0 R21: P5WUECR (Port 5 Wake-up Edge Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WUE_P57 WUE_P56 WUE_P55 WUE_P54 WUE_P53 WUE_P52 WUE_P51 WUE_P50
Bits 7~0 (WUE_P57~WUE_P50): Wake-up signal edge select for Port 5.
0: Falling edge trigger
1: Rising edge trigger
6.3.26 Bank 0 R22: P7WUCR (Port 7 Wake-up Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WU_P77
WU_P76
WU_P75
WU_P74
WU_P73
WU_P72
WU_P71
WU_P70
Bits 7~0 (WU_P77~WU_P70): Wake-up function control for Port 7.
0: Disable wake-up function
1: Enable wake-up function
6.3.27 Bank 0 R23: P7WUECR (Port 7 Wake-up Edge Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WUE_P77 WUE_P76 WUE_P75 WUE_P74 WUE_P73 WUE_P72 WUE_P71 WUE_P70
Bits 7~0 (WUE_P77~WUE_P70): Wake-up signal edge select for Port 7.
0: Falling edge trigger
1: Rising edge trigger
6.3.28 Bank 0 R24~R2A (Not Used)
Product Specification (V1.2) 03.15.2013
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8-Bit Microcontroller
6.3.29 Bank 0 R2B: SPICR (SPI Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CES
SPIE
SRO
SSE
SDOC
SBRS2
SBRS1
SBRS0
Bit 7 (CES):
Clock Edge Select bit
0: Data shifts out on a rising edge and shifts in on a falling edge. Data
is on hold during low-level.
1: Data shifts out on a falling edge and shifts in on a rising edge. Data
is on hold during high-level.
Bit 6 (SPIE): SPI Enable bit
0: Disable SPI mode
1: Enable SPI mode
Bit 5 (SRO): SPI Read Overflow bit
0: No overflow
1: A new data is received while the previous data is still being held in
the SPIR register. Under this condition, the data in the SPI Shift
register will be destroyed. To avoid setting this bit, users are
required to read the SPIR register although only transmission is
implemented. This can only occur in Slave mode.
Bit 4 (SSE):
SPI Shift Enable bit
0: Reset as soon as shifting is completed and the next byte is ready to
shift.
1: Start to shift and keep at “1” while the current byte is being
transmitted.
Bit 3 (SDOC): SDO output status control bit
0: After Serial data output, the SDO remains high
1: After Serial data output, the SDO remains low
Bits 2~0 (SBRS2~SBRS0): SPI Baud Rate Select bits
64 •
SBRS2
SBRS1
SBRS0
Mode
SPI Baud Rate
0
0
0
Master
Fosc/2
0
0
1
Master
Fosc/4
0
1
0
Master
Fosc/8
0
1
1
Master
Fosc/16
1
0
0
Master
Fosc/32
1
0
1
Master
Fosc/64
1
1
0
Slave
/SS enable
1
1
1
Slave
/SS disable
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.30 Bank0 R2C: SPIS (SPI Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DORD
TD1
TD0
0
OD3
OD4
0
RBF
Bit 7 (DORD): Data transmission order
0: Shift left (MSB first)
1: Shift right (LSB first)
Bits 6~5 (TD1~TD0): SDO status output delay time options. When CPU oscillator
source uses Fs, it delays 1 CLK time.
TD1
TD0
Delay Time
0
0
8 CLK
0
1
16 CLK
1
0
24 CLK
1
1
32 CLK
Bit 4: Not used, fixed to “0” all the time.
Bit 3 (OD3): Open Drain control bit
0: Open drain disable for SDO
1: Open drain enable for SDO
Bit 2 (OD4): Open Drain control bit
0: Open drain disable for SCK
1: Open drain enable for SCK
Bit 1: Not used, fixed to “0” all the time.
Bit 0 (RBF):
Read Buffer Full flag
0: Receiving not completed, and SPIR has not fully exchanged data.
1: Receiving completed, and SPIR has fully exchanged data.
6.3.31 Bank 0 R2D: SPIR (SPI Read Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRB7
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB0
Bits 7~0 (SRB7~SRB0): SPI Read Data Buffer
6.3.32 Bank 0 R2E: SPIW (SPI Write Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SWB7
SWB6
SWB5
SWB4
SWB3
SWB2
SWB1
SWB0
Bits 7~0 (SWB7~SWB0): SPI Write Data Buffer
Product Specification (V1.2) 03.15.2013
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EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.33 Bank 0 R2F: WUCR1 (Wake-up Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
SPIWE
LVDWE
ICWE
0
Bit 2
Bit 1
CMP2WE CMP1WE
Bit 0
EXWE
Bit 7: Not used, fixed to “0” all the time
Bit 6 (SPIWE): SPI Wake-up enable bit. Applicable only when SPI works in Slave
mode.
0: Disable SPI Wake up
1: Enable SPI Wake up.
Bit 5 (LVDWE): Low Voltage Detect Wake-up Enable bit
Bit 4 (ICWE):
Port 6 Input Status Change Wake-up enable bit
0: Disable Port 6 input status change Wake-up
1: Enable Port 6 input status change Wake-up
When the Port 6 input status change is used to enter interrupt vector
or to wake-up IC from Sleep/Idle mode, the ICWE bit must be set to
“Enable“.
Bit 3:
Not used, fixed to “0” all the time.
Bits 2~1 (CMP2WE~CMP1WE): Comparators 2~1 Wake-up enable bits
0: Disable Comparator Wake-up
1: Enable Comparator Wake-up
When the Comparators 2~1 output status change is used to enter an
interrupt vector or to Wake-up the IC from Sleep, the CMPWE bit
must be set to “Enable“.
Bit 0 (EXWE): External Interrupts Wake-up Function Enable bit
0: Disable external interrupt Wake-up
1: Enable external interrupt Wake-up
When the External Interrupt status changed is used to enter an
interrupt vector or to Wake-up the IC from Sleep, the EXWE bits
must be set to “Enable“.
6.3.34 Bank 0 R30~R31 (Not Used)
66 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.35 Bank 0 R32: URCR1 (UART Control Register 1)
Bit 7
URTD8
Bit 6
Bit 5
UMODE1 UMODE0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BRATE2
BRATE1
BRATE0
UTBE
TXE
Bit 7 (URTD8): UART transmit data buffer 8th bit
Bits 6~5 (UMODE1~UMODE0): UART mode select bits
UMODE1
UMODE0
UART Mode
0
0
Mode 1: 7-bit
0
1
Mode 1: 8-bit
1
0
Mode 1: 9-bit
1
1
Reserved
Bits 4~2 (BRATE2~BRATE0): Transmit baud rate selection
BRATE2
BRATE1
BRATE0
Baud Rate
8 MHz
0
0
0
Fc/13
38400
0
0
1
Fc/26
19200
0
1
0
Fc/52
9600
0
1
1
Fc/104
4800
1
0
0
Fc/208
2400
1
0
1
Fc/416
1200
1
1
0
TC3
−
1
1
1
Reserved
Bit 1 (UTBE): UART transfer buffer empty flag. Set to “1” when transfer buffer is
empty. Reset to “0” automatically when write into URTD register.
NOTE
UTBE bit is cleared by hardware when transmission is enabled, and
UTBE bit is read-only. Therefore, Write URTD register is necessary
when you want to start shift transmitting.
Bit 0 (TXE):
Enable transmission
0: Disable transmission
1: Enable transmission
6.3.36 Bank 0 R33: URCR2 (UART Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
SBIM1
SBIM0
UINVEN
0
0
0
Bits 7~6: Not used, fixed to “0” all the time.
Product Specification (V1.2) 03.15.2013
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8-Bit Microcontroller
Bits 5~4 (SBIM1~SBIM0): Serial bus interface operation mode select
SBIM1
SBIM0
Operation Mode
0
0
I/O mode
0
1
SPI mode
1
0
UART mode
1
1
I2C mode
Bit 3 (UINVEN): Enable UART TX and RX port inverse output
0: Disable TX and RX port inverse output
1: Enable TX and RX port inverse output
Bits 2~0: Not used, fixed to “0” all the time.
6.3.37 Bank 0 R34: URS (UART Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URRD8
EVEN
PRE
PRERR
OVERR
FMERR
URBF
RXE
Bit 7 (URRD8): UART receive data buffer 8th bit
Bit 6 (EVEN):
Select parity check
0: Odd parity
1: Even parity
Bit 5 (PRE):
Enable parity addition
0: Disable
1: Enable
Bit 4 (PRERR): Parity error flag. Set to “1” when parity error occurs and clear to “0”
by software.
Bit 3 (OVERR): Over running error flag. Set to “1” when overrun error occurs and
clear to “0” by software.
Bit 2 (FMERR): Framing error flag. Set to “1” when framing error occurs and clear to
“0” by software.
Bit 1 (URBF):
UART read buffer full flag. Set to “1” when one character is received.
Reset to “0” automatically when read from URS register. URBF is
cleared by hardware when Receive is enabled. The URBF bit is
read-only. Therefore, reading the URS register is necessary to
avoid overrun error.
Bit 0 (RXE):
Enable Receive
0: Disable Receive
1: Enable Receive
68 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.38 Bank 0 R35: URRD (UART Receive Data Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URRD7
URRD6
URRD5
URRD4
URRD3
URRD2
URRD1
URRD0
Bits 7~0 (URRD7~URRD0): UART receive data buffer. Read only.
6.3.39 Bank 0 R36: URTD (UART Transmit Data Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URTD7
URTD6
URTD5
URTD4
URTD3
URTD2
URTD1
URTD0
Bits 7~0 (URTD7~URTD0): UART transmit data buffer. Write only.
6.3.40 Bank 0 R37: TBPTL (Table Pointer Low Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
Bits 7~0 (TB7~TB0): Table point address Bits 7~0
6.3.41 Bank 0 R38: TBPTH (Table Pointer High Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HLB
GP1
GP0
TB12
TB11
TB10
TB9
TB8
Bit 7 (HLB): Take MLB or LSB at machine code
Bits 6~5 (GP1~GP0): General purpose read/write bits
Bits 4~0 (TB12~TB8): Table Pointer Address Bits 12~8.
6.3.42 Bank 0 R39: CMP1CR (Comparator 1 Control Register)
Bit 7
C1RS
Bit 6
Bit 5
Bit 4
CP1OUT CMP1COS1 CMP1COS0
Bit 3
Bit 2
CP1NS
CP1PS
Bit 1
Bit 0
CP1NRE CP1NRDT
Bit 7 (C1RS): Comparator input reference source select bit
0: CIN1+ source external
1: CIN1+ source internal
Bit 6 (CP1OUT): The result of comparator output
Product Specification (V1.2) 03.15.2013
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EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bits 5~4 (CMP1COS1~CMP1COS0): Comparator 1/OP1 select bits
CMP1COS1 CMP1COS0
Bit 3 (CP1NS):
0
0
0
1
1
0
1
1
Function Description
Comparator 1 not used. P70, P71, and
P72 act as normal I/O pin
P71 and P72 function as Comparator 1
input pin and P70 functions as normal I/O
pin
P71 and P72 function as Comparator 1
input pin and P70 functions as Comparator
1 output pin (CO1).
Reserved
Negative end of Comparator 1 is connected to ground.
0: Disable, P72/CIN1- functions as CIN11: Enable, P72/CIN1- functions as P72
Bit 2 (CP1PS):
Positive end of Comparator 1 is connected to ground.
0: Disable, P71/CIN1+ functions as CIN1+
1: Enable, P71/CIN1+ functions as P71
Bit 1 (CP1NRE): Noise Rejection Enable bit for Comparator 1
0: Disable noise rejection
1: Enable noise rejection (default)
NOTE
In Low Crystal 2 Oscillator (LXT2) mode, Green mode, and Idle
mode, the noise rejection circuits are always disabled.
Bit 0 (CP1NRDT): Comparator 1 Noise Rejection Delay Time.
In Low XTAL1 oscillator (LXT1) mode, the noise rejection high/low
pulse is always 4/Fm.
0: Comparator 1 output H/L pulse equal to 4/Fm (0.5μs at 8 MHz)
is considered as signal.
1: Comparator 1 output H/L pulse equal to 8/Fm (1μs at 8 MHz) is
considered as signal.
6.3.43 Bank 0 R3A~R3B: (Not Used)
70 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.44 Bank 0 R3C: CMP2CR (Comparator 2 Control Register)
Bit 7
C2RS
Bit 6
Bit 5
Bit 4
CP2OUT CMP2COS1 CMP2COS0
Bit 7 (C2RS):
Bit 3
Bit 2
CP2NS
CP2PS
Bit 1
Bit 0
CP2NRE CP2NRDT
Comparator 2 input reference source select bit
0: CIN2+ source external
1: CIN2+ source internal
Bit 6 (CP2OUT): The result of Comparator 2 output
Bits 5~4 (CMP1COS1~CMP1COS0): Comparator 2/OP2 select bits
CMP2COS1 CMP2COS0
Bit 3 (CP2NS):
Function Description
0
0
Comparator 2 not used. P80, P81, P82 act
as normal I/O pin
0
1
P81, P82, act as an Comparator 2 input pin
and P80 acts as normal I/O pin
1
0
P81, P82 act as an Comparator 2 input pin
and P80 acts as Comparator 2 output pin
(CO2).
1
1
Reserved
Negative end of Comparator 2 is connected to ground.
0: disable, P82/CIN2- as CIN2-.
1: enable, P82/CIN2- as P82
Bit 2 (CP2PS):
Positive end of Comparator 2 is connected to ground.
0: disable, P81/CIN2+ as CIN2+.
1: enable, P81/CIN2+ as P81
Bit 1 (CP2NRE): Noise Rejection Enable bit for Comparator 2
0: Disable noise rejection
1: Enable noise rejection (default). But in Low Crystal 2 Oscillator
(LXT2) mode, Green mode, and Idle mode, the noise rejection
circuits are always disabled.
Bit 0 (CP2NRDT): Comparator 2 Noise Rejection Delay Time.
In Low XTAL1 oscillator (LXT1) mode, the noise rejection high/low
pulse is always 4/Fm.
0: Comparator 1 output H/L pulse equal to 4/Fm (0.5 μs at 8 MHz)
is considered as signal.
1: Comparator 1 output H/L pulse equal to 8/Fm (1 μs at 8 MHz) is
considered as signal.
Product Specification (V1.2) 03.15.2013
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8-Bit Microcontroller
6.3.45 Bank 0 R3D~R42: (Not Used)
6.3.46 Bank 0 R43: CPIRLCON (Comparator Internal Reference
Level Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BG2OUT
C2IRL2
C2IRL1
C2IRL0
BG1OUT
C1IRL2
C1IRL1
C1IRL0
Bit 7 (BG2OUT): When this bit set to “1”, Pin P83 will output the bandgap reference
voltage.
Bits 6~4 (C2IRL2~C2IRL0): Comparator 2 internal reference level
Bit 3 (BG1OUT): When this bit set to “1”, Pin P73 will output the bandgap reference
voltage
Bits 2~0 (C1IRL2~C1IRL0): Comparator 1 internal reference level
CxIRL2
CxIRL1
CxIRL0
Voltage Level(V)
0
0
0
0.5
0
0
1
0.8
0
1
0
1.0
0
1
1
1.5
1
0
0
2.0
1
0
1
2.2
1
1
0
2.5
1
1
1
3.0
6.3.47 Bank 0 R44~R47: (Not Used)
6.3.48 Bank 0 R48: TC1CR (Timer 1 Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1CAP
TC1S
TC1CK1
TC1CK0
TC1M
TC1ES
0
0
Bit 7 (TC1CAP): Software capture control
0: Software capture control disabled
1: Software capture control enabled
Bit 6 (TC1S):
Timer/Counter 1 start control
0: Stop and clear counter
1: Start timer/counter
72 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bits 5~4 (TC1CK1~TC1CK0): Timer/Counter 1 clock source select bits
TC1CK1
TC1CK0
0
0
0
Clock
Source
Resolution
8 MHz
Max. Time
8 MHz
Resolution
16kHz
Max. Time
16kHz
Normal
FC=8M
FC=8M
FC=16K
FC=16K
12
512 μs
131072 μs
256 ms
65536 ms
10
128 μs
32768 μs
64 ms
16384 ms
7
FC/2
1
FC/2
1
0
FC/2
16 μs
4096 μs
8 ms
2048 ms
1
1
External
clock
(TC1 pin)
-
-
-
-
Bit 3 (TC1M):
Timer/Counter 1 mode select
0: Timer/Counter 1 mode
1: Capture mode
Bit 2 (TC1ES):
Timer/Counter 1 signal edge
0: Increment if the transition from low to high (rising edge) take
place on TC1 pin.
1: increment if the transition from high to low (falling edge) take
place on TC1 pin.
Bits 1~0:
Not used, fixed to “0” all the time.
Timer/Counter 1 Configuration
Figure 6-8a Timer/Counter 1 Configuration Block Diagram
Product Specification (V1.2) 03.15.2013
• 73
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
In Timer mode, counting up is performed using internal clock. When the contents of
up-counter match the TCR1DA, interrupt is then generated and the counter is cleared.
Counting up resumes after the counter is cleared. The current contents of the upcounter are loaded into TCR1DB by setting TC1CAP to “1” and the TC1CAP is
cleared to “0” after capture is completed automatically.
In Counter mode, counting up is performed using external clock input pin (TC1 pin)
and either rising or falling edge can be selected by TC1ES, but both edges cannot
be used. When the contents of up-counter match the TCR1DA, interrupt is then
generated and the counter is cleared. Counting up resumes after the counter is
cleared. The current contents of the up-counter are loaded into TCR1DB by setting
TC1CAP to “1” and the TC1CAP is cleared to “0” after capture is completed
automatically.
In Capture mode, the pulse width, period, and duty of the TC1 input pin are
measured under this mode to decode the remote control signal. The counter is made
free running by the internal clock. On the rising (falling) edge of TC1 pin input, the
contents of the counter are loaded into TCR1DA, then the counter is cleared and
interrupt is generated. On the falling (rising) edge of TC1 pin input, the contents of
the counter are loaded into TCR1DB. At the next rising edge of TC1 pin input while
the counter is still counting, the contents of the counter are loaded into TCR1DA.
Then the counter is cleared and interrupt is generated again. If an overflow is
detected before the edge, FFH is loaded into TCR1DA and an overflow interrupt is
generated. During the interrupt process, user can check and determine whether an
overflow has occurred by checking if the TCR1DA value is FFH. After an interrupt
(capture to TCR1DA or overflow detected) is generated, capture and overflow
detection are halted until TCR1DA is read out.
Source clock
Up-counter
K-2
1
K-1 K 0
m-1
m m+1
n-1 n 0
1
2
3
FE FF 0
1
2
3
TC1 pin input
TCR1DA
K
TCR1DB
m
capture
TC1 interrupt
n
FF (overflow)
FE
capture
overflow
Reading TCR1DA
Figure 6-8b Capture Mode Timing Diagram
74 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.49 Bank 0 R49: TCR1DA (Timer 1 Data Buffer A)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCR1DA7 TCR1DA6 TCR1DA5 TCR1DA4 TCR1DA3 TCR1DA2 TCR1DA1 TCR1DA0
Bits 7~0 (TCR1DA7~TCR1DA0): 8-bit Timer/Counter 1 of Data Buffer A
6.3.50 Bank 0 R4A: TCR1DB (Timer 1 Data Buffer B)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCR1DB7 TCR1DB6 TCR1DB5 TCR1DB4 TCR1DB3 TCR1DB2 TCR1DB1 TCR1DB0
Bits 7~0 (TCR1DB7~TCR1DB0): 8-bit Timer/Counter 1 of Data Buffer B
6.3.51 Bank 0 R4B: TC2CR (Timer 2 Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
TC2ES
TC2M
TC2S
TC2CK2
TC2CK1
TC2CK0
Bits 7~6: Not used, fixed to “0” all the time.
Bit 5 (TC2ES): TC2 signal edge
0: Increment if the transition from low to high (rising edge) takes place
on TC2 pin
1: Increment if the transition from high to low (falling edge) takes
place on TC2 pin
Bit 4 (TC2M): Timer/Counter2 mode select
0: Timer/Counter 2 mode
1: Window mode
Bit 3 (TC2S):
Timer/Counter 2 start control
0: Stop and clear counter
1: Start timer/counter
Bits 2~0 (TC2CK2~TC2CK0): Timer/Counter 2 clock source select
TC2CK2
TC2CK1
Clock
Source
TC1CK0
Normal
0
0
0
0
0
1
0
1
0
Resolution
8 MHz
Max time
8 MHz
Resolution
16kHz
Max time
16kHz
FC=8M
FC=8M
FC=16K
FC=16K
23
1.05s
19.1hr
145hr
9544hr
13
1.024ms
66.21s
512ms
33554.432s
8
32μs
2.097s
16ms
1048.576s
3
FC/2
FC/2
FC/2
0
1
1
FC/2
1μs
65.536ms
0.5ms
32768ms
1
0
0
FC
125ns
8.192ms
0.0625ms
4096ms
1
0
1
1
1
1
1
-
-
-
-
-
0
-
-
-
-
-
1
External clock
(TC2 pin)
-
-
-
-
Product Specification (V1.2) 03.15.2013
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8-Bit Microcontroller
Timer/Counter 2 Configuration
Figure 6-9a Timer/Counter 2 Configuration Block Diagram
In Timer mode, counting up is performed using internal clock. When the contents of
the up-counter match the TCR2 (TCR2H+TCR2L), interrupt is then generated and the
counter is cleared. Counting up resumes after the counter is cleared.
Internal clock
Up-counter
0
TCR2
n
1
2
3
4
5
n-3
n-2
n-1
match
n
0
1
2
3
counter clear
TC2 interrupt
Figure 6-9b Timer Mode Timing Diagram
In Counter mode, counting up is performed using external clock input pin (TC2 pin)
and either rising or falling edge can be select by setting TC2ES. When the contents
of the up-counter match the TCR2 (TCR2H+TCR2L), interrupt is then generated and
the counter is cleared. Counting up resumes after the counter is cleared.
76 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
TC2 Pin
Up-counter
0
TCR2
1
2
3
4
n-2
n-1
n 0
1
2
3
n
match
counter clear
TC2 interrupt
Figure 6-9c Counter Mode Timing (INT2ES = 1) Diagram
In Window mode, counting up is performed on rising edge of the pulse that is logical
AND of an internal clock and of the TC2 pin (window pulse). When the contents of
up-counter match the TCR2 (TCR2H+TCR2L), the interrupt is then generated and the
counter is cleared. The frequency (window pulse) must be slower than the
selected internal clock.
When writing to the TCR2L, the comparison is inhibited until TCR2H is written.
Figure 6-9d Window Mode Timing Diagram
6.3.52 Bank 0 R4C: TCR2DH (Timer 2 High Byte Data Buffer
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
TCR2D15 TCR2D14 TCR2D13 TCR2D12 TCR2D11 TCR2D10
Bit 1
Bit 0
TCR2D9
TCR2D8
Bits 7~0 (TCR2D15~ TCR2D8): 16-bit Timer/Counter 2 of high byte data buffer
Product Specification (V1.2) 03.15.2013
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8-Bit Microcontroller
6.3.53 Bank 0 R4D: TCR2DL (Timer 2 Low Byte Data Buffer
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCR2D7
TCR2D6
TCR2D5
TCR2D4
TCR2D3
TCR2D2
TCR2D1
TCR2D0
Bits 7~0 (TCR2D7~ TCR2D0): 16-bit Timer/Counter 2 of low byte data buffer
6.3.54 Bank 0 R4E: TC3CR (Timer 3 Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC3FF1
TC3FF0
TC3S
TC3CK2
TC3CK1
TC3CK0
TC3M1
TC3M0
Bits 7~6 (TC3FF1~TC3FF0): Timer/Counter 3 flip-flop control
TC3FF1
TC3FF0
Operating Mode
0
0
1
1
0
1
0
1
Clear
Toggle
Set
Reserved
Bit 5 (TC3S): Timer/Counter 3 start control
0: Stop and clear counter
1: Start timer/counter
Bits 4~2 (TC3CK2~TC3CK0): Timer/Counter 3 clock source select
TC3CK2
TC3CK1
TC3CK0
Clock Source
Resolution
8 MHz
Max Time
8 MHz
Resolutio
n 16kHz
Max Time
16kHz
Normal
FC=8M
FC=8M
FC=16K
FC=16K
0
0
0
FC/211
256μs
65536μs
128ms
32768ms
0
0
1
FC/27
16μs
4096μs
8ms
2048ms
0
1
0
FC/25
4μs
1024μs
2ms
512ms
0
1
1
FC/23
1μs
256μs
500μs
128ms
1
0
0
FC/22
500ns
128μs
250μs
64ms
1
0
1
FC/2
250ns
64μs
125μs
32ms
1
1
0
FC
125ns
32μs
62.5μs
16ms
1
1
1
External clock
(TC3 pin)
-
-
-
-
Bits 1~0 (TC3M1~TC3M0): Timer/Counter 3 operation mode select.
78 •
TC3M1
TC3M0
Operating Mode
0
0
Timer/Counter
0
1
Reserved
1
0
Programmable Divider output
1
1
Pulse Width Modulation output
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Timer/Counter 3 Configuration
Figure 6-10a Timer/Counter3 Configuration Block Diagram
In Timer mode, counting up is performed using the internal clock (rising edge trigger).
When the contents of up-counter match the TCR3D, the interrupt is generated and
the counter is then cleared. Counting up resumes after the counter is cleared.
In Counter mode, counting up is performed using the external clock input pin (TC3
pin). When the contents of up-counter match the TCR3D, interrupt is generated and
the counter is then cleared. Counting up resumes after the counter is cleared.
In Programmable Divider Output (PDO) mode, counting up is performed using the
internal clock. The contents of TCR3D are compared with the contents of up-counter.
The F/F output is toggled and the counter is cleared each time a match is found. The
F/F output is inverted and output to /PDO pin. This mode can generate 50% duty pulse
output. The F/F can be initialized by programming and it is initialized to “0”
during a reset. A TC3 interrupt is generated each time the /PDO output is toggled.
Figure 6-10b PDO Mode Timing Diagram
Product Specification (V1.2) 03.15.2013
• 79
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
In Pulse Width Modulation (PWM) Output mode, counting up is performed using
internal clock. The contents of TCR3 are compared with the contents of up-counter.
The F/F is toggled when match is found. While the counter continues counting, the
F/F is toggled again when counter overflow occurs, then counter is cleared. The F/F
output is inverted and output to /PWM pin. A TC3 interrupt is generated each time an
overflow occurs. TCR3 is configured as 2-stage shift register and, during output,
will not switch until one output cycle is completed even if TCR3 is overwritten.
Therefore, the output can be changed continuously. TRC3 is also shifted for the first
time by setting TC3S to “1” after data is loaded to TCR3.
Figure 6-10c PWM Mode Timing Diagram
6.3.55 Bank 0 R4F: TCR3D (Timer 3 Duty Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCR3D7
TCR3D6
TCR3D5
TCR3D4
TCR3D3
TCR3D2
TCR3D1
TCR3D0
Bits 7~0 (TCR3DB7~TCR13DB0): 8-bit Timer/Counter 3 of duty data buffer
6.3.56 Bank 1 R5: P5PHCR (Port 5 Pull High Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH57
/PH56
/PH55
/PH54
/PH53
/PH52
/PH51
/PH50
Bit 7 (/PH57): Control bit used to enable pull high of the P57 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PH56): Control bit used to enable pull high of the P56 pin
Bit 5 (/PH55): Control bit used to enable pull high of the P55 pin
Bit 4 (/PH54): Control bit used to enable pull high of the P54 pin
Bit 3 (/PH53): Control bit used to enable pull high of the P53 pin
Bit 2 (/PH52): Control bit used to enable pull high of the P52 pin
Bit 1 (/PH51): Control bit used to enable pull high of the P51 pin
Bit 0 (/PH50): Control bit used to enable pull high of the P50 pin
80 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.57 Bank 1 R6: P6PHCR (Port 6 Pull High Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH67
/PH66
/PH65
/PH64
/PH63
/PH62
/PH61
/PH60
Bit 7 (/PH67): Control bit used to enable pull high of the P67 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PH66): Control bit used to enable pull high of the P66 pin
Bit 5 (/PH65): Control bit used to enable pull high of the P65 pin
Bit 4 (/PH64): Control bit used to enable pull high of the P64 pin
Bit 3 (/PH63): Control bit used to enable pull high of the P63 pin
Bit 2 (/PH62): Control bit used to enable pull high of the P62 pin
Bit 1 (/PH61): Control bit used to enable pull high of the P61 pin
Bit 0 (/PH60): Control bit used to enable pull high of the P60 pin
6.3.58 Bank 1 R7: P7PHCR (Port 7 Pull High Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH77
/PH76
/PH75
/PH74
/PH73
/PH72
/PH71
/PH70
Bit 7 (/PH77): Control bit used to enable pull high of the P77 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PH76): Control bit used to enable pull high of the P76 pin
Bit 5 (/PH75): Control bit used to enable pull high of the P75 pin
Bit 4 (/PH74): Control bit used to enable pull high of the P74 pin
Bit 3 (/PH73): Control bit used to enable pull high of the P73 pin
Bit 2 (/PH72): Control bit used to enable pull high of the P72 pin
Bit 1 (/PH71): Control bit used to enable pull high of the P71 pin
Bit 0 (/PH70): Control bit used to enable pull high of the P70 pin
6.3.59 Bank 1 R8: P8PHCR (Port 8 Pull High Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH87
/PH86
/PH85
/PH84
/PH83
/PH82
/PH81
/PH80
Bit 7 (/PH87): Control bit used to enable pull high of the P87 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PH86): Control bit used to enable pull high of the P86 pin
Bit 5 (/PH85): Control bit used to enable pull high of the P85 pin
Bit 4 (/PH84): Control bit used to enable pull high of the P84 pin
Product Specification (V1.2) 03.15.2013
• 81
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 3 (/PH83): Control bit used to enable pull high of the P83 pin
Bit 2 (/PH82): Control bit used to enable pull high of the P82 pin
Bit 1 (/PH81): Control bit used to enable pull high of the P81 pin
Bit 0 (/PH80): Control bit used to enable pull high of the P80 pin
6.3.60 Bank 1 R9: P9PHCR (Port 9 Pull High Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH97
/PH96
/PH95
/PH94
/PH93
/PH92
/PH91
/PH90
Bit 7 (/PH97): Control bit used to enable pull high of the P97 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PH96): Control bit used to enable pull high of the P96 pin
Bit 5 (/PH95): Control bit used to enable pull high of the P95 pin
Bit 4 (/PH94): Control bit used to enable pull high of the P94 pin
Bit 3 (/PH93): Control bit used to enable pull high of the P93 pin
Bit 2 (/PH92): Control bit used to enable pull high of the P92 pin
Bit 1 (/PH91): Control bit used to enable pull high of the P91 pin
Bit 0 (/PH90): Control bit used to enable pull high of the P90 pin
6.3.61 Bank 1 RA (Not Used)
6.3.62 Bank 1 RB: P5PLCR (Port 5 Pull Low Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PL57
/PL56
/PL55
/PL54
/PL53
/PL52
/PL51
/PL50
Bit 7 (/PL57): Control bit used to enable pull low of the P57 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PL56): Control bit used to enable pull low of the P56 pin
Bit 5 (/PL55): Control bit used to enable pull low of the P55 pin
Bit 4 (/PL54): Control bit used to enable pull low of the P54 pin
Bit 3 (/PL53): Control bit used to enable pull low of the P53 pin
Bit 2 (/PL52): Control bit used to enable pull low of the P52 pin
Bit 1 (/PL51): Control bit used to enable pull low of the P51 pin
Bit 0 (/PL50): Control bit used to enable pull low of the P50 pin
82 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.63 Bank 1 RC: P6PLCR (Port 6 Pull Low Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PL67
/PL66
/PL65
/PL64
/PL63
/PL62
/PL61
/PL60
Bit 7 (/PL67): Control bit used to enable pull low of the P67 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PL66): Control bit used to enable pull low of the P66 pin
Bit 5 (/PL65): Control bit used to enable pull low of the P65 pin
Bit 4 (/PL64): Control bit used to enable pull low of the P64 pin
Bit 3 (/PL63): Control bit used to enable pull low of the P63 pin
Bit 2 (/PL62): Control bit used to enable pull low of the P62 pin
Bit 1 (/PL61): Control bit used to enable pull low of the P61 pin
Bit 0 (/PL60): Control bit used to enable pull low of the P60 pin
6.3.64 Bank 1 RD: P7PLCR (Port 7 Pull Low Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PL77
/PL76
/PL75
/PL74
/PL73
/PL72
/PL71
/PL70
Bit 7 (/PL77): Control bit used to enable pull low of the P77 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PL76): Control bit used to enable pull low of the P76 pin
Bit 5 (/PL75): Control bit used to enable pull low of the P75 pin
Bit 4 (/PL74): Control bit used to enable pull low of the P74 pin
Bit 3 (/PL73): Control bit used to enable pull low of the P73 pin
Bit 2 (/PL72): Control bit used to enable pull low of the P72 pin
Bit 1 (/PL71): Control bit used to enable pull low of the P71 pin
Bit 0 (/PL70): Control bit used to enable pull low of the P70 pin
Product Specification (V1.2) 03.15.2013
• 83
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.65 Bank 1 RE: P8PLCR (Port 8 Pull Low Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PL87
/PL86
/PL85
/PL84
/PL83
/PL82
/PL81
/PL80
Bit 7 (/PL87): Control bit used to enable pull low of the P87 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PL86): Control bit used to enable pull low of the P86 pin
Bit 5 (/PL85): Control bit used to enable pull low of the P85 pin
Bit 4 (/PL84): Control bit used to enable pull low of the P84 pin
Bit 3 (/PL83): Control bit used to enable pull low of the P83 pin
Bit 2 (/PL82): Control bit used to enable pull low of the P82 pin
Bit 1 (/PL81): Control bit used to enable pull low of the P81 pin
Bit 0 (/PL80): Control bit used to enable pull low of the P80 pin
6.3.66 Bank 1 RF: P9PLCR (Port 9 Pull Low Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PL97
/PL96
/PL95
/PL94
/PL93
/PL92
/PL91
/PL90
Bit 7 (/PL97): Control bit used to enable the pull low of P97 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PL96): Control bit used to enable pull low of the P96 pin
Bit 5 (/PL95): Control bit used to enable pull low of the P95 pin
Bit 4 (/PL94): Control bit used to enable pull low of the P94 pin
Bit 3 (/PL93): Control bit used to enable pull low of the P93 pin
Bit 2 (/PL92): Control bit used to enable pull low of the P92 pin
Bit 1 (/PL91): Control bit used to enable pull low of the P91 pin
Bit 0 (/PL90): Control bit used to enable pull low of the P90 pin
6.3.67 Bank 1 R10 (Not Used)
6.3.68 Bank 1 R11: P5HD/SCR (Port 5 High Drive/Sink Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/H57
/H56
/H55
/H54
/H53
/H52
/H51
/H50
Bits 7~0 (/H57~/H50): P57~P50 high drive/sink current control bits
0: Enable high drive/sink
1: Disable high drive/sink
84 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.69 Bank 1 R12: P6HD/SCR (Port 6 High Drive/Sink Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/H67
/H66
/H65
/H64
/H63
/H62
/H61
/H60
Bits 7~0 (/H67~/H60): P67~P60 high drive/sink current control bits
0: Enable high drive/sink
1: Disable high drive/sink
6.3.70 Bank 1 R13: P7HD/SCR (Port 7 High Drive/Sink Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/H77
/H76
/H75
/H74
/H73
/H72
/H71
/H70
Bits 7~0 (/H77~/H70): P77~P70 high drive/sink current control bits
0: Enable high drive/sink
1: Disable high drive/sink
6.3.71 Bank 1 R14: P8HD/SCR (Port 8 High Drive/Sink Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/H87
/H86
/H85
/H84
/H83
/H82
/H81
/H80
Bits 7~0 (/H87~/H80): P87~P80 high drive/sink current control bits
0: Enable high drive/sink
1: Disable high drive/sink
6.3.72 Bank 1 R15: P9HD/SCR (Port 9 High Drive/Sink Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/H97
/H96
/H95
/H94
/H93
/H92
/H91
/H90
Bits 7~0 (/H97~/H90): P97~P90 high drive/sink current control bits
0: Enable high drive/sink
1: Disable high drive/sink
6.3.73 Bank 1 R16 (Not Used)
Product Specification (V1.2) 03.15.2013
• 85
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.74 Bank 1 R17: P5ODCR (Port 5 Open Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD57
OD56
OD55
OD54
OD53
OD52
OD51
OD50
Bits 7~0 (OD57~OD50): Open-Drain control bits
0: Disable open-drain function
1: Enable open-drain function
6.3.75 Bank 1 R18: P6ODCR (Port 6 Open Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD67
OD66
OD65
OD64
OD63
OD62
OD61
OD60
Bits 7~0 (OD67~OD60): Open-Drain control bits
0: Disable open-drain function
1: Enable open-drain function
6.3.76 Bank 1 R19: P7ODCR (Port 7 Open Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD77
OD76
OD75
OD74
OD73
OD72
OD71
OD70
Bits 7~0 (OD77~OD70): Open-Drain control bits
0: Disable open-drain function
1: Enable open-drain function
6.3.77 Bank 1 R1A: P8ODCR (Port 8 Open Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD87
OD86
OD85
OD84
OD83
OD82
OD81
OD80
Bits 7~0 (OD87~OD80): Open-Drain control bits
0: Disable open-drain function
1: Enable open-drain function
6.3.78 Bank 1 R1B: P9ODCR (Port 9 Open Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD97
OD96
OD95
OD94
OD93
OD92
OD91
OD90
Bits 7~0 (OD97~OD90): Open-Drain control bits
0: Disable open-drain function
1: Enable open-drain function
86 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.79 Bank 1 R1C (Not Used)
6.3.80 Bank 1 R1D: IRCS (IRC Frequency Selection Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
RCM1
RCM0
0
0
0
0
Bits 7~6: Not used, fixed to “0” all the time.
Bits 5~4 (RCM1 ~ RCM0): IRC Mode Frequency select bits
RCM 1
0
0
1
1
RCM 0
0
1
0
1
Frequency (MHz)
4
16
8
455kHz
Word 1 COBS0 = 0: The R1D<5, 4> of the initialized values will be
kept the same as Word 1<6,5>.
The R1D<5, 4> can’t be changed.
Word 1 COBS0 = 1: The R1D<5, 4> of the initialized values will be
kept the same as Word 1<6,5>.
The R1D<5, 4> can be changed if user wants to
work on other IRC frequency.
Ex: 4M Æ16M
Bits 3~0: Not used, fixed to “0” all the time.
6.3.81 Bank 1 R1E (Not Used)
6.3.82 Bank 1 R1F: EEPROM Control
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RD
WR
EEWE
EEDF
EEPC
0
0
0
Bit 7 (RD):
Read control bit
0: Don’t execute EEPROM read
1: Read EEPROM contents (RD can be set by software. When Read
instruction is completed, RD will be cleared by hardware.)
Bit 6 (WR):
Write control bit
0: Write cycle to the EEPROM is completed.
1: Initiate a Write cycle (WR can be set by software. When Write
cycle is completed, WR will be cleared by hardware.)
Bit 5 (EEWE): EEPROM Write enable bit
0: Prohibit Write to the EEPROM
1: Allow EEPROM Write cycles
Product Specification (V1.2) 03.15.2013
• 87
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 4 (EEDF): EEPROM Detect flag
0: Write cycle is completed
1: Write cycle is uncompleted
Bit 3 (EEPC): EEPROM power down control bit
0: Switch OFF EEPROM
1: EEPROM is operating
Bits 2~0:
Not used, fixed to “0” all the time.
NOTE
The EM78F548N currently does not support EEPROM function. Therefore, the
corresponding control registers (Bank 1 R1F~R21) are reserved.
6.3.83 Bank 1 R20: EEPROM ADDR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EERA7
EERA6
EERA5
EERA4
EERA3
EERA2
EERA1
EERA0
Bits 7~0 (EERA7~EERA0): EEPROM address register
NOTE
The EM78F548N currently does not support EEPROM function. Therefore, the
corresponding control registers (Bank 1 R1F~R21) are reserved.
6.3.84 Bank 1 R21: EEPROM DATA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EERD7
EERD6
EERD5
EERD4
EERD3
EERD2
EERD1
EERD0
Bits 7~0 (EERD7~EERD0): EEPROM data register. Read only.
NOTE
The EM78F548N currently does not support EEPROM function. Therefore, the
corresponding control registers (Bank 1 R1F~R21) are reserved.
6.3.85 Bank1 R22 (Not Used)
6.3.86 Bank1 R23: I2CCR1 (I2C Status and Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Strobe/Pend
IMS
ISS
STOP
SAR_EMPTY
ACK
FULL
EMPTY
Bit 7 (Strobe/Pend): In Master mode, it is used as strobe signal to control I2C circuit
in sending SCL clock. Automatically resets after receiving or
transmitting handshake signal (ACK or NACK). In Slave mode, it is
used as pending signal. You should clear it after filling data into Tx
buffer or taking data from Rx buffer to inform the Slave I2C circuit to
release SCL signal.
88 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 6 (IMS):
I2C Master/Slave mode select bit.
0: Slave
1: Master
Bit 5 (ISS):
I2C Fast/Standard mode select bit (If Fm is 4MHz and I2CTS1~0<0,0>)
0: Standard mode (100K bit/s)
1: Fast mode (400K bit/s)
Bit 4 (STOP): In Master mode, if STOP=1 and R/nW=1, then EM78F648N/F548N
must return an nACK signal to the Slave device before sending a
STOP signal. If STOP=1 and R/nW=0, then EM78F648N/F548N
sends a STOP signal after receiving an ACK signal. Resets when
EM78F648N/F548N sends a STOP signal to the Slave device.
In Slave mode, if STOP=1 and R/nW=0, then EM78F648N/F548N
must return an nACK signal to the Master device.
Bit 3 (SAR_EMPTY): Set when EM78F648N/F548N transmits 1 byte data from I2C
Slave Address Register and receive an ACK (or nACK) signal. Reset
when the MCU writes 1 byte data to the I2C Slave Address Register.
Bit 2 (ACK): The ACK condition bit is set to “1” by hardware when the device
responds acknowledge (ACK). Resets when the device responds with
a “not-acknowledge” (nACK) signal.
Bit 1 (FULL): Set by hardware when I2C Receive (Rx) Buffer register is full. Resets
by hardware when MCU reads data from I2C Receive (Rx) Buffer
register.
Bit 0 (EMPTY): Set by hardware when I2C Transmit (Tx) Buffer register is empty and
receive ACK (or nACK) signal. Reset by hardware when MCU writes
new data to I2C Transmit (Tx) Buffer register.
6.3.87 Bank 1 R24: I2CCR2 (I2C Status and Control Register2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2CBF
GCEN
0
0
I2CTS1
I2CTS0
0
I2CEN
Bit 7 (I2CBF): I2C Busy Flag bit
0: Clear to “0” under Slave mode if the received STOP signal or I2C
Slave address does not match.
1: Set when I2C communicate with Master in Slave mode.
Bit 6 (GCEN): I2C General Call Function Enable bit
0: Disable General Call Function
1: Enable General Call Function
Bits 5~4:
Not used, fixed to “0” all the time.
Product Specification (V1.2) 03.15.2013
• 89
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bits 3~2 (I2CTS1~I2CTS0): I2C Transmit Clock Source Select bits (When I2CCS=0).
When operating under different Fm, these bits must be set to correct
value to let SCL clock match with Standard/Fast mode.
I2CCR1 Bit 5=0, Standard mode:
I2CTS1
I2CTS0
SCL CLK
Operating Fm (MHz)
0
0
Fm/40
4
0
1
Fm/80
8
1
0
Fm/120
12
1
1
Fm/160
16
I2CCR1 Bit5=1, Fast mode:
I2CTS1
I2CTS0
SCL CLK
Operating Fm (MHz)
0
0
Fm/10
4
0
1
Fm/20
8
1
0
Fm/30
12
1
1
Fm/40
16
Bit 1: Not used, fixed to “0” all the time.
Bit 0 (I2CEN): I2C Enable Bit
0: Disable I2C mode
1: Enable I2C mode
6.3.88 Bank 1 R25: I2CSA (I2C Slave Address Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SA6
SA5
SA4
SA3
SA2
SA1
SA0
IRW
Bits 7~1 (SA6~SA0): When EM78F648N/F548N is used as Master device for I2C
application, this is the Slave device address register.
Bit 0 (IRW):
When EM78F648N is used as Master device for I2C application, this
bit is Read/Write transaction control bit.
0: Write
1: Read
6.3.89 Bank 1 R26: I2CDA (I2C Device Address Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
Bits 7~0 (DA7~DA0): When EM78F648N/F548N is used as Slave device for I2C
application, this register stores the address of EM78F648N/F548N. It
is used to identify the data on the I2C bus and to extract the message
delivered to the EM78F648N/F548N.
90 •
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(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.90 Bank 1 R27: I2CDB (I2C Data Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Bits 7~0 (DB7~DB0): I2C Receive/Transmit Data Buffer.
6.3.91 Bank 1 R28: I2CA (I2C Data Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
DA9
DA8
Bits 7~2: Not used, fixed to “0” all the time.
Bits 1~0 (DA9~DA8): Device Address high bits
6.3.92 Bank 1 R29 (Not Used)
6.3.93 Bank 1 R2A: PWMER (PWM Enable Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
PWMBE
PWMAE
Bits 7~2: Not used, fixed to “0” all the time.
Bit 1 (PWMBE): PWM B Enable bit
0: PWM B is off (default value), and its related Pin P52 carries out
the I/O pin function.
1: PWM B is on, and its related pin is automatically set to output.
Bit 0 (PWMAE): PWM A Enable bit
0: PWM A is OFF (default value), and its related pin carries out the
I/O pin function.
1: PWM A is ON, and its related pin is automatically set to output.
6.3.94 Bank 1 R2B: TIMEN (Timer/PWM Enable Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
TBEN
TAEN
Bits 7~2: Not used, fixed to “0” all the time.
Bit 1 (TBEN):
Timer B enable bit
0: Timer B is off (Default)
1: Timer B is on
Bit 0 (TAEN):
Timer A enable bit
0: Timer A is off (Default)
1: Timer A is on
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6.3.95 Bank 1 R2C~R2E: (Not Used)
6.3.96 Bank 1 R2F: PWMACR (PWM A Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
TRCBA
0
0
0
Bits 7~4: Not used, fixed to “0” all the time.
Bit 3(TRCBA):
Timer A Read Control bit
0: When this bit set to “0”, the values of PRDA[9]~PRDA[0] in
PRDAL and PRDxH are PWMA period data.
1: When this bit set to “1”, READ values FROM PRDA[9]~PRDA[0]
in PRDAL and PRDxH are PWMA timer data.
Bits 2~0: Not used, fixed to “0” all the time.
6.3.97 Bank 1 R30: PWMBCR (PWM B Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
TRCBB
0
0
0
Bits 7~4: Not used, fixed to “0” all the time.
Bit 3(TRCBB): B Read Control bit
0: When this bit set to 0, the values of PRDB[9]~PRDB[0] in PRDBL
and PRDxH are PWMB period data
1: When this bit set to 1, the values of PRDB[9]~PRDB[0] in PRDBL
and PRDxH are PWMB timer data
Bits 2~0: Not used, fixed to “0” all the time.
6.3.98 Bank 1 R31: (Not Used)
6.3.99 Bank 1 R32: TACR (Timer A Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
TAP2
TAP1
TAP0
Bits 7~3: Not used, fixed to “0” all the time.
92 •
TAP2
TAP1
T1AP0
Prescaler
0
0
0
1 : 2 (Default)
0
0
1
1:4
0
1
0
1:8
0
1
1
1 : 16
1
0
0
1 : 32
1
0
1
1 : 64
1
1
0
1 : 128
1
1
1
1 : 256
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.3.100 Bank1 R33: TBCR (Timer B Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
TBP2
TBP1
TBP0
Bits 7~3: Not used, fixed to “0” all the time.
Bits 2~0 (TBP2~TBP0): Timer B Prescaler bits
TBP2
TBP1
TBP0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Prescaler
1 : 2 (Default)
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
6.3.101 Bank 1 R34: (Not Used)
6.3.102 Bank 1 R35: TAPRDH (Timer A Period Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRDA[9]
PRDA[8]
PRDB[7]
PRDB[6]
PRDB[5]
PRDB[4]
PRDB[3]
PRDB[2]
Bits 7~0 (PRDA[9]~PRDA[2]): The contents of this register is a period of Timer A.
6.3.103 Bank 1 R36: TBPRDH (Timer B Period Buffer Register)
Bit 7
Bit 6
Bit 5
PRDB[9]
PRDB[8]
PRDB[7]
Bit 4
PRDB[6]
Bit 3
PRDB[5]
Bit 2
PRDB[4]
Bit 1
PRDB[3]
Bit 0
PRDB[2]
Bits 7~0 (PRDB[9]~PRDB[2]): The contents of this register is a period of Timer B.
6.3.104 Bank 1 R37: (Not Used)
6.3.105 Bank 1 R38: TADTH (Timer A Duty Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DTA[9]
DTA[8]
DTA[7]
DTA[6]
DTA[5]
DTA[4]
DTA[3]
DTA[2]
Bits 7~0 (DTA[9]~ DTA[2]): The contents of this register is a duty of Timer A.
6.3.106 Bank 1 R39: TBDTH (Timer B Duty Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DTB[9]
DTB[8]
DTB[7]
DTB[6]
DTB[5]
DTB[4]
DTB[3]
DTB[2]
Bits 7~0 (DTB[7]~DTB[0]): The contents of this register is a duty of Timer B.
6.3.107 Bank 1 R3A: (Not Used)
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6.3.108 Bank 1 R3B: PRDxL (PWM A/B/C Period Buffer Low Bits
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
PRDB[1]
PRDB[0]
PRDA[1]
PRDA[0]
Bits 7~4: Not used, fixed to “0” all the time.
Bits 3~2 (PRDB[1]~PRDB[0]): PWM B period buffer low bits
Bits 1~0 (PRDA[1]~PRDA[0]): PWM A period buffer low bits
6.3.109 Bank 1 R3C: DTxL (PWM1/2 Duty Buffer Low Bits
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
DTB[1]
DTB[0]
DTA[1]
DTA[0]
Bits 7~4: Not used, fixed to “0” all the time.
Bits 3~2 (DTB[1]~DTB[0]):
PWM B duty buffer high bits
Bits 1~0 (DTA[1]~DTA[0]):
PWM A duty buffer high bits
6.3.110 Bank 1 R3D~R4F (Not Used)
6.3.111 Bank 0 R50~R7F, Bank0~1 R80~RFF
These are all 8-bit general-purpose registers.
6.4 TCC/WDT and Prescaler
Two 8-bit counters are available as prescalers for the TCC and WDT respectively.
The PST0~PST2 bits of the TCCCR register (Bank 0 R13) are used to determine the
ratio of the prescaler of TCC. Likewise, the PSW0~PSW2 bits of the WDTCR register
Bank 0 R11) are used to determine the prescaler of WDT. The prescaler counter is
cleared by the instructions each time they are written into TCC. The WDT and
prescaler are cleared by the “WDTC” and “SLEP” instructions. Figure 6-11 depicts
the circuit diagram of the TCC/WDT.
TCCDATA (Bank 0 R14) is an 8-bit timer/counter. The clock source of TCC can be
internal clock or external signal input (edge selectable from the TCC pin). If the TCC
signal source is from the internal clock, TCC will be incremented by 1 at Fc clock
(without prescaler). As illustrated in the following figure, if TCC signal source is from
an external clock input, TCC will be incremented by 1 at every falling edge or rising
edge of the TCC pin. The TCC pin input time length (keep in High or low level) must
be greater than 1/Fc. The TCC will stop running when sleep mode occurs.
94 •
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(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on
running even after the oscillator driver has been turned off (i.e., in Sleep mode).
During the normal operation or the Sleep mode, a WDT time-out (if enabled) will
cause the device to reset. The WDT can be enabled or disabled at any time during
Normal mode by software programming. Refer to WDDTE bit of Bank 0 R11 register
(Section 6.3.14). Without prescaler, the WDT time-out period is approximately 18
ms 1 (one oscillator start-up timer period).
Fc
0
TCC Pin
1
TS (CONT)
WDTE
(IOCA)
Data Bus
8 to 1 MUX
TCC (R1)
MUX
TE (CONT)
WDT
8-Bit Counter
8-Bit counter
8 to 1 MUX
WDT Time out
Prescaler
PST2~0
(CONT)
TCC overflow
interrupt
Prescaler
PSW2~0
(IOCA)
Figure 6-11 TCC and WDT Block Diagram
6.5 I/O Ports
6.5.1 I/O for EM78F644N/642/641/544/542/541N
The I/O registers, Ports 5, 6, 7, and 8, are bidirectional tri-state I/O ports. Port 6 or
Port 7 can be pulled high internally by software. Moreover, Port 6 can also have an
open-drain output by software. Input status change interrupt (or wake-up) function on
Port 6 P50~P53, P60 ~ P63, and Port 7 pins can be pulled down by software. Each
I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~
IOC8).
The I/O registers and I/O control registers are both readable and writable.
1
VDD=5V, WDT time-out period = 16.5ms ± 8%, VDD=3V, WDT time-out period = 18ms ± 8%.
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6.5.2 I/O for EM78F648/548N
The I/O registers, Port 5~Port 9 are bi-directional tri-state I/O ports. All have high
sink/drive setting by software. Port 5, Port 6, and Port 7 also feature Wake up
function. Furthermore, Port 6 is also equipped with input status change interrupt
function. Each I/O pin can be defined as "input" or "output" pin by the I/O control
register (IOC5 ~ IOC9).
The I/O registers and I/O control registers are both readable and writable.
The Table below shows the usage of EM78F64xN/54xN Port 6 Input Change Wakeup/Interrupt functions:
Usage of Port 6 input status changed Wake-up/Interrupt
I. Wake-up from Port 6 Input Status Change
II Port 6 Input Status Change Interrupt
a) Before SLEEP
1. Read I/O Port 6 (MOV R6,R6)
2
1. Disable WDT (execute very carefully)
2. Execute "ENI"
2. Read I/O Port 6 (MOV R6,R6)
3. Enable interrupt
3. Enable interrupt: After wake-up, if “ENI,” switch
to interrupt vector (006H). If “DISI,” execute the
next instruction.
4. IF Port 6 change (interrupt) → Interrupt vector
(006H)
Disable interrupt: Always execute the next
instruction.
4. Enable wake-up enable bit
5. Execute "SLEP" instruction
b) After Wake-up
1. If "ENI" Æ Interrupt vector (006H)
2. If "DISI" Æ Next instruction
2
Software disables WDT (watchdog timer) but hardware must be enabled before applying Port 6 Change
Wake-up function (Code Option Register and Bit 11 (ENWDTB-) set to “1”).
96 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.6 UART (Universal Asynchronous Receiver/Transmitter)
Figure 6-12a UART Function Block Diagram
In Universal Asynchronous Receiver Transmitter (UART), each transmitted or received
character is individually synchronized by framing it with a start bit and stop bit.
Full duplex data transfer is possible since the UART has independent transmit and
receive sections. Double buffering for both sections allows the UART to be
programmed for continuous data transfer.
The figure below shows the general format of one character sent or received. The
communication channel is normally held in the marked state (high). Character
transmission or reception starts with a transition to the space state (low).
The first bit transmitted or received is the start bit (low). It is followed by the data bits,
in which the least significant bit (LSB) comes first. The data bits are followed by the
parity bit. If present, then the stop bit or bits (high) confirm the end of the frame.
In receiving, the UART synchronizes on the falling edge of the start bit. When two or
three “0” are detected during three samples, it is recognized as normal start bit and
the receiving operation is started.
Figure 6-12b UART Data Format
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6.6.1 UART Mode
Three UART modes are available. Mode 1 (7 bits data) and Mode 2 (8 bits data)
allow the addition of parity bits. The parity bit addition is not available in Mode 3.
Figure below shows the data format in each mode.
Figure 6-13 UART Modes 1, 2, &3 Data Formats
6.6.2 Transmitting
In transmitting serial data, the UART operates as follows:
1. Sets the TXE bit of the URCR1 register to enable the UART transmission function.
2. Writes data into the URTD register and the UTBE bit of the URCR1 register will
be set by hardware.
3. Then start transmitting.
4. Serially transmitted data in the following order from the TX pin (see Figure 6-12b
above):
a) Start bit:
One “0” bit is output.
b) Transmit data: 7, 8, or 9 bits data are output from the LSB to the MSB.
c) Parity bit:
One parity bit (odd or even selectable) is output.
d) Stop bit:
One “1” bit (stop bit) is output.
e) Mark state:
Output “1” continues until the start bit of the next transmitted
data.
NOTE
After transmitting the Stop bit, the UART generates a TBEF interrupt (if enabled).
98 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.6.3
Receiving
During Receiving, the UART operates as follows:
1. Sets RXE bit of the URS register to enable the UART receiving function. The
UART monitors the RX pin and synchronizes internally when it detects a Start bit.
2. Received data is shifted into the URRD register in LSB to MSB order.
3. The parity bit and the stop bit are received. After one character is received, the
URBF bit of the URS register will be set to “1” to allow UART interrupt to occur.
4. The UART then makes the following checks:
a) Parity check:
The number of ones (“1”) of the received data must match
the even or odd parity setting of the EVEN bit in the URS
register.
b) Frame check:
The start bit must be “0” and the stop bit must be “1”.
c) Overrun check: The URBF bit of the URS register must be cleared (i.e., the
URRD register should be read out) before the next received
data is loaded into the URRD register.
If any of the checks failed, the UERRIF interrupt will be generated (if enabled),
and an error flag is indicated in PRERR, OVERR or FMERR bit. The error flag
should be cleared by software. Otherwise, UERRIF interrupt will occur when the
next byte is received.
5. Read the received data from the URRD register and the URBF bit will be cleared
by hardware.
6.6.4 Baud Rate Generator
The baud rate generator features a circuit that generates a clock pulse to determine
the transfer speed for transmission/reception in the UART.
The BRATE 2 ~ BRATE 0 bits of the URC register determine the desired baud rate.
6.6.5 UART Timing
Transmission Counter Timing:
Figure 6-14a UART Transmission Counter Timing Diagram
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Receiving Counter Timing:
Figure 6-14b UART Receiving Counter Timing Diagram
6.7 SPI Function
6.7.1 Overview and Features
6.7.1.1 Overview
Figures 6-15a, 6-15b, and 6-16a below, illustrate how the MCUs communicate with
other devices through SPI module. If the MCUs are Master controllers, they send
clock through the SCK pin. A couple of 8-bit data are transmitted and received at the
same time. However, if the MCUs are defined as Slaves, their SCK pins could be
programmed as input pins. Data will continue to be shifted based on both the clock
rate and the selected edge. User can also set the SPIS Bit 7(DORD) to decide the
SPI transmission order, set the SPIS Bit 6 (TD1), Bit 5 (TD0) to determine the SDO
status output delay time (see Section 6.3.30), and set SPICR Bit 3 (SDOC) to
determine SDO pin status after serial data output (see Section 6.3.29).
6.7.1.2 Features
Operation in either Master mode or Slave mode
Three-wire or four-wire full duplex synchronous communication
Programmable baud rates of communication
Programming clock polarity
Interrupt flag available for the read buffer full
SPI transmission order
After serial data output SDO status select
SDO status output delay time
SPI handshake pin
Up to 2 MHz (maximum) bit frequency. If the system frequency (Fosc) operates at
8 MHz, it is recommended to choose Fosc/4 as maximum baud rate option for the
SPI function.
100 •
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Figure 6-15a SPI Master/Slave Communication Block Diagram
Figure 6-15b Single-Master and Multi-Slave SPI Configuration
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6.7.2 SPI Function Description
Figure 6-16a SPI Function Block Diagram
Figure 6-16b SPI Transmission Function Block Diagram
102 •
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8-Bit Microcontroller
The following describes the functions of each block and on how to carry out the SPI
communication with the signals depicted in Figures 6-16a and 6-16b above.

SI: Serial Data In

SO: Serial Data Out

SCK: Serial Clock

/SS: /Slave Select (Option). This pin (/SS) may be required during a Slave
mode

RBF: Set by Buffer Full Detector

Buffer Full Detector: Set to “1” when an 8-bit shifting is completed.

SSE: Loads the data in the SPIS register, and begin to shift. The SSE bit is
kept at “1” while communication is continuing and to determine if the next write
attempt is available. This flag must be cleared when shifting is completed.

SPIS reg.: Shifting byte in and out. The MSB is shifted first. Both the SPIR and
the SPIW registers are shifted at the same time. Once data are written, SPIS
starts transmission / reception. The data received will be moved to the SPIR
register as the shifting of the 8-bit data is completed. The RBF (Read Buffer Full)
flag and the SPIIF (SPI Interrupt) flag are then set.

SPIR reg.: Read buffer. The buffer will be updated as the 8-bit shifting is
completed. The data must be read before the next reception is completed. The
RBF flag is cleared as the SPIR register is being read.

SPIW reg.: Write buffer. The buffer will ignore any attempts to write until the
8-bit shifting is completed.

SBRS2~SBRS0: Programms the clock frequency/rates and sources.

Clock Select: Selects either the internal or the external clock as the shifting
clock.

Edge Select: Selects the appropriate clock edges by programming the CES bit
6.7.3 SPI Signal and Pin Description
The detailed functions of the four pins, SI, SO, SCK, and /SS are as follows:

SI:
●
Serial Data In
●
Receive in sequential order. The Most Significant Bit (MSB) first, the Least
Significant Bit (LSB) last.
●
Defined as high-impedance, if not selected.
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104 •
●
Program the same clock rate and clock edge to latch on both the Master and
the Slave devices.
●
The received byte will update the transmitted byte.
●
The RBF will be set when the SPI operation is completed.
●
Timing is shown in Figures 6-17a and 6-17b (Section 6.7.4).
SO:
●
Serial Data Out
●
Transmit in sequential order. The Most Significant Bit (MSB) first, the Least
Significant Bit (LSB) last
●
Program the same clock rate and clock edge to latch on both the Master and
the Slave devices
●
The received byte will update the transmitted byte
●
The CES bit will reset as the SPI operation is completed
●
Timing is shown in Figures 6-17a and 6-17b (Section 6.7.4).
SCK:
●
Serial Clock
●
Generated by a Master device
●
Synchronize the data communication on both the SI and SO pins
●
The CES is used to select the edge to communicate.
●
The SBR0~SBR2 is used to determine the communication baud rate.
●
The CES, SBR0, SBR1, and SBR2 bits have no effect under Slave mode
●
Timing is shown in Figures 6-17a and 6-17b (Section 6.7.4).
/SS:
●
Slave Select; negative logic
●
Generated by a Master device to indicate the Slave(s) to receive data
●
Goes low before the first cycle of SCK appears, and remains low until the
last (eighth) cycle is completed.
●
Ignores the data on the SI and SO pins while /SS is high. This is because
the SO is no longer driven.
●
Timing is shown in Figures 6-17a and 6-17b (Section 6.7.4).
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.7.4 SPI Mode Timing
Figure 6-17a SPI Mode with /SS Disabled Timing Diagram
The SCK edge is selected by programming the CES bit. The waveform shown in the
above figure (Figure 17a) is applicable regardless of whether the EM78F648N/644N/
548N/544N is in Master or Slave mode with /SS disabled. However, the waveform in
the figure below (Figure 17b) can only be implemented in Slave mode with /SS
enabled.
Figure 6-17b SPI Mode with /SS Enabled Timing Diagram
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6.8 I2C Function
EM78F648N/F548N Registers for I2C Circuit
R_BANK Address Name
Bank 1
0X23
I2CCR1
Bank 1
0X24
I2CCR2
Bank 1
0X25
I2CSA
Bank 1
0X26
I2CDA
Bank 1
0X27
I2CDB
Bank 1
0X28
I2CA
Bank 0
0x0E
ISR3
Bank 0
0x1E
IMR3
Bit 7
Bit 6
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ISS
STOP
SAR_
EMPTY
ACK
FULL
EMPTY
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
I2CTS1
I2CTS0
I2CCS
I2CEN
R
R
R
R
R/W
R/W
R/W
R/W
SA6
SA5
SA4
SA3
SA2
SA1
SA0
IRW
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
DA9
DA8
R
R
R
R
R
R
R/W
R/W
Strobe/
Pend
IMS
R/W
Bit 5
0
0
0
0
I2CSTPIF
0
I2CRIF
I2CTIF
R
R
R
R
R/W
R
R/W
R/W
0
0
0
0
I2CSTPIE
0
I2CRIE
I2CTIE
R
R
R
R
R/W
R
R/W
R/W
Figure 6-18a EM78F648N/F548N I2C Block Diagram
106 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
The EM78F648N/F548N supports bidirectional, 2-wire bus, 7-bit and 10-bit
addressing as well as data transmission protocol. A device that sends data onto the
bus is defined as transmitter, while a device that receives data is defined as a
receiver. The bus has to be controlled by a Master device which generates the Serial
Clock (SCL), controls the bus access, and generates the Start and Stop conditions.
Both Master and Slave can operate as transmitter or receiver, but only the Master
device can determine which mode is activated.
Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via
a pull-up resistor. When the bus is free, both lines are HIGH. The output stages of
the devices that are connected to the bus must have an open-drain or open-collector
to perform the wired-AND function. Data on the I2C-bus can be transferred at the
rates of up to 100k bit/s in Standard-mode or up to 400k bit/s in the Fast-mode.
The data on the SDA line must be stable during the HIGH period of the clock. The
HIGH or LOW state of the data line can only change when the clock signal on the
SCL line is LOW.
Within the procedure of the I2C bus, unique situations could arise, which are defined
as START (S) and STOP (P) conditions.
A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique
case. This situation indicates a START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP
condition.
Figure 6-18b I2C Transfer Condition
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8-Bit Microcontroller
6.8.1 7-Bit Slave Address
Master-transmitter transmits to Slave-receiver. The transfer direction is not changed.
Master reads Slave immediately after the first byte. At the moment of the first
acknowledge, the Master-transmitter becomes a Master-receiver and the Slavereceiver becomes a Slave-transmitter. This first acknowledge is still generated by the
Slave. The STOP condition is generated by the Master, which has previously sent a
not-acknowledge (A). The difference between Master-transmitter and Masterreceiver is only with their in R//W bit. If the R//W bit is “0”, the Master device
becomes a transmitter. Otherwise, the Master device turns to be a receiver (R//W bit
is “1”). The Master-transmitter operation is illustrated in Figure 6-19a, and that of
Master-receiver is shown in “Figure 6-19b below.
Figure 6-19a Master-Transmitter Transmits to Slave-Receiver with 7-Bit Slave Address
Figure 6-19b Master-Receiver Reads from Slave-Transmitter with 7-Bit Slave Address
6.8.2 10-Bit Slave Address
In 10-bit Slave Address mode, using 10-bit for addressing exploits the reserved
combination 11110XX for the first 7 bits of the first byte following a START (S) or
repeated START (Sr) condition. The first 7 bits of the first byte are the combination
11110XX of which the last 2 bits (XX) are the two most-significant bits of the 10-bit
address. If the R//W bit were “0”, the second byte after acknowledge would be the 8
address bits of the10-bit Slave address. Otherwise, the second byte would just be
the next transmitted data from a Slave to Master device. The first bytes 11110XX are
transmitted using the Slave address register (I2CSA), and the second bytes
XXXXXXXX are transmitted using the data buffer (I2CDB).
108 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
The possible data transfer formats for 10-bit Slave Address Mode are explained in the
following paragraphs:
6.8.2.1 Master-Transmitter Transmits to Slave-Receiver with a 10-bit Slave
Address
When the Slave received the first byte after the START bit from the Master, each
Slave device will compare with the 7 bits of the first byte (11110XX) with their own
address and the 8th bit (R//W). If the R//W bit is “0”, the Slave will return an
Acknowledge A1. It is possible that more than one Slave devices will return the
Acknowledge A1. Then all Slave devices will continue to compare with the second
address (XXXXXXXX). If a Slave device has found a match, that particular Slave
device will be the only one to return an Acknowledge A2. The matched Slave device
will remain addressed by the Master until it receives a STOP condition or a repeated
START condition followed by a different Slave address.
Figure 6-20a Master-Transmitter Transmits to Slave-Receiver with a 10-Bit Slave Address
6.8.2.2 Master-Receiver Reads from Slave-Transmitter with a 10-bit Slave
Address
Up to, and including Acknowledge Bit A2, the procedure is the same as that described
above for Master-transmitter addressing a Slave receiver. After the Acknowledge A2,
a repeated START (Sr) condition takes place, followed by 7 bits Slave address
(11110XX) but the 8th bit R//W is “1”. The addressed Slave device will then return an
Acknowledge A3. If the repeated START (Sr) condition occurs and the 7 bits of the
first byte (11110XX) are received by the Slave device, all the Slave devices will
compare with their own address and test the 8th bit (R//W). However, none of the
Slave devices can return an Acknowledge because R//W=1.
Figure 6-20b Master-Receiver Read Slave-Transmitter with a 10-Bit Slave Address
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8-Bit Microcontroller
6.8.2.3 Master Transmits and Receives Data to and from the Same Slave Device
with 10-Bit Addresses
The Initial operation of this data transfer format is the same as explained in Section
6.8.2.1. Then the Master device starts to transmit the data to the Slave device.
When the Slave device receives an Acknowledge or Not Acknowledge that is
followed by repeat START (Sr), the operation “Master-Receiver Reads from SlaveTransmitter with 10-bit Slave Address” described in the preceding Section 6.8.2.2, is
then performed.
Figure 6-20c Master Addresses a Slave with 10-Bit addresses Transmits and Receives Data
in the Same Slave Device.
6.8.2.4 Master Device Transmits Data to Two or More Slave Devices with 10 and
7 Bits Slave Address
For 10-bit Slave address transmittal, the initial operation of this data transmit format is
the same as explained in the Section 6.8.2.1 which describes how to transmit the
data to Slave device. After the Master device completed the initial transmittal, and
user wants to continue transmitting data to another device, the Master needs to
address each of the new Slave devices by repeating the initial operation mentioned
above.
110 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
When the Master device wants to transmit data in 7-bit and 10-bit Slave address
modes successively, this could be done after the START or repeat START conditions
as illustrated in the following figures.
Figure 6-20d Master Transmitting to More than One Slave Devices with 10-Bit Slave Address
Figure 6-20e Master Successively Transmitting 7-Bit and 10-Bit Slave Addresses to Slave
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6.8.3 Master Mode I2C Transmit
In transmitting serial data, the I2C operates as follows:
1. Set I2CTS1~0, I2CCS, and ISS bits to select I2C transmit clock source.
2. Set I2CEN and IMS bits to enable I2C master function.
3. Write Slave address into the I2CSA register and IRW bit to select Read or Write.
4. Set strobe bit to start transmitting and then Check SAR_EMPTY bit.
5. Write 1st data into the I2CDB register, set Strobe bit and Check EMPTY bit.
6. Write 2nd data into the I2CDB register, set Strobe bit, STOP bit and Check
EMPTY bit.
6.8.2 Slave Mode I2C Transmit
In receiving, the I2C operates as follows:
1. Set I2CTS1~0, I2CCS, and ISS bits to select I2C transmit clock source.
2. Set I2CEN and IMS bits to enable I2C Slave function.
3. Write device address into the I2CDA register.
4. Check FULL bit, read I2CDB register (address), and then clear the Pend bit.
5. Check FULL bit, read I2CDB register (1st data), and then clear the Pend bit.
6. Check FULL bit, read I2CDB register (2nd data), and then clear the Pend bit.
6.9 Dual Set of PWM (Pulse Width Modulation)
6.9.1 Overview
In PWM mode, PWMA and PWMB pins produce up to a 10-bit resolution PWM output
(see Figure 6-21a below for the functional block diagram). A PWM output has a
period and a duty cycle, and it keeps the output in high. The baud rate of the PWM is
the inverse of the period. Figure 6-21b depicts the relationships between a period and
a duty cycle.
112 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
latch
DLAH +DLAL
Fosc
To
PWMAIF
DTAH
+
DTAL
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Duty Cycle
Match
Comparator
MUX
PWMA
R
TMRAH +TMRAL
reset
Q
S
Bank3,
R7<1>
Comparator
TAP2 TAP1 TAP0 TAEN
Period
Match
PRDA
Data Bus
Data Bus
DLBH + DLBL
DTBH
+
DTBL
TBP2 TBP1 TBP0 TBEN
latch
Comparator
To
PWMBIF
Duty Cycle
Match
PWMB
Fosc
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
TMRBH + TMRBL
R
Q
reset
S
MUX
Bank3,
R7<0>
Comparator
Period
Match
PRDB
Figure 6-21a Two PWMs Functional Block Diagram
Period
Duty
Cycle
PRDA = TMRA
DTA = TMRA
Figure 6-21b PWM Output Timing Diagram
6.9.2 Increment Timer Counter (TMRX: TMRAH/L or TMRBH/L)
TMRX are 10-bit clock counters with programmable prescalers. They are designed
as baud rate clock generators for the PWM module. TMRX is Read only. When in
use, they can be turned off for power saving by setting the TAEN or TBEN bits to “0”.
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6.9.3 PWM Period (PRDX: PRDA or PRDB)
The PWM period is defined by writing to the PRDX register. When TMRX is equal to
PRDX, the following events occur on the next increment cycle:
1) TMRX is cleared.
2) The PWMX pin is set to 1.
3) The PWM duty cycle is latched from DTA/DTB to DLA/DLB.
NOTE
The PWM output will not be set, if the duty cycle is “0”.
(4) The PWMXIF pin is set to “1”.
To calculate the PWM time period, use the following formula:
⎛ 1 ⎞
Period = (PRDX + 1) × ⎜
⎟ × (TMRX prescaler value )
⎝ Fosc ⎠
Example:
PRDX = 49; Fosc = 4 MHz, TMRX (0, 0, 0) = 1 : 2,
Then-
⎛ 1 ⎞
Period = (49 + 1) × ⎜
⎟ × 2 = 25μs
⎝ 4M ⎠
6.9.4 PWM Duty Cycle (DTX: DTA or DTB)
The PWM duty cycle is defined by writing to the DTX register, and is latched from
DTX to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is
cleared. DTX can be loaded at any time. However, it cannot be latched into DLX
until the current value of DLX is equal to TMRX.
The following formula describes how to calculate the PWM duty cycle:
Duty cycle =
⎛ 1
⎝ FOSC
(DTX ) × ⎜⎜
⎞
⎟⎟ × (TMRX prescale value )
⎠
Example:
DTX = 10; Fosc = 4 MHz;
TMRX (0, 0, 0) = 1 : 2,
Then-
⎛ 1 ⎞
Duty cycle = (10 ) × ⎜
⎟ × 2 = 5 μs
⎝ 4M ⎠
114 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.10 Comparator
EM78F664N/F662N/F661N/F564N/F562N/F561N has one comparator; while
F648N/F548N has two comparators. Each one has two analog inputs and one
output. The comparators can be utilized to Wake up the MCU from Sleep mode. The
following figure illustrates the comparator circuit and operation mode.
CIN-
CMP
CIN+
CO
+
10mV
CINCIN+
10mV
CO
Figure 6-22 Comparator Circuit and Operation Mode
6.10.1 External Reference Signal
The analog signal that is presented at CIN- compares to the signal at CIN+, and the
digital output (CO) of the comparator is adjusted accordingly.
The reference signal must be between VSS and VDD.
The reference voltage can be applied to either pin of the comparator.
Threshold detector applications may use the same reference.
The comparator can operate from the same or different reference source.
6.10.2 Internal Reference Signal
EM78F648N/F548N offers two internal voltage references which are applicable to
CIN1+/CIN2+. User can utilize the voltage references in setting C1RS of R39 Bank 0
/ C2RS of R3C Bank 0 and the corresponding voltage level in R43 Bank 0.
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6.10.3 Comparator Outputs
For EM78F664N/F662N/F661N/F564N/F562N/F561N:
The compared result is stored in the CPOUT2 of R7 Bit 4 of Bank 3.
The comparator is output to CO2 (P80) by programming Bit 3, Bit 2 <COS21,
COS20> of Register R7 Bank 3.
For EM78F648N/F548N:
The compared result is stored in CP1OUT of R39 Bit 6 of Bank 0 for Comparator
1; in CP2OUT of R3C Bit 6 of Bank 0 for Comparator 2.
By programming Bit 5, Bit 4 <CMP1COS1, CMP1COS0> of Register R39 Bank 0
and Bit 5, Bit 4 <CMP2COS1, CMP2COS0> of Register R3C Bank 0, the
compared results can be output to CO1 and CO2 pins.
The following figure depicts the comparator output block diagram.
Figure 6-23 Comparator Output Block Diagram
6.10.4 Interrupt
For EM78F664N/F662N/F661N/F564N/F562N/F561N:
CMP2IE (IOCE.7) and the “ENI” instruction execution must be enabled.
Interrupt is executed whenever a change occurs on the output pin of the
comparator.
The actual change on the pin can be determined by reading the Bit CPOUT2, R7
Bit 4 of Bank 3.
CMP2IF (RF.7 Bank 1) and the comparator interrupt flag, can only be cleared by
software.
116 •
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EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
For EM78F648N/F548N:
CMP1IE, CMP2IE, and the “ENI” instruction execution must be enabled.
Interrupt occurs whenever a change occurs on the comparators output pins.
The actual change on the pins can be determined by reading the bit CP1OUT of
R39 Bit 6 of Bank 0 for Comparator 1 and the bit CP2OUT of R3C Bit 6 of Bank 0
for Comparator 2.
CMP1IF, CMP2IF, and the comparator interrupt flags, can only be cleared by
software.
6.10.5 Wake-up from Sleep Mode
When enabled, the comparator remains active and the interrupt remains
functional, even under Sleep mode.
If a mismatch occurs, the interrupt will wake up the device from Sleep mode.
The power consumption should be taken into consideration for the benefit of
energy conservation.
If the function is not utilized during Sleep mode, turn off the comparator before
going into Sleep mode.
6.11 Reset and Wake-up
6.11.1 Reset and Wake-up for EM78F644/642/641/544/542/541N
A Reset is initiated by one of the following events:
1) Power-on reset
2) /RESET pin input "low"
3) WDT time-out (if enabled)
The device is kept in a Reset condition for a period of approximately 18 ms (one
oscillator start-up timer period) after a Reset is detected. Once a Reset occurs, the
following functions are performed.
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0".
All I/O port pins are configured as input mode (high-impedance state).
The Watchdog timer and prescaler are cleared.
When power is switched on, the upper three bits of R3 are cleared.
The bits of RB, RC, RD registers are set to their previous status.
The bits of CONT register are set to all "0".
The bits of IOCA register are set to all "0".
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8-Bit Microcontroller
The bits of IOCB register are set to all "1".
The bits of IOCC register are set to all "0".
The bits of IOCD register are set to all "1".
The bits of IOCE register are set to all "0".
The bits of IOCF register are set to all "0".
The Sleep (power down) mode is asserted by executing the “SLEP” instruction.
While entering Sleep mode, the WDT (if enabled) is cleared but keeps on running
until wake-up is triggered by one of the following events (wake-up time in RC mode,
the wake-up time is 10µs and in High Crystal (XTAL) mode is 800 µs):
Event 1) External reset input on /RESET pin
Event 2) WDT time-out (if enabled)
Event 3) Port 6 input status changes (if enabled)
Event 4) Comparator output status changes (if CMPWE is enabled)
Event 5) External (P60, /INT) pin changes (if EXWE is enabled)
Event 6) SPI receives data while SPI is acting as Slave device (if SPIWE is enabled)
The first two events will cause the IC to reset. The T and P flags of R3 can be used
to determine the source of the reset (wake-up). Events 3, 4, 5, and 6 are considered
as continuation of program execution and the global interrupt ("ENI" or "DISI" being
executed) determines whether or not the controller branches to the interrupt vector
following a wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from the Address 0×6, 0×15, 0×3, 0×12 after wake-up. If DISI is executed
before SLEP, the execution will restart from the instruction right next to SLEP after
wake-up. In RC mode, the wake-up time is 10 µs and that of High Crystal (XTAL)
mode, is 800 µs.
Only one event of Events 2 to 6 can be enabled before entering into Sleep mode.
That is a) If WDT is enabled before SLEP, all the RA register bits are disabled. Hence, the
IC can wake-up only under Events 1 or 2 conditions. Refer to the Interrupt
section (Section 6.12) for further details.
b) If Port 6 Input Status Change is used to wake-up the IC and the ICWE bit of RA
register is enabled before SLEP, WDT must be disabled. Hence, the IC can
wake-up only under Event 3 conditon.
118 •
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EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Under this situation, the following instructions must be executed before SLEP:
MOV
A, @0xxx1000b ;
;
IOW
IOCA
WDTC
;
MOV
R6, R6
;
ENI (or DISI)
;
;
BC
R4, 7
;
BC
R4, 6
MOV
A, @0100xxxxb ;
;
MOV
RA,A
MOV
A, @xxxxxx1xb ;
;
IOW
IOCF
SLEP
;
Select WDT prescaler and
Disable the WDT
Clear WDT and prescaler
Read Port 6
Enable (or disable) global
interrupt
Select Bank 0
Enable Port 6 input change
wake-up bit
Enable Port 6 input change
interrupt
Sleep
c) If Comparator 2 Output Status Change is used to wake-up the IC and the CMPWE
bit of RA register is enabled before SLEP, WDT must be disabled by software.
Hence, the IC can wake-up only under Event 4 condition.
Under this situation, the following instructions must be executed before SLEP:
BS
BS
MOV
MOV
MOV
IOW
WDTC
ENI (or DISI)
BC
BC
MOV
MOV
MOV
IOW
SLEP
R4, 7
; Select Bank 3
R4, 6
A, @xxxx10xxb ; Select a comparator and P80 act
; as CO pin
R7,A
A, @0xxx1000b ; Select WDT prescaler and
; Disable the WDT
IOCA
; Clear WDT and prescaler
; Enable (or disable) global
; interrupt
R4, 7
; Select Bank 0
R4, 6
A, @1000xxxxb ; Enable comparator output status
; change wake-up bit
RA,A
A, @10000000b ; Enable comparator output status
; change interrupt
IOCE
; Sleep
d) If External (P60, /INT) pin change is used to wake-up IC and the EXWE bit of RA
register is enabled before SLEP, WDT must be disabled. Hence, the IC can wake
up only under Event 5 condition.
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e) When SPI is used as Slave device, IC will wake-up after receiving data, and the
SPIWE bit of the RA register is enabled before SLEP. The WDT must be
disabled by software. Hence, the IC can wake up only under Event 6 condition.
Summary of all types of Wake-up and Interrupt modes:
Wake-up Condition
Signal
Signal
EXWE = 0,
EXIE = 0
EXWE = 0,
EXIE = 1
Sleep Mode
DISI
Idle Mode
ENI
DISI
Wake-up is invalid
ENI
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
External
INT
EXWE = 1,
EXIE = 0
Port 6
Pin
Change
DISI
ENI
Interrupt is invalid
Normal Mode
DISI
ENI
Interrupt is invalid
Interrupt
Interrupt
Next
Next
+
+
Instruction Interrupt Instruction Interrupt
Vector
Vector
Wake-up
Wake-up
Interrupt is invalid
Interrupt is invalid
+
+
Next Instruction
Next Instruction
Wake-up Wake-up Wake-up Wake-up
Interrupt
Interrupt
EXWE = 1,
Next
Next
+
+
+
+
+
+
Next
Interrupt
Next
Interrupt Instruction Interrupt Instruction Interrupt
EXIE = 1
Instruction Vector Instruction Vector
Vector
Vector
ICWE = 0,
Wake-up is invalid
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid
ICIE = 0
Interrupt
Interrupt
ICWE = 0,
Next
Next
+
+
Wake-up is invalid
Wake-up is invalid.
Instruction Interrupt Instruction Interrupt
ICIE = 1
Vector
Vector
Wake-up
Wake-up
ICWE = 1,
Interrupt is invalid
Interrupt is invalid
+
+
ICIE = 0
Next Instruction
Next Instruction
Wake-up Wake-up Wake-up Wake-up
Interrupt
Interrupt
ICWE = 1,
Next
Next
+
+
+
+
+
+
Next
Interrupt
Next
Interrupt Instruction Interrupt Instruction Interrupt
ICIE = 1
Instruction Vector Instruction Vector
Vector
Vector
TCIE = 0
TCC
Overflow
Green Mode
TCIE = 1
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid
Wake-up Wake-up
Interrupt
Interrupt
Next
Next
+
+
+
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector
Vector
Vector
SPIWE = 0,
Wake-up is invalid
SPIIE = 0
Wake-up is invalid.
SPIWE = 0,
Wake-up is invalid
SPIIE = 1
Wake-up is invalid
SPI
Interrupt SPIWE = 1,
SPIIE = 0
Interrupt is invalid.
Interrupt is invalid.
Interrupt
Interrupt
Next
Next
+
+
Instruction Interrupt Instruction Interrupt
Vector
Vector
Wake-up
Wake-up
+
+
Interrupt is invalid
Interrupt is invalid
Next Instruction*
Next Instruction*
Interrupt
Interrupt
Wake-up Wake-up Wake-up Wake-up
SPIWE = 1,
Next
Next
+
+
+
+
+
+
Interrupt Instruction Interrupt Instruction Interrupt
Next
Interrupt
Next
SPIIE = 1
Vector
Vector
Instruction* Vector* Instruction* Vector*
* SPI must be in Slave mode
120 •
Product Specification (V1.2) 03.15.2013
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EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Wake-up
Signal
Condition
Signal
Sleep Mode
DISI
ENI
Idle Mode
DISI
ENI
CMP2WE=0,
Wake-up is invalid
CMP2IE = 0
Wake-up is invalid
CMP2WE=0,
Wake-up is invalid
Comparator 2 CMP2IE = 1
Wake-up is invalid
(Comparator
Output Status CMP2WE=1,
CMP2IE = 0
Change)
Wake-up +
Next Instruction
Wake-up +
Next Instruction
Green Mode
DISI
ENI
Interrupt is invalid
Normal Mode
DISI
ENI
Interrupt is invalid
Interrupt +
Interrupt +
Next
Next
Interrupt
Interrupt
Instruction
Instruction
Vector
Vector
Interrupt is invalid
Interrupt is invalid
Wake-up +
Wake-up + Wake-up + Wake-up +
Interrupt +
Interrupt +
CMP2WE=1, Next
Next
Next
Interrupt
Next
Interrupt
Interrupt
Interrupt
Instruction
Instruction
CMP2IE = 1 Instructio
Vector Instruction Vector
Vector
Vector
n
TC1
interrupt
TC1IE = 0
Wake-up is invalid
TC1IE = 1
Wake-up is invalid
UTIE = 0
UART
Transmit
Complete
Interrupt UTIE = 1
TC2
Interrupt
TC3
Interrupt
PWM A/B
(When
TimerA/B
Match
PRDA/B)
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
UERRIE = 0
wake-up is invalid
Wake-up is invalid
UERRIE = 1
Wake-up is invalid
Wake-up is invalid
TC2IE = 0
Wake-up is invalid
Wake-up is invalid
TC2IE = 1
Wake-up is invalid
TC3IE = 0
Wake-up is invalid
TC3IE = 1
Wake-up is invalid
PWMxIE = 0
Wake-up is invalid
( x = A or B )
PWMxIE = 1
Wake-up is invalid
( x = A or B )
Interrupt is invalid
Interrupt is invalid
Wake-up + Wake-up +
Interrupt +
Interrupt +
Next
Next
Next
Interrupt
Interrupt
Interrupt
Instruction
Instruction
Instruction Vector
Vector
Vector
Wake-up is invalid
UART
URIE = 0
Receive
Data
Buffer Full URIE = 1
Interrupt
UART
Receive
Error
Interrupt
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid
Interrupt +
Interrupt +
Next
Next
Interrupt
Interrupt
Instruction
Instruction
Vector
Vector
Interrupt is invalid
Interrupt is invalid
Interrupt +
Interrupt +
Next
Next
Interrupt
Interrupt
Instruction
Instruction
Vector
Vector
Interrupt is invalid
Interrupt is invalid
Interrupt +
Interrupt +
Next
Next
Interrupt
Interrupt
Instruction
Instruction
Vector
Vector
Interrupt is invalid
Interrupt is invalid
Wake-up + Wake-up +
Interrupt +
Interrupt +
Next
Next
Next
Interrupt
Interrupt
Interrupt
Instruction
Instruction
Instruction Vector
Vector
Vector
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid
Wake-up + Wake-up +
Interrupt +
Interrupt +
Next
Next
Next
Interrupt
Interrupt
Interrupt
Instruction
Instruction
Instruction Vector
Vector
Vector
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid
Wake-up + Wake-up +
Interrupt +
Interrupt +
Next
Next
Next
Interrupt
Interrupt
Interrupt
Instruction
Instruction
Instruction Vector
Vector
Vector
NOTE
After wake up:
1. If interrupt enabled Æ interrupt + next instruction
2. If interrupt disabled Æ next instruction
Product Specification (V1.2) 03.15.2013
• 121
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Summary of the Initialized Values for Registers:
Legend: U: Unknown or don’t care, P: Previous value before reset, T: Check table in (next) Section 6.11.3.
Address
N/A
N/A
N/A
N/A
N/A
0×00
0×01
0×02
Name
IOC5
IOC6
IOC7
IOC8
CONT
R0 (IAR)
R1 (TCC)
R2 (PC)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Reset Type
C57
C56
C55
C54
C53
C52
C51
C50
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
C67
C66
C65
C64
C63
C62
C61
C60
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
C77
C76
C75
C74
C73
C72
-
-
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
*C83
C82
C81
C80
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
INTE
INT
TS
TE
PSTE
PST2
PST1
PST0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
SBS0
-
-
-
-
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
Jump to interrupt vector address or continue to execute next instruction.
* For F644N/544N, Bit 3 is unused. Set to “0” all the time
122 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address
0×03
0×04
0×05
0×06
0×07
0×08
0×09
0×0A
0×0B
Name
R3 (SR)
R4 (RSR)
P5
(Bank 0)
P6
(Bank 0)
P7
(Bank 0)
P8
(Bank 0)
R9
(Bank 0)
RA
(Bank 0)
RB (ECR)
(Bank 0)
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
-
-
-
T
P
Z
DC
C
Power-on
0
0
0
1
1
U
U
U
/RESET and WDT
0
0
0
t
t
P
P
P
Wake-up from Pin
Change
P
P
P
t
t
P
P
P
Bit Name
Bank 1
Bank 0
-
-
-
-
-
-
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
P57
P56
P55
P54
P53
P52
P51
P50
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
P67
P66
P65
P64
P63
P62
P61
P60
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
P77
P76
P75
P74
P73
P72
-
-
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
P83
P82
P81
P80
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
RBit7
RBit6
RBit5
RBit4
RBit3
RBit2
RBit1
RBit0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
CMP2WE
ICWE
-
EXWE
SPIWE
-
-
-
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
RD
WR
EEWE
EEDF
EEPC
-
-
-
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.2) 03.15.2013
• 123
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address
Name
Reset Type
Bit Name
0×0C
0×0D
0×0E
0×0F
RC
(Bank 0)
RD
(Bank 0)
RE
(Bank 0)
RF (ISR)
(Bank 0)
R5
(Bank 1)
0×06
R7
(Bank 1)
TCR1DB
R8
(Bank 1)
TC2CR
124 •
R9
(Bank 1)
Bit 2
Bit 1
Bit 0
EE_A7
EE_A6
EE_A5
EE_A4
EE_A3
EE_A2
EE_A1
EE_A0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
EE_D7
EE_D6
EE_D5
EE_D4
EE_D3
EE_D2
EE_D1
EE_D0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
IDLE
-
-
-
-
Power-on
0
1
1
1
0
0
0
0
/RESET and WDT
0
1
1
1
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
TIMERSC CPUS
Bit Name
-
-
SPIIF
EXIF
ICIF
TCIF
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
PWMBIF PWMAIF
TC1CAP
TC1S
TC1M
TC1ES
-
-
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
TC1CK1 TC1CK0
TCR1DA7 TCR1DA6 TCR1DA5 TCR1DA4 TCR1DA3 TCR1DA2 TCR1DA1 TCR1DA0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
TCR1DB7 TCR1DB6 TCR1DB5 TCR1DB4 TCR1DB3 TCR1DB2 TCR1DB1 TCR1DB0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
RCM1
RCM0
TC2ES
TC2M
TC2S
TC2CK2 TC2CK1 TC2CK0
Power-on
Word1<3,2>
0
0
0
0
0
0
/RESET and WDT
Word1<3,2>
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
Bit Name
0×09
Bit 3
0
Bit Name
0×08
Bit 4
P
Bit Name
0×07
Bit 5
/RESET and WDT
Bit Name
R6
(Bank 1)
TCR1DA
Bit 6
Power-on
Bit Name
0×05
Bit 7
P
TC2D15 TC2D14 TC2D13 TC2D12 TC2D11 TC2D10 TC2D9
TC2D8
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address
0×0A
0×0B
0×0C
0×0D
0×0E
0×0F
Name
RA
(Bank 1)
RB
(Bank 1)
SPIS
RC
(Bank 1)
SPIC
RD
(Bank 1)
SPIRB
RE
(Bank 1)
SPIWB
RF
(Bank 1)
ISR2
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
TC2D7
TC2D6
TC2D5
TC2D4
TC2D3
TC2D2
TC2D1
TC2D0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
DORD
TD1
TD0
-
OD3
OD4
-
RBF
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
CES
SPIE
SRO
SSE
SDOC
SBRS2
SBRS1
SBRS0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
SRB7
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB0
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
SWB7
SWB6
SWB5
SWB4
SWB3
SWB2
SWB1
SWB0
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
CMP2IF
-
TC3IF
TC2IF
TC1IF
UERRIF
RBFF
TBEF
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
UTBE
TXE
Bit Name
0×0A
0×0B
RA
(Bank 2)
URC1
RB
(Bank 2)
URC2
Power-on
U
0
0
0
0
0
0
0
/RESET and WDT
P
P
P
P
P
P
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
-
SBIM1
SBIM0
UINVEN
-
-
-
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
P
P
P
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
URRD8
EVEN
PRE
URBF
RXE
Bit Name
0×0C
RC
(Bank 2)
URS
URTD8 UMODE1 UMODE0 BRATE2 BRATE1 BRATE0
PRERR OVERR FMERR
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
P
P
P
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.2) 03.15.2013
• 125
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address
Name
Reset Type
Bit Name
0×0D
0×0E
0×0F
0×05
0×06
0×07
RD
(Bank 2)
URRD
RE
(Bank 2)
URTD
RF
(Bank 2)
PHCR1
R5
(Bank 3)
TMRCON
R6
(Bank 3)
TBHP
R7
(Bank 3)
CMPCON
0×08
0×09
0×0A
126 •
RA
(Bank 3)
DTAH
Bit 5
Bit 4
Bit 3
Bit 2
URRD7 URRD6 URRD5 URRD4 URRD3 URRD2
Bit 1
Bit 0
URRD1
URRD0
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
URTD7
URTD6
URTD5
URTD4
URTD3
URTD2
URTD1
URTD0
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
/PH77
/PH76
/PH75
/PH74
/PH73
/PH72
-
-
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
TAEN
TAP2
TAP1
TAP0
TBEN
TBP2
TBP1
TBP0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
MLB
-
-
-
RBit11
RBit10
RBit9
RBit8
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
PRDA[1] PRDA[0] DTA[1]
CPOUT2 COS21
COS20 PWMAE PWMBE
DTA[0] PRDB[1] PRDB[0] DTB[1]
DTB[0]
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
R9
(Bank 3)
PRDAH
Bit 6
Power-on
Bit Name
R8
(Bank 3)
PWMCON
Bit 7
PRDA[9] PRDA[8] PRDA[7] PRDA[6] PRDA[5] PRDA[4] PRDA[3] PRDA[2]
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
DTA[9]
DTA[8]
DTA[7]
DTA[6]
DTA[5]
DTA[4]
DTA[3]
DTA[2]
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address
Name
Reset Type
Bit Name
0×0B
0×0C
RB
(Bank 3)
PRDBH
RC
(Bank 3)
DTBH
0×0D
0×0F
0×0A
0×0B
0×0C
0×0D
RE
(Bank 3)
TC3D
RF
(Bank 3)
PDCR1
IOCA
WDTCR
IOCB
PDCR2
IOCC
ODCR
IOCD
PHCR2
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRDB[9] PRDB[8] PRDB[7] PRDB[6] PRDB[5] PRDB[4] PRDB[3] PRDB[2]
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
DTB[9]
DTB[8]
DTB[7]
DTB[6]
DTB[5]
DTB[4]
DTB[3]
DTB[2]
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
TC3FF1 TC3FF0
TC3S
TC3CK2 TC3CK1 TC3CK0 TC3M1
TC3M0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
0×0E
Bit 6
Power-on
Bit Name
RD
(Bank 3)
TC3CR
Bit 7
TCR3D7 TCR3D6 TCR3D5 TCR3D4 TCR3D3 TCR3D2 TCR3D1 TCR3D0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
/PD77
/PD76
/PD75
/PD74
/PD73
/PD72
-
-
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
WDTE
EIS
-
-
PSWE
PSW2
PSW1
PSW0
Power-un
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
/PD63
/PD62
/PD61
/PD60
/PD53
/PD52
/PD51
/PD50
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
OD67
OD66
OD65
OD64
OD63
OD62
OD61
OD60
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
/PH67
/PH66
/PH65
/PH64
/PH63
/PH62
/PH61
/PH60
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.2) 03.15.2013
• 127
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address
0×0E
0×0F
0×10 ~
0×3F
Name
IOCE
IMR2
IOCF
IMR1
R10~R3F
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
CMP2IE
-
TC3IE
TC2IE
TC1IE
UERRIE
URIE
UTIE
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
-
SPIIE
EXIE
ICIE
TCIE
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
PWMBIE PWMAIE
6.11.2 Reset and Wake-up for EM78F648/548N
A Reset is initiated by one of the following events:
1) Power on reset
2) /RESET pin input "low"
3) WDT time-out (if enabled)
The device is kept in a Reset condition for a period of approximately 18 ms 3 (one
oscillator start-up timer period) after a reset is detected. If the /Reset pin goes “low”
or WDT time-out is active, a Reset is generated. In RC mode the reset time is
34 clocks, while in High XTAL mode, reset time is 2 ms + 32 clocks. In Low XTAL
mode, the reset time is 500 ms. Once a Reset occurs, the following functions are
performed.
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0".
All I/O port pins are configured as input mode (high-impedance state).
The Watchdog timer and prescaler are cleared.
The bits of the control register are set as indicated in the table on “Summary of the
Initialized Values for Registers” as shown below.
3
Vdd = 5V, set up time period = 16.8ms ± 8%
Vdd = 3V, set up time period = 18ms ± 8%
128 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
The Sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering Sleep mode, the WDT (if enabled) is cleared but keeps on running until wakeup is triggered by one of the following events (wake-up time in RC mode is 34 clocks, in
High XTAL mode is 2 ms + 32 clocks, and in Low XTAL mode, is 500 ms):
Event 1) External reset input on /RESET pin
Event 2) WDT time-out (if enabled)
Event 3) External (P60, /INT) pin changes (if EXWE is enabled)
Event 4) Port 6 input status changes (if ICWE is enabled)
Event 5) Comparator 1 or 2 output status changes (if CMP1WE/CMP2WE is enabled)
Event 6) SPI receives data while SPI is acting as Slave device (if SPIWE is enabled)
Event 7) Port 5/Port 7 input status changes (if corresponding control bits are enabled)
The first two cases will cause the EM78F648N/F548N to reset. The T and P flags of
R3 can be used to determine the source of the reset (wake-up). Events 3, 4, 5, 6,
and 7 are considered as the continuation of program execution and the global
interrupt ("ENI" or "DISI" being executed) decides whether or not the controller
branches to the interrupt vector following a wake-up. If ENI is executed before SLEP,
the instruction will begin to execute from Address 0x3, 0x6, 0X15, 0X30 after wake-up.
If DISI is executed before SLEP, the execution will restart from the instruction right
next to SLEP after wake-up. All of the Sleep mode wake-up time is 150 µs,
regardless of what the status is of the oscillation mode (except for Low XTAL mode
which has a wake-up time of 500 ms).
Only one of Events 2 to 7 can be enabled before entering into Sleep mode. That is a) If WDT is enabled before SLEP, the EM78F648N/F548N can wake-up only by
Events 1 or 2. Refer to the Interrupt section (Section 12) for further details.
b) If External (P60, /INT) pin change is used to wake-up EM78F648N/F548N and the
EXWE bit is enabled before SLEP, the WDT must be disabled. Hence, the
controller can wake-up only under Event 3 condition.
c) If Port 6 Input Status Change is used to wake-up EM78F648N/F548N and the
corresponding wake-up setting is enabled before SLEP, the WDT must be
disabled. Hence, the controller can wake-up only under Event 4 condition.
d) If Comparator 1 or 2 Output Status Change is used to wake-up EM78F648N /
F548N and the CMP1WE/CMP2WE bit of Bank 0 R2F register is enabled before
SLEP, the WDT must be disabled by software. Hence, the controller can wake-up
only under Event 5 condition.
e) When SPI is acting as Slave device, EM78F648N/F548N will wake-up after
receiving data, and the SPIWE bit of Bank 0 R2F register is enabled before SLEP,
the WDT must be disabled by software. Hence, the controller can wake-up only
under Event 6 condition.
f) If Ports 6 and 7 Input Status Change is used to wake-up EM78F648N/F548N and
the corresponding wake-up setting is enabled before SLEP, the WDT must be
disabled. Hence, the controller can wake-up only under Event 7 condition.
Product Specification (V1.2) 03.15.2013
• 129
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Summary of all types of Wake-up and Interrupt modes (for EM78F648/548N only):
Wake-up Condition
Signal
Signal
EXWE = 0,
EXIE = 0
EXWE = 0,
EXIE = 1
Sleep Mode
DISI
Idle Mode
ENI
DISI
Wake-up is invalid
ENI
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
External
INT
EXWE = 1,
EXIE = 0
Port 6
Pin
Change
DISI
ENI
Interrupt is invalid
Normal Mode
DISI
ENI
Interrupt is invalid
Interrupt
Interrupt
Next
Next
+
+
Instruction Interrupt Instruction Interrupt
Vector
Vector
Wake-up
Wake-up
Interrupt is invalid
Interrupt is invalid
+
+
Next Instruction
Next Instruction
Interrupt
Interrupt
Wake-up Wake-up Wake-up Wake-up
EXWE = 1,
Next
Next
+
+
+
+
+
+
Next
Interrupt
Next
Interrupt Instruction Interrupt Instruction Interrupt
EXIE = 1
Vector
Vector
Instruction Vector Instruction Vector
ICWE = 0,
Wake-up is invalid
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid
ICIE = 0
Interrupt
Interrupt
ICWE = 0,
Next
Next
+
+
Wake-up is invalid
Wake-up is invalid
Instruction Interrupt Instruction Interrupt
ICIE = 1
Vector
Vector
Wake-up
Wake-up
ICWE = 1,
Interrupt is invalid
Interrupt is invalid
+
+
ICIE = 0
Next Instruction
Next Instruction
Wake-up Wake-up Wake-up Wake-up
Interrupt
Interrupt
ICWE = 1,
Next
Next
+
+
+
+
+
+
Next
Interrupt
Next
Interrupt Instruction Interrupt Instruction Interrupt
ICIE = 1
Instruction Vector Instruction Vector
Vector
Vector
TCIE = 0
TCC
Overflow
Green Mode
TCIE = 1
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid
Interrupt
Interrupt
Wake-up Wake-up
Next
Next
+
+
+
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Vector
Vector
Instruction Vector
SPIWE = 0,
Wake-up is invalid
SPIIE = 0
Wake-up is invalid
SPIWE = 0,
Wake-up is invalid
SPIIE = 1
Wake-up is invalid
SPI
Interrupt SPIWE = 1,
SPIIE = 0
Interrupt is invalid
Interrupt is invalid.
Interrupt
Interrupt
Next
Next
+
+
Instruction Interrupt Instruction Interrupt
Vector
Vector
Wake-up
Wake-up
+
+
Interrupt is invalid
Interrupt is invalid
Next Instruction*
Next Instruction*
Interrupt
Interrupt
Wake-up Wake-up Wake-up Wake-up
SPIWE = 1,
Next
Next
+
+
+
+
+
+
Interrupt Instruction Interrupt Instruction Interrupt
Next
Interrupt
Next
SPIIE = 1
Vector
Vector
Instruction* Vector* Instruction* Vector*
* SPI must be in Slave mode
130 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Wake-up Condition
Signal
Signal
Sleep Mode
DISI
ENI
CMPxWE=0
Wake-up is invalid
CMPxIE = 0
Comparator CMPxWE=0
x
CMPxIE = 1
(Comparator
Output Status
CMPxWE=1
Change)
x = 1, 2
DISI
ENI
Wake-up is invalid
Wake-up is invalid
TC1IE = 1
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
UART
Receive
Data
Buffer
Full
Interrupt
Wake-up is invalid
Wake-up is invalid
TC2
Interrupt
DISI
ENI
Interrupt is invalid
Normal Mode
DISI
ENI
Interrupt is invalid
Interrupt
Interrupt
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Vector
URIE = 0
Wake-up is invalid
URIE = 1
Wake-up is invalid
Wake-up is invalid
UERRIE = 0
Wake-up is invalid
Wake-up is invalid
UERRIE = 1
Wake-up is invalid
Wake-up is invalid
TC2IE = 0
Wake-up is invalid
Wake-up is invalid
TC2IE = 1
Wake-up is invalid
Product Specification (V1.2) 03.15.2013
Interrupt is invalid
Interrupt is invalid
Wake-up Wake-up
Interrupt
Interrupt
+
+
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector
Vector
Vector
UTIE = 0
UART
Transmit
Complete
Interrupt UTIE = 1
UART
Receive
Error
Interrupt
Green Mode
Wake-up
Wake-up
+
+
Interrupt is invalid
Interrupt is invalid
CMPxIE = 0
Next Instruction
Next Instruction
Wake-up Wake-up Wake-up Wake-up
Interrupt
Interrupt
CMPxWE=1
+
+
Next
+
Next
+
+
+
Next
Interrupt
CMPxIE = 1
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector Instruction Vector
Vector
Vector
TC1IE = 0
TC1
interrupt
Wake-up is invalid
Idle Mode
Interrupt is invalid
Interrupt is invalid
Interrupt
Interrupt
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Vector
Interrupt is invalid
Interrupt is invalid
Interrupt
Interrupt
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Vector
Interrupt is invalid
Interrupt is invalid
Interrupt
Interrupt
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Vector
Interrupt is invalid
Interrupt is invalid
Wake-up Wake-up
Interrupt
Interrupt
+
+
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector
Vector
Vector
• 131
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Wake-up Condition
Signal
Signal
LVDWE = 0,
CMPxIE = 0
LVDWE = 0,
LVDIE = 1
LVD
DISI
ENI
Wake-up is invalid
Wake-up is invalid
TC3IE = 1
I2CTIE = 0
I2C RX
Interrupt
I2C
STOP
Interrupt
DISI
ENI
Wake-up is invalid
Wake-up is invalid
Green Mode
DISI
ENI
Interrupt is invalid
Normal Mode
DISI
ENI
Interrupt is invalid
Interrupt
Interrupt
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Vector
Wake-up
Wake-up
+
+
Interrupt is invalid
Interrupt is invalid
Next Instruction
Next Instruction
Wake-up Wake-up Wake-up Wake-up
Interrupt
Interrupt
LVDWE = 1,
+
+
Next
+
Next
+
+
+
Next
Interrupt
LVDIE = 1
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector Instruction Vector
Vector
Vector
Wake-up is invalid
Wake-up is invalid
PWMxIE = 0
Wake-up is invalid
PWM A/B
( x = A or B )
(When
TimerA/B
PWMxIE = 1
Match
Wake-up is invalid
PRDA/B) ( x = A or B )
I2C TX
Interrupt
Idle Mode
LVDWE = 1,
LVDIE = 0
TC3IE = 0
TC3
Interrupt
Sleep Mode
Wake-up is invalid
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid
Wake-up Wake-up
Interrupt
Interrupt
+
+
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector
Vector
Vector
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid
Wake-up Wake-up
Interrupt
Interrupt
+
+
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector
Vector
Vector
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid
Interrupt
Interrupt
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Vector
I2CTIE = 1
Wake-up is invalid
Wake-up is invalid
I2CRIE = 0
Wake-up if received
correct address
Wake-up if received
correct address
I2CRIE = 1
Wake-up if received
correct address
Interrupt
Interrupt
Wake-up if received
Next
+
Next
+
correct address
Instruction Interrupt Instruction Interrupt
Vector
Vector
I2CSTPIE=0 Wake-up is invalid
Wake-up is invalid
I2CSTPIE=1 Wake-up is invalid
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid
Interrupt is invalid
Interrupt is invalid
Interrupt
Interrupt
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Vector
NOTE
After wake up:
1. If interrupt is enabled Æ interrupt + next instruction
2. If interrupt is disabled Æ next instruction
132 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Summary of the Initialized Values for Registers (for EM78F648/548N only):
Legend: U: Unknown or don’t care, P: Previous value before reset, T: Check table in (next) Section 6.11.3.
Address Bank, Name
0x00
0x01
0x02
0x03
0x04
0X05
0x06
0x07
0x08
R0
(IAR)
R1
(BSR)
R2
(PC)
R3
(SR)
R4
(RSR)
Bank 0, R5
(Port 5)
Bank 0, R6
(Port 6)
Bank 0, R7
(Port 7)
Bank 0, R8
(Port 8)
Reset Type
Bit 7
Bit Name
Power-on
U
/RESET and WDT
P
Wake-up from Pin
P
Change
Bit Name
0
Power-on
0
/RESET and WDT
0
Wake-up from Pin
0
Change
Bit Name
Power-on
0
/RESET and WDT
0
Wake-up from Pin
P
Change
Bit Name
0
Power-on
0
/RESET and WDT
0
Wake-up from Pin
0
Change
Bit Name
RSR7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
U
P
U
P
U
P
U
P
U
P
U
P
U
P
P
P
P
P
P
P
P
0
0
0
0
0
0
SBS0
U
0
0
0
0
0
0
0
0
0
0
GBS0
U
0
0
0
P
0
0
0
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
0
0
0
0
0
0
T
1
t
P
1
t
Z
U
P
DC
U
P
C
U
P
0
0
t
t
P
P
P
RSR6
RSR5
RSR4
RSR3
RSR2
RSR1
RSR0
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P57
0
0
P56
0
0
P55
0
0
P54
0
0
P53
0
0
P52
0
0
P51
0
0
P50
0
0
P
P
P
P
P
P
P
P
P67
0
0
P66
0
0
P65
0
0
P64
0
0
P63
0
0
P62
0
0
P61
0
0
P60
0
0
P
P
P
P
P
P
P
P
P77
0
0
P76
0
0
P75
0
0
P74
0
0
P73
0
0
P72
0
0
P71
0
0
P70
0
0
P
P
P
P
P
P
P
P
P87
0
0
P86
0
0
P85
0
0
P84
0
0
P83
0
0
P82
0
0
P81
0
0
P80
0
0
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Product Specification (V1.2) 03.15.2013
• 133
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address Bank Name
0x09
0X0B
0x0C
0X0D
0x0E
0x10
0x11
0x12
0X13
134 •
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
P97
Power-on
0
Bank 0, R9
/RESET
and
WDT
0
(Port 9)
Wake-up from Pin
P
Change
Bit Name
CPUS
Reset Type
P96
0
0
P95
0
0
P94
0
0
P93
0
0
P92
0
0
P91
0
0
P90
0
0
P
P
P
P
P
P
P
TASS
TBSS
0
Power-on
1
Bank 0, RB
1
(OMCR) /RESET and WDT
Wake-up from Pin
P
Change
Bit Name
LVDIF
IDLE
TC1SS TC2SS TC3SS
1
0
0
0
0
0
0
1
0
0
0
0
0
0
P
P
P
P
P
P
P
ADIF
SPIF
ICIF
TCIF
Power-on
0
0
0
Bank 0, RC
/RESET and WDT
0
0
0
(ISR1)
Wake-up from Pin
P
P
P
Change
Bit Name
CMP2IF CMP1IF TC3IF
Power-on
Bank 0, RD
/RESET and WDT
(ISR2)
Wake-up from Pin
Change
Bit Name
Bank 0, RE Power-on
/RESET and WDT
(ISR3)
Wake-up from Pin
Change
Bit Name
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
TC2IF
TC1IF UERRIF RBFF
TBEF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
0
0
0
0
0
0
0
0
0
0
0
0
I2CDTPIF
0
0
0
0
0
P
P
P
P
P
P
P
P
0
0
0
0
0
0
0
EIES
Power-on
0
Bank 0, R10
0
EIESCR /RESET and WDT
Wake-up from Pin
0
Change
Bit Name
WDTE
Power-on
0
Bank 0, R11
0
WDTCR /RESET and WDT
Wake-up from Pin
P
Change
Bit Name
0
Power-on
0
Bank 0, R12 /RESET and WDT
0
LVDCR
Wake-up from Pin
0
Change
Bit Name
Bank 0, R13 Power-on
TCCCR /RESET and WDT
Wake-up from Pin
Change
PWMBIF PWMAIF EXIF
I2CRIF I2CTIF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
EIS
0
0
INT
0
0
0
0
0
PSWE
0
0
PSW2
0
0
PSW1
0
0
PSW0
0
0
P
P
0
P
P
P
P
0
0
0
0
0
0
0
0
0
LVDEN
0
0
/LVD
R
R
LVD1
0
0
LVD0
0
0
0
0
0
P
R
P
P
0
0
0
TCCS
0
0
TS
0
0
TE
0
0
PSTE
0
0
PST2
0
0
PST1
0
0
PST0
0
0
0
P
P
P
P
P
P
P
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address Bank Name
0X14
0X15
0X16
0X17
0X18
0X19
0X1C
0X1D
0X1E
Bank 0, R14
TCCDATA
Bank 0, R15
IOCR5
Bank 0, R16
IOCR6
Bank 0, R17
IOCR7
Bank 0, R18
IOCR8
Bank 0, R19
IOCR9
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
IOC57
1
1
IOC56
1
1
IOC55
1
1
IOC54
1
1
IOC53
1
1
IOC52
1
1
IOC51
1
1
IOC50
1
1
P
P
P
P
P
P
P
P
IOC67
1
1
IOC66
1
1
IOC65
1
1
IOC64
1
1
IOC63
1
1
IOC62
1
1
IOC61
1
1
IOC60
1
1
P
P
P
P
P
P
P
P
IOC77
1
1
IOC76
1
1
IOC75
1
1
IOC74
1
1
IOC73
1
1
IOC72
1
1
IOC71
1
1
IOC70
1
1
P
P
P
P
P
P
P
P
IOC87
1
1
IOC86
1
1
IOC85
1
1
IOC84
1
1
IOC83
1
1
IOC82
1
1
IOC81
1
1
IOC80
1
1
P
P
P
P
P
P
P
P
IOC97
1
1
IOC96
1
1
IOC95
1
1
IOC94
1
1
IOC93
1
1
IOC92
1
1
IOC91
1
1
IOC90
1
1
P
P
P
P
P
P
P
P
LVDIE
0
ICIE
TCIE
SPIE PWMBIE PWMAIE EXIE
Power-on
0
0
0
Bank 0, R1C
/RESET and WDT
0
0
0
IMR1
Wake-up from Pin
P
P
P
Change
Bit Name
CMP2IE CMP1IE TC3IE
Power-on
Bank 0, R1D
/RESET and WDT
IMR2
Wake-up from Pin
Change
Bit Name
Power-on
Bank 0, R1E
/RESET and WDT
IMR3
Wake-up from Pin
Change
Product Specification (V1.2) 03.15.2013
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
TC2IE
TC1IE UERRIE URIE
UTIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
0
0
0
0
I2CSTPIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
I2CRIE I2CTIE
• 135
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address Bank Name
Reset Type
Bit Name
0X20
Power-on
Bank 0, R20
P5WUCR /RESET and WDT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WU_P57 WU_P56 WU_P55 WU_P54 WU_P53 WU_P52 WU_P51 WU_P50
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Wake-up from Pin
P
P
P
P
P
P
P
P
Change
WUE_P57 WUE_P56 WUE_P55 WUE_P54 WUE_P53 WUE_P52 WUE_P51 WUE_P50
Bit Name
0X21
Power-on
Bank 0, R21
P5WUECR /RESET and WDT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Wake-up from Pin
P
P
P
P
P
P
P
P
Change
WU_P77 WU_P76 WU_P75 WU_P74 WU_P73 WU_P72 WU_P71 WU_P70
Bit Name
0X22
Power-on
Bank 0, R22
P7WUCR /RESET and WDT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Wake-up from Pin
P
P
P
P
P
P
P
P
Change
WUE_P77 WUE_P76 WUE_P75 WUE_P74 WUE_P73 WUE_P72 WUE_P71 WUE_P70
Bit Name
0X23
0X2B
0X2C
0X2D
0X2E
0X2F
136 •
Power-on
Bank 0, R23
P7WUECR /RESET and WDT
Bank 0, R2B
SPICR
Bank 0, R2C
SPIS
Bank 0, R2D
SPIR
Bank 0, R2E
SPIW
Bank 0, R2F
WUCR1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
Wake-up from Pin
P
P
P
P
Change
Bit Name
CES
SPIE
SRO
SSE
Power-on
0
0
0
0
/RESET and WDT
0
0
0
0
Wake-up from Pin
P
P
P
P
Change
Bit Name
DORD
TD1
TD0
0
Power-on
0
0
0
0
/RESET and WDT
0
0
0
0
Wake-up from Pin
P
P
P
0
Change
Bit Name
SRB7 SRB6 SRB5 SRB4
Power-on
U
U
U
U
/RESET and WDT
P
P
P
P
Wake-up from Pin
P
P
P
P
Change
Bit Name
SWB7 SWB6 SWB5 SWB4
Power-on
U
U
U
U
/RESET and WDT
P
P
P
P
Wake-up from Pin
P
P
P
P
Change
Bit Name
0
SPIWE LVDWE ICWE
Power-on
0
0
0
0
/RESET and WDT
0
0
0
0
Wake-up from Pin
0
P
P
P
Change
SDOC SBRS2 SBRS1 SBRS0
0
0
0
0
0
0
0
0
P
P
P
P
OD3
0
0
OD4
0
0
0
0
0
RBF
0
0
P
P
0
P
SRB3
U
P
SRB2
U
P
SRB1
U
P
SRB0
U
P
P
P
P
P
SWB3
U
P
SWB2
U
P
SWB1
U
P
SWB0
U
P
P
P
P
P
0
0
0
P
CMP2WECMP1WE EXWE
0
0
0
0
0
0
P
P
P
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Addr
0X32
0X33
0X34
0X35
0X36
0X37
0X38
0X39
0X3C
0X43
Bank
Name
Reset Type
Bit Name
Bank 0, Power-on
R32
/RESET and WDT
URCR1 Wake-up from Pin
Change
Bit Name
Bank 0, Power-on
R33
/RESET and WDT
URCR2 Wake-up from Pin
Change
Bit Name
Bank 0, Power-on
R34
/RESET and WDT
URS Wake-up from Pin
Change
Bit Name
Bank 0, Power-On
R35
/RESET and WDT
URRD Wake-up from Pin
Change
Bit Name
Bank 0, Power-on
R36
/RESET and WDT
URTD Wake-up from Pin
Change
Bit Name
Bank 0, Power-On
R37
/RESET and WDT
TBPTL Wake-up from Pin
Change
Bit Name
Bank 0, Power-on
R38
/RESET and WDT
TBPTH Wake-up from Pin
Change
Bit Name
Bank 0, Power-on
R39
/RESET and WDT
CMP1CR Wake-up from Pin
Change
Bit Name
Bank 0, Power-on
R3C /RESET and WDT
CMP2CR Wake-up from Pin
Change
Bit Name
Bank 0,
Power-on
R43
CPIRLC /RESET and WDT
Wake-up from Pin
ON
Change
Bit 7
Bit 6
Bit 5
URTD8 UMODE1 UMODE0
U
0
0
P
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BRATE2 BRATE1 BRATE0 UTBE
0
0
0
1
0
0
0
1
TXE
0
0
P
P
P
P
P
P
P
P
0
0
0
0
0
0
SBIM1
0
0
SBIM0
0
0
UINVEN
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
0
0
0
URRD8 EVEN
U
0
P
0
P
P
URRD7 URRD6
U
U
P
P
P
P
URTD7 URTD6
U
U
P
P
PRE
0
0
P
URRD5
U
P
PRERR OVERR FMERR URBF
0
0
0
0
0
0
0
0
P
P
P
P
RXE
0
0
P
URRD4 URRD3 URRD2 URRD1 URRD0
U
U
U
U
U
P
P
P
P
P
P
P
URTD5
U
P
URTD4
U
P
P
P
P
P
URTD3 URTD2 URTD1 URTD0
U
U
U
U
P
P
P
P
P
P
P
P
P
P
P
P
TB7
0
0
TB6
0
0
TB5
0
0
TB4
0
0
TB3
0
0
TB2
0
0
TB1
0
0
TB0
0
0
P
P
P
P
P
P
P
P
HLB
0
0
GP1
0
0
GP0
0
0
TB12
0
0
TB11
0
0
TB10
0
0
TB9
0
0
TB8
0
0
P
P
P
P
P
P
P
P
C1RS CP1OUT CMP1COS1 CMP1COS0 CP1NS CP1PS CP1NRE CP1NRDT
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
C2RS CP2OUT CMP2COS1 CMP2COS0 CP2NS CP2PS CP2NRE CP2NRDT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
BG2OUT C2IRL2
0
0
0
0
P
Product Specification (V1.2) 03.15.2013
P
0
C2IRL1
0
0
P
0
P
P
0
0
C2IRL0 BG1OUT C1IRL2 C1IRL1 C1IRL0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
• 137
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address Bank Name
0X48
0X49
0X4A
0X4B
0X4C
0X4D
0X4E
0X4F
0X05
Bank 0, R48
TC1CR
Bank 0, R49
TCR1DA
Bank 0, R4A
TCR1DB
Bank 0, R4B
T2CR
Bank 0, R4C
TCR2DH
Bank 0, R4D
TCR2DL
Bank 0, R4E
TC3CR
Bank 0, R4F
TC3RD
Reset Type
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
Bank 1, R5
P5PHCR /RESET and WDT
Bit 7
P
138 •
Bit 5
Bit 4
Bit 3
Bit 2
P
P
P
P
P
Bit 1
Bit 0
0
0
0
0
0
0
0
0
TCR1DA7 TCR1DA6 TCR1DA5 TCR1DA4 TCR1DA3 TCR1DA2 TCR1DA1 TCR1DA0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
TCR1DB7 TCR1DB6 TCR1DB5 TCR1DB4 TCR1DB3 TCR1DB2 TCR1DB1 TCR1DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
0
0
0
0
0
0
0
0
TC2ES TC2M
0
0
0
0
P
P
TC2S TC2CK2 TC2CK1 TC2CK0
0
0
0
0
0
0
0
0
P
P
P
P
TCR2D15 TCR2D14 TCR2D13 TCR2D12 TCR2D11 TCR2D10 TCR2D9 TCR2D8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
TCR2D7 TCR2D6 TCR2D5 TCR2D4 TCR2D3 TCR2D2 TCR2D1 TCR2D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
TC3FF1 TC3FF0 TC3S TC3CK2 TC3CK1 TC3CK0 TC3M1 TC3M0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
TCR3D7 TCR3D6 TCR3D5 TCR3D4 TCR3D3 TCR3D2 TCR3D1 TCR3D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
/PH57
/PH56
/PH55
/PH54
/PH53
/PH52
/PH51
/PH50
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
/PH66
/PH65
/PH64
/PH63
/PH62
/PH61
/PH60
Wake-Up from Pin
P
Change
Bit Name
/PH67
0X06
Bit 6
TC1CAP TC1S TC1CK1 TC1CK0 TC1M TC1ES
0
0
0
0
0
0
0
0
0
0
0
0
Power-on
Bank 1, R6
P6PHCR /RESET and WDT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address Bank Name
Reset Type
Bit Name
0X07
0X08
0X09
0X0D
0X0E
Power-on
Bank 1, R9
P9PHCR /RESET and WDT
Power-on
Bank 1, RB
P5PLCR /RESET and WDT
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH77
/PH76
/PH75
/PH74
/PH73
/PH72
/PH71
/PH70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
/PH86
/PH85
/PH84
/PH83
/PH82
/PH81
/PH80
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
/PH96
/PH95
/PH94
/PH93
/PH92
/PH91
/PH90
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
/PL57
/PL56
/PL55
/PL54
/PL53
/PL52
/PL51
/PL50
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
/PL67
/PL66
/PL65
/PL64
/PL63
/PL62
/PL61
/PL60
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
/PL76
/PL75
/PL74
/PL73
/PL72
/PL71
/PL70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
/PL86
/PL85
/PL84
/PL83
/PL82
/PL81
/PL80
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
/PL97
/PL96
/PL95
/PL94
/PL93
/PL92
/PL91
/PL90
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
Power-on
1
Bank 1, RC
1
P6PLCR /RESET and WDT
Wake-up from Pin
P
Change
Bit Name
/PL77
Power-on
1
Bank 1, RD
1
P7PLCR /RESET and WDT
Wake-up from Pin
P
Change
Bit Name
/PL87
Power-on
Bank 1, RE
P8PLCR /RESET and WDT
Wake-up from Pin
Change
Bit Name
0X0F
Bit 5
Power-on
1
Bank 1, R8
1
P8PHCR /RESET and WDT
Wake-up from Pin
P
Change
Bit Name
/PH97
Wake-up from Pin
Change
Bit Name
0X0C
Bit 6
Power-on
1
Bank 1, R7
1
P7PHCR /RESET and WDT
Wake-up from Pin
P
Change
Bit Name
/PH87
Wake-up from Pin
Change
Bit Name
0X0B
Bit 7
Power-on
Bank 1, RF
P9PLCR /RESET and WDT
Wake-up from Pin
Change
Product Specification (V1.2) 03.15.2013
• 139
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address Bank Name
Reset Type
Bit Name
0X11
0X12
0X13
Power-on
Bank 1, R11
P5HD/SCR /RESET and WDT
Wake-up from Pin
Change
Bit Name
Bank 1, R12 Power-on
P6HD/SCR /RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
Bank 1, R13
P7HD/SCR /RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
0X14
0X15
0X17
Bank 1, R14
P8HD/SCR /RESET and WDT
Wake-up from Pin
Change
Bit Name
0X19
Power-on
Bank 1, R17
P5ODCR /RESET and WDT
140 •
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/H57
/H56
/H55
/H54
/H53
/H52
/H51
/H50
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
/H67
1
1
/H66
1
1
/H65
1
1
/H64
1
1
/H63
1
1
/H62
1
1
/H61
1
1
/H60
1
1
P
P
P
P
P
P
P
P
/H77
/H76
/H75
/H74
/H73
/H72
/H71
/H70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
/H87
/H86
/H85
/H84
/H83
/H82
/H81
/H80
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
/H97
/H96
/H95
/H94
/H93
/H92
/H91
/H90
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
OD56
OD55
OD54
OD53
OD52
OD51
OD50
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
OD67
OD66
OD65
OD64
OD63
OD62
OD61
OD60
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
OD76
OD75
OD74
OD73
OD72
OD71
OD70
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
OD87
OD86
OD85
OD84
OD83
OD82
OD81
OD80
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Power-on
0
Bank 1, R18
0
P6ODCR /RESET and WDT
Wake-up from Pin
P
Change
Bit Name
OD77
Power-on
Bank 1, R19
P7ODCR /RESET and WDT
Wake-up from Pin
Change
Bit Name
0X1A
Bit 6
Power-on
1
Bank 1, R15
1
P9HD/SCR /RESET and WDT
Wake-up from Pin
P
Change
Bit Name
OD57
Wake-up from Pin
Change
Bit Name
0X18
Bit 7
Power-on
Bank 1, R1A
P8ODCR /RESET and WDT
Wake-up from Pin
Change
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address Bank Name
Reset Type
Bit Name
0X1B
0X1D
0X1F
0X20
0X21
0X23
0X24
0X25
0X26
Power-on
Bank 1, R1B
P9ODCR /RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
Bank 1, R1D
IRCS
/RESET and WDT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD97
OD96
OD95
OD94
OD93
OD92
OD91
OD90
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
0
0
RCM1
RCM0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Wake-up from Pin
P
P
P
P
P
P
P
P
Change
Bit Name
RD
WR
EEWE EEDF EEPC
0
0
0
Bank 1, R1F Power-on
0
0
0
0
0
0
0
0
EEPROM /RESET and WDT
0
0
0
0
0
0
0
0
Control
Wake-Up from Pin
P
P
P
P
P
P
P
P
Change
Bit Name
EERA7 EERA6 EERA5 EERA4 EERA3 EERA2 EERA1 EERA0
Bank 1, R20 Power-on
0
0
0
0
0
0
0
0
EEPROM /RESET and WDT
0
0
0
0
0
0
0
0
ADDR
Wake-up from Pin
P
P
P
P
P
P
P
P
Change
Bit Name
EERD7 EERD6 EERD5 EERD4 EERD3 EERD2 EERD1 EERD0
Bank 1, R21 Power-on
0
0
0
0
0
0
0
0
EEPROM /RESET and WDT
0
0
0
0
0
0
0
0
DATA
Wake-up from Pin
P
P
P
P
P
P
P
P
Change
Strobe/
SAR_
Bit Name
IMS
ISS
STOP
ACK
FULL EMPTY
Pend
EMPTY
Bank 1, R23 Power-on
0
0
0
0
U
U
U
U
I2CCR1 /RESET and WDT
0
0
0
0
U
U
U
U
Wake-up from Pin
P
P
P
P
P
P
P
P
Change
Bit Name
I2CBF GCEN
0
0
I2CTS1 I2CTS0
0
I2CEN
Power-on
0
0
0
0
0
0
0
0
Bank 1, R24
/RESET
and
WDT
0
0
0
0
0
0
0
0
I2CCR2
Wake-up from Pin
0
0
0
0
P
P
P
P
Change
Bit Name
SA6
SA5
SA4
SA3
SA2
SA1
SA0
IRW
Power-on
0
0
0
0
0
0
0
0
Bank 1, R25
/RESET
and
WDT
0
0
0
0
0
0
0
0
I2CSA
Wake-up from Pin
P
P
P
P
P
P
P
P
Change
Bit Name
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
Power-on
0
0
0
0
0
0
0
0
Bank 1, R26
/RESET and WDT
0
0
0
0
0
0
0
0
I2CDA
Wake-up from Pin
P
P
P
P
P
P
P
P
Change
Product Specification (V1.2) 03.15.2013
• 141
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address Bank Name
0X27
0X28
0X2A
0X2B
0X2F
0X30
0X32
0X33
0X35
0X36
142 •
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bank 1, R27 Power-on
/RESET and WDT
I2CDB
Wake-up from Pin
Change
Bit Name
Reset Type
DB7
0
0
DB6
0
0
DB5
0
0
DB4
0
0
DB3
0
0
DB2
0
0
DB1
0
0
DB0
0
0
P
P
P
P
P
P
P
P
0
0
0
0
0
0
DA9
DA8
Power-on
Bank 1, R28
/RESET and WDT
I2CA
Wake-up from Pin
Change
Bit Name
Bank 1, R2A Power-on
PWMER /RESET and WDT
Wake-up from Pin
Change
Bit Name
Bank 1, R2B Power-on
/RESET and WDT
TIMEN
Wake-up from Pin
Change
Bit Name
Bank 1, R2F Power-on
PWMACR /RESET and WDT
Wake-up from Pin
Change
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TBEN
0
0
TAEN
0
0
0
0
0
0
0
P
P
P
0
0
0
0
0
0
0
0
0
0
0
0
TRCBA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
0
0
0
0
0
0
0
TRCBB
0
0
0
0
0
0
0
Bank 1, R30 Power-on
0
0
0
0
0
0
PWMBCR /RESET and WDT
Wake-up from Pin
0
0
0
0
P
0
Change
Bit Name
0
0
0
0
0
TAP2
Power-on
0
0
0
0
0
0
Bank 1, R32
/RESET
and
WDT
0
0
0
0
0
0
TACR
Wake-up from Pin
0
0
0
0
0
P
Change
Bit Name
0
0
0
0
0
TBP2
0
0
0
0
0
0
Bank 1, R33 Power-on
/RESET
and
WDT
0
0
0
0
0
0
TBCR
Wake-up from Pin
0
0
0
0
0
P
Change
Bit Name
PRDA[9] PRDA[8] PRDA[7] PRDA[6] PRDA[5] PRDA[4]
Power-on
0
0
0
0
0
0
Bank 1, R35
/RESET
and
WDT
0
0
0
0
0
0
TAPRDH
Wake-up from Pin
P
P
P
P
P
P
Change
Bit Name
PRDB[9] PRDB[8] PRDB[7] PRDB[6] PRDB[5] PRDB[4]
Power-on
0
0
0
0
0
0
Bank 1, R36
/RESET
and
WDT
0
0
0
0
0
0
TBPRDH
Wake-up from Pin
P
P
P
P
P
P
Change
PWMBE PWMAE
0
0
0
0
0
0
0
0
0
0
0
0
TAP1
0
0
TAP0
0
0
P
P
TBP1
0
0
TBP0
0
0
P
P
PRDA[3] PRDA[2]
0
0
0
0
P
P
PRDB[3] PRDB[2]
0
0
0
0
P
P
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Address Bank Name
0X38
0X39
0X3B
0X3C
Bank 1, R38
TADTH
Bank 1, R39
TBDTH
Bank 1, R3B
PRDxL
Bank 1, R3C
DTxL
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit Name
DTA[9] DTA[8] DTA[7] DTA[6] DTA[5] DTA[4]
Power-on
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
Wake-up from Pin
P
P
P
P
P
P
Change
Bit Name
DTB[9] DTB[8] DTB[7] DTB[6] DTB[5] DTB[4]
Power-on
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
Wake-up from Pin
P
P
P
P
P
P
Change
Bit Name
0
0
0
0
PRDB[1] PRDB[0]
Power-on
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
Wake-up from Pin
0
0
P
P
P
P
Change
Bit Name
0
0
0
0
DTB[1] DTB[0]
Power-on
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
Wake-up from Pin
0
0
P
P
P
P
Change
Bit 1
Bit 0
DTA[3] DTA[2]
0
0
0
0
P
P
DTB[3] DTB[2]
0
0
0
0
P
P
PRDA[1] PRDA[0]
0
0
0
0
P
P
DTA[1] DTA[0]
0
0
0
0
P
P
6.11.3 The Status of RST, T, and P of STATUS Register
A Reset condition is initiated by the following events:
1) A power-on condition
2) A high-low-high pulse on /RESET pin
3) Watchdog timer time-out
The values of T and P as listed in the following table are used to check how the
processor wakes up.
Values of RST, T, and P after RESET:
Reset Type
Power on
/RESET during Operating mode
T
P
1
1
P*
P*
/RESET wake-up during Sleep mode
1
0
WDT during Operating mode
WDT wake-up during Sleep mode
0
0
P*
0
Wake-up on pin change during Sleep mode
1
0
* Previous status before reset
The table below shows the events that may affect the status of T and P.
Status of T and P Being Affected by Events
Event
T
P
Power on
1
1
WDTC instruction
1
1
WDT time-out
0
P*
SLEP instruction
1
0
Wake-up on pin change during Sleep mode
1
0
* Previous status before reset
Product Specification (V1.2) 03.15.2013
• 143
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
VDD
D
CLK
Oscillator
Q
CLK
CLR
Power-on
Reset
Voltage
Detector
WDTE
WDT
WDT Timeout
RESET
Setup Time
/RESET
Figure 6-24 Controller Reset Block Diagram
6.12 Interrupt
6.12.1 Interrupt for EM78F644/642/641/544/542/541N
The EM78F644/544N has 13 interrupts (3 external, 10 internal) as listed below:
Interrupt Source
144 •
Enable Condition
Int. Flag
Int. Vector
Priority
-
-
0000
High 0
Internal /
External
Reset
External
INT
ENI + EXIE=1
EXIF
0003
1
External
Port 6 pin change
ENI +ICIE=1
ICIF
0006
2
Internal
TCC
ENI + TCIE=1
TCIF
0009
3
Internal
SPI
ENI + SPIIE=1
SPIIF
0012
4
External
Comparator 2
ENI+CMP2IE=1
CMP2IF
0015
5
Internal
TC1
ENI + TC1IE=1
TC1IF
0018
6
Internal
UART Transmit
ENI + UTIE=1
TBEF
001B
7
Internal
UART Receive
ENI + URIE=1
RBFF
001E
8
Internal
UART Receive error ENI+UERRIE=1
UERRIF
0021
9
Internal
TC2
ENI + TC2IE=1
TC2IF
0024
10
Internal
TC3
ENI + TC3IE=1
TC3IF
0027
11
Internal
PWMA
ENI+PWMAIE=1
PWMAIF
002A
12
Internal
PWMB
ENI+PWMBIE=1
PWMBIF
002D
13
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller

The EM78F642/542N has 6 interrupts (3 external, 3 internal) listed below:
Interrupt Source

Enable Condition
Int. Flag
Int. Vector
Priority
-
-
0000
High 0
Internal /
External
Reset
External
INT
ENI + EXIE=1
EXIF
0003
1
External
Port 6 pin change
ENI +ICIE=1
ICIF
0006
2
Internal
TCC
ENI + TCIE=1
TCIF
0009
3
External
Comparator2
ENI+CMP2IE=1
CMP2IF
0015
4
Internal
TC2
ENI + TCIE2=1
TCIF2
0024
5
Internal
TC3
ENI + TCIE3=1
TCIF3
0027
6
The EM78F641/541N has 5 interrupts (3 external, 2 internal) as listed below:
Interrupt Source
Internal /
External
External
External
Internal
External
Internal
Reset
INT
Port 6 pin change
TCC
Comparator 2
TC3
Enable Condition
Int. Flag
Int. Vector
Priority
-
-
0000
High 0
0003
0006
0009
0015
0027
1
2
3
4
5
ENI + EXIE=1
ENI +ICIE=1
ENI + TCIE=1
ENI+CMP2IE=1
ENI + TC3IE=1
EXIF
ICIF
TCIF
CMP2IF
TC3IF
RE and RF are the Interrupt Status registers that record the interrupt requests in the
relative flags/bits. IOCE and IOCF are the Interrupt Mask registers. The global
interrupt is enabled by the ENI instruction and disabled by the DISI instruction. When
one of the enabled interrupts occurs, the next instruction will be fetched from their
individual address. The interrupt flag bit must be cleared by instructions before
leaving the interrupt service routine and before interrupts are enabled to avoid
recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF and RE) is set
regardless of the status of its mask bit or the execution of ENI. The RETI instruction
ends the interrupt routine and enables the global interrupt (the execution of ENI).
The external interrupt is equipped with an on-chip digital noise rejection circuit (input
pulse of less than 8 system clock time is eliminated as noise), but in Low Crystal
oscillator (LXT) mode, the noise rejection circuit is disabled. When an interrupt
(Falling edge) is generated by the External interrupt (when enabled), the next
instruction will be fetched from Address 003H.
Before the interrupt subroutine is executed, the contents of ACC and the R3 and R4
registers are saved by hardware. If another interrupt occurs, the ACC, R3 and R4 will
be replaced by the new interrupt. After the interrupt service routine is completed,
ACC, R3, and R4 will be pushed back.
Product Specification (V1.2) 03.15.2013
• 145
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.12.2 Interrupt for EM78F648/548N
The EM78F648/548N has 18 interrupts (4 external, 14 internal) listed below:
Interrupt Source
Internal /
External
External
External
Internal
INT
Port 6 pin change
TCC
Internal
LVD
External
Internal
External
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Comparator 1
SPI
Comparator 2
TC1
UART Transmit
UART Receive
UART Receive error
TC2
TC3
PWMA
PWMB
I2C Transmit
I2C Receive
I2C Stop
Reset
Enable Condition
Int. Flag
Int. Vector
Priority
0000
High 0
EXIF
ICIF
TCIF
0003
0006
0009
1
2
3
LVDIF
000C
4
CMP1IF
SPIIF
CMP2IF
TC1IF
TBEF
RBFF
UERRIF
TC2IF
TC3IF
PWMAIF
PWMBIF
I2CTIF
I2CRIF
I2CSTPIF
000F
0012
0015
0018
001B
001E
0021
0024
0027
002A
002D
0036
0039
003F
5
6
7
8
9
10
11
12
13
14
15
16
17
18
-
-
ENI + EXIE=1
ENI +ICIE=1
ENI + TCIE=1
ENI+LVDEN and
LVDIE=1
ENI+CMP1IE=1
ENI + SPIIE=1
ENI+CMP2IE=1
ENI + TC1IE=1
ENI + UTIE=1
ENI + URIE=1
ENI+UERRIE=1
ENI + TC2IE=1
ENI + TC3IE=1
ENI+PWMAIE=1
ENI+PWMBIE=1
ENI+ I2CTIE
ENI+ I2CRIE
ENI+ I2CSTPIE
Bank 0 RC~RF are the Interrupt Status registers that record the interrupt requests in
the relative flags/bits. Bank 0 R1C~R1F is the Interrupt Mask register. The global
interrupt is enabled by the ENI instruction and disabled by the DISI instruction. When
one of the interrupts (enabled) occurs, the next instruction will be fetched from their
individual address. The interrupt flag bit must be cleared by instructions before
leaving the interrupt service routine and before interrupts are enabled to avoid
recursive interrupts.
The flag (except ICIF bit delete) in the Interrupt Status Register is set regardless of
the status of its mask bit or the execution of ENI. The RETI instruction ends the
interrupt routine and enables the global interrupt (the execution of ENI).
The External interrupt is equipped with digital noise rejection circuit (input pulse of
less than 8 system clocks time is eliminated as noise), but in Low XTAL oscillator
(LXT) mode the noise rejection circuit is disabled. When an interrupt (Falling
edge) is generated by the External interrupt (when enabled), the next instruction will
be fetched from Address 003H.
Before the interrupt subroutine is executed, the contents of ACC and the R3 and R4
registers are saved by hardware. If another interrupt occurs, the ACC, R3 and R4 will
be replaced by the new interrupt. After the interrupt service routine is completed,
ACC, R3, and R4 will be pushed back.
146 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
VCC
P
R
D
/IRQn
CLK
RF
C
L
Q
IRQn
INT
_
Q
IRQm
RFRD
ENI/DISI
P
R
Q
IOCF
_
Q
C
L
IOD
D
CLK
IOCFWR
/RESET
IOCFRD
RFWR
Figure 6-25a Interrupt Input Circuit Diagram
Interrupt sources
ACC
Interrupt
occurs
STACKACC
ENI/DISI
R3
STACKR3
RETI
R4
STACKR4
Figure 6-25b Interrupt Backup Diagram
6.13 LVD (Low Voltage Detector) for EM78F648/548N
When an unstable power source condition occurs, such as external power noise
interference or EMS test condition, a violent power vibration is generated. At the
same time, the Vdd becomes unstable as it maybe operating below working voltage.
When the system is operating under low voltage condition, the IC kernel will
automatically keep all register status.
6.13.1 LVD Level Control
LVD property is set at Bank 0 R12 (Section 6.3.15). Bits 1 and 0 operation mode is
as follows.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
LVDEN
/LVD
LVD1
LVD0
Bit 1~Bit 0 (LVD1~LVD0): Low Voltage Detect level control bits
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8-Bit Microcontroller
6.13.2 LVD Interrupt
The LVD status and interrupt flag refers to Bank 0 RC (Section 6.3.9) and Bank 0
R1C (Section 6.3.20). Their respective Bit 7 operation mode is as follows.
LVD Interrupt Flag (Bank 0 RC)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDIF
0
SPIF
PWMBIF
PWMAIF
EXIF
ICIF
TCIF
Bit 7 (LVDIF): Low Voltage Detector Interrupt Flag
When LVD1, LVD0 = “0, 0”, Vdd > 2.2V, LVDIF is “0”, Vdd ≤ 2.2V,
set LVDIF to “1”. LVDIF is reset to “0” by software.
When LVD1, LVD0 = “0, 1”, Vdd > 3.3V, LVDIF is “0”, Vdd ≤ 3.3V,
set LVDIF to “1”. LVDIF is reset to “0” by software.
When LVD1, LVD0 = “1, 0”, Vdd > 4.0V, LVDIF is “0”, Vdd ≤ 4.0V,
set LVDIF to “1”. LVDIF is reset to “0” by software.
When LVD1, LVD0 = “1, 1”, Vdd > 4.5V, LVDIF is “0”, Vdd ≤ 4.5V,
set LVDIF to “1”. LVDIF is reset to “0” by software.
LVD Interrupt Enable (Bank 0 R1C)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDIE
0
SPIE
PWMBIE
PWMAIE
EXIE
ICIE
TCIE
Bit 7 (LVDIE): LVDIF interrupt enable bit
0: Disable LVDIF interrupt
1: Enable LVDIF interrupt
6.13.3 LVD Function Setup
To setup the LVD function, perform the following steps:
1) Set the LVDEN to “1”, then use Bits 1, 0 (LVD1, LVD0) of Register RB to set the
LVD interrupt level
2) Enable LVDIE
3) Wait for the LVD interrupt to occur
4) Clear the LVD interrupt flag
148 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
NOTE
The internal LVD module uses the internal circuit to match low voltage
detection. When the LVDEN is set to enable the LVD module, the
current consumption will increase to about 10 μA.
During Sleep mode, the LVD module continues to operate. If the
device voltage drops slowly and crosses the detection point, the LVDIF
bit will be set and the device will not wake-up from Sleep mode. Until
the other wake-up sources wakes-up the EM78F648/548N, the LVD
interrupt flag setting will remain at priority status.
When the system resets, the LVD flag is cleared.
Figure 6-26 below shows the LVD module detection point in an external voltage
condition.
When Vdd drops but above VLVD, LVDIF is kept at “0”.
When Vdd drops below VLVD, LVDIF is set to “1”. If the global ENI is enabled,
LVDIF is also set to “1” and the next instruction will branch to interrupt vector. The
LVD interrupt flag is cleared to “0” by software.
When Vdd drops below VRESET at less than 80 μs, the system will keep all the
register status and halts its operation, but oscillation remains active.
When Vdd drops below VRESET at more than 80 μs, system Reset will occur.
LVDXIF cleared by software
Vdd
VLVD
VRESET
LVDXIF
Internal
Reset
< 50, 40, 30 us
> 50, 40, 30 us
Vdd < Vreset not longer than 80us,system keep on going
18 ms
System reset occur s
Figure 6-26 LVD Waveform Characteristics Showing Detection Point
in an External Voltage Condition
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6.14 Data EEPROM
The Data EEPROM is readable and writable during normal operation over the whole
Vdd range. The operation for Data EEPROM is base on a single byte. A write
operation makes an erase-then-write cycle to take place on the allocated byte.
The Data EEPROM memory provides high erase and write cycles. A byte write
automatically erases the location and writes the new value.
The following are the steps to write to or read data from the EEPROM:
1) Set the EEPC bit to “1” for enable the EEPROM power
2) Write the address to EERA8~EERA0 (512 bytes EEPROM address)
3) A. ● Set the EEWE bit to “1”, if the write function is employed
● Write the 8-bit value of the data to be programmed (256 bytes EEPROM data)
● Set the WR bit to “1”, then; execute write function
B. Set the RD bit to “1”, then; execute read function
4) A. Wait for the EEDF or WR to be cleared
B. Wait for the EEDF to be cleared
5) For the next conversion, go to Step 2 as required
6) To save power and make sure the EEPROM are data not used, clear the EEPC.
6.15 Oscillator
6.15.1 Oscillator Modes
The EM78F64x/F54xN can be operated in the four different oscillator modes, such as
Internal RC oscillator mode (IRC), External RC oscillator mode (ERC), High XTAL
oscillator mode (HXT), and Low XTAL oscillator mode (LXT). User can select one of
them by programming OSC2, OCS1, and OSC0 in the Code Option register. The
following table depicts how these four modes are defined.
The maximum operation frequencies of the crystal/resonator under different VDD
voltages are listed in the table.
Oscillator Modes defined by OSC2 ~ OSC0
Mode
XT (XTAL Oscillator mode)
150 •
OSC2
0
OSC1
0
OSC0
0
HXT (High XTAL Oscillator mode)
0
0
1
LXT1 (Low XTAL1 Oscillator mode)
0
1
0
LXT2 (Low XTAL2 Oscillator mode)
0
1
1
IRC mode, OSCO (P54) acts as I/O pin
1
0
0
IRC mode, OSCO (P54) acts as RCOUT pin
1
0
1
ERC mode, OSCO (P54) acts as I/O pin
ERC mode, OSCO (P54) acts as RCOUT pin
1
1
1
1
0
1
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
In LXT1, LXT2, XT, HXT, and ERC modes, OSCI and OSCO are used. These pins
cannot be used as normal I/O pins. In IRC mode, P55 is used as normal I/O pin.
NOTE
1. Frequency range of HXT mode is 20 MHz ~ 6 MHz.
2. Frequency range of XT mode is 6 MHz ~ 1 MHz.
3. Frequency range of LXT1 mode is 1 MHz ~ 100kHz.
4. Frequency range of XT mode is 32kHz.
Summary of Maximum Operating Speed:
Conditions
Two cycles with two clocks
VDD
Fxt Max. (MHz)
2.5
4.0
3.0
8.0
5.0
20.0
6.15.2 Crystal Oscillator/Ceramic Resonators (XTAL)
EM78F64x/54xN can be driven by an external clock signal through the OSCI pin as
illustrated below.
Figure 6-27a External Clock Input Circuit
In most applications, Pins OSCI and OSCO are connected with a crystal or ceramic
resonator to generate oscillation as depicted in the circuit diagram below. The same
thing applies under HXT or LXT mode. The following table (next page) provides the
recommended values for C1 and C2. Since each resonator has its own attribute, you
should refer to the pertinent resonator specification for appropriate C1/C2 values. RS,
a serial resistor, may be necessary for AT strip cut crystal or low frequency mode.
Figure 6-27b Crystal/Resonator Circuit
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Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator:
Oscillator Type
Frequency
Mode
Ceramic Resonators
HXT
Frequency
LXT
Crystal Oscillator
HXT
C1 (pF)
C2 (pF)
455kHz
2.0 MHz
4.0 MHz
100~150
20~40
10~30
100~150
20~40
10~30
32.768kHz
100kHz
200kHz
455kHz
1.0 MHz
2.0 MHz
4.0 MHz
25
25
25
20~40
15~30
15
15
15
25
25
20~150
15~30
15
15
6.15.3 External RC Oscillator Mode
For some applications that do not require a very precise timing calculation, the use of
RC oscillator (see the figure below) offers a lot of cost savings. Nevertheless, it
should be noted that the frequency of the RC oscillator is influenced by such factors
as supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by
the operation temperature. Moreover, the frequency also changes slightly from one
chip to another due to the manufacturing process variations.
In order to maintain a stable system frequency, the values of the Cext should be more
than 20pF, and that the value of Rext should be less than 1 MΩ. If the values cannot
be kept within the prescribed range, the frequency can be easily affected by noise,
humidity, and leakage.
The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the
contrary, for very low Rext values, for instance, 1 KΩ, the oscillator becomes unstable
because the NMOS cannot discharge the current of the capacitance correctly.
Based on the above reasons, it must be kept in mind that all of the supply voltage, the
operation temperature, the components of the RC oscillator, the package types, the
PCB is layout, could affect the system frequency.
Vcc
Rext
OSCI
Cext
Figure 6-28 Circuit for External RC Oscillator Mode
152 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
RC Oscillator Frequencies:
Cext
20 pF
100 pF
300 pF
Rext
Average Fosc 5V, 25°C
Average Fosc 3V, 25°C
3.3k
3.5 MHz
3.2 MHz
5.1k
2.5 MHz
2.3 MHz
10k
1.30 MHz
1.25 MHz
100k
140kHz
140kHz
3.3k
1.27 MHz
1.21 MHz
5.1k
850kHz
820kHz
10k
450kHz
450kHz
100k
48kHz
50kHz
3.3k
560kHz
540kHz
5.1k
370kHz
360kHz
10k
196kHz
192kHz
100k
20kHz
20kHz
Note: 1. Data are obtained from DIP package measurement.
2. Data are provided for design reference only.
6.15.4 Internal RC Oscillator Mode
The EM78F64x/54xN series MCUs offer a versatile internal RC mode with default
frequency value of 4 MHz. The internal RC oscillator mode has other frequencies
(4 MHz, 16 MHz, 8 MHz, and 455kHz), that can be set by Code Option: RCM1 and
RCM0. All these four main frequencies can be calibrated by programming the Code
Option Bits C4~C0. The following tables show typical drift rates of the calibration.
F644/544N Internal RC Drift Rate (Ta=25°C, VDD=5 V± 5%, VSS=0V):
Drift Rate
Internal RC
Temperature
(-40°C~85°C)
Voltage
(2.4V~5.5V)
Process
Total
4 MHz
± 3%
± 5%
± 2.5%
± 10.5%
16 MHz*
± 3%
± 5%
± 2.5%
± 10.5%
8 MHz
± 3%
± 5%
± 2.5%
± 10.5%
455kHz
± 3%
± 5%
± 2.5%
± 10.5%
*16 MHz Operating Temperature: -40°C ~ 50°C
F642/542N Internal RC Drift Rate (Ta=25°C, VDD=5 V± 5%, VSS=0V):
Drift Rate
Internal RC
Temperature
(-40°C~85°C)
Voltage
(2.4V~5.5V)
Process
Total
1 MHz
± 5%
± 4%
± 2.5%
± 11.5%
4 MHz
± 5%
± 4%
± 2.5%
± 11.5%
8 MHz
± 5%
± 5%
± 2.5%
± 12.5%
16 MHz
± 5%
± 5%
± 2.5%
± 12.5%
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8-Bit Microcontroller
F641/541N Internal RC Drift Rate (Ta=25°C, VDD=5V± 5%, VSS=0V)
Drift Rate
Internal RC
Temperature
(-40°C~85°C)
Voltage
(2.4V~5.5V)
Process
Total
4 MHz
± 3%
± 5%
± 2.5%
± 10.5%
16 MHz
± 3%
± 5%
± 2.5%
± 10.5%
8 MHz
± 3%
± 5%
± 2.5%
± 10.5%
F648/548N Internal RC Drift Rate (Ta=25°C , VDD=5V± 5%, VSS=0V)
Internal RC
Frequency
Drift Rate
455kHz
Temperature
(-40°C+85°C)
± 5%
Voltage
(2.2V~5.5V)
± 5%
4 MHz
± 5%
± 5%
8 MHz
± 5%
± 5%
± 4%
± 14%
16 MHz
± 5%
± 5%
± 4%
± 14%
Process
Total
± 4%
± 14%
± 4%
± 14%
6.16 Power-on Considerations
Any microcontroller is not guaranteed to start operating properly before the power
supply reaches its steady state. EM78F64x/54xN is equipped with a Power-On
Voltage Detector (POVD) with a detection level of 2.0V. Power will work normally if
the Vdd rises fast enough (50 ms or less). However, in critical applications, extra
devices are still required to assist in solving power-up problems.
6.17 External Power-on Reset Circuit
The circuit diagram shown below implements an external RC to generate a reset
pulse. The pulse width (time constant) should be kept long enough for Vdd to
reached minimum operational voltage. Apply this circuit when the power supply has a
slow rise time. Since the current leakage from the /RESET pin is about ± 5 μA, it is
recommended that R should not be greater than 40 KΩ in order for the /RESET pin
voltage to remain at below 0.2V. The diode (D) acts as a short circuit at the moment
of power down. The capacitor (C) will discharge rapidly and fully. The current-limited
resistor (Rin), will prevent high current or ESD (electrostatic discharge) from flowing
into the /RESET pin.
Vdd
R
/RESET
D
Rin
C
Figure 6-29 External Power-up Reset Circuit
154 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.18 Residue-Voltage Protection
When battery is replaced, device power (Vdd) is taken off but residue-voltage remains.
The residue-voltage may trip below Vdd minimum, but not to zero. This condition
may cause a poor power-on reset. Figures 6-30a and 6-30b show how to accomplish
a proper residue-voltage protection circuit.
Vdd
Vdd
33K
Q1
10K
/RESET
40K
1N4684
Figure 6-30a Residue Voltage Protection Circuit 1
Vdd
Vdd
R1
Q1
/RESET
40K
R2
Figure 6-30b Residue Voltage Protection Circuit 2
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8-Bit Microcontroller
6.19 Code Option Register
The EM78F648/644/642/641/548/544/542/541N have Code Option Words that are
not part of the normal program memory. The option bits cannot be accessed during
normal program execution.
Their respecrtive Code Option Register and Customer ID Register arrangement
distribution are as follows:
EM78F644/642/641/544/542/541N
Word 0
Word 1
Word 2
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
Word 0
Word 1
Word 2
Bit 14 ~ Bit 0
Bit 14 ~ Bit 0
Bit 14 ~ Bit 0
EM78F648/548N
6.19.1 Code Option Register (Word 0)
6.19.1.1 EM78F644/642/641/544/542/541N Code Option Word 0
Word 0
Bit 12 Bit 11 Bit 10 Bit 9
-
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
RESET
EN
NRE
CLKS1 CLKS0
OSC2 OSC1 OSC0
ENB
WDTB
NRHL
Bit 12:
Protect
Not used, set to “0” all the time.
Bit 11 (NRHL): Noise Rejection High/Low Pulse Define bit. INT pin is a falling edge
trigger.
0: Pulses equal to 32/fc [s] is regarded as signal (default)
1: Pulses equal to 8/fc [s] is regarded as signal
NOTE
The noise rejection function is turned off in LXT2 and in Sleep mode.
Bit 10 (NRE):
Noise Rejection Enable bit. The INT pin is a falling edge trigger.
0: Enable noise rejection (default)
1: Disable noise rejection
Note that in Low Crystal oscillator (LXT2) mode, the noise rejection
circuit is always disabled.
Bit 9 (RESETENB): Reset Pin Enable Bit
0: P83 set to I/O pin (default)
1: P83 set to /RESET pin
NOTE
The “RESETENB” bit is NOT available in EM78F644/544N
156 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Bit 8 ~ Bit 7 (CLKS1 ~ CLKS0): Instruction period option bit
Instruction Period
CLKS1
CLKS0
4 clocks (default)
0
0
2 clocks
0
1
8 clocks
1
0
16 clocks
1
1
Refer to the Instruction Set in Section 6.20.
NOTE
ELAN UICE only supports two or four clocks instruction period.
Bit 6 (ENWDTB): Watchdog Timer Enable bit
0: Disable (default)
1: Enable
Bit 5 ~ Bit 3 (OSC2 ~ OSC0): Oscillator Mode selection bits
Oscillator Modes as defined by OSC2 ~ OSC0:
Mode
OSC2
OSC1
OSC0
0
0
0
0
0
1
0
1
0
LXT2 (Low Crystal 2 oscillator mode)
0
1
1
IRC (Internal RC oscillator mode)
P55, P54 act as I/O pin
1
0
0
IRC (Internal RC oscillator mode)
P55 act as I/O pin
P54 act as RCOUT pin
1
0
1
ERC (External RC oscillator mode);
P55 act as ERCin pin
P54 act as I/O pin
1
1
0
ERC (External RC oscillator mode);
P55 act as ERCin pin
P54 act as RCOUT pin with Open-Drain
1
1
1
1
XT (Crystal oscillator mode) (default)
2
HXT (High Crystal oscillator mode)
3
LXT1 (Low Crystal 1 oscillator mode)
4
1
Frequency range of XT mode is 6 MHz ~ 1 MHz.
Frequency range of HXT mode is 16 MHz ~ 6 MHz.
3
Frequency range of LXT1 mode is 1 MHz ~ 100kHz.
4
Frequency range of LXT2 mode is 32kHz.
2
Bit 2 ~ Bit 0 (Protect): Protect select bits as shown below:
Protect
Product Specification (V1.2) 03.15.2013
Protect
1
Enable
0
Disable
• 157
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8-Bit Microcontroller
6.19.1.1 EM78F648/548 Code Option Word 0
Word 0
Bit 14
Bit 13
Bit 12
COBS0
-
-
Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
CLKS0
LVR1
LVR0
-
Bit 14 (COBS0):
-
Bit 4
Bit 3
Bit 2 ~ Bit 0
RESETEN ENWDT NRHL
Bit 6
Bit 5
NREB
Protect
IRC mode selection bit
0: Select IRC frequency from the code option
1: Select IRC frequency from the register
Bits 13~12:
Not used, set to “0” all the time.
Bit 11 (CLKS0):
Instruction period option bits
Instruction Period
4 clocks
2 clocks
Bits 10~9:
CLKS0
0
1
Not used, set to “0” all the time.
Bits 8~7 (LVR1~LVR0): Low voltage reset enable bit
LVR1, LVR0
00
01
VDD reset level
NA
2.7V
10
3.7V
11
4.2V
Bit 6 (RESETEN): P83//RST pin selection bit
0: P83 pin
1: /RST pin
Bit 5 (ENWDT):
WDT enable bit
0: Disable
1: Enable
Bit 4 (NRHL):
Noise rejection high/low pulse definition bit
0: Pulses equal to 32/fc [s] is regarded as signal
1: Pulses equal to 8/fc [s] is regarded as signal
Bit 3 (NREB):
Noise rejection enable bit
0: Enable
1: Disable
Bits 2~0 (Protect): Protect bits
158 •
Protect
Protect
1
Enable
0
Disable
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.19.2 Code Option Register (Word 1)
6.19.2.1 EM78F644/642/641/544/542/541N Code Option Word 1
Word 1
Bit 12 Bit 11 Bit 10 Bit 9
COBS0 TCEN
“0”
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
C4
C3
C2
C1
C0
“1”
Bit 3
Bit 2
Bit 1
Bit 0
RCM1 RCM0 LVR1 LVR0
Bit 12 (COBS0): IRC mode selection bit
0: Select IRC frequency from the code option (default)
1: Select IRC frequency from the register
Bit 11 (TCEN): TCC enable bit
0: P77/TCC is set as P77 (default)
1: P77/TCC is set as TCC
NOTE
The TCEN must be set to "0" in EM78F641/541N
Bit 10:
Not used, set to “0” all the time.
Bit 9:
Not used, set to “1” all the time.
Bit 8 ~ Bit 4 (C4 ~ C0): Internal RC mode calibration bits.
C4 ~ C0 must be set to “0” only (auto-calibration).
Bit 3 ~ Bit 2 (RCM1 ~ RCM0): RC mode selection bits
RCM 1
RCM 0
Frequency (MHz)
0
0
4 (default)
0
1
16
1
0
8
1
1
455kHz
NOTE
The 455kHz frequency is NOT available in EM78F641/541N
Bit 1 ~ Bit 0 (LVR1 ~ LVR0): Low Voltage Reset Enable bits
LVR1
LVR0
Reset Level
Release Level
0
0
NA
NA
0
1
2.7V
2.9V
1
0
3.5V
3.7V
1
1
4.0V
4.2V
LVR1, LVR0=“0, 0”: LVR is disabled. The IC power-on reset is
2.0~2.1V (default).
LVR1, LVR0=“0, 1”: If Vdd < 2.7V, the IC will reset.
LVR1, LVR0=“1, 0”: If Vdd < 3.5V, the IC will reset.
LVR1, LVR0=“1, 1”: If Vdd < 4.0V, the IC will reset.
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8-Bit Microcontroller
6.19.2.2 EM78F648/548N Code Option Word 1
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
HLFS
-
SHE
C4
C3
Bit 14 (HLFS):
Word 1
Bit 7 Bit 6
Bit 8
C2
C1
C0
Bit 5
Bit 4
RCM1 RCM0
-
Bit 3
Bit 2
Bit 1
Bit 0
OSC2 OSC1 OSC0 RCOD
Initialize CPU operation mode
0: Normal mode
1: Green mode
Bit 13:
Not used, set to “1” all the time.
Bit 12 (SHE):
System Halt Enable bit.
0: Disable
1: Enable
Bits 11~7 (C4~C0): IRC trim bits. This part will be auto setup by the writer
Bits 6~5 (RCM1~RCM0): IRC frequency selection bits
Bit 4:
RCM 1
RCM 0
Frequency (MHz)
0
0
4 (default)
0
1
16
1
0
8
1
1
455kHz
Not used, set to “1” all the time.
Bits 3~1 (OSC2~OSC0): Oscillator mode selection bits
Mode
OSC2
0
OSC1
0
OSC0
0
HXT (High XTAL oscillator mode)
0
0
1
LXT1 (Low XTAL1 oscillator mode)
0
1
0
LXT2 (Low XTAL2 oscillator mode)
0
1
1
IRC mode, OSCO (P54) act as I/O pin
IRC mode, OSCO (P54) act as RCOUT pin
1
1
0
0
0
1
ERC mode, OSCO (P54) act as I/O pin
1
1
0
ERC mode, OSCO (P54) act as RCOUT pin
1
1
1
XT (XTAL oscillator mode)
Bit 0 (RCOD):
Oscillator output or I/O port selection bit
RCOD
160 •
Pin Function
1
OSCO pin is open drain
0
OSCO output system clock (default)
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
6.19.3 Customer ID Register (Word 2)
6.19.3.1 EM78F644/642/641/544/542/541N Code Option Word 2
Word 2
Bit 12 Bit 11 Bit 10 Bit 9
SC3
SC2
SC1
SC0
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
“0”
“1”
“0”
“0”
ID4
ID3
ID2
ID1
ID0
Bits 12 ~ 9 (SC3 ~ SC0): Calibrator of sub frequency (WDT frequency, auto calibration)
Bit 8:
Not used, set to “0” all the time.
Bit 7:
Not used, set to “1” all the time.
Bits 6 ~ 5:
Not used, set to “0” all the time.
Bits 4 ~ 0 (ID4 ~ ID0):
Customer’s ID code.
6.19.3.2 EM78F648/548N Code Option Word 2
Word 1
Bit14 Bit13 Bit12 Bit11 Bit10
SC3
SC2
SC1
SC0
“0”
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
“0”
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Bits 14 ~ 11 (SC3 ~ SC0): Calibrator of sub frequency (WDT frequency, auto calibration)
Bits 10 ~ 9:
Not used, set to “0” all the time.
Bits 8 ~ 0 (ID8 ~ ID0):
Customer’s ID code.
6.20 Instruction Set
Each instruction in the Instruction Set is a 13-bit word for EM78F664N/F662N/F661N/
F564N/F562N/F561N and 15-bit for EM78F648/548N, divided into an OP code and
one or more operands. Normally, all instructions are executed within one single
instruction cycle (one instruction consists of two oscillator periods), unless the
program counter is changed by instructions "MOV R2,A", "ADD R2,A", or by
instructions of arithmetic or logic operation on R2 (e.g., "SUB R2,A", "BS(C) R2,6",
"CLR R2", ⋅etc.). Under this condition, the execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitableyou’re your
certain applications, try to modify the instruction as follows:
A) Change one instruction cycle to consist of four oscillator periods.
B) "LJMP", "LCALL", "TBRD", "RET", "RETL", "RETI", or the conditional skip ("JBS",
"JBC", "JZ", "JZA", "DJZ", "DJZA") commands which were tested to be true, are
executed within two instruction cycles. The instructions that are written to the
program counter also take two instruction cycles.
Product Specification (V1.2) 03.15.2013
• 161
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
Case (A) is selected by the Code Option bit called CLK1:0. One instruction cycle
consists of two oscillator clocks if CLK1:0 is ”01”, and four oscillator clocks if CLK1:0
is ”00”.
Note that once the four oscillator periods within one instruction cycle is selected as in
Case (A), the internal clock source to TCC should be CLK = Fosc/4, instead of
Fosc/2, as indicated in Figure 6-11 in Section 6.4 TCC/WDT and Prescaler.
In addition, the Instruction Set also has the following features:
1) Every bit of any register can be set, cleared, or tested directly.
2) The I/O register can be regarded as general register. That is, the same instruction
can operate on the I/O register.
6.20.1 Instruction Set Table
In the following symbols are used in the Instruction Set table shown below:
"R" represents a register designator that specifies which one of the registers
(including operational registers and general purpose registers) is to be utilized by
the instruction.
"b" represents a bit field designator that selects the value for the bit which is located
in the register "R", and affects operation.
"k" represents an 8 or 10-bit constant or literal value.
Instruction Set table
Binary Instruction
162 •
Hex
Mnemonic
Operation
Status
Affected
0 0000 0000 0000
000 0000 0000 0000
0000
NOP
No Operation
0 0000 0000 0001
000 0000 0000 0001
0001
DAA
Decimal Adjust A
0 0000 0000 0010
0002
CONTW
A → CONT
0 0000 0000 0011
000 0000 0000 0011
0003
SLEP
0 → WDT, Stop
oscillator
T, P
0 0000 0000 0100
000 0000 0000 0100
0004
WDTC
0 → WDT
T, P
0 0000 0000 rrrr
000r
IOW R
A → IOCR
0 0000 0001 0000
000 0000 0001 0000
0010
ENI
Enable Interrupt
None
0 0000 0001 0001
000 0000 0001 0001
0011
DISI
Disable Interrupt
None
0 0000 0001 0010
000 0000 0001 0010
0012
RET
[Top of Stack] → PC
None
0 0000 0001 0011
000 0000 0001 0011
0013
RETI
[Top of Stack] → PC,
Enable Interrupt
None
None
C
1
None
None
1, 2
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Binary Instruction
Hex
Mnemonic
Operation
Status
Affected
1
0 0000 0001 0100
0014
CONTR
CONT → A
0 0000 0001 rrrr
001r
IOR R
IOCR → A
0 0000 01rr rrrr
000 0001 rrrr rrrr
00rr
01rr
MOV R,A
A→R
None
0 0000 1000 0000
000 0010 0000 0000
0080
0200
CLRA
0→A
Z
0 0000 11rr rrrr
000 0011 rrrr rrrr
00rr
03rr
CLR R
0→R
Z
0 0001 00rr rrrr
000 0100 rrrr rrrr
01rr
04rr
SUB A,R
R-A → A
Z, C, DC
0 0001 01rr rrrr
000 0101 rrrr rrrr
01rr
05rr
SUB R,A
R-A → R
Z, C, DC
0 0001 10rr rrrr
000 0110 rrrr rrrr
01rr
06rr
DECA R
R-1 → A
Z
0 0001 11rr rrrr
000 0111 rrrr rrrr
01rr
07rr
DEC R
R-1 → R
Z
0 0010 00rr rrrr
000 1000 rrrr rrrr
02rr
08rr
OR A,R
A∨R→A
Z
0 0010 01rr rrrr
000 1001 rrrr rrrr
02rr
09rr
OR R,A
A∨R→R
Z
0 0010 10rr rrrr
000 1010 rrrr rrrr
02rr
0Arr
AND A,R
A&R→A
Z
0 0010 11rr rrrr
000 1011 rrrr rrrr
02rr
0Brr
AND R,A
A&R→R
Z
0 0011 00rr rrrr
000 1100 rrrr rrrr
03rr
0Crr
XOR A,R
A⊕R→A
Z
0 0011 01rr rrrr
000 1101 rrrr rrrr
03rr
0Drr
XOR R,A
A⊕R→R
Z
0 0011 10rr rrrr
000 1110 rrrr rrrr
03rr
0Err
ADD A,R
A+R→A
Z, C, DC
0 0011 11rr rrrr
000 1111 rrrr rrrr
03rr
0Frr
ADD R,A
A+R→R
Z, C, DC
0 0100 00rr rrrr
001 0000 rrrr rrrr
04rr
10rr
MOV A,R
R→A
Z
0 0100 01rr rrrr
001 0001 rrrr rrrr
04rr
11rr
MOV R,R
R→R
Z
0 0100 10rr rrrr
001 0010 rrrr rrrr
04rr
12rr
COMA R
/R → A
Z
0 0100 11rr rrrr
001 0011 rrrr rrrr
04rr
13rr
COM R
/R → R
Z
0 0101 00rr rrrr
001 0100 rrrr rrrr
05rr
14rr
INCA R
R+1 → A
Z
0 0101 01rr rrrr
001 0101 rrrr rrrr
05rr
15rr
INC R
R+1 → R
Z
Product Specification (V1.2) 03.15.2013
None
1, 2
None
• 163
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Binary Instruction
164 •
Hex
Mnemonic
Operation
Status
Affected
0 0101 10rr rrrr
001 0110 rrrr rrrr
05rr
16rr
DJZA R
R-1 → A, skip if zero
None
0 0101 11rr rrrr
001 0111 rrrr rrrr
05rr
17rr
DJZ R
R-1 → R, skip if zero
None
0 0110 00rr rrrr
001 1000 rrrr rrrr
06rr
18rr
RRCA R
R(n) → A(n-1),
R(0) → C, C → A(7)
C
0 0110 01rr rrrr
001 1001 rrrr rrrr
06rr
19rr
RRC R
R(n) → R(n-1),
R(0) → C, C → R(7)
C
0 0110 10rr rrrr
001 1010 rrrr rrrr
06rr
1Arr
RLCA R
R(n) → A(n+1),
R(7) → C, C → A(0)
C
0 0110 11rr rrrr
001 1011 rrrr rrrr
06rr
1Brr
RLC R
R(n) → R(n+1),
R(7) → C, C → R(0)
C
0 0111 00rr rrrr
001 1100 rrrr rrrr
07rr
1Crr
SWAPA R
R(0-3) → A(4-7),
R(4-7) → A(0-3)
None
0 0111 01rr rrrr
001 1101 rrrr rrrr
07rr
1Drr
SWAP R
R(0-3) ↔ R(4-7)
None
0 0111 10rr rrrr
001 1110 rrrr rrrr
07rr
1Err
JZA R
R+1 → A, skip if zero
None
0 0111 11rr rrrr
001 1111 rrrr rrrr
07rr
1Frr
JZ R
R+1 → R, skip if zero
None
0 100b bbrr rrrr
010 0bbb rrrr rrrr
0xxx
2xrr
BC R,b
0 → R(b)
None
0 101b bbrr rrrr
010 1bbb rrrr rrrr
0xxx
2xrr
BS R,b
1 → R(b)
None
0 110b bbrr rrrr
011 0bbb rrrr rrrr
0xxx
3xrr
JBC R,b
if R(b)=0, skip
None
0 111b bbrr rrrr
011 1bbb rrrr rrrr
0xxx
3xrr
JBS R,b
if R(b)=1, skip
None
1 00kk kkkk kkkk
100 kkkk kkkk kkkk
1kkk
4kkk
CALL k
PC+1 → [SP],
(Page, k) → PC
None
1 01kk kkkk kkkk
101 kkkk kkkk kkkk
1kkk
5kkk
JMP k
(Page, k) → PC
None
1 1000 kkkk kkkk
110 0000 kkkk kkkk
18kk
60kk
MOV A,k
k→A
None
1 1001 kkkk kkkk
110 0100 kkkk kkkk
19kk
64kk
OR A,k
A∨k→A
Z
1 1010 kkkk kkkk
110 1000 kkkk kkkk
1Akk
68kk
AND A,k
A&k→A
Z
1 1011 kkkk kkkk
110 1100 kkkk kkkk
1Bkk
6Ckk
XOR A,k
A⊕k→A
Z
3
4
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Hex
1 1100 kkkk kkkk
111 0000 kkkk kkkk
1Ckk
70kk
RETL k
k → A,
[Top of Stack] ® PC
1 1101 kkkk kkkk
111 0100 kkkk kkkk
1Dkk
74kk
SUB A,k
k-A → A
Z, C, DC
1 1111 kkkk kkkk
111 1100 kkkk kkkk
1Fkk
7Ckk
ADD A,k
k+A → A
Z, C, DC
1 1110 1001 kkkk
1E9k
BANK k
K → R4(7:6)
None
111 1010 1000 kkkk
7A0k
SBANK k
K → R1(4)
None
111 1010 0100 kkkk
7A4k
GBANK k
K → R1(0)
None
1
k
111
kkk
1110
kkkk
1010
kkkk
1010
kkkk
1000
kkkk
kkkk
kkkk
kkkk
kkkk
1EAk
kkkk
7A8k
kkkk
LCALL k
Next instruction : k kkkk
kkkk kkkk
PC+1 → [SP], k → PC
None
1
k
111
kkk
1110
kkkk
1010
kkkk
1011
kkkk
1100
kkkk
kkkk
kkkk
kkkk
kkkk
1EBk
kkkk
7ACk
kkkk
LJMP k
Next instruction: k kkkk
kkkk kkkk
k → PC
None
1Err
7Brr
TBRD R
ROM[(TABPTR)] → R
None
1 1110 11rr rrrr
111 1011 rrrr rrrr
1
2
3
4
5
Mnemonic
Operation
Status
Affected
Binary Instruction
None
1
5
5
This instruction is applicable to EM78F644/642/641/544/542/541N only.
This instruction is applicable to IOC5~IOC7, IOCA ~ IOCF only.
This instruction is not recommended for Interrupt Status Register operation.
This instruction cannot operate under Interrupt Status Register.
This instruction is applicable to EM78F648/548N only.
Product Specification (V1.2) 03.15.2013
• 165
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
7
Timing Diagram
7.1 AC Test Input/Output Waveform
2.4
2.0
0.8
.0.4
Note:
TEST POINTS
2.0
0.8
AC Testing: Input are driven at 2.4V for logic “1,” and 0.4V for logic “0”
Timing measurements are made at 2.0V for logic “1,” and 0.8V for logic “0”
Figure 7-1a AC Test Timing Diagram
7.2 Reset Timing (CLK1:0 = "01")
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
Figure 7-1b Reset Timing Diagram
166 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
8
Absolute Maximum Ratings
8.1 For EM78F648/548N
Items
Rating
Temperature under bias
-40°C
to
85°C
Storage temperature
-65°C
to
150°C
Working voltage
2.3V
to
5.5V
Working frequency
DC
to
16 MHz
Input voltage
Vss-0.3V
to
Vdd+0.5V
Output voltage
Vss-0.3V
to
Vdd+0.5V
NOTE
These parameters are theoretical values only and have not been tested or verified.
9
DC Electrical Characteristics
9.1 For EM78F648/548N
Ta=25°C, VDD=5.0V±5%, VSS=0V
Symbol
Parameter
XTAL: VDD to 3V
Fxt
XTAL: VDD to 5V
Condition
Two cycles with two clocks
Min.
Typ.
Max.
Unit
DC
−
8
MHz
DC
−
16
MHz
F-30%
370
F+30%
kHz
ERC: VDD to 5V
R: 5.1KΩ, C: 100 pF
IRC: VDD to 5V
4 MHz, 1 MHz, 455kHz, 8 MHz F-2.5%
F
F+2.5%
Hz
IIL
Input Leakage Current for input pins
VIN = VDD, VSS
-
-
±1
μA
IRC1
IRC: VDD to 5V
RCM0:RCM1=1:1
2.9
4
5.7
MHz
IRCE
Internal RC oscillator error per stage
±4.3
± 4.5
± 4.7
%
IRC2
IRC: VDD to 5V
RCM0:RCM1=1:0
5.8
8
11.4
MHz
IRC3
IRC: VDD to 5V
RCM0:RCM1=0:1
0.725
1
1.425
MHz
IRC4
IRC: VDD to 5V
RCM0:RCM1=0:0
330
455
645
kHz
VIHRC
Input High Threshold Voltage
(Schmitt trigger)
OSCI in RC mode
3.9
4
4.1
V
IERC1
Sink current
VI from low to high , VI=5V
21
22
23
mA
VILRC
Input Low Threshold Voltage
(Schmitt trigger)
OSCI in RC mode
1.7
1.8
1.9
V
IERC2
Sink current
VI from high to low, VI=2V
16
17
18
mA
IIL
Input Leakage Current for input pins
VIN = VDD, VSS
-1
0
1
μA
Product Specification (V1.2) 03.15.2013
-
• 167
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VIH1
Input High Voltage (Schmitt trigger) Ports 5, 6, 7, 8, 9
0.7Vdd
-
Vdd+0.3V
V
VIL1
Input Low Voltage (Schmitt trigger) Ports 5, 6, 7, 8, 9
-0.3V
-
0.3Vdd
V
VIHT1
Input High Threshold Voltage
(Schmitt trigger)
/RESET
0.7Vdd
-
Vdd+0.3V
V
VILT1
Input Low Threshold Voltage
(Schmitt trigger)
/RESET
-0.3V
-
0.3Vdd
V
VIHT2
Input High Threshold Voltage
(Schmitt trigger)
TCC, INT
0.7Vdd
-
Vdd+0.3V
V
VILT2
Input Low Threshold Voltage
(Schmitt trigger)
TCC, INT
-0.3V
-
0.3Vdd
V
VIHX1
Clock Input High Voltage
OSCI in crystal mode
2.9
3.0
3.1
V
VILX1
Clock Input Low Voltage
OSCI in crystal mode
1.7
1.8
1.9
V
IOH1
Output High Voltage
(Ports 5, 6, 7, 8, 9)
VOH = VDD - 0.5V
(IOH =3.7mA)
-4.1
-4.45
-5
mA
IOL1
Output Low Voltage
(Ports 5, 6, 7, 8, 9)
VOL = GND+ 0.5V
(IOL =10mA)
11
12
13.5
mA
LVR1
Low voltage reset level
Ta= 25°C
2.4
2.7
3.02
V
Ta= -40~85°C
2.07
2.7
3.37
V
LVR2
Low voltage reset level
Ta= 25°C
3.29
3.7
4.18
V
Ta= -40~85°C
2.78
3.7
4.66
V
LVR3
Low voltage reset level
IPH
Ta= 25°C
3.71
4.2
4.71
V
Ta= -40~85°C
3.18
4.2
5.26
V
Pull-high current
Pull-high active, Input pin at VSS
-70
-75
-80
μA
IPL
Pull-low current
Pull-low active, Input pin at Vdd
35
40
45
μA
ISB1
Power down current
All input and I/O pins at VDD
Output pin floating,
WDT disabled
0.6
2.0
2.5
μA
ISB2
Power down current
All input and I/O pins at VDD,
Output pin floating,
WDT enabled
6
7
8
μA
ICC1
Operating supply current for two
clocks
/RESET= 'High', Fosc=32kHz
(Crystal type,CLKS="0"), Output
pin floating, WDT disabled
20
22
24
μA
ICC2
Operating supply current for two
clocks
/RESET= 'High', Fosc=32kHz
(Crystal type,CLKS="0"), Output
pin floating, WDT enabled
25
27
29
μA
ICC3
Operating supply current for two
clocks
/RESET= 'High', Fosc=4 MHz
(Crystal type, CLKS="0"), Output
pin floating, WDT enabled
1.5
1.6
1.7
mA
ICC4
Operating supply current for two
clocks
/RESET= 'High', Fosc=10 MHz
(Crystal type, CLKS="0"), Output
pin floating, WDT enabled
2.1
2.2
2.3
mA
168 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
NOTE
The parameters shown above are theoretical values only and have not been
tested or verified.
Data under “Min”, “Typ”, and “Max” columns are based on theoretical results at
25°C.
These data are for design reference only and have not been tested or verified.
9.1.1 Program Flash Memory Electrical Characteristics
Symbol
Parameter
Tprog
Erase/Write cycle time
Treten
Data Retention
Tendu
Endurance time
Condition
Min.
−
Typ.
Max.
Unit
Vdd = 5.0V
Temperature = -40°C ~ 85°C
−
−
−
ms
10
−
−
years
100K
−
cycles
Condition
Min.
−
Typ.
Max.
Unit
Vdd = 2.0~ 5.5V
Temperature = -40°C ~ 85°C
−
6
−
ms
10
−
−
years
1000K
−
cycles
Min.
Typ.
Max.
Unit
−
−
10
mV
9.1.2 Data EEPROM Electrical Characteristics
(for EM78F648N only)
Symbol
Parameter
Tprog
Erase/Write cycle time
Treten
Data Retention
Tendu
Endurance time
9.1.3 Comparator Electrical Characteristics
Symbol
1
2
3
Parameter
Condition
1
VOS
Input offset voltage
Vcm
Input common-mode
2
voltage range
−
GND
−
VDD
V
ICO
Supply current of
Comparator
−
−
300
−
uA
TRS
Response time
Vin(-)=2.5V, Vdd=5V, CL=15p
(comparator output load),
Overdrive = 30mV
−
0.8
−
us
VS
Operating range
2.5
−
5.5
V
3
RL = 5.1K
−
The output voltage is in the unit gain circuitry and over the full input common-mode range.
The input common-mode voltage or either input signal voltage should not be allowed to go
negative by more than 0.3V. The upper end of the common-mode voltage range is VDD.
The response time specified is a 100 mV input step with 30 mV overdrive.
Product Specification (V1.2) 03.15.2013
• 169
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
9.2 For EM78F644/544N
Ta=25°C, VDD=5.0V ± 5%, VSS=0V
Symbol
Parameter
Crystal: VDD to 3V
Fxt
Crystal: VDD to 5V
Condition
Two cycles with two clocks
Min.
Typ.
Max.
Unit
DC
−
8
MHz
DC
−
16
MHz
F-30%
370
F+30%
kHz
F
F+2.5%
Hz
ERC: VDD to 5V
R: 5.1KΩ, C: 300 pF
IRC: VDD to 5V
4 MHz, 16 MHz, 8 MHz, 455kHz F-2.5%
IIL
Input Leakage Current for Input pins VIN = VDD, VSS
−
−
±1
μA
VIHRC
Input High Threshold Voltage
(Schmitt Trigger)
OSCI in RC mode
−
3.5
−
V
IERC1
Sink current
VI from low to high, VI=5V
21
22
23
mA
VILRC
Input Low Threshold Voltage
(Schmitt Trigger)
OSCI in RC mode
−
1.5
−
V
IERC2
Sink current
VI from high to low, VI=2V
16
17
18
mA
VIH1
Input High Voltage (Schmitt Trigger) Ports 5, 6, 7, 8
0.7VDD
−
VDD+0.3V
V
VIL1
Input Low Voltage (Schmitt Trigger)
Ports 5, 6, 7, 8
-0.3V
−
0.3VDD
V
VIHT1
Input High Threshold Voltage
(Schmitt Trigger)
/RESET
0.7VDD
−
VDD+0.3V
V
VILT1
Input Low Threshold Voltage
(Schmitt Trigger)
/RESET
-0.3V
−
0.3VDD
V
VIHT2
Input High Threshold Voltage
(Schmitt Trigger)
TCC, INT
0.7VDD
−
VDD+0.3V
V
VILT2
Input Low Threshold Voltage
(Schmitt Trigger)
TCC, INT
-0.3V
−
0.3VDD
V
VIHX1
Clock Input High Voltage
OSCI in crystal mode
−
3.0
−
V
VILX1
Clock Input Low Voltage
OSCI in crystal mode
−
1.8
−
V
IOH1
Output High Voltage (Ports 5~8)
VOH = VDD-0.5V
(IOH =3.7mA)
-3.3
-4.2
−
mA
IOL1
Output Low Voltage (Ports 5, 7, 8)
VOL = GND+0.5V
9
11
−
mA
IOL2
Output Low Voltage (Port 6)
VOL = GND+0.5V
14
18
−
mA
LVR1
Low voltage reset level
Ta= 25°C
2.4
2.7
3.02
V
Ta= -40~85°C
2.07
2.7
3.37
V
LVR2
Low voltage reset level
Ta= 25°C
3.09
3.5
3.98
V
Ta= -40~85°C
2.58
3.5
4.46
V
LVR3
Low voltage reset level
Ta= 25°C
3.51
4.0
4.51
V
Ta= -40~85°C
2.98
4.0
5.06
V
170 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
IPH
Pull-high current
Pull-high active,
Input pin at VSS
−
-70
-80
μA
IPL
Pull-low current
Pull-low active,
Input pin at Vdd
−
20
30
μA
ISB1
Power down current
All input and I/O pins at VDD,
Output pin floating,
WDT disabled
−
1.0
1.5
μA
ISB2
Power down current
All input and I/O pins at VDD,
Output pin floating,
WDT enabled
−
8
10
μA
ICC1
/RESET= 'High', Fosc=32kHz
(Crystal type, LKS1:0="01"),
Operating supply current for two clocks
Output pin floating,
WDT disabled
−
39
42
μA
ICC2
/RESET= 'High', Fosc=32kHz
(Crystal type, LKS1:0="01"),
Operating supply current for two clocks
Output pin floating,
WDT enabled
−
39
42
μA
−
110
120
μA
/RESET= 'High',
Fosc=455kHz (Crystal type,
CLKS1:0="01"),
Output pin floating, WDT
enabled (*VDD = 3V)
ICC3
Operating supply current at two clocks
ICC4
/RESET = 'High',
Fosc=455kHz (IRC type,
Operating supply current for two clocks CLKS1:0="01"),
Output pin floating,
WDT enabled (*VDD = 3V)
−
100
110
μA
ICC5
/RESET = 'High',
Fosc = 4 MHz (Crystal type,
Operating supply current for two clocks CLKS1:0 = "01"),
Output pin floating,
WDT enabled
−
1.1
1.5
mA
ICC6
/RESET = 'High',
Fosc = 10 MHz (Crystal type,
Operating supply current for two clocks CLKS1:0 = "01"),
Output pin floating,
WDT enabled
−
2.6
3
mA
NOTE
The parameters shown above are theoretical values only and have not been
tested or verified.
Data under “Min”, “Typ”, and “Max” columns are based on theoretical results at
25°C.
These data are for design reference only and have not been tested or verified.
Product Specification (V1.2) 03.15.2013
• 171
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
9.2.1 Program Flash Memory Electrical Characteristics
Symbol
Parameter
Tprog
Erase/Write cycle time
Treten
Tendu
Data Retention
Endurance time
Condition
Min.
−
Vdd = 5.0V
Temperature = -40°C ~ 85°C
−
Typ.
Max.
Unit
−
−
ms
years
10
−
−
100K
−
cycles
Min.
−
Typ.
Max.
Unit
4.5
−
ms
−
10
−
years
−
1000K
−
cycles
Min.
Typ.
Max.
Unit
−
−
10
mV
9.2.2 Data EEPROM Electrical Characteristics
(for EM78F644N only)
Symbol
Parameter
Tprog
Erase/Write cycle time
Condition
Treten
Data Retention
Tendu
Endurance time
Vdd = 2.5~ 5.5V
Temperature = -40°C ~ 85°C
9.2.3 Comparator Electrical Characteristics
Symbol
1
Condition
Input offset voltage
Vcm
Input common-mode
2
voltage range
−
GND
−
VDD
V
ICO
Supply current of
Comparator
−
−
200
−
uA
TRS
Response time
Vin(-)=2.5V, Vdd=5V, CL=15p
(comparator output load),
Overdrive = 30mV
−
0.7
−
us
TLRS
Large signal response
time
Vin(-)=2.5V, Vdd=5V, CL=15p
(comparator output load)
−
300
−
ns
VS
Operating range
2.5
−
5.5
V
1
2
3
172 •
Parameter
VOS
3
RL = 5.1K
−
The output voltage is in the unit gain circuitry and over the full input common-mode range.
The input common-mode voltage or either input signal voltage should not be allowed to go
negative by more than 0.3V. The upper end of the common-mode voltage range is VDD.
The response time specified is a 100 mV input step with 30 mV overdrive.
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
9.3 EM78F642/542N
Ta=25°C, VDD = 5.0V ± 5%, VSS = 0V
Symbol
Parameter
Crystal: VDD to 3V
Fxt
Crystal: VDD to 4.5V
Condition
Two cycles with two clocks
Min.
Typ.
Max.
Unit
DC
−
8
MHz
DC
−
16
MHz
F-30%
370
F+30%
kHz
F
F+2.5%
Hz
ERC: VDD to 5V
R: 5.1KΩ, C: 300 pF
IRC: VDD to 5V
4 MHz, 16 MHz, 8 MHz, 455kHz F-2.5%
IIL
Input Leakage Current for Input pins
VIN = VDD, VSS
−
−
±1
μA
VIHRC
Input High Threshold Voltage
(Schmitt Trigger)
OSCI in RC mode
−
3.5
−
V
IERC1
Sink current
VI from low to high, VI=5V
21
22
23
mA
VILRC
Input Low Threshold Voltage
(Schmitt Trigger)
OSCI in RC mode
−
1.5
−
V
IERC2
Sink current
VI from high to low, VI=2V
16
17
18
mA
VIH1
Input High Voltage (Schmitt Trigger)
Ports 5, 6, 7, 8
0.7VDD
−
VDD+0.3V
V
VIL1
Input Low Voltage (Schmitt Trigger)
Ports 5, 6, 7, 8
-0.3V
−
0.3VDD
V
VIHT1
Input High Threshold Voltage
(Schmitt Trigger)
/RESET
0.7VDD
−
VDD+0.3V
V
VILT1
Input Low Threshold Voltage
(Schmitt Trigger)
/RESET
-0.3V
−
0.3VDD
V
VIHT2
Input High Threshold Voltage
(Schmitt Trigger)
TCC, INT
0.7VDD
−
VDD+0.3V
V
VILT2
Input Low Threshold Voltage
(Schmitt Trigger)
TCC, INT
-0.3V
−
0.3VDD
V
VIHX1
Clock Input High Voltage
OSCI in crystal mode
−
3.0
−
V
VILX1
Clock Input Low Voltage
OSCI in crystal mode
−
1.8
−
V
IOH1
Output High Voltage (Ports 5, 6, 7, 8)
VOH = VDD-0.5V
(IOH =3.7mA)
-3.0
-4.2
−
mA
IOL1
Output Low Voltage (Ports 5, 7, 8)
VOL = GND+0.5V
14
18
−
mA
IOL2
Output Low Voltage (Port 6)
VOL = GND+0.5V
18
23
−
mA
LVR1
Low voltage reset level
Ta= 25°C
2.4
2.7
3.02
V
Ta= -40~85°C
2.07
2.7
3.37
V
LVR2
Low voltage reset level
Ta= 25°C
3.09
3.5
3.98
V
Ta= -40~85°C
2.58
3.5
4.46
V
LVR3
Low voltage reset level
Ta= 25°C
3.51
4.0
4.51
V
Ta= -40~85°C
2.98
4.0
5.06
V
IPH
Pull-high current
Pull-high active,
Input pin at VSS
−
-70
-80
μA
IPL
Pull-low current
Pull-low active,
Input pin at Vdd
−
20
30
μA
Product Specification (V1.2) 03.15.2013
• 173
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
−
1.0
1.5
μA
−
8
10
μA
All input and I/O pins at VDD,
ISB1
Power down current
ISB2
Power down current
ICC1
/RESET= 'High', Fosc=32kHz
(Crystal type, LKS1:0="01"),
Operating supply current for two clocks
Output pin floating,
WDT disabled
−
37
40
μA
ICC2
/RESET= 'High', Fosc=32kHz
(Crystal type, CLKS1:0="01"),
Operating supply current for two clocks
Output pin floating,
WDT enabled
−
39
43
μA
ICC3
/RESET= 'High', Fosc=455kHz
(Crystal type, CLKS1:0="01"),
Operating supply current for two clocks
Output pin floating,
WDT enabled (VDD = 3V)
−
110
120
μA
−
100
110
μA
Output pin floating,
WDT disabled
All input and I/O pins at VDD,
Output pin floating,
WDT enabled
/RESET = 'High', Fosc=455kHz
(IRC type, CLKS1:0="01"),
ICC4
Operating supply current for two clocks
ICC5
/RESET = 'High',
Fosc = 4 MHz (Crystal type,
Operating supply current for two clocks CLKS1:0 = "01"),
Output pin floating,
WDT enabled
−
1.1
1.5
mA
ICC6
/RESET = 'High',
Fosc = 10 MHz (Crystal type,
Operating supply current for two clocks CLKS1:0 = "01"),
Output pin floating,
WDT enabled
−
2.8
3
mA
Output pin floating,
WDT enabled (VDD = 3V)
NOTE
The parameters shown above are theoretical values only and have not been
tested or verified.
Data under “Min.”, “Typ.”, and “Max.” columns are based on theoretical results at
25°C.
These data are for design guidance only and have not been tested or verified.
174 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
9.3.1 Program Flash Memory Electrical Characteristics
Symbol
Parameter
Condition
Tprog
Erase/Write cycle time
Treten
Data Retention
Tendu
Endurance time
Vdd = 5.0V
Temperature = -40°C ~ 85°C
Min.
Typ.
Max.
Unit
−
−
−
ms
−
10
−
years
−
100K
−
cycles
Min.
Typ.
Max.
Unit
−
4.5
−
ms
−
10
−
years
−
1000K
−
cycles
Min.
Typ.
Max.
Unit
−
−
5
mV
9.3.2 Data EEPROM Electrical Characteristics
(for EM78F642N only)
Symbol
Parameter
Condition
Tprog
Erase/Write cycle time
Treten
Data Retention
Tendu
Endurance time
Vdd = 2.5 ~ 5.5V
Temperature = -40°C ~ 85°C
9.3.3 Comparator Electrical Characteristics
Symbol
1
2
3
Parameter
Condition
1
RL = 5.1K
VOS
Input offset voltage
Vcm
Input common-mode
2
voltages range
−
GND
−
VDD
V
ICO
Supply current of
Comparator
−
−
200
−
uA
TRS
Response time
Vin(-)=2.5V, Vdd=5V, CL=15p
(comparator output load),
Overdrive = 30mV
−
0.7
−
us
TLRS
Large signal response
time
Vin(-)=2.5V, Vdd=5V, CL=15p
(comparator output load)
−
260
−
ns
VS
Operating range
2.5
−
5.5
V
3
−
The output voltage is in the unit gain circuitry and over the full input common-mode range.
The input common-mode voltage or either input signal voltage should not be allowed to go
negative by more than 0.3V. The upper end of the common-mode voltage range is VDD.
The response time specified is a 100 mV input step with 30 mV overdrive.
Product Specification (V1.2) 03.15.2013
• 175
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
9.4 EM78F641/541N
Ta=25°C, VDD=5.0V±5%, VSS=0V
Symbol
Parameter
Crystal: VDD to 3V
Fxt
Crystal: VDD to 5V
Condition
Two cycles with two clocks
Min.
Typ.
Max.
Unit
DC
−
8
MHz
DC
−
16
MHz
ERC: VDD to 5V
R: 5.1KΩ, C: 300 pF
F-30%
370
F+30%
kHz
IRC: VDD to 5V
4 MHz, 16 MHz, 8 MHz
F-2.5%
F
F+2.5%
Hz
IIL
Input Leakage Current for input pins VIN = VDD, VSS
−
−
±1
μA
VIHRC
Input High Threshold Voltage
(Schmitt Trigger)
OSCI in RC mode
−
3.5
−
V
VI from low to high, VI=5V
21
22
23
mA
OSCI in RC mode
−
1.5
−
V
VI from high to low, VI=2V
16
17
18
mA
IERC1 Sink current
VILRC
Input Low Threshold Voltage
(Schmitt Trigger)
IERC2 Sink current
VIH1
Input High Voltage (Schmitt Trigger) Ports 5, 6, 8
0.7VDD
−
VDD+0.3V
V
VIL1
Input Low Voltage (Schmitt Trigger)
Ports 5, 6, 8
-0.3V
−
0.3 VDD
V
VIHT1
Input High Threshold Voltage
(Schmitt Trigger)
/RESET
0.7VDD
−
VDD+0.3V
V
VILT1
Input Low Threshold Voltage
(Schmitt Trigger)
/RESET
-0.3V
−
0.3 VDD
V
VIHT2
Input High Threshold Voltage
(Schmitt Trigger)
INT
0.7VDD
−
VDD+0.3V
V
VILT2
Input Low Threshold Voltage
(Schmitt Trigger)
INT
-0.3V
−
0.3 VDD
V
VIHX1
Clock Input High Voltage
OSCI in crystal mode
−
3.0
−
V
VILX1
Clock Input Low Voltage
OSCI in crystal mode
−
1.8
−
V
IOH1
Output High Voltage (Ports 5, 6, 8)
VOH = VDD-0.5V
(IOH =3.7mA)
-3.0
-4.2
−
mA
IOL1
Output Low Voltage (Ports 5, 8)
VOL = GND+0.5V
9
11
−
mA
IOL2
Output Low Voltage (Port 6)
VOL = GND+0.5V
15
18
−
mA
LVR1
Low voltage reset level
Ta= 25°C
2.4
2.7
3.02
V
Ta= -40~85°C
2.07
2.7
3.37
V
LVR2
Low voltage reset level
Ta= 25°C
3.09
3.5
3.98
V
LVR3
Low voltage reset level
Ta= 25°C
3.51
4.0
4.51
V
Ta= -40~85°C
2.98
4.0
5.06
V
IPH
Pull-high current
Pull-high active,
Input pin at VSS
−
-70
-80
μA
IPL
Pull-low current
Pull-low active,
Input pin at Vdd
−
20
30
μA
176 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
(Continuation)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
ISB1
Power down current
All input and I/O pins at VDD,
Output pin floating,
WDT disabled
−
1.0
1.5
μA
ISB2
Power down current
All input and I/O pins at VDD,
Output pin floating,
WDT enabled
−
8
10
μA
ICC1
/RESET= 'High', Fosc=32kHz
(Crystal type, CLKS1:0="01"),
Operating supply current for two clocks
Output pin floating,
WDT disabled, HLP=1
−
37
40
μA
ICC2
/RESET= 'High', Fosc=32kHz
(Crystal type, CLKS1:0="01"),
Operating supply current for two clocks
Output pin floating,
WDT enabled, HLP=1
−
39
43
μA
−
110
120
μA
−
1.1
1.5
mA
−
2.7
3
mA
/RESET= 'High', Fosc=455kHz
(Crystal type, CLKS1:0="01"),
ICC3
Operating supply current for two clocks Output pin floating,
WDT enabled,
HLP=1 (VDD = 3V)
ICC4
Operating supply current for two clocks
/RESET = 'High', Fosc=4 MHz
(Crystal type, CLKS1:0 = "01"),
Output pin floating,
WDT enabled
/RESET = 'High', Fosc=10 MHz
ICC5
Operating supply current for two clocks
(Crystal type, CLKS1:0 = "01"),
Output pin floating,
WDT enabled
NOTE
The parameters shown above are theoretical values only and have not been
tested or verified.
Data under “Min.”, “Typ.”, and “Max.” columns are based on theoretical results at
25°C.
These data are for design reference only and have not been tested or verified.
Product Specification (V1.2) 03.15.2013
• 177
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
9.4.1 Program Flash Memory Electrical Characteristics
Symbol
Parameter
Tprog
Erase/Write cycle time
Condition
Treten
Data Retention
Tendu
Endurance time
Min.
−
Typ.
Max.
Unit
−
−
ms
−
10
−
years
−
100K
−
cycles
Min.
−
Typ.
Max.
Unit
4.5
−
ms
−
10
−
years
−
1000K
−
cycles
Min.
Typ.
Max.
Unit
−
−
5
mV
−
GND
−
VDD
V
−
−
200
−
μA
−
0.7
−
μs
−
260
−
ns
2.5
−
5.5
V
Vdd = 5.0V
Temperature = -40°C ~ 85°C
9.4.2 Data EEPROM Electrical Characteristics
(for EM78F641N only)
Symbol
Parameter
Tprog
Erase/Write cycle time
Condition
Treten
Data Retention
Tendu
Endurance time
Vdd = 2.5~ 5.5V
Temperature = -40°C ~ 85°C
9.4.3 Comparator Electrical Characteristics
Symbol
VOS
Vcm
ICO
Parameter
Condition
1
Input offset voltage
Input common-mode
voltages range
2
Supply current of
Comparator
RL = 5.1K
Vin(-)=2.5V, Vdd=5V, CL=15p
TRS
Response time
3
(comparator output load),
Overdrive = 30mV
TLRS
VS
1
2
3
178 •
Large signal response
Vin(-)=2.5V, Vdd=5V, CL=15p
time
(comparator output load)
Operating range
−
The output voltage is in the unit gain circuitry and over the full input common-mode range.
The input common-mode voltage or either input signal voltage should not be allowed to go
negative by more than 0.3V. The upper end of the common-mode voltage range is VDD.
The response time specified is a 100 mV input step with 30 mV overdrive.
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
10 AC Electrical Characteristics
NOTE
The parameters shown below are theoretical values only and have not been tested
or verified.
Data under “Min.”, “Typ.”, and “Max.” columns are based on theoretical results at
25°C.
These data are for design guidance only and have not been tested or verified.
10.1 EM78F648/548N
-40 ≤ Ta ≤ 85°C, VDD=5V, VSS=0V
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Dclk
Input CLK duty cycle
−
45
50
55
%
Tins
Instruction cycle time
(CLKS1:0="01")
Crystal type
100
−
DC
ns
RC type
500
−
DC
ns
Ttcc
TCC input period
−
(Tins+20)/N*
−
−
ns
Tdrh
Device reset hold time
−
11.8
16.8
21.8
ms
Trst
/RESET pulse width
Ta = 25°C
100
−
−
ns
Twdt
Watchdog timer period
Ta = 25°C
11.8
16.8
21.8
ms
Tset
Input pin setup time
−
−
0
−
ns
Thold
Input pin hold time
−
−
20
−
ns
Tdelay
Output pin delay time
−
50
−
ns
Cload = 20 pF
* N: Selected prescaler ratio
10.2 EM78F644/642/641/544/542/541N
--40 ≤ Ta ≤ 85°C, VDD=5V, VSS=0V
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Dclk
Input CLK duty cycle
−
45
50
55
%
Tins
Instruction cycle time
(CLKS1:0="01")
Crystal type
100
−
DC
ns
RC type
500
−
DC
ns
Ttcc
TCC input period
−
(Tins+20)/N*
−
−
ns
Tdrh
Device reset hold time
−
14
16
18
ms
Trst
/RESET pulse width
Ta = 25°C
2000
−
−
ns
Twdt
Watchdog timer period
Ta = 25°C
14
16
18
ms
Tset
Input pin setup time
−
−
0
−
ns
Thold
Input pin hold time
−
−
20
−
ns
Tdelay
Output pin delay time
Cload = 20 pF
−
50
−
ns
* N: Selected prescaler ratio
Product Specification (V1.2) 03.15.2013
• 179
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
APPENDIX
A Package Type
Flash MCU
Package Type
Pin Count
Package Size
EM78F648/548NQ44J/S
QFP
44
10mm x 10mm
EM78F648/548ND40J/S
DIP
40
600 mil
EM78F648/548NK28J/S
Skinny DIP
28
300 mil
EM78F648/548ND28J/S
DIP
28
600 mil
EM78F648/548NSO28J/S
SOP
28
300 mil
Skinny DIP
28
300 mil
SOP
28
300 mil
Skinny DIP
24
300 mil
EM78F644/544NSO24J/S
SOP
24
300 mil
EM78F642/542ND20J/S
DIP
20
300 mil
EM78F642/542NSO20J/S
SOP
20
300 mil
EM78F642/542NSS20J/S
SSOP
20
209mil
EM78F642/542ND18J/S
DIP
18
300 mil
EM78F642/542NSO18J/S
SOP
18
300 mil
EM78F641/541NAD16J/S
DIP
16
300 mil
EM78F641/541NASO16AJ/S
SOP
16
150 mil
MSOP
10
118 mil
EM78F644/544NK28J/S
EM78F644/544NSO28J/S
EM78F644/544NK24J/S
EM78F641/541NMS10J/S
A.1 Green Products Compliance
These MCUs are Green products which do not contain hazardous substances. They
complied with the third edition of Sony SS-00259 standard.
The Pb contents are less the 100 ppm and complied with Sony specifications.
Part No.
EM78F64x/54xNxJ/xS
Electroplate type
Pure Tin
Ingredient (%)
Sn: 100%
232°C
Melting point (°C)
180 •
Electrical resistivity (µΩ cm)
11.4
Hardness (hv)
8~10
Elongation (%)
>50%
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B Packaging Configuration
B.1
EM78F648/548N
B.1.1 44-Pin QFP Package
Figure B-1 EM78F648/548N 44-Pin QFP Package Type
Product Specification (V1.2) 03.15.2013
• 181
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.1.2
40-Pin DIP Package
Figure B-2 EM78F648/548N 40-Pin DIP Package Type
182 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.1.3
28-Pin Skinny DIP Package
Symbal
A
A1
A2
c
D
E1
E
eB
B
B1
L
e
θ
Min
0.381
3.175
0.152
35.204
7.213
7.620
8.382
0.356
1.422
3.251
0
Normal
Max
5.334
3.302
3.429
0.254
0.356
35.255 35.306
7.315
7.417
7.874
8.128
8.890
9.398
0.457
0.559
1.524
1.626
3.302
3.353
2.540(TYP)
10
Figure B-3 EM78F648/548N 28-Pin Skinny DIP Package Type
Product Specification (V1.2) 03.15.2013
• 183
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.1.4
28-Pin DIP Package
Figure B-4 EM78F648/548N 28-Pin DIP Package Type
184 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.1.5 28-Pin SOP Package
Symbal
A
A1
b
c
E
E1
D
L
L1
e
θ
Min
2.370
0.102
0.350
7.410
10.000
17.700
0.678
1.194
0
Normal
2.500
0.406
0.254(TYP)
7.500
10.325
17.900
0.881
1.397
1.27(TYP)
Max
2.630
0.300
0.500
7.590
10.650
18.100
1.084
1.600
8
TITLE:
SOP-28L(300MIL)
PACKAGE OUTLINE
DIMENSION
File :
Edtion: A
SO28
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-5 EM78F648/548N 28-Pin SOP Package Type
Product Specification (V1.2) 03.15.2013
• 185
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.2 EM78F644/544N
B.2.1 28-Pin Skinny DIP Package
Symbal
A
A1
A2
c
D
E1
E
eB
B
B1
L
e
θ
Min
0.381
3.175
0.152
35.204
7.213
7.620
8.382
0.356
1.422
3.251
0
Normal
Max
5.334
3.302
3.429
0.254
0.356
35.255 35.306
7.315
7.417
7.874
8.128
8.890
9.398
0.457
0.559
1.524
1.626
3.302
3.353
2.540(TYP)
10
TITLE:
PDIP-28L SKINNY 300MIL
PACKAGE OUTLINE
DIMENSION
File :
Edtion: A
K28
Unit : mm
Scale: Free
Material:
Sheet:1 of
1
Figure B-6 EM78F644/544N 28-pin Skinny DIP Package Type
186 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.2.2 28-Pin SOP Package
Symbal
A
A1
b
c
E
E1
D
L
L1
e
θ
Min
2.370
0.102
0.350
7.410
10.000
17.700
0.678
1.194
0
Normal
2.500
0.406
0.254(TYP)
7.500
10.325
17.900
0.881
1.397
1.27(TYP)
Max
2.630
0.300
0.500
7.590
10.650
18.100
1.084
1.600
8
TITLE:
SOP-28L(300MIL)
PACKAGE OUTLINE
DIMENSION
File :
Edtion: A
SO28
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-7 EM78F644/544N 28-Pin SOP Package Type
Product Specification (V1.2) 03.15.2013
• 187
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.2.3 24-Pin Skinny DIP Package
13
24
E
12
Min
0.381
3.175
0.203
31.750
6.426
7.370
8.380
0.356
1.470
3.048
0
Normal
Max
5.334
3.302
3.429
0.254
0.356
31.801 31.852
6.628
6.830
7.620
7.870
8.950
9.520
0.457
0.559
1.520
1.630
3.302
3.556
2.540(TYP)
15
A1
A2
1
Symbal
A
A1
A2
c
D
E1
E
eB
B
B1
L
e
θ
e
TITLE:
PDIP-24L SKINNY 300MIL
PACKAGE OUTLINE
DIMENSION
File :
K24
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-8 EM78F644/544N 24-Pin Skinny DIP Package Type
188 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.2.4 24-Pin SOP Package
Symbal
A
A1
b
c
E
H
D
L
e
θ
b
Min
2.350
0.102
Normal
Max
2.650
0.300
0.406(TYP)
0.230
7.400
10.000
15.200
0.630
0.838
1.27(TYP)
0
0.320
7.600
10.650
15.600
1.100
8
e
c
TITLE:
SOP-24L(300MIL) PACKAGE
OUTLINE DIMENSION
File :
SO24
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-9 EM78F644/544N 24-Pin SOP Package Type
Product Specification (V1.2) 03.15.2013
• 189
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.3 EM78F642/542N
B.3.1 20-Pin DIP Package
Figure B-10 EM78F642/542N 20-Pin DIP Package Type
190 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.3.2 20-Pin SOP Package
Figure B-11 EM78F642/542N 20-Pin SOP Package Type
Product Specification (V1.2) 03.15.2013
• 191
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.3.3 20-Pin SSOP Package
Figure B-12 EM78F642/542N 20-Pin SSOP Package Type
192 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.3.4 18-Pin DIP Package
Figure B-13 EM78F642/542N 18-Pin DIP Package Type
Product Specification (V1.2) 03.15.2013
• 193
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.3.5 18-Pin SOP Package
Figure B-14 EM78F642/542N 18-Pin SOP Package Type
194 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.4 EM78F641/541N
B.4.1 16-Pin DIP Package
Symbal
A
A1
A2
c
D
E
E1
eB
B
B1
L
e
θ
Min
0.381
3.175
0.203
19.000
6.174
7.370
8.510
0.356
1.143
3.048
0
Normal
Max
4.318
3.302
3.429
0.254 0.356
19.050 19.100
6.401
6.628
7.620
7.870
9.020
9.530
0.457 0.559
1.524 1.778
3.302 3.556
2.540(TYP)
15
Figure B-15 EM78F641/541N 16-Pin DIP Package Type
Product Specification (V1.2) 03.15.2013
• 195
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.4.2 16-Pin SOP Package
Symbal
A
A1
A2
b
c
E
H
D
L
e
θ
Min
1.350
0.100
1.300
0.330
0.190
3.800
5.800
9.800
0.600
Normal
1.400
Max
1.750
0.250
1.500
0.510
0.250
4.000
6.200
10.000
1.270
1.27(TYP)
0
8
Figure B-16 EM78F641/541N 16-Pin SOP Package Type
196 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
B.4.3 10-Pin MSOP Package
Symbal
A
A1
A2
D
E
E1
b
c
L
e
θ
Min
0.05
0.75
2.90
2.90
4.7
0.19
0.15
0.4
0°
Normal
0.85
3.00
3.00
4.9
0.5BSC
-
Max
1.1
0.15
0.95
3.10
3.10
5.1
0.28
0.2
0.7
8°
Figure B-17 EM78F641/541N 10-Pin MSOP Package Type
Product Specification (V1.2) 03.15.2013
• 197
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
C Quality Assurance and Reliability
Test Category
Test Conditions
Remarks
Solder temperature=245 ± 5°C, for 5 seconds up to the
stopper using a rosin-type flux
Solderability
–
Step 1: TCT, 65°C (15 min)~150°C (15 min), 10 cycles
Step 2: Bake at 125°C, TD (endurance) = 24 hrs
Step 3: Soak at 30°C/60%，TD (endurance) = 192 hrs
Step 4: IR flow 3 cycles
Pre-condition
(Pkg thickness ≥ 2.5 mm or
Pkg volume ≥ 350 mm3 ----225 ± 5°C)
For SMD IC (such as
SOP, QFP, SOJ, etc)
(Pkg thickness ≤ 2.5 mm or
Pkg volume ≤ 350 mm3 ----240 ± 5°C)
Temperature cycle test
-65°C (15 min)~150°C (15 min), 200 cycles
–
Pressure cooker test
TA =121°C, RH = 100%, pressure=2 atm,
TD (endurance) = 96 hrs
–
High temperature /
High humidity test
TA=85°C , RH=85%，TD (endurance) = 168, 500 hrs
–
High-temperature
storage life
TA=150°C, TD (endurance) = 500, 1000 hrs
–
High-temperature
operating life
TA=125°C, VCC = Max. operating voltage,
TD (endurance) = 168, 500, 1000 hrs
–
Latch-up
TA=25°C, VCC = Max. operating voltage, 150mA/20V
–
ESD (HBM)
TA=25°C, ≥∣± 3KV∣
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
ESD (MM)
TA=25°C, ≥ ∣± 300V∣
IP_PS,OP_PS,IO_PS,
VDD-VSS(+),VDD_VSS
(-) mode
C.1 Address Trap Detect
The MCU is embedded with an “Address Trap Detect” feature. It is one of the failsafe functions that detects MCU malfunction caused by noise or the like. Whenever
the MCU attempts to fetch an instruction from a certain section of ROM, an internal
recovery circuit is auto started. If a noise-caused address error is detected, the MCU
will repeat execution of the program until the noise is eliminated. The MCU will then
continue to execute the next program.
198 •
Product Specification (V1.2) 03.15.2013
(This specification is subject to change without further notice)

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