Chapter 1

EM78P151
8-Bit
Microcontroller
Product
Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
December 2014
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are trademarks of ELAN Microelectronics Corporation.
Copyright © 2014 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
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responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
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Contents
Contents
1
General Description ................................................................................................ 1
2
Features ................................................................................................................... 1
3
Pin Assignment ....................................................................................................... 2
4
Pin Description ........................................................................................................ 3
4.1
EM78P151D8/SO8 ........................................................................................... 3
4.2
EM78P151ST6 ................................................................................................. 4
5
Block Diagram ......................................................................................................... 5
6
Functional Description ............................................................................................ 6
6.1
Operational Registers ....................................................................................... 6
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
6.2
Special Function Registers ............................................................................. 11
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.3
R0 (Indirect Addressing Register) ....................................................................... 6
R1 (Timer Clock/Counter) ................................................................................... 6
R2 (Program Counter and Stack)........................................................................ 6
R3 (Status Register) ............................................................................................ 8
R4 (RAM Select Register) ................................................................................... 9
R5 GPR (General Purpose Register)................................................................. 9
R6 (Port 6)........................................................................................................... 9
R7 GPR (General Purpose Register)................................................................. 9
R9 GPR (General Purpose Register)................................................................ 10
RA GPR (General Purpose Register) .............................................................. 10
RF ISR(Interrupt Status Register) ..................................................................... 10
R10~R3F ........................................................................................................... 10
A (Accumulator)................................................................................................. 11
CONT (Control Register)................................................................................... 11
IOC6 (I/O Port Control Register) ....................................................................... 12
IOCB/RB PDCR (Pull-down Control Register) .................................................. 12
IOCC/RC ODCR (Open-drain Control Register) ............................................... 12
IOCD/RD PHCR(Pull-high Control Register) .................................................... 13
IOCE/R8 (WDT Control Register) ..................................................................... 13
IOCF/RE (Interrupt Mask Register)................................................................... 14
Operational Registers ..................................................................................... 15
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
R0 (Indirect Addressing Register) ..................................................................... 15
R1 (Timer Clock/Counter) ................................................................................. 15
R2 (Program Counter and Stack)...................................................................... 15
R3 (Status Register) .......................................................................................... 17
R4 (RAM Select Register) ................................................................................. 17
R5 GPR (General Purpose Register)............................................................... 17
Product Specification (V1.0) 12.29.2014
 iii
Contents
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.4
R6 (Port 6)......................................................................................................... 18
R7 GPR (General Purpose Register)................................................................ 18
R9 IIWK (Port6 Input Change Interrupt/Wake-up control Register) .................. 18
RA PCH (High byte buffer of Program Counter) .............................................. 19
RF ISR(Interrupt Status Register) ..................................................................... 19
R10~R3F ........................................................................................................... 19
Special Function Registers ............................................................................. 20
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
A (Accumulator)................................................................................................. 20
CONT (Control Register)................................................................................... 20
IOC6 (I/O Port Control Register) ....................................................................... 21
IOCB/RB PDCR (Pull-down Control Register) .................................................. 21
IOCC/RC ODCR (Open-drain Control Register) ............................................... 21
IOCD/RD PHCR(Pull-high Control Register) .................................................... 22
IOCE/R8 (WDT Control Register) ..................................................................... 22
IOCF/RE (Interrupt Mask Register)................................................................... 23
6.5
TCC/WDT and Prescaler ................................................................................ 24
6.6
I/O Ports ......................................................................................................... 25
6.7
Reset and Wake-up ........................................................................................ 28
6.7.1
6.7.2
6.7.3
Reset ................................................................................................................. 28
Register Initial Values after Reset ..................................................................... 30
Status of T and P of the Status Register ........................................................... 34
6.8
Interrupt .......................................................................................................... 36
6.9
Oscillator ........................................................................................................ 38
6.9.1
6.9.2
6.9.3
6.9.4
6.10
Oscillator Modes ............................................................................................... 38
Crystal Oscillator/Ceramic Resonators (Crystal) .............................................. 38
External RC Oscillator Mode ............................................................................. 40
Internal RC Oscillator Mode .............................................................................. 41
Power-on Considerations ............................................................................... 42
6.10.1 Programmable Oscillator Set-up Time .............................................................. 42
6.10.2 External Power-on Reset Circuits ..................................................................... 42
6.10.3 Residue-Voltage Protection .............................................................................. 42
6.11
Code Option ................................................................................................... 44
6.11.1
6.11.2
6.11.3
6.11.4
6.12
Code Option Register (Word 0) ........................................................................ 44
Code Option Register (Word 1) ........................................................................ 46
Customer ID Register (Word 2) ........................................................................ 48
Code Option Register (Word 3) ........................................................................ 48
Instruction Set ................................................................................................ 51
7
Absolute Maximum Ratings .................................................................................. 54
8
DC Electrical Characteristics ................................................................................ 54
9
AC Electrical Characteristics ................................................................................ 56
10
Timing Diagrams ................................................................................................... 57
iv 
Product Specification (V1.0) 12.29.2014
Contents
APPENDIX
A
Ordering and Manufacturing Information ............................................................ 58
B
Package Type ......................................................................................................... 59
C
Packaging Configurations .................................................................................... 60
C.1
8-Lead Plastic Dual in-line (DIP) － 300 mil ................................................... 60
C.2
8-Lead Small Outline Package (SOP) － 150 mil ........................................... 60
C.3
6-Lead Small Outline Transistor Plastic Package (SOT) ................................ 61
Product Specification (V1.0) 12.29.2014
v
Contents
Specification Revision History
Doc. Version
0.9
1.0
vi 
Revision Description
Preliminary version
1. Modified the IRC 4 MHz and 8 MHz spec.
2. Modified the table of WDT warm-up time.
Date
2014/08/06
2014/12/29
Product Specification (V1.0) 12.29.2014
EM78P151
8-Bit Microcontroller
1
General Description
The EM78P151 is an 8-bit microprocessor designed and developed with low-power and high-speed
CMOS technology. The devices have on-chip 102413-bit Electrical One Time Programmable Read Only
Memory (OTP-ROM). They provide a protection bit to prevent intrusion of user’s OTP memory code.
Fifteen Code option bits are also available to meet user’s requirements.
With enhanced OTP-ROM features, the EM78P151 provides a convenient way of developing and verifying
user’s programs. Moreover, this OTP devices offer the advantages of easy and effective program updates,
using development and programming tools. You can avail of the ELAN Writer to easily program your
development code.
2 Features
 CPU configuration
 1K13 bits on chip ROM
 528 bits on chip registers (SRAM, general purpose)
when KTYPE=1
 508 bits on chip registers (SRAM, general purpose)
when KTYPE=0
 5 level stacks for subroutine nesting
 Less than 1.5 mA at 5V/4MHz
 Typically 15 A, at 3V/32kHz
 Typically 1 A, during Sleep mode
 I/O port configuration
 1 bi-directional I/O port: P6
 6 I/O pins
 Wake-up port: P6
 6 Programmable pull-down I/O pins
 5 programmable pull-high I/O pins
 5 programmable open-drain I/O pins and
1 open-drain pin (P63)
 External interrupt : P60
Drift Rate
Internal
RC Freq.
± 1%
± 1%
8 MHz
± 1.5%
± 1.5%
± 1%
± 4%
1 MHz
± 1.5%
± 1%
± 1%
± 3.5%
455 kHz
± 1.5%
± 1%
± 1%
± 3.5%



 Crystal mode:
DC ~ 20 MHz / 2clks @ 5V; (DC ~ 100ns inst. Cycle)
DC ~ 16 MHz / 2clks @ 4.5V; (DC ~ 125ns inst. Cycle)
DC ~ 8 MHz / 2clks @ 3V; (DC ~ 250ns inst. Cycle)
DC ~ 4 MHz / 2clks @ 2.3V; (DC ~ 500ns inst. Cycle) 
The transient point of system frequency between HXT
and LXT is 400 kHz.
 IRC,ERC mode:
DC ~ 20 MHz / 2clks @ 5V; (DC ~ 100ns inst. Cycle)
DC ~ 16 MHz / 2clks @ 4.5V; (DC ~ 125ns inst. Cycle)
DC ~ 8 MHz / 2clks @ 3V; (DC ~ 250ns inst. Cycle)
DC ~ 4 MHz / 2clks @ 2.0V; (DC ~ 500ns inst. Cycle)
 IRC mode:
Oscillation mode: 4 / 8 / 1 MHz and 455kHz
(This specification is subject to change without prior notice)
Total
± 1.5%
 2.0V~5.5V at 0C~70C (Commercial)
Product Specification (V1.0) 12.29.2014
Voltage
Process
(2.0 ~ 5.5V)
4 MHz
 Operating voltage range
 Operating frequency range (base on two clocks)
Temp.
(0°C~70°C)
± 3.5%
Peripheral Configuration
 8-bit real time clock/counter (TCC) with selective signal
sources, trigger edges, and overflow interrupt
 3 programmable level voltage reset
LVR : 4.0, 3.5, 2.7V, 1.8V (POR, default)
 2 / 4 / 8 clocks per instruction cycle selected by code
option
Three Available Interrupts:
 TCC overflow interrupt
 Input-port status changed interrupt (wake-up from sleep
mode)
 External interrupt
Special Features
 Programmable free running watchdog timer
 Power saving Sleep mode
 Selectable Oscillation mode
 Programmable prescaler of oscillator set-up time
Package Type:
 8-pin DIP 300mill : EM78P151D8S/J
 8-pin SOP 150mil : EM78P151S8S/J
 6-pin SOT23
: EM78P151ST6S/J
NOTE
These are Green Products which do not
contain hazardous substances.
1
EM78P151
8-Bit Microcontroller
3
Pin Assignment
1
P65/OSCI/ERCin
2
P64/OSCO/RCOUT
3
P63//RST
4
EM78P151
VDD
8
Vss
7
P60//INT
6
P61 (CLK)
5
P62/TCC (DATA)
Figure 3-1 EM78P151D8/SO8
1
Vss
2
P64/OSCO/RCOUT
3
EM78P151
P61 (CLK)
6
P62/TCC (DATA)
5
VDD
4
P63//RST
Figure 3-2 EM78P151ST6
2
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
4
Pin Description
4.1 EM78P151D8/SO8
Legend: ST: Schmitt Trigger input
AN: Analog pin
CMOS: CMOS output
Name
XTAL: Oscillation pin for crystal/ resonator
Function
Input
Type
Output
Type
Description
P60
ST
CMOS
Bidirectional I/O pin with programmable pull- high, pull-low,
open-drain and wake up pin from sleep mode when the
status of the pin changes.
/INT
ST
-
P61
ST
CMOS
CLK
ST
-
P62
ST
CMOS
TCC
ST
-
DATA
ST
CMOS
Programming data pin
P63
ST
CMOS
Input pin or open-drain output pin and wake up pin from
sleep mode when the status of the pin changes.
P60//INT
P61/CLK
P62/TCC/DATA
P63//RESET
External interrupt pin triggered by a falling edge
Bidirectional I/O pin with programmable pull- high, pull-low,
open-drain and wake up pin from sleep mode when the
status of the pin changes.
Programming clock pin
Bidirectional I/O pin with programmable pull- high, pull-low,
open-drain and wake up pin from sleep mode when the
status of the pin changes.
Real Time Clock/Counter clock input
I/O pin with programmable pull-low.
/RESET
ST
-
P64
ST
CMOS
Bidirectional I/O pin with programmable pull- high, pull-low,
open-drain and wake up pin from sleep mode when the
status of the pin changes.
OSCO
-
XTAL
Clock output of crystal/ resonator oscillator
RCOUT
-
CMOS
P65
ST
CMOS
OSCI
XTAL
-
Clock input of crystal/resonator oscillator
ERCin
AN
-
External RC input pin
VDD
VDD
Power
-
Power
VSS
VSS
Power
-
Ground
P64/OSCO/RCOUT
P65/OSCI/ERCin
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
Active low RESET to the device.
Clock output of internal RC oscillator and external RC
oscillator
Bidirectional I/O pin with programmable pull- high, pull-low,
open-drain and wake up pin from sleep mode when the
status of the pin changes.
3
EM78P151
8-Bit Microcontroller
4.2 EM78P151ST6
Legend: ST: Schmitt Trigger input
AN: Analog pin
CMOS: CMOS output
Name
XTAL: Oscillation pin for crystal/ resonator
Function
Input
Type
Output
Type
Description
P61
ST
CMOS
Bidirectional I/O pin with programmable pull- high, pull-low,
open-drain and wake up pin from sleep mode when the
status of the pin changes.
CLK
ST
-
P62
ST
CMOS
TCC
ST
-
DATA
ST
CMOS
Programming data pin
P63
ST
CMOS
Input pin or open-drain output pin and wake up pin from
sleep mode when the status of the pin changes.
P61/CLK
P62/TCC/DATA
P63//RESET
Programming clock pin
Bidirectional I/O pin with programmable pull- high, pull-low,
open-drain and wake up pin from sleep mode when the
status of the pin changes.
Real Time Clock/Counter clock input
I/O pin with programmable pull-low.
/RESET
ST
-
P64
ST
CMOS
Bidirectional I/O pin with programmable pull- high, pull-low,
open-drain and wake up pin from sleep mode when the
status of the pin changes.
OSCO
-
XTAL
Clock output of crystal/ resonator oscillator
RCOUT
-
CMOS
Clock output of internal RC oscillator and external RC
oscillator
VDD
VDD
Power
-
Power
VSS
VSS
Power
-
Ground
P64/OSCO/RCOUT
4
Active low RESET to the device.
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
5
Block Diagram
ROM
PC
Ext.
OSC.
Int.
RC
Ext.
RC
TCC
Instruction
Register
5-level
Stack
(13 bit)
Oscillation
Generation
WDT
TCC
Reset
Instruction
Decoder
P6
P60
P61
P62
P63
P64
P65
Ext INT
Mux.
ALU
R4
LVR
RAM
ACC
R3 (Status
Reg.)
Interrupt
Control
Circuit
Figure 5-1 Functional Block Diagram of EM78P151
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
5
EM78P151
8-Bit Microcontroller
6
Functional Description
KTYPE = 1 (Type A)
6.1 Operational Registers
6.1.1
R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as an indirect addressing
pointer. Any instruction using R0 as a pointer actually accesses data pointed by the
RAM Select Register (R4).
6.1.2

R1 (Timer Clock/Counter)
Incremented by an external signal edge, which is defined by TE bit (CONT-4)
through the TCC pin, or by the instruction cycle clock.

Writable and readable as any other registers.

Defined by resetting PAB (CONT-3).

The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.

The contents of the prescaler counter will be cleared only when the TCC register
is written with a value.
6.1.3

R2 (Program Counter and Stack)
Depending on the device type, R2 and hardware stack are 10-bit wide. The
structure is depicted in the following figure.
PC (A9 ~ A0)
000H
001H
008H
On-chip Program
Memory
User Memory Space
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
Reset Vector
S/W Interrupt Vector
H/W Interrupt Vector
3FFH
Figure 6-1-1 Program Counter Organization

The configuration structure generates 1024  13 bits on-chip OTP ROM
addresses to the relative programming instruction codes. One program page is
1024 words long.
6

If KTYPE bit =1 R2 is set as all "0" when under RESET condition.

If KTYPE bit =0 R2 is set as all "3FF" when under RESET condition.
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller

"JMP" instruction allows direct loading of the lower 10 program counter bits.
Thus, "JMP" allows the PC to go to any location within a page.

"CALL" instruction loads the lower 10 bits of the PC, and PC+1 are pushed onto
the stack. Thus, the subroutine entry address can be located anywhere within a
page.

"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top-level stack.

If KTYPE bit =1, ENHS bit =1 : Any instruction written to R2 (e.g. “ADD R2, A”,
"MOV R2, A", "BC R2, 6", etc.) will cause the ninth bit and the tenth bit (A8 ~ A9)
of the PC to be cleared. Hence, the computed jump is limited to the first 256
locations of a page.

If KTYPE bit =1, ENHS bit =0 : "ADD R2, A" allows a relative address to be added
to the current PC, and the ninth and above bits of the PC will increase
progressively.

All instructions are single instruction cycle (FCLK / 2, FCLK / 4 or FCLK / 8) except for
instructions that would change the contents of R2. Such instructions will need
one more instruction cycle.
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
7
EM78P151
8-Bit Microcontroller

The Data Memory Configuration is as follows:
Address
R PAGE Registers
IOC PAGE Registers
00
R0
(IAR)
Reserve
01
R1
(TCC)
CONT
02
R2
(PC)
Reserve
03
R3
(Status)
Reserve
04
R4
(RSR)
Reserve
05
R5
(GPR)
Reserve
06
R6
(Port 6)
IOC6
07
R7
(GPR)
Reserve
08
R8
(WDTCR)
Reserve
09
R9
(GPR)
Reserve
0A
RA
(GPR)
Reserve
0B
RB
(PDCR)
IOCB
(PDCR)
0C
R
C
(ODCR)
IOCC
(ODCR)
0D
R
D
(PHCR)
IOCD
(PHCR)
0E
RE
(IMR)
IOCE
(WDTCR)
0F
RF
(ISR)
IOCF
(IMR)
(Control Register)
(I/O Port Control Register)
10
:
General Registers
3F
Figure 6-1-2 Data Memory Configuration
6.1.4
R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
GP1
GP0
T
P
Z
DC
C
Bit 7 (RST): Bit for reset type
0: Set to 0 if the device wakes up from other reset type
1: Set to 1 if the device wakes up from sleep mode on a pin change
Bits 6 ~ 5 (GP1 ~ GP0): General-purpose read/write bits
Bit 4 (T):
Time-out bit
Set to “1” by the "SLEP" and "WDTC" commands or during power up;
and reset to “0” by WDT time-out.
Bit 3 (P):
Power down bit
Set to “1” during power on or by a "WDTC" command; and reset to “0”
by a "SLEP" command.
8
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
Bit 2 (Z):
Zero flag
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC):
Auxiliary carry flag
Bit 0 (C):
Carry flag
6.1.5
R4 (RAM Select Register)

Bits 7 ~ 6 are not used. (Read only).

Bits 7 ~ 6 set to “1” at all time.

Bits 5 ~ 0 are used to select registers (address: 0x00 ~ 0x3F) in the indirect
addressing mode.

6.1.6
See the Data Memory Configuration in Figure 6-1-2.
R5 GPR (General Purpose Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
GP
GP
GP
GP
GP
GP
GP
Bits 7~0 (GP): General purpose register
6.1.7
R6 (Port 6)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
GP
P65
P64
P63
P62
P61
P60
Bits 7~6 (GP): General purpose register
Bit 5 (P65): P65 control bit
Bit 4 (P64): P64 control bit
Bit 3 (P63): P63 control bit
Bit 2 (P62): P62 control bit
Bit 1 (P61): P61 control bit
Bit 0 (P60): P60 control bit
R6 is I/O register.
6.1.8
R7 GPR (General Purpose Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
GP
GP
GP
GP
GP
GP
GP
Bits 7~0 (GP): General purpose register
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
9
EM78P151
8-Bit Microcontroller
6.1.9
R9 GPR (General Purpose Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
GP
GP
GP
GP
GP
GP
GP
If KTYPE Bit =1, Port 6 Input Change Interrupt/Wake-up function always enable.
Bits 7~0 (GP): General purpose registers
6.1.10 RA GPR (General Purpose Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
GP
GP
GP
GP
GP
GP
GP
Bits 7~0 (GP): General purpose registers
6.1.11 RF ISR(Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
EXIF
ICIF
TCIF
Note: “1” means with interrupt request
Bits 7 ~ 3:
“0” means no interrupt occurs
Not used. Set to “0” at all time.
Bit 2 (EXIF): External Interrupt Flag. Set by a falling edge on /INT pin, reset by
software.
Bit 1 (ICIF): Port 6 input status changed interrupt flag. Set when Port 6 input
changes, reset by software.
Bit 0 (TCIF): TCC Overflow Interrupt Flag. Set when TCC overflows, reset by
software.
RF can be cleared by instruction but cannot be set.
IOCF is the interrupt mask register.
NOTE
The result of reading RF is the "logic AND" of RF and IOCF.
6.1.12 R10~R3F
These are all 8-bit general-purpose registers.
10 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
6.2 Special Function Registers
6.2.1
A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator, which is not an addressable register.
6.2.2
CONT (Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
/INT
TS
TE
PAB
PSR2
PSR1
PSR0
Bit 7 (GP):
General purpose register.
Bit 6 (/INT):
Interrupt enable flag.
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instructions
Bit 5 (TS):
TCC signal source
0: internal instruction cycle clock, P62 is a bidirectional I/O pin
1: transition on TCC pin
Bit 4 (TE):
TCC signal edge
0: increment if the transition from low to high takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin
Bit 3 (PAB): Prescaler Assigned Bit
0: TCC
1: WDT
Bits 2 ~ 0 (PSR2 ~ PSR0): TCC / WDT prescaler bits
PSR2
PSR1
PSR0
TCC Rate
WDT Rate
0
0
0
1:2
1:1
0
0
1
1:4
1:2
0
1
0
1:8
1:4
0
1
1
1:16
1:8
1
0
0
1:32
1:16
1
0
1
1:64
1:32
1
1
0
1:128
1:64
1
1
1
1:256
1:128
The CONT register is both readable and writable.
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 11
EM78P151
8-Bit Microcontroller
6.2.3
IOC6 (I/O Port Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
C65
C64
C63
C62
C61
C60
Bits 7~6: Not used, set to “1” all the time.
Bit 5 (C65): P65 I/O control register
0: defines the relative I/O pin as output
1: puts the relative I/O pin into high impedance
Bit 4 (C64): P64 I/O control register
Bit 3 (C63): P63 I/O control register
Bit 2 (C62): P62 I/O control register
Bit 1 (C61): P61 I/O control register
Bit 0 (C60): P60 I/O control register
IOC6 registers is both readable and writable.
6.2.4
IOCB/RB PDCR (Pull-down Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
/PD62
/PD61
/PD60
GP
GP
GP
GP
Bit 7 (GP):
General purpose register.
Bit 6 (/PD62): Control bit used to enable pull-down of the P62 pin.
0: Enable internal pull-down
1: Disable internal pull-down
Bit 5 (/PD61): Control bit used to enable pull-down of the P61 pin.
Bit 4 (/PD60): Control bit used to enable pull-down of the P60 pin.
Bits 3~0 (GP): General purpose register.
The IOCB Register is both readable and writable.
6.2.5
IOCC/RC ODCR (Open-drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
GP
OD65
OD64
GP
OD62
OD61
OD60
Bits 7~6 (GP): General purpose register.
Bit 5 (OD65): Control bit used to enable open-drain of the P65 pin.
0: Disable open-drain output
1: Enable open-drain output
12 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
Bit 5 (OD65): Control bit used to enable open-drain of the P65 pin.
Bit 4 (OD64): Control bit used to enable open-drain of the P64 pin.
Bit 3 (GP):
General purpose register.
Bit 2 (OD62): Control bit used to enable open-drain of the P62 pin.
Bit 1 (OD61): Control bit used to enable open-drain of the P61 pin.
Bit 0 (OD60): Control bit used to enable open-drain of the P60 pin.
The IOCC Register is both readable and writable.
6.2.6
IOCD/RD PHCR(Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
GP
/PH65
/PH64
GP
/PH62
/PH61
/PH60
Bits 7~6 (GP): General purpose register.
Bit 5 (/PH65): Control bit used to enable pull-high of the P65 pin.
0: Enable internal pull-high
1: Disable internal pull-high
Bit 4 (/PH64): Control bit used to enable pull-high of the P64 pin.
Bit 3 (GP):
General purpose register.
Bit 2 (/PH62): Control bit used to enable pull-high of the P62 pin.
Bit 1 (/PH61): Control bit used to enable pull-high of the P61 pin.
Bit 0 (/PH60): Control bit used to enable pull-high of the P60 pin.
The IOCD Register is both readable and writable.
6.2.7
IOCE/R8 (WDT Control Register)
ENHS(opt.)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
WDTE
EIS
GP
GP
GP
GP
GP
GP
0
WDTE
EIS
GP
GP
GP
/PD65
/PD64
/PD63
Bit 7 (WDTE): Control bit used to enable the Watchdog timer.
0: Disable WDT
1: Enable WDT
WDTE is both readable and writable.
Bit 6 (EIS):
Control bit is used to define the function of P60 (/INT) pin.
0: P60, bidirectional I/O pin.
1: /INT, external interrupt pin. In this case, the I/O control bit of P60 (Bit
0 of IOC6) must be set to "1".
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 13
EM78P151
8-Bit Microcontroller
When EIS is "0," the path of /INT is masked. When EIS is "1", the status
of the /INT pin can also be read by way of reading Port 6 (R6). See
Figure 6-5 under Section 6.6 for reference.
EIS is both readable and writable.
Bits 5~3:
Not used. Set to “0” at all time.
If ENHS bit = 1
Bits 2~0:
General purpose register.
If ENHS bit = 0
Bit 2 (/PD65): Control bit used to enable pull-down of the P65 pin.
0: Enable internal pull-down
1: Disable internal pull-down
Bit 1 (/PD64): Control bit used to enable pull-down of the P64 pin.
Bit 0 (/PD63): Control bit used to enable pull-down of the P63 pin.
6.2.8
IOCF/RE (Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
GP
GP
GP
GP
EXIE
ICIE
TCIE
Bits 7~3 (GP): General purpose registers
Bit 2 (EXIE): EXIF interrupt enable bit
0: disable EXIF interrupt
1: enable EXIF interrupt
Bit 1 (ICIE): ICIF interrupt enable bit
0: disable ICIF interrupt
1: enable ICIF interrupt
Bit 0 (TCIE): TCIF interrupt enable bit
0: disable TCIF interrupt
1: enable TCIF interrupt
The IOCF register is both readable and writable.
14 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
KTYPE = 0 (Type B)
6.3
Operational Registers
6.3.1
R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as an indirect addressing
pointer. Any instruction using R0 as a pointer actually accesses data pointed by the
RAM Select Register (R4).
6.3.2

R1 (Timer Clock/Counter)
Incremented by an external signal edge, which is defined by TE bit (CONT-4)
through the TCC pin, or by the instruction cycle clock.

Writable and readable as any other registers.

Defined by resetting PAB (CONT-3).

The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.

The contents of the prescaler counter will be cleared only when the TCC register
is written with a value.
6.3.3

R2 (Program Counter and Stack)
Depending on the device type, R2 and hardware stack are 10-bit wide. The
structure is depicted in the following figure.
PC (A9 ~ A0)
000H
002H
008H
On-chip Program
Memory
Reset Vector
User Memory Space
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
S/W Interrupt Vector
H/W Interrupt Vector
3FFH
Figure 6-3-1 Program Counter Organization

The configuration structure generates 102413 bits on-chip OTP ROM
addresses to the relative programming instruction codes. One program page is
1024 words long.

If KTYPE bit =1 R2 is set as all "0" when under RESET condition.

If KTYPE bit =0 R2 is set as all "3FF" when under RESET condition.

"JMP" instruction allows direct loading of the lower 10 program counter bits.
Thus, "JMP" allows PC to go to any location within a page.
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 15
EM78P151
8-Bit Microcontroller

"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 are pushed
onto the stack. Thus, the subroutine entry address can be located anywhere
within a page.

"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top-level stack.

If KTYPE bit =0, ENHS bit =x : Any instruction written to R2 (e.g. “ADD R2, A”,
"MOV R2, A", "BC R2, 6", etc.) will cause the ninth bit and the tenth bit (A8 ~ A9)
from PCHBUF

All instructions are single instruction cycle (FCLK / 2, FCLK / 4 or FCLK / 8) except for
instructions that would change the contents of R2. Such instructions will need
one more instruction cycle.

The Data Memory Configuration is as follows:
Addres
s
16 
R PAGE Registers
IOC PAGE Registers
00
R0
(IAR)
Reserve
01
R1
(TCC)
CONT
02
R2
(PC)
Reserve
03
R3
(Status)
Reserve
04
R4
(RSR)
Reserve
05
R5
(GPR)
Reserve
06
R6
(Port 6)
IOC6
07
R7
(GPR)
Reserve
08
R8
(WDTCR)
Reserve
09
R9
(IIWK)
Reserve
0A
RA
(PCHBUF)
Reserve
0B
RB
(PDCR)
IOCB
(PDCR)
0C
RC
(ODCR)
IOCC
(ODCR)
0D
RD
(PHCR)
IOCD
(PHCR)
0E
RE
(IMR)
IOCE
(WDTCR)
0F
RF
(ISR)
IOCF
(IMR)
(Control Register)
(I/O Port Control Register)
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
10
:
General Registers
3F
Figure 6-3-2 Data Memory Configuration
6.3.4
R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
GP1
GP0
T
P
Z
DC
C
Bit 7 (RST): Bit for reset type
0: Set to 0 if the device wakes up from other reset type
1: Set to 1 if the device wakes up from sleep mode on a pin change
Bits 6 ~ 5 (GP1 ~ GP0): General-purpose read/write bits
Bit 4 (T):
Time-out bit
Set to “1” by the "SLEP" and "WDTC" commands, or during power up;
and reset to “0” by WDT time-out.
Bit 3 (P):
Power down bit
Set to “1” during power on or by a "WDTC" command; and reset to “0”
by a "SLEP" command.
Bit 2 (Z):
Zero flag
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC):
Auxiliary carry flag
Bit 0 (C):
Carry flag
6.3.5
R4 (RAM Select Register)

Bits 7 ~ 6 are not used. (Read only).

Bits 7 ~ 6 set to “1” at all time.

Bits 5 ~ 0 are used to select registers (Address: 0x00 ~ 0x3F) in the indirect
addressing mode.

6.3.6
See the Data Memory Configuration in Figure 6-3-2.
R5 GPR (General Purpose Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
GP
GP
GP
GP
GP
GP
GP
Bits 7~0 (GP): General purpose registers
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 17
EM78P151
8-Bit Microcontroller
6.3.7
R6 (Port 6)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
GP
P65
P64
P63
P62
P61
P60
Bits 7~6 (GP): General purpose registers
Bit 5 (P65): P65 control bit.
Bit 4 (P64): P64 control bit.
Bit 3 (P63): P63 control bit.
Bit 2 (P62): P62 control bit.
Bit 1 (P61): P61 control bit.
Bit 0 (P60): P60 control bit.
R6 is I/O register.
6.3.8
R7 GPR (General Purpose Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
GP
GP
GP
GP
GP
GP
GP
This is 8-bit general-purpose register.
6.3.9
R9 IIWK (Port6 Input Change Interrupt/Wake-up control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
GP
IIWK65
IIWK64
IIWK63
IIWK62
IIWK61
IIWK60
Bits 7~0 (GP): General purpose registers
Bit 5 (IIWK65):
Control bit used to enable Input Change Interrupt/Wake-up of the
P65 pin.
0: Disable Input Change Interrupt/Wake-up function
1: Enable Input Change Interrupt/Wake-up function
Bit 4 (IIWK64):
Control bit used to enable Input Change Interrupt/Wake-up of the
P64 pin.
Bit 3 (IIWK63):
Control bit used to enable Input Change Interrupt/Wake-up of the
P63 pin.
Bit 2 (IIWK62):
Control bit used to enable Input Change Interrupt/Wake-up of the
P62 pin.
Bit 1 (IIWK61):
Control bit used to enable Input Change Interrupt/Wake-up of the
P61 pin.
18 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
Bit 0 (IIWK60):
Control bit used to enable Input Change Interrupt/Wake-up of the
P60 pin.
If KTYPE bit =1, Port6 Input Change Interrupt/Wake-up function always enable.
6.3.10 RA PCH (High byte buffer of Program Counter)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
GP
GP
GP
GP
GP
GP
Bit 1
Bit 0
PC9BUF PC8BUF
Bits 7~2 (GP): General purpose registers
Bit 1 (PC9BUF): buffer of Program Counter Bit 9
Bit 0 (PC8BUF): buffer of Program Counter Bit 8
6.3.11 RF ISR(Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
EXIF
ICIF
TCIF
Note: “1” means with interrupt request
Bits 7 ~ 3:
“0” means no interrupt occurs
Not used. Set to “0” at all time.
Bit 2 (EXIF): External Interrupt Flag. Set by a falling edge on /INT pin, reset by
software.
Bit 1 (ICIF): Port 6 input status changed interrupt flag. Set when Port 6 input
changes, reset by software.
Bit 0 (TCIF): TCC Overflow Interrupt Flag. Set when TCC overflows, reset by
software.
RF can be cleared by instruction but cannot be set.
IOCF is the interrupt mask register.
NOTE
The result of reading RF is the "logic AND" of RF and IOCF.
6.3.12 R10~R3F
These are all 8-bit general-purpose registers.
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 19
EM78P151
8-Bit Microcontroller
6.4
Special Function Registers
6.4.1
A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator, which is not an addressable register.
6.4.2
CONT (Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
INTEG
TS
TE
PAB
PSR2
PSR1
PSR0
Bit 7 (GP):
General purpose register.
Bit 6 (INTEG): Interrupt edge select bit.
0: interrupt on the falling edge of INT pin.
1: interrupt on the rising edge of INT pin.
Bit 5 (TS):
TCC signal source
0: internal instruction cycle clock, P62 is a bidirectional I/O pin
1: transition on TCC pin
Bit 4 (TE):
TCC signal edge
0: increment if the transition from low to high takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin
Bit 3 (PAB): Prescaler Assigned Bit
0: TCC
1: WDT
Bits 2 ~ 0 (PSR2 ~ PSR0): TCC / WDT prescaler bits
PSR2
PSR1
PSR0
TCC Rate
WDT Rate
0
0
0
1:2
1:1
0
0
1
1:4
1:2
0
1
0
1:8
1:4
0
1
1
1:16
1:8
1
0
0
1:32
1:16
1
0
1
1:64
1:32
1
1
0
1:128
1:64
1
1
1
1:256
1:128
The CONT register is both readable and writable.
20 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
6.4.3
IOC6 (I/O Port Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
C65
C64
C63
C62
C61
C60
Bits 7~6: Not used, set to “1” all the time.
Bit 5 (C65): P65 I/O control register
0: defines the relative I/O pin as output
1: puts the relative I/O pin into high impedance
Bit 4 (C64): P64 I/O control register
Bit 3 (C63): P63 I/O control register
Bit 2 (C62): P62 I/O control register
Bit 1 (C61): P61 I/O control register
Bit 0 (C60): P60 I/O control register
IOC6 registers is both readable and writable.
6.4.4
IOCB/RB PDCR (Pull-down Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
/PD62
/PD61
/PD60
GP
GP
GP
GP
Bit 7 (GP):
General purpose register.
Bit 6 (/PD62): Control bit used to enable pull-down of the P62 pin.
0: Enable internal pull-down
1: Disable internal pull-down
Bit 5 (/PD61): Control bit used to enable pull-down of the P61 pin.
Bit 4 (/PD60): Control bit used to enable pull-down of the P60 pin.
Bits 3~0 (GP): General purpose register.
The IOCB Register is both readable and writable.
6.4.5
IOCC/RC ODCR (Open-drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
GP
OD65
OD64
GP
OD62
OD61
OD60
Bits 7~6 (GP): General purpose registers
Bit 5 (OD65): Control bit used to enable open-drain of the P65 pin.
0: Disable open-drain output
1: Enable open-drain output
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 21
EM78P151
8-Bit Microcontroller
Bit 4 (OD64): Control bit used to enable open-drain of the P64 pin.
Bit 3 (GP):
General purpose register.
Bit 2 (OD62): Control bit used to enable open-drain of the P62 pin.
Bit 1 (OD61): Control bit used to enable open-drain of the P61 pin.
Bit 0 (OD60): Control bit used to enable open-drain of the P60 pin.
The IOCC Register is both readable and writable.
6.4.6
IOCD/RD PHCR(Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
GP
/PH65
/PH64
GP
/PH62
/PH61
/PH60
Bits 7~6 (GP): General purpose registers
Bit 5 (/PH65): Control bit used to enable pull-high of the P65 pin.
0: Enable internal pull-high
1: Disable internal pull-high
Bit 4 (/PH64): Control bit used to enable pull-high of the P64 pin.
Bit 3 (GP):
General purpose register.
Bit 2 (/PH62): Control bit used to enable pull-high of the P62 pin.
Bit 1 (/PH61): Control bit used to enable pull-high of the P61 pin.
Bit 0 (/PH60): Control bit used to enable pull-high of the P60 pin.
The IOCD Register is both readable and writable.
6.4.7
IOCE/R8 (WDT Control Register)
ENHS(opt.)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
WDTE
EIS
GP
GP
GP
GP
GP
GP
0
WDTE
EIS
GP
GP
GP
/PD65
/PD64
/PD63
Bit 7 (WDTE): Control bit used to enable the Watchdog timer.
0: Disable WDT
1: Enable WDT
WDTE is both readable and writable.
Bit 6 (EIS):
Control bit is used to define the function of P60 (/INT) pin.
0: P60, bidirectional I/O pin.
1: /INT, external interrupt pin. In this case, the I/O control bit of P60 (Bit
0 of IOC6) must be set to "1."
22 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
When EIS is "0," the path of /INT is masked. When EIS is "1," the status
of the /INT pin can also be read by way of reading Port 6 (R6). For
reference, see Figure 6-5 under Section 6.6.
EIS is both readable and writable.
Bits 5~3:
Not used. Set to “0” at all time.
If ENHS bit = 1
Bits 2~0:
General purpose register.
If ENHS bit = 0
Bit 2 (/PD65): Control bit used to enable pull-down of the P65 pin.
0: Enable internal pull-down
1: Disable internal pull-down
Bit 1 (/PD64): Control bit used to enable pull-down of the P64 pin.
Bit 0 (/PD63): Control bit used to enable pull-down of the P63 pin.
6.4.8
IOCF/RE (Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/INT
GP
GP
GP
GP
EXIE
ICIE
TCIE
Bit 7 (/INT):
Interrupt Enable flag. If KTYPE Bit = 0
0: BC RE, 7
1: BS RE, 7
Bits 6 ~ 3 (GP): General purpose register.
Bit 2 (EXIE): EXIF interrupt enable bit
0: disable EXIF interrupt
1: enable EXIF interrupt
Bit 1 (ICIE): ICIF interrupt enable bit
0: disable ICIF interrupt
1: enable ICIF interrupt
Bit 0 (TCIE): TCIF interrupt enable bit
0: disable TCIF interrupt
1: enable TCIF interrupt
The IOCF register is both readable and writable.
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 23
EM78P151
8-Bit Microcontroller
6.5
TCC/WDT and Prescaler
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is
available for the TCC only or the WDT only at the same time and the PAB bit of the
CONT register is used to determine the prescaler assignment. The PSR0 ~ PSR2 bits
determine the ratio. The prescaler is cleared each time the instruction is written to
TCC under TCC mode. The WDT and prescaler, when assigned to WDT mode, are
cleared by the “WDTC” or “SLEP” instructions. Figure 6-4 depicts the circuit diagram
of TCC / WDT.

R1 (TCC) is an 8-bit timer / counter. The TCC clock source can be internal or
external clock input (edge selectable from TCC pin). If the TCC signal source is
from an internal clock, TCC will be incremented by 1 at every instruction cycle
(without prescaler). Referring to Figure 6-3, CLK = FOSC / 2, CLK = FOSC / 4 or
CLK = FOSC / 8 depends on the Code Option bit CLK[1:0]. CLK = FOSC / 2 is used
if CLK[1:0] is set to "10", CLK = FOSC / 4 is used if CLK[1:0] is set to "11", and
CLK[1:0] = FOSC / 8 is used if CLK[1:0] is set to "0x". If the TCC signal source is
from an external clock input, TCC is incremented by 1 at every falling edge or
rising edge of the TCC pin.

The Watchdog Timer is a free running on-chip RC oscillator. The WDT will keep
running even when the oscillator driver has been turned off (i.e. in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause
the device to reset. The WDT can be enabled or disabled any time during normal
mode by software programming. Refer to WDTE bit of the IOCE register. Without
prescaler, the WDT time-out period is approximately 18 ms1 (default).
Data Bus
CLK (FOSC / 2 or FOSC / 4 or Fosc /8)
0
1
M
U
X
TCC
Pin
0
1
TE
TS
0
WDT
M
U
X
M
U
X
TCC (R1)
PAB TCC Overflow Interrupt
8-bit Counter
1
PSR0~PSR2
8-to-1 MUX
PAB
WDTE
(in IOCE)
0
1
MUX
PAB
WDT Time Out
Figure 6-4 TCC and WDT Block Diagram
1
Vdd = 5V, set up time period = 16.5ms ± 30% at 25°C
Vdd = 3V, set up time period = 18ms ± 30% at 25°C
24 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
6.6
I/O Ports
The I/O register, port 6, is bidirectional tri-state I/O port. Port 6 can be pulled-high
internally by software except P63. In addition, Port 6 can also have open-drain output
by software except P63. Input status changed interrupt (or wake-up) function is
available from Port 6. P60 ~ P62 pins can be pulled-down by software. Each I/O pin
can be defined as "input" or "output" pin by the I/O control register (IOC6) except P63.
The I/O registers and I/O control registers are both readable and writable. The I/O
interface circuits for Port 6 are shown in Figure 6-5 ~ Figure 6-7 respectively.
PCRD
Port
Bit 6 of
IOCE
0
1
D P
R Q
CLK _
C Q
L
Q P
RD
_ CLK
Q C
L
PCWR
Q P
R D
_ CLK
Q C
L
PDWR
IOD
M
U
X
PDRD
T10
P
D R Q
CLK _
C Q
L
Note: Pull-high (down) and open-drain are not shown in the figure.
Figure 6-5 I/O Port and I/O Control Register Circuit for P60 (/INT)
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 25
EM78P151
8-Bit Microcontroller
PORT
0
1
Q
_
Q
P
R D
CLK
C
L
PCWR
Q
_
Q
P
R D
CLK
C
L
PDWR
IOD
M
U
X
TIN
PDRD
P
R
CLK
C
L
D
Q
_
Q
Note: Pull-high (down) and open-drain are not shown in the figure.
Figure 6-6 I/O Port and I/O Control Register Circuit for P61~P62, P64~P65
ICIE
D
P
R
Q
Interrupt
CLK
_
C Q
L
ICIF
ENI Instruction
P
D R Q
P60
P61
P62
P63
P64
P65
CLK
_
C Q
L
P
Q R
D
CLK
_
Q C
L
DISI Instruction
/SLEP
Interrupt
(Wake-up from
SLEEP)
Next Instruction
(Wake-up from
SLEEP)
Figure 6-7 Block Diagram of I/O Port 6 with input change interrupt/wake-up
26 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
Table 6-1 Usage of Port 6 Input Change Wake-up / Interrupt Function
Usage of Port 6 Input Status Change Wake-up/Interrupt
(I) Wake-up from Port 6 Input Status Change
(a) Before Sleep
(II) Port 6 Input Status Change Interrupt
1. Read I/O Port 6 (MOV R6,R6)
1. Disable WDT
2. Execute “ENI”
2. Read I/O Port 6 (MOV R6,R6)
3. Enable interrupt (Set IOCF.1)
3. Execute "ENI" or "DISI"
4. IF Port 6 change (interrupt)
4. Enable interrupt (Set IOCF.1)
 Interrupt vector (008H)
5. Execute "SLEP" instruction
(b) After Wake-up
1. IF "ENI"  Interrupt vector (008H)
2. IF "DISI"  Next instruction
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 27
EM78P151
8-Bit Microcontroller
6.7 Reset and Wake-up
6.7.1
Reset
A Reset is initiated by one of the following events:
1) Power-on reset
2) /RESET pin input "low"
3) WDT time-out (if enabled)
4) Low Voltage Reset
2
The device is kept under reset condition for a period of approximately 18ms (one
oscillator start-up timer period) after a reset is detected. Once a Reset occurs, the
following functions are performed:

The oscillator is running, or will be started.

The Program Counter (R2) is set to all "0."

All I/O port pins are configured as input mode (high-impedance state)

The Watchdog timer and prescaler are cleared.

When power is switched on, the upper 3 bits of R3 are cleared.

The bits of the CONT register are set to all "1" except for Bit 6 (INT flag).

The bits of the IOCB register are set to all "1."

The IOCC register is cleared.

The bits of the IOCD register are set to all "1."

Bit 7 of the IOCE register is set to "1," and Bits 4 and 6 are cleared.

Bits 0 ~ 2 of RF and Bits 0 ~ 2 of IOCF registers are cleared.
The Sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering Sleep mode, WDT (if enabled) is cleared but keeps on running.
The controller can be awakened by:
1) External reset input on /RESET pin
2) WDT time-out (If enabled)
3) Port 6 Input Status changed (If enabled)
The first two cases will cause the EM78P151 to reset. The T and P flags of R3 are
used to determine the source of the reset (wake-up). The last case is considered the
continuation of program execution and the global interrupt ("ENI" or "DISI" being
executed) determines whether or not the controller branches to the interrupt vector
following a wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from Address 008H after wake-up. If DISI is executed before SLEP, the
2
28 
Vdd = 5V, set up time period = 16.8ms ± 30%
Vdd = 3V, set up time period = 18ms ± 30%
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
operation will restart from the succeeding instruction right next to SLEP after a
wake-up.
Only one of Cases 2 and 3 can be enabled before going into the Sleep mode. That is,
[a] If Port 6 Input Status Change Interrupt is enabled before SLEP, WDT must be
disabled by software. Hence, the EM78P151 can be awakened only by Case 1 or
Case 3.
[b] If WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be
disabled. Hence, the EM78P151 can be awakened only by Case 1 or Case 2.
Refer to Section 7.6, Interrupt for further details.
If Port 6 Input Status Change Interrupt is used to wake-up the EM78P151 (Case [a]
above), the following instructions must be executed before SLEP:
MOV A, @xxxx1110b
; Select the WDT prescaler, it must be
; set over 1:1
CONTW
WDTC
; Clear WDT and prescaler
MOV A, @0xxxxxxxb
; Disable WDT
IOW RE
MOV R6, R6
; Read Port 6
MOV A, @00000x1xb
; Enable Port 6 input change interrupt
IOW RF
ENI (or DISI)
; Enable (or disable) global interrupt
SLEP
; Sleep
NOTE
1. After waking up from sleep mode, WDT is automatically enabled. The WDT enable
/ disable operation after waking up from sleep mode should be appropriately defined in
the software.
2. To avoid a reset from occurring when the Port 6 Input Status Changed Interrupt
enters into interrupt vector or is used to wake-up the MCU, the WDT prescaler must be
set above the 1:1 ratio.
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 29
EM78P151
8-Bit Microcontroller
6.7.2
Register Initial Values after Reset
Legend: : Not used
U: Unknown or don’t care
Address
Name
R0
000
IAR
R1
001
TCC
R2
002
PC
R3
003
SR
R4
004
RSR
R5
005
GPR
R6
006
P6
0X07
30 
R7
GPR
P: Previous value before reset
t: Check table on “Reset Type” in Section 6.4.3
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
U
U
U
U
U
U
U
U
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Jump to Address 0x08 or continue to execute next instruction
RST
0
GP1
0
GP0
0
T
1
P
1
Z
U
DC
U
C
U
0
0
0
*
*
P
P
P
1
P
P
*
*
P
P
P
GP1
U
GP0
U
U
U
U
U
U
U
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
GP
U
GP
U
GP
U
GP
U
GP
U
GP
U
GP
U
GP
U
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
GP
U
GP
U
P65
1
P64
1
P63
1
P62
1
P61
1
P60
1
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
GP
U
P
GP
U
P
GP
U
P
GP
U
P
GP
U
P
GP
U
P
GP
U
P
GP
U
P
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
Address
00E
0X08
Name
IOCE
(ENHS=1)
R8
WDTCR
R9
0X09
IIWK
(KTYPE =0)
R9
0X09
GPR
(KTYPE =1)
0X0A
RA
PCHBUF
RA
0X0A
GPR
(KTYPE =1)
0X0B
0X0C
RB
PDCR
RC
ODCR
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P
P
P
P
P
P
P
P
WDTE
1
EIS
0
GP
U
GP
U
GP
U
GP
U
GP
U
GP
U
1
0
P
P
P
P
P
P
1
P
P
P
P
P
P
P
WDTE
1
EIS
0
GP
U
GP
U
GP
U
1
0
P
P
P
1
1
1
1
P
P
P
P
P
P
P
GP
U
GP
U
P
P
0
0
0
0
0
0
P
P
P
P
P
P
P
P
GP
U
GP
U
GP
U
GP
U
GP
U
GP
U
GP
U
GP
U
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Bit Name
GP
GP
GP
GP
GP
GP
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
U
U
U
U
U
U
P
P
P
P
P
P
0
0
P
P
P
P
P
P
P
P
GP
U
GP
U
GP
U
GP
U
GP
U
GP
U
GP
U(0)
GP
U(0)
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
GP
U
GP
U
GP
U
GP
U
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
GP
U
/PD65 /PD64 /PD63
1
1
1
IIWK65 IIWK64 IIWK63 IIWK62 IIWK61 IIWK60
0
0
0
0
0
0
/PD62 /PD61 /PD60
1
1
1
PC9B PC8BU
UF
F
0
0
P
1
1
1
P
P
P
P
P
P
P
P
P
P
P
P
GP
U
GP
U
OD65
0
OD64
0
GP
U
OD62
0
OD61
0
OD60
0
P
P
0
0
P
0
0
0
P
P
P
P
P
P
P
P
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 31
EM78P151
8-Bit Microcontroller
Address
0X0D
Name
RD
PHCR
RE
00E
IMR
(KTYPE=1)
RE
0X0E
IMR
(KTYPE=0)
RF
00F
ISR
CONT
N/A
(KTYPE=1)
N/A
006
0X0B
32 
CONT
(KTYPE=0)
IOC6
IOCB
Reset Type
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
Bit 7
Bit 6
GP
U
GP
U
P
P
1
1
P
1
1
1
P
P
P
P
P
P
P
P
GP
U(0)
GP
U
GP
U
GP
U
GP
U
EXIE
0
ICIE
0
TCIE
0
P
P
P
P
P
0
0
0
P
P
P
P
P
P
P
P
/INT
0
GP
U
GP
U
GP
U
GP
U
EXIE
0
ICIE
0
TCIE
0
0
P
P
P
P
0
0
0
0
P
P
P
P
P
P
P

0

0

0

0

0
EXIF
0
ICIF
0
TCIF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
N
P
GP
U
/INT
0
TS
1
TE
1
PAB
1
PSR2
1
PSR1
1
PSR0
1
P
0
1
1
1
1
1
1
P
0
P
P
P
P
P
P
GP
U
INTEG
0
TS
1
TE
1
PAB
1
PSR2
1
PSR1
1
PSR0
1
P
0
1
1
1
1
1
1
P
P
P
P
P
P
P
P
1
1
C65
1
C64
1
C63
1
C62
1
C61
1
C60
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
GP
U
GP
U
GP
U
GP
U
GP
U
Bit 5
Bit 4
/PH65 /PH64
1
1
/PD62 /PD61 /PD60
1
1
1
Bit 3
GP
U
Bit 2
Bit 1
Bit 0
/PH62 /PH61 /PH60
1
1
1
P
1
1
1
P
P
P
P
P
P
P
P
P
P
P
P
GP
U
GP
U
OD65
0
OD64
0
GP
U
OD62
0
OD61
0
OD60
0
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
Address
Name
00C
IOCC
00D
00E
IOCD
IOCE
(ENHS=1)
IOCE
00E
(ENHS=0)
IOCF
00F
(KTYPE=1)
00F
IOCF
(KTYPE=0)
010
~
03F
R10~R3F
Reset Type
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET and
WDT
Wake-up from
Pin Change
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P
P
0
0
P
0
0
0
P
P
P
P
P
P
P
P
GP
U
GP
U
P
P
1
1
P
1
1
1
P
P
P
P
P
P
P
P
WDTE
1
EIS
0
GP
U
GP
U
GP
U
GP
U
GP
U
GP
U
1
0
P
P
P
P
P
P
1
P
P
P
P
P
P
P
WDTE
1
EIS
0
GP
U
GP
U
GP
U
1
0
P
P
P
1
1
1
1
P
P
P
P
P
P
P
GP
U(0)
GP
U
GP
U
GP
U
GP
U
EXIE
0
ICIE
0
TCIE
0
P
P
P
P
P
0
0
0
P
P
P
P
P
P
P
P
/INT
0
GP
U
GP
U
GP
U
GP
U
EXIE
0
ICIE
0
TCIE
0
0
P
P
P
P
0
0
0
0
P
P
P
P
P
P
P
U
U
U
U
U
U
U
U
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
/PH65 /PH64
1
1
GP
U
/PH62 /PH61 /PH60
1
1
1
/PD65 /PD64 /PD63
1
1
1
 33
EM78P151
8-Bit Microcontroller
6.7.3
Status of T and P of the Status Register
A Reset condition is initiated by the following events
1) A power-on condition
2) A high-low-high pulse on /RESET pin
3) Watchdog timer time-out
The values of T and P listed in the table below are used to check how the processor
wakes up.
Table 6-2 Values of RST, T, and P after a Reset
Reset Type
RST
T
P
Power on
0
1
1
/RESET during Operating mode
0
*P
*P
/RESET wake-up during Sleep mode
0
1
0
WDT during Operating mode
0
0
*P
WDT wake-up during Sleep mode
0
0
0
Wake-up on pin change during Sleep mode
1
1
0
* P: Previous status before reset
The following table shows the events that may affect the status of T and P.
Table 6-3 Status of T and P Being Affected by Events
Event
RST
T
P
Power on
0
1
1
WDTC instruction
*P
1
1
WDT time-out
0
0
*P
SLEP instruction
*P
1
0
Wake-up on pin change during Sleep mode
1
1
0
* P: Previous status before reset
34 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
VDD
D
Q
CLK
CLR
Oscillator
CLK
Power-on
Reset
Voltage
Detector
WDTE
WDT
WDT
Timeout
Setup Time
RESET
/RESET
Figure 6-8 Controller Reset Block Diagram
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 35
EM78P151
8-Bit Microcontroller
6.8
Interrupt
The EM78P151 has three falling-edge interrupts as listed herewith:
1) TCC overflow interrupt
2) Port 6 Input Status Change Interrupt
3) External interrupt [(P60, /INT) pin]
Before the Port 6 Input Status Changed Interrupt is enabled, reading Port 6 (e.g.
"MOV R6, R6") is necessary. Each pin of Port 6 will have this feature if its status
changes. Any pin configured as output or P60 pin configured as /INT is excluded from
this function. The Port 6 Input Status Changed Interrupt can wake up the EM78P151
from Sleep mode if Port 6 is enabled prior to going into Sleep mode by executing
SLEP instruction. When the chip wakes-up, the controller will continue to execute the
program in-line if the global interrupt is disabled. If the global interrupt is enabled, it
will branch to the interrupt Vector 008H.
RF is the interrupt status register that records the interrupt requests in the relative
flags / bits. IOCF is an interrupt mask register. The global interrupt is enabled by the
ENI instruction and is disabled by the DISI instruction. When one of the interrupts
(enabled) occurs, the next instruction will be fetched from Address 008H. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the
flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine before interrupts are enabled to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or the execution of ENI. Note that the outcome of RF will be the
logic AND of RF and IOCF (refer to Figure 6-9). The RETI instruction ends the
interrupt routine and enables the global interrupt (the execution of ENI).
When an interrupt is generated by the INT instruction (enabled), the next instruction
will be fetched from Address 001H.
36 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
VCC
D P
R Q
CLK _
C Q
L
RF
/IRQn
/RESET
IRQn
RFRD
INT
IRQm
ENI/DISI
IOCF
Q
_
Q
P
R D
CLK
C
L
IOD
IOCFWR
IOCFRD
RFWR
Figure 6-9 Interrupt Input Circuit
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 37
EM78P151
8-Bit Microcontroller
6.9 Oscillator
6.9.1
Oscillator Modes
The EM78P151 can be operated in four different oscillator modes, such as External RC
oscillator mode (ERC), Internal RC oscillator mode (IRC), High Crystal oscillator mode
(HXT), and Low Crystal oscillator mode (LXT). The desired mode can be selected by
programming OSC2 ~ OSC0 in the Code Option register. Table 6-4 describes how these
oscillator modes are defined.
Table 6-4 Oscillator Modes Defined by OSC
Oscillator Modes
RCOUT
OSC1
OSC0
LXT (Low crystal oscillator mode, Freq. range is over 400 kHz)
x
0
0
HXT (High crystal oscillator mode, Freq. range is above 400 kHz)
x
0
1
1
0
1
0
1
ERC (External RC oscillator mode); P64/RCOUT act as P64
ERC (External RC oscillator mode); P64/RCOUT act as RCOUT
1
1
0
2
0
1
1
2
1
1
1
IRC (Internal RC oscillator mode); P64/RCOUT act as P64
IRC (Internal RC oscillator mode); P64/RCOUT act as RCOUT
1
2
In ERC mode, ERCin is used as oscillator pin. RCOUT/P64 is defined by code option Word 1 Bits 3 ~ 1.
In IRC mode, P64 is normal I/O pin. RCOUT/P64 is defined by code option Word 1 Bits 3 ~ 1.
The maximum operational frequency of the crystal/resonator under different V DD is listed
below.
Table 6-5 Summary of Maximum Operating Speeds
Conditions
Two cycles with two clocks
6.9.2
VDD
Max Freq. (MHz)
2.3
4.0
3.0
8.0
5.0
20.0
Crystal Oscillator/Ceramic Resonators (Crystal)
The EM78P151 can be driven by an external clock signal through the OSCI pin as
shown in the following figure.
OSCI
Ext. Clock
OSCO
Figure 6-10 Circuit for External Clock Input
38 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
In most applications, pin OSCI and pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation. Figure 6-11 depicts such a circuit. The
same thing applies whether it is in the HXT mode or in the LXT mode.
In Figure 6-11-1, when the connected resonator in OSCI and OSCO is used in
applications, the 1 M R1 needs to be shunted with resonator.
C1
OSCI
Crystal
OSCO
RS
C2
Figure 6-11 Circuit for Crystal/Resonator
C1
OSCI
Resonator
R1
OSCO
C2
Figure 6-11-1 Circuit for Crystal/Resonator
The following table provides the recommended values of C1 and C2. Since each
resonator has its own attribute, refer to its specification for appropriate values of C1
and C2. RS, a serial resistor, may be necessary for the AT strip cut crystal or low
frequency mode.
Table 6-6 Capacitor Selection Guide for Crystal Oscillator or Ceramic
Resonator
Oscillator Type
Ceramic Resonators
Frequency
Mode
HXT
LXT
Crystal Oscillator
HXT
Frequency
C1 (pF)
C2 (pF)
455 kHz
2.0 MHz
4.0 MHz
32.768 kHz
100 kHz
200 kHz
455 kHz
1.0 MHz
2.0 MHz
4.0 MHz
100 ~ 150
20 ~ 40
10 ~ 30
25
25
25
20 ~ 40
15 ~ 30
15
15
100 ~ 150
20 ~ 40
10 ~ 30
15
25
25
20 ~ 150
15 ~ 30
15
15
Note: The values of capacitors C1 and C2 are for reference only
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 39
EM78P151
8-Bit Microcontroller
6.9.3
External RC Oscillator Mode
For some applications that do not require a very precise timing calculation, the RC
oscillator (Figure 6-12) offers a cost-effective oscillator configuration. Nevertheless, it
should be noted that the frequency of the RC oscillator is influenced by the supply
voltage, the values of the resistor (REXT), the capacitor (CEXT), and even by the
operation temperature. Moreover, the frequency also changes slightly from one chip
to another due to manufacturing process variations.
In order to maintain a stable system frequency, the values of the CEXT should not be
lesser than 20pF, and that the value of REXT should not be greater than 1 M. If they
cannot be kept in this range, the frequency can be easily affected by noise, humidity,
and leakage.
The smaller the REXT in the RC oscillator is, the faster its frequency will be. On the
contrary, for very low REXT values, for instance, 1 k, the oscillator becomes unstable
because the NMOS cannot discharge the current of the capacitance correctly.
Based on the above reasons, it must be kept in mind that all of the supply voltage, the
operation temperature, the components of the RC oscillator, the package types, the
way the PCB is layout, will affect the system frequency.
Vcc
REXT
OSCI
CEXT
Figure 6-12 External RC Oscillator Mode Circuit
Table 6-7 RC Oscillator Frequencies
CEXT
20 pF
100 pF
300 pF
40 
REXT
Average FOSC
5V, 25C
Average FOSC
3V, 25C
3.3 kΩ
5.1 kΩ
10 kΩ
100 kΩ
3.3 kΩ
5.1 kΩ
10 kΩ
100 kΩ
3.3 kΩ
3.92 MHz
2.67 MHz
1.4 MHz
150 kHz
1.4 MHz
940 kHz
476 kHz
50 kHz
595 kHz
3.65 MHz
2.60 MHz
1.40 MHz
156 kHz
1.33 MHz
917 kHz
480 kHz
52 kHz
570 kHz
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
REXT
Average FOSC
5V, 25C
Average FOSC
3V, 25C
5.1 kΩ
10 kΩ
100 kΩ
400 kHz
200 kHz
20.9 kHz
384 kHz
203 kHz
20 kHz
CEXT
1
Note: : These are measured in DIP packages
6.9.4
2
. The values are for design reference only
3
. The frequency drift is  30%
Internal RC Oscillator Mode
EM78P151 offers a versatile internal RC mode with default frequency value of 4 MHz.
The Internal RC oscillator mode has other frequencies (1 MHz, 8 MHz and 455 kHz)
that can be set by Code Option (Word 1), RCM1, and RCM0. All these four main
frequencies can be calibrated by programming the Option Bits CT0 ~ CT3, RT0 ~
RT3. The table below describes the EM78P151 internal RC drift with variation of
voltage, temperature, and process.
Table 6-8 Internal RC Drift Rate (TA = 25C, VDD = 5V, VSS = 0V)
Drift Rate
Internal RC
Freq.
Temp. (0C ~ 70C)
Voltage
Process
Total
4 MHz
± 1.5%
± 1% @ 2.0V ~ 5.5V
± 1%
± 3.5%
8 MHz
± 1.5%
± 1.5% @ 2.0V ~ 5.5V
± 1%
± 4%
1 MHz
± 1.5%
± 1% @ 2.0V ~ 5.5V
± 1%
± 3.5%
455 kHz
± 1.5%
± 1% @ 2.0V ~ 5.5V
± 1%
± 3.5%
Note: These are theoretical values provided for reference only. Actual values may vary
depending on the actual process.
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 41
EM78P151
8-Bit Microcontroller
6.10
Power-on Considerations
Any microcontroller is not guaranteed to start to operate properly before the power
supply stabilizes at its steady state. Under customer application, when power is OFF,
VDD must drop to below 1.8V and remains OFF for 10 µs before power can be
switched ON again. This way, the EM78P151 will reset and operate normally. The
extra external reset circuit will work well if VDD can rise at very fast speed (50ms or
less). However, under most cases where critical applications are involved, extra
devices are required to assist in solving the power-up problems.
6.10.1 Programmable Oscillator Set-up Time
The Option word contains SUT0 and SUT1 which can be used to define the oscillator
set-up time. Theoretically, the range is from 4.5ms to 72ms. For most of crystal or
ceramic resonators, the lower the operation frequency, the longer the Set-up time
may be required. Table 12 describes the values of the Oscillator Set-up Time.
6.10.2 External Power-on Reset Circuits
The circuitry in the figure implements an external RC to produce the reset pulse. The
pulse width (time constant) should be kept long enough for VDD to reach minimum
operation voltage. This circuit is used when the power supply has a slow rise time.
Vdd
R
/RESET
D
Rin
C
Figure 6-13 External Power-up Reset Circuit
Since the current leakage from the /RESET pin is  5 A, it is recommended that R
should not be greater than 40k. In this way, the /RESET pin voltage is held below
0.2V. The diode (D) acts as a short circuit at the moment of power down. The
capacitor C will discharge rapidly and fully. RIN, the current-limited resistor, will
prevent high current or ESD (electrostatic discharge) from flowing to pin /RESET.
6.10.3 Residue-Voltage Protection
When the battery is replaced, the device power (VDD) is cut off but residue-voltage
remains. The residue-voltage may trip below the minimum VDD, but not to zero. This
condition may cause a poor power-on reset. The following figures illustrate two
recommended methods on how to build a residue-voltage protection circuit for the
EM78P151.
42 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
Vdd
Vdd
33K
Q1
10K
/RESET
100K
1N4684
Figure 6-14 Residue Voltage Protection Circuit 1
Vdd
Vdd
R1
Q1
/RESET
R2
R3
Figure 6-15 Residue Voltage Protection Circuit 2
Note
Figure 6-14 and Figure 6-15 should be designed to ensure that the voltage of the
/RESET pin is larger than VIH (min).
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 43
EM78P151
8-Bit Microcontroller
6.11
Code Option
The EM78P151 has three Code option words and one Customer ID word that are not
part of the normal program memory.
Word 0
Word1
Word 2
Word 3
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
6.11.1 Code Option Register (Word 0)
Word 0
Bit
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 ~ 0
Mnemonic
RESETEN
ENWDT
CLKS0
LVR1
LVR0
-
WDTPS1
WDTPS0
WDTPS
CLKS1
Protect
1
Disable
Disable
High
High
High
-
High
High
High
High
Disable
0
Enable
Enable
Low
Low
Low
-
Low
Low
Low
Low
Enable
Bit 12 (RESETEN): Define Pin 63 as a reset pin
0: /RESET enable (only Schmitt trigger)
1: /RESET disable
Bit 11 (ENWDT): Watchdog timer enable bit
0: Enable
1: Disable
Bit 10 (CLKS0): Instruction period option bit.
Refer to the Instruction Set section.
CLKS1
CLKS0
Instruction Period
1
1
Fosc/4
1
0
Fosc/2
0
1
Fosc/8
0
0
Fosc/8
Bits 9 ~ 8 (LVR1 ~ LVR0): Low Voltage Reset control bits
LVR1, LVR0
11
VDD Reset Level
VDD Release Level
NA (Power-on Reset) (default)
10
2.7V
2.9V
01
3.5V
3.7V
00
4.0V
4.2V
Refer to the Instruction Set section.
Bit 7: Not used, set it to “1” all the time.
44 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
Bits 6 ~ 4 (WDTPS1, WDTPS0, WDTPS): WDT Time-out Period of device bits.
Warm up time from
/RESET, WDTO
Condition: IRC, ERC
Warm up time from
/RESET, WDTO
Condition: XT
*WDT Time-out
Period or
Warm up time
from POR, LVR
Condition: XT
WDTPS1
WDTPS0
WDTPS
Warm up time from
POR, LVR
Condition: IRC, ERC
1
1
1
18 ms
IRC or ERC *8 clocks
1
0
1
4.5 ms
IRC or ERC *8 clocks
0
1
1
288 ms
IRC or ERC *8 clocks
HXT * 510
LXT * 254
288 ms
0
0
1
72 ms
IRC or ERC *8 clocks
HXT * 510
LXT * 254
72 ms
HXT * 510
LXT * 254
HXT * 510
LXT * 254
18 ms
4.5 ms
Note: These are theoretical values, provided for reference only
Bit 3 (CLKS1): Instruction period option bit ii.
Refer to the Instruction Set section.
CLKS1
CLKS0
Instruction period
1
1
Fosc/4
1
0
Fosc/2
0
1
Fosc/8
0
0
Fosc/8
Bits 2 ~ 0 (Protect): Protect Bits. Each protect status is as follows:
Protect Bits
Protect
0
Enable
1
Disable (Default)
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 45
EM78P151
8-Bit Microcontroller
6.11.2 Code Option Register (Word 1)
Word 1
Bit
Bit 12
Mnemonic
-
1
0
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
KTYPE DisSMT
EnSMT
ENHS
-
RCM1
RCM0
-
RCOUT
OSC1
OSC0
-
-
Type A
Schmitt
Inverter
Normal
-
High
High
-
High
High
High
-
-
Type B
Inverter
Schmitt
Enhance
-
Low
Low
-
Low
Low
Low
-
Bit 12: Not used, set to “0” all the time.
Bit 11 (KTYPE): Kernel type selection
0: Type B
1: Type A (default)
KTYPE = 0
KTYPE = 1
Reset Address
0X3FF
0X000
S/W Interrupt Vector
0x002
0x001
ENHS=1, A8,A9 =0
ENHS=0, "ADD R2, A" allows a
PC: A8, A9
Any instruction written to
A8, A9 from PCHBUF bit1,0
relative address to be added to the
current PC, and the ninth and
R2
above bits of the PC will increase
progressively.
CONT BIT6
INTEG
/INT
IOCF/RE BIT7
/INT
General purpose register
IIWK65~IIWK60 ( Input Change
R9 BIT5~0
Interrupt/Wake-up)
PC9BUF~PC8BUF (buffer of
RA BIT1~0
Program Counter Bits 9,8)
General purpose register
General purpose register
Bit 10 (DISSMT): P60~P62, P63 Schmitt trigger disable
0: Inverter
1: Schmitt trigger
Bit 9 (ENSMT): P64 and P65 Schmitt trigger enable
0: Schmitt trigger
1: Inverter
46 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
Bit 8 (ENHS): Function Enhance selection
0: Enhance mode.
A. 6 pin Pull-low function (/PD60 ~ /PD65)
B. "ADD R2, A" allows a relative address to be added to the current
PC, and the ninth and above bits of the PC will increase
progressively.
1: Normal mode.
A. 3 pin Pull-low function (/PD60 ~ /PD62).
B. Any instruction written to R2 (e.g. “ADD R2, A”, "MOV R2, A",
"BC R2, 6",) will cause the ninth bit and the tenth bit (A8 ~ A9)
of the PC to be cleared. Hence, the computed jump is limited to
the first 256 locations of a page
ENHS = 0
PC A9, A8
ENHS = 1
"ADD R2, A" allows a relative
address to be added to the
Any instruction written to R2 will
current PC, and the ninth and
cause the ninth and the tenth bit
above bits of the PC will
(A8 ~ A9) of the PC to be cleared.
increase progressively.
R8/IOCE Bits 2~0
/PD65~PD63: Enable
Pull-down function.
RB/IOCB Bits 6~4
General purpose register
/PD62~PD60: Enable Pull-down function
Bit 7: Not used, set to “1” all the time.
Bits 6 ~ 5 (RCM1, RCM0): RC mode selection bits
RCM 1
RCM 0
*Frequency (MHz)
1
1
4
1
0
8
0
1
1
0
0
455 kHz
* Theoretical values, for reference only
Bit 4: Not used, set to “1” all the time.
Bit 3 (RCOUT): Selection bit of Oscillator output or I/O port
0: P64
1: OSCO
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 47
EM78P151
8-Bit Microcontroller
Bits 2 ~ 1 (OSC1 and OSC0): Oscillator Mode Select bits
Mode
OSC1 OSC0
LXT (Low crystal oscillator mode, Freq. range is below 400 kHz)
0
0
HXT (High crystal oscillator mode, Freq. range is above 400 kHz)
0
1
ERC (External RC oscillator mode)
1
0
IRC (Internal RC oscillator mode)
1
1
Oscillator Modes
RCOUT OSC1 OSC0
LXT (Low crystal oscillator mode, Freq. range is over 400 kHz)
x
0
0
HXT (High crystal oscillator mode, Freq. range is above 400 kHz)
x
0
1
1
0
1
0
1
ERC (External RC oscillator mode); P64/RCOUT act as P64
ERC (External RC oscillator mode); P64/RCOUT act as RCOUT
1
1
0
2
0
1
1
2
1
1
1
IRC (Internal RC oscillator mode); P64/RCOUT act as P64
IRC (Internal RC oscillator mode); P64/RCOUT act as RCOUT
1
In ERC mode, ERCin is used as oscillator pin. RCOUT/P64 is defined by code option Word 1
Bits 3 ~ Bit 1.
2
In IRC mode, P64 is normal I/O pin. RCOUT/P64 is defined by code option Word 1 Bits 3 ~ 1.
Bit 0: Not used, set it to “1” all the time.
6.11.3 Customer ID Register (Word 2)
Word 2
Bit 12 Bit 11 Bit 10 Bit 9



Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0










Customer’s ID code
Bits 12 ~ 0:
6.11.4 Code Option Register (Word 3)
Word 3
Bit
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
-
HLP
PSS
-
-
CT3
CT2
CT1
CT0
RT3
RT2
RT1
RT0
1
-
High
Int.
Vref
-
-
High
High
High
High
High
High
High
High
0
-
Low
VDD
-
-
Low
Low
Low
Low
Low
Low
Low
Low
Bit 12: Not used, set to “1” all the time.
Bit 11 (HLP): Power Consumption Selection
0: Low power consumption, apply to working frequency at 4 MHz or below
4 MHz
1: High power consumption, apply to working frequency above 4 MHz
48 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
Bit 10 (PSS): Power Source Selection
0: VDD
1: Internal voltage reference
Bits 9 ~ 8: Not used, set to “1” all the time.
Bits 7 ~ 4 (CT3 ~ CT0): Internal RC mode Capacitance Trim bits (Coarse Calibration).
These bits must always be set to “1” only (auto calibration).
Trimming Code
CLK Period
Frequency
CT[3]
CT[2]
CT[1]
CT[0]
0
0
0
0
Period*(1+40%)
F*(1-28.57%)
0
0
0
1
Period*(1+35%)
F*(1-25.93%)
0
0
1
0
Period*(1+30%)
F*(1-23.08%)
0
0
1
1
Period*(1+25%)
F*(1-20.00%)
0
1
0
0
Period*(1+20%)
F*(1-16.67%)
0
1
0
1
Period*(1+15%)
F*(1-13.04%)
0
1
1
0
Period*(1+10%)
F*(1-9.09%)
0
1
1
1
Period*(1+5%)
F*(1-4.76%)
1
1
1
1
Period (default)
F (default)
1
1
1
0
Period*(1-5%)
F*(1+5.26%)
1
1
0
1
Period*(1-10%)
F*(1+11.11%)
1
1
0
0
Period*(1-15%)
F*(1+17.65%)
1
0
1
1
Period*(1-20%)
F*(1+25.00%)
1
0
1
0
Period*(1-25%)
F*(1+33.33%)
1
0
0
1
Period*(1-30%)
F*(1+42.86%)
1
0
0
0
Period*(1-35%)
F*(1+53.85%)
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 49
EM78P151
8-Bit Microcontroller
Bits 3 ~ 0 (RT3 ~ RT0): Internal RC mode Resistance Trim bits (Fine Calibration).
These bits must always be set to “1” only (auto calibration).
Trimming Code
CLK Period
50 
Frequency
RT[3]
RT[2]
RT[1]
RT[0]
0
0
0
0
Period*(1+8%)
F*(1-7.41%)
0
0
0
1
Period*(1+7%)
F*(1-6.54%)
0
0
1
0
Period*(1+6%)
F*(1-5.66%)
0
0
1
1
Period*(1+5%)
F*(1-4.76%)
0
1
0
0
Period*(1+4%)
F*(1-3.85%)
0
1
0
1
Period*(1+3%)
F*(1-2.91%)
0
1
1
0
Period*(1+2%)
F*(1-1.96%)
0
1
1
1
Period*(1+1%)
F*(1-0.99%)
1
1
1
1
Period (default)
F (default)
1
1
1
0
Period*(1-1%)
F*(1+1.01%)
1
1
0
1
Period*(1-2%)
F*(1+2.04%)
1
1
0
0
Period*(1-3%)
F*(1+3.09%)
1
0
1
1
Period*(1-4%)
F*(1+4.17%)
1
0
1
0
Period*(1-5%)
F*(1+5.26%)
1
0
0
1
Period*(1-6%)
F*(1+6.38%)
1
0
0
0
Period*(1-7%)
F*(1+7.53%)
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
6.12
Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single
instruction cycle (one instruction consists of 2 oscillator time periods), unless the
program counter is changed by instructions "MOV R2,A," "ADD R2,A," or by
instructions of arithmetic or logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6,"
"CLR R2," etc.).
In addition, the instruction set has the following features:
1. Every bit of any register can be set, cleared, or tested directly.
2. The I/O registers can be regarded as general registers. That is, the same
instruction can operate on I/O registers.
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 51
EM78P151
8-Bit Microcontroller
 EM78P151 Instruction Set Table:
The following symbols are used in the table:
“R” Register designator that specifies which one of the registers (including operation and
general purpose registers) is to be utilized by the instruction.
“B” Bit field designator that selects the value for the bit located in the register R and which
affects the operation.
“k” 8 or 10-bit constant or literal value
Mnemonic
52 
Operation
Status Affected
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
RETI
CONTR
IOR R
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
No Operation
Decimal Adjust A
A  CONT
0  WDT, Stop oscillator
0  WDT
A  IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack]  PC
[Top of Stack]  PC, Enable Interrupt
CONT  A
IOCR  A
AR
0A
0R
R-A  A
R-A  R
R-1  A
R-1  R
None
C
None
T, P
T, P
1
None
None
None
None
None
None
1
None
None
Z
Z
Z, C, DC
Z, C, DC
Z
Z
OR A,R
A  VR  A
Z
OR R,A
A  VR  R
Z
AND A,R
A&RA
Z
AND R,A
A&RR
Z
XOR A,R
ARA
Z
XOR R,A
ARR
Z
ADD A,R
A+RA
Z, C, DC
ADD R,A
A+RR
Z, C, DC
MOV A,R
RA
Z
MOV R,R
RR
Z
COMA R
/R  A
Z
COM R
/R  R
Z
INCA R
R+1  A
Z
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
(Continuation)
Mnemonic
Operation
Status Affected
INC R
R+1  R
DJZA R
R-1  A, skip if zero
None
DJZ R
R-1  R, skip if zero
None
RRCA R
R(n)  A(n-1), R(0)  C, C  A(7)
C
RRC R
R(n)  R(n-1), R(0)  C, C  R(7)
C
RLCA R
R(n)  A(n+1), R(7)  C, C  A(0)
C
RLC R
R(n)  R(n+1), R(7)  C, C  R(0)
C
SWAPA R
R(0-3)  A(4-7), R(4-7)  A(0-3)
None
SWAP R
R(0-3)  R(4-7)
None
JZA R
R+1  A, skip if zero
None
JZ R
R+1  R, skip if zero
None
BC R,b
0  R(b)
None
2
BS R,b
1  R(b)
None
3
JBC R,b
if R(b)=0, skip
None
JBS R,b
if R(b)=1, skip
None
CALL k
PC+1  SP, k  PC
None
JMP k
k  PC
None
MOV A,k
kA
None
OR A,k
AkA
Z
AND A,k
A&kA
Z
XOR A,k
AkA
Z
RETL k
k  A, [Top of Stack]  PC
SUB A,k
k-A  A
INT
PC + 1  [SP], 001H  PC
Decimal Adjust A after either
DAS
subtraction operation
ADC A,R
ADC A,R
R+A+CA
r = 0x00~0x1F
R+A+CA
r = 0x20~0x3F
Z
None
Z, C, DC
None
C
Z, C, DC
Z, C, DC
ADC R,A
R+A+CR
Z, C, DC
SBC A,R
R+A+CA
Z, C, DC
SBC R,A
R+A+CR
Z, C, DC
ADD A,k
k+A  A
Z, C, DC
1
Note: This instruction is applicable to IOC5 ~ IOC6, IOCB ~ IOCF only.
2
This instruction is not recommended for RF operation.
3
This instruction cannot operate under RF.
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 53
EM78P151
8-Bit Microcontroller
7
Absolute Maximum Ratings
Items
8
Rating
Temperature under bias
-40C
to
85C
Storage temperature
-65C
to
150C
Input voltage
Vss-0.3V
to
Vdd+0.5V
Output voltage
Vss-0.3V
to
Vdd+0.5V
Working Voltage
2.0V
to
5.5V
Working Frequency
DC
to
20 MHz
DC Electrical Characteristics
 Ta = 25C, VDD = 5.0V, VSS = 0V
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Two cycles with two clocks
Two cycles with two clocks
Two cycles with two clocks
R: 5 k, C: 39 pF
VIN = VDD, VSS
DC
DC
DC
F30




1500

4.0
8.0
20.0
F30
1
MHz
MHz
MHz
kHz
A
Port 6
1.52

VDD+0.3
V
Port 6
VSS 0.3

1.12
V
Port 6
1.52

VDD+0.3
V
Port 6
VSS 0.3

1.52
V
VIHT1
Crystal: VDD to 2.3V
Crystal: VDD to 3V
Crystal: VDD to 5V
ERC: VDD to 5V
Input Leakage Current for Input Pins
Input High Voltage (VDD = 5V)
(P60 ~P62,P64~P65 are Schmitt trigger)
Input Low Voltage (VDD = 5V)
(P60 ~P62,P64~P65 are Schmitt trigger)
Input High Voltage (VDD = 5V)
(P60 ~P65 are inverter trigger)
Input Low Voltage (VDD = 5V)
(P60 ~P65 are inverter trigger)
Input High Threshold Voltage (VDD = 5V)
/RESET, TCC (Schmitt trigger)
1.8

VDD+0.3
V
VILT1
Input Low Threshold Voltage (VDD = 5V)
/RESET, TCC (Schmitt trigger)
VSS - 0.3

1.1
V
Port 6
1.35

VDD+0.3
V
Port 6
VSS - 0.3

0.55
V
Port 6
1.35

VDD+0.3
V
Port 6
VSS - 0.3

1.35
V
OSCI
1.52

VDD+0.3
V
FXT
ERC
IIL
VIH0
VIL0
VIH1
VIL1
VIH2
VIL2
VIH3
VIL3
VIHX2
Input High Voltage (VDD = 3V)
(P60 ~P62, P64~P65 are Schmitt trigger)
Input Low Voltage (VDD = 3V)
(P60 ~P62,P64~P65 are Schmitt trigger)
Input High Voltage (VDD = 3V)
(P60 ~P65 are inverter trigger)
Input Low Voltage (VDD = 3V)
(P60 ~P65 are inverter trigger)
Clock Input High Voltage (VDD = 3V)
VILX2
Clock Input Low Voltage (VDD = 3V)
OSCI
VSS - 0.3

1.12
V
VOH1
VOH2
VOL1
VOL2
IPH
IPD
Output High Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage
Pull-High Current
Pull-Down Current
IOH = -13 mA
IOH = -6 mA
IOL = 14.5 mA
IOL = 20 mA
Pull-high active, input pin at VSS
Pull-down active, input pin at VDD
2.4
3.6


-45
15




-60
30


0.4
0.6
-75
45
V
V
V
V
A
A
54 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
Symbol
Parameter
ISB1
Power Down Current
ISB2
Power Down Current
ICC1
Operating Supply Current
at Two Clocks (VDD = 3V)
ICC2
Operating Supply Current
at Two Clocks (VDD = 3V)
ICC3
Operating Supply Current
at Two Clocks (VDD = 5.0V)
ICC4
Operating Supply Current
at Two Clocks (VDD = 5.0V)
Condition
All input and I/O pins at VDD,
Output pin floating, WDT disabled
All input and I/O pins at VDD,
Output pin floating, WDT enabled
/RESET = 'High', FOSC = 32kHz
(XTAL type, CLKS[1:0] = "10"),
Output pin floating, WDT disabled
/RESET = 'High', FOSC = 32kHz
(XTAL type, CLKS[1:0] = "10"),
Output pin floating, WDT enabled
/RESET = 'High', FOSC = 4 MHz
(Crystal type, CLKS[1:0) = "10"),
Output pin floating
/RESET = 'High', FOSC = 10 MHz
(XTAL type, CLKS[1:0] = "10"),
Output pin floating
Min.
Typ.
Max.
Unit
-
-
1
A
-
5
10
A
-
15
30
A
-
19
35
A
-
-
2.0
mA
-
-
4.0
mA
 Internal RC Electrical Characteristics
(Ta = 25C, VDD = 5.0V, VSS = 0V)
Internal RC
Drift Rate
Temperature
Voltage
Min.
Typ.
Max.
4 MHz
25C
5V
3.96 MHZ
4 MHz
4.04 MHz
8 MHz
25C
5V
7.88 MHz
8 MHz
8.12 MHz
1 MHz
25C
5V
0.9 MHz
1 MHz
1.1 MHz
455kHz
25C
5V
450.45 kHz
455 kHz
459.55 kHz
 Internal RC Electrical Characteristics
(Ta = 0 ~ 70C, VDD = 2 ~ 5.5V, VSS = 0V)
Internal RC
Drift Rate
Temperature
Voltage
Min.
Typ.
Max.
4 MHz
0 ~ 70C
2 ~ 5.5V
3.86 MHz
4 MHz
4.14 MHz
8 MHz
0 ~ 70C
2 ~ 5.5V
7.68 MHz
8 MHz
8.32 MHz
1 MHz
0 ~ 70C
2 ~ 5.5V
0.65 MHz
1 MHz
1.35 MHz
455 kHz
0 ~ 70C
2 ~ 5.5V
439.075 kHz
455 KHz
470.925 kHz
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 55
EM78P151
8-Bit Microcontroller
9
AC Electrical Characteristics
 Ta=25C, VDD=5V  5%, VSS=0V
Symbol
Parameter
Conditions
Min.
Type
Max.
Unit
Dclk
Input CLK duty cycle

45
50
55
%
Tins
Instruction cycle time
(CLKS="0")
Crystal type
100

DC
ns
RC type
500

DC
ns
Ttcc
TCC input time period



ns
Tdrh
Device reset hold time
Ta = 25C
11.3
16.2
21.6
ms
Trst
/RESET pulse width
Ta = 25C
2000


ns
Twdt
Watchdog timer duration
Ta = 25C
11.3
16.2
21.6
ms
Tset
Input pin setup time


0

ns
Thold
Input pin hold time

15
20
25
ns
Tdelay
Output pin delay time
Cload = 20 pF
45
50
55
ns
ERC delay time
Ta = 25C
1
3
5
ns
Tdrc
(Tins+20)  N*
*N = Selected prescaler ratio
56 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
10 Timing Diagrams
 AC Test Input / Output Waveform
VDD-0.5V
0.75 VDD
0.75 VDD
TEST POINTS
0.25VDD
0.25VDD
GND+0.5V
Note: AC Testing: Input is driven at VDD-0.5V for logic “1”, and GND+0.5V for logic “0”
Timing measurements are made at 0.75VDD for logic “1”, and 0.25VDD for logic “0”
Figure 10-1a AC Test Input / Output Waveform Timing Diagram
 Reset Timing (CLK = 0)
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
Figure 10-1b Reset Timing Diagram
 TCC Input Timing (CLKS = 0)
ins
CLK
TCC
tcc
Figure 10-1c TCC Input Timing Diagram
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 57
EM78P151
8-Bit Microcontroller
APPENDIX
A Ordering and Manufacturing Information
EM78P151D8J
Material Type
J: RoHS complied
Pin Number
Package Type
D: DIP
SO: SOP
ST: SOT
Product Number
Product Type
P: OTP
Elan 8-bit Product
‧‧‧‧‧‧‧
EM78Paaaa
1041 bbbbbb
‧‧‧‧‧‧‧
58 
Elan Product Number
Batch Number
Date of Manufacture
“YYWW”
YY is year and WW is week
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
B Package Type
OTP MCU
Package Type
Pin Count
Package Size
EM78P151D8J
DIP
8
300 mil
EM78P151SO8J
SOP
8
150 mil
EM78P151ST6J
SOT23-6
6
-
(For product code “J”)
These are Green products that comply with RoHS specifications.
Part No.
Electroplate type
Ingredient (%)
Melting point (C)
EM78P151D8J
EM78P151SO8J
EM78P151ST6J
Pure Tin
Sn: 100%
232C
Electrical resistivity (-cm)
11.4
Hardness (hv)
8~10
Elongation (%)
50%
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 59
EM78P151
8-Bit Microcontroller
C Packaging Configurations
C.1 8-Lead Plastic Dual in-line (DIP) － 300 mil
Figure C-1 EM78P151 8-Pin DIP (300 mil) Package Type
C.2
8-Lead Small Outline Package (SOP) － 150 mil
Figure C-2 EM78P151 8-Pin SOP (150 mil) Package Type
60 
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
EM78P151
8-Bit Microcontroller
C.3 6-Lead Small Outline Transistor Plastic Package (SOT)
Figure C-3 EM78P151 8-Pin SOT23-6 Package Type
Product Specification (V1.0) 12.29.2014
(This specification is subject to change without prior notice)
 61