Data Sheet(eng)

EM78P153A
8-Bit Microcontroller
with OTP ROM
Product
Specification
DOC. VERSION 1.3
ELAN MICROELECTRONICS CORP.
April 2011
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2008~2011 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
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or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
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Hsinchu, TAIWAN 308
Tel: +886 3 563-9977
Fax: +886 3 563-9966
[email protected]
http://www.emc.com.tw
Elan (HK) Microelectronics
Corporation, Ltd.
Flat A, 19F., World Tech Centre
95 How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
Fax: +852 2723-7780
Elan Information
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Cupertino, CA 95015
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Tel: +1 408 366-8225
Fax: +1 408 366-8225
Korea:
Shenzhen:
Shanghai:
Elan Korea Electronics
Company, Ltd.
Elan Microelectronics
Shenzhen, Ltd.
Elan Microelectronics
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CHINA 201203
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Fax: +86 21 5080-0273
[email protected]
Contents
Contents
1
2
3
4
General Description .................................................................................................. 1
Features ..................................................................................................................... 1
Pin Assignment ......................................................................................................... 2
Pin Description.......................................................................................................... 3
5
4.1 EM78P153AD14/SO14 ...................................................................................... 3
Functional Description ............................................................................................. 4
5.1
Operational Registers......................................................................................... 4
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.2
R0 (Indirect Addressing Register) .......................................................................4
R1 (Timer Clock /Counter) ..................................................................................4
R2 (Program Counter) and Stack........................................................................5
R3 (Status Register) ............................................................................................7
R4 (RAM Select Register)...................................................................................7
R5 ~ R6 (Port 5 ~ Port 6) ....................................................................................7
RF (Interrupt Status Register) .............................................................................8
R10 ~ R2F ...........................................................................................................8
Special Function Registers................................................................................. 9
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
A (Accumulator)...................................................................................................9
CONT (Control Register).....................................................................................9
IOC5 ~ IOC6 (I/O Port Control Register) ............................................................9
IOCB (Pull-down Control Register) ...................................................................10
IOCC (Open-drain Control Register).................................................................10
IOCD (Pull-high Control Register).....................................................................10
IOCE (WDT Control Register) ...........................................................................11
IOCF (Interrupt Mask Register).........................................................................12
5.3
TCC/WDT and Prescaler.................................................................................. 13
5.4
I/O Ports ........................................................................................................... 13
5.5
Reset and Wake-up.......................................................................................... 17
5.5.1
5.5.2
5.5.3
Reset .................................................................................................................17
Summary of Registers Initialized Values...........................................................19
Status of RST, T, and P of the Status Register..................................................21
5.6
Interrupt ............................................................................................................ 22
5.7
Oscillator .......................................................................................................... 23
5.7.1
5.7.2
5.7.3
5.7.4
Oscillator Modes................................................................................................23
Crystal Oscillator/Ceramic Resonators (Crystal)...............................................24
External RC Oscillator Mode.............................................................................25
Internal RC Oscillator Mode ..............................................................................27
Product Specification (V1.3) 04. 22.2011
• iii
Contents
5.8
Code Option Register....................................................................................... 27
5.8.1
5.9
Code Option Register (Word 0).........................................................................27
Power-on Considerations ................................................................................. 29
5.10 Programmable Oscillator Set-up Time ............................................................. 29
5.11 External Power-on Reset Circuit ...................................................................... 30
5.12 Residue-Voltage Protection .............................................................................. 30
6.
7
8
5.13 Instruction Set .................................................................................................. 31
Timing Diagrams ..................................................................................................... 34
Absolute Maximum Ratings ................................................................................... 35
Electrical Characteristics ....................................................................................... 35
8.1
DC Characteristics ........................................................................................... 35
8.2
AC Characteristics............................................................................................ 36
APPENDIX
A
B
C
Package Type........................................................................................................... 50
Package Information............................................................................................... 51
Application Notes.................................................................................................... 51
Specification Revision History
Doc. Version
iv •
Revision Description
Date
1.0
Initial version
2008/06/30
1.1
Deleted the LVD function
2009/01/20
1.2
Added the LVD function
2009/07/13
1.3
1. Modified the Electrical Characteristics of the ERC item
2. Added Application Note in Appendix C
3. Added Device Characteristics in Section 8.3
2011/04/22
Product Specification (V1.3) 04.22.2011
EM78P153A
8-Bit Microcontroller with OTP ROM
1 General Description
The EM78P153A is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS
technology. It has an on-chip 1024×13-bit Electrical One Time Programmable Read Only Memory
(OTP-ROM). It provides a protection bit to prevent intrusion of user’s OTP memory code. Fifteen Code
option bits are also available to meet user’s requirements.
With its enhanced OTP-ROM feature, the EM78P153A provides a convenient way of developing and
verifying user’s programs. Moreover, this OTP device offers the advantages of easy and effective program
updates, using development and programming tools. User can avail of the ELAN Writer to easily program his
development code.
2 Features
„
CPU Configuration
„
• 32×8 bits on-chip registers (SRAM,
general purpose)
• 5 level stacks for subroutine nesting
„
„
Three available Interrupts:
• Less than 1.5 mA at 5V/4MHz
• TCC overflow interrupt
• Typically 15 μA, at 3V/32kHz
• Typically 1 μA, during Sleep mode
• Input-port status changed interrupt
(wake-up from sleep mode)
I/O Port Configuration
• External interrupt
• 2 bidirectional I/O ports : P5, P6
„
• 1 Input and 11 I/O pins
Special Features
• Wake-up port : P6
• Programmable free running watchdog
timer
• 6 Programmable pull-down I/O pins
• Power saving Sleep mode
• 7 programmable pull-high I/O pins
• Selectable Oscillation mode
• 7 programmable open-drain I/O pins
„
• External interrupt : P60
„
Peripheral Configuration
• 8-bit real time clock/counter (TCC) with
selective signal sources, trigger edges,
and overflow interrupt
• 1K×13 bits on-chip ROM
• Programmable prescaler of oscillator
set-up time
Operating Voltage Range:
• One security register to prevent intrusion
of user’s OTP memory code
• OTP version:
Operating voltage range: 2.3V~5.5V
„
Operating Temperature range: 0~70°C
„
Operating Frequency range (base on 2 clocks):
• One configuration register to match user’s
requirement
• Two clocks per instruction cycle
• Crystal Mode:
DC~20MHz/2clks @ 5V; DC~100ns inst. cycle @ 5V
DC~8MHz/2clks @ 3V; DC~250ns inst. cycle @ 3V
DC~4MHz/2clks @ 2.3V; DC~500ns inst. cycle @ 2.3V
• ERC Mode:
DC~4MHz/2clks @ 5V; DC~500ns inst. cycle @ 5V
DC~4MHz/2clks @ 3V; DC~500ns inst. cycle @ 3V
DC~4MHz/2clks @ 2.3V; DC~500ns inst. cycle @ 2.3V
• IRC Mode:
Oscillation mode 4 MHz, 8 MHz, 1 MHz, 455kHz
Process deviation: Typ. ± 5.5%, Max. ± 6%
Temperature deviation: ±10% (0°C~70°C )
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
Other Features
• Two LVD level selection / POR
(with ± 0.3V allowance for error)
„
Package Type:
• 14-pin DIP 300mil : EM78P153AD14J
• 14-pin SOP 150mil : EM78P153ASO14J
Note: These are Green products which do not
contain hazardous substances.
•1
EM78P153A
8-Bit Microcontroller with OTP ROM
3
Pin Assignment
(1) 14-pin DIP/SOP
1
14
P51
P67
2
13
P52
P66
3
12
P53
Vdd
4
11
Vss
P65/OSCI
5
10
P60//INT
P64/OSCO
6
9
P61
P63//RST
7
8
P62/TCC
EM78P153AD14/SO14
P50
Figure 3-1 EM78P153AD14/SO14
2•
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
4
Pin Description
4.1 EM78P153AD14/SO14
Function
Input
Type
Output
Type
P50~P52
P50~P52
ST
CMOS
Bidirectional I/O pin with programmable
pull-down.
P53
P53
ST
CMOS
Bidirectional I/O pin
P60
ST
CMOS
Bidirectional I/O pin with programmable
pull-down, open-drain, pull-high and pin
change wake-up.
/INT
ST
−
P61
ST
CMOS
P62
ST
CMOS
TCC
ST
−
P63
ST
CMOS
/RESET
ST
−
P64
ST
CMOS
−
XTAL
Name
P60//INT
P61
P62/TCC
P63//RESET
P64/OSCO/RCOUT OSCO
Description
External interrupt pin
Bidirectional I/O pin with programmable
pull-down, open-drain, pull-high and pin
change wake-up.
Bidirectional I/O pin with programmable
pull-down, open-drain, pull-high and pin
change wake-up.
Real Time Clock/Counter clock input
Only input pin.
External pull-high reset pin
Bidirectional I/O pin with programmable
open-drain, pull-high and pin change
wake-up.
Clock output of crystal/ resonator oscillator
Clock output of internal RC oscillator
Clock output of external RC oscillator
(open-drain)
Bidirectional I/O pin with programmable
open-drain, pull-high and pin change
wake-up.
−
CMOS
ST
CMOS
OSCI
XTAL
−
Clock input of crystal/resonator oscillator
ERCin
AN
−
External RC input pin
P66~P67
P66~P67
ST
CMOS
VDD
VDD
Power
−
Power
VSS
VSS
Power
−
Ground
RCOUT
P65
P65/OSCI/ERCin
Bidirectional I/O pin with programmable
open-drain, pull-high and pin change
wake-up.
Legend: ST: Schmitt Trigger input, AN: analog pin, CMOS: CMOS output,
XTAL: oscillation pin for crystal/ resonator
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
•3
EM78P153A
8-Bit Microcontroller with OTP ROM
5
Functional Description
ROM
Instruction
Register
P5
P50
P51
P52
P53
Ext.
OSC.
PC
Int.
RC
Ext.
RC
Oscillation
Generation
8-level
stack
(13 bit)
TCC
TCC
LVD
Reset
Instruction
Decoder
Ext INT
Mux.
ALU
P6
R4
P60
P61
P62
P63
P64
P65
P66
P67
RAM
ACC
R3(Status
Reg.)
Interrupt
control
circuit
Figure 5-1 EM78P153A Functional Block Diagram
5.1 Operational Registers
5.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as an indirect addressing
pointer. Any instruction using R0 as a pointer actually accesses data pointed by the
RAM Select Register (R4).
5.1.2 R1 (Timer Clock /Counter)
4•
„
Incremented by an external signal edge, which is defined by TE bit (CONT-4)
through the TCC pin, or by the instruction cycle clock.
„
Writable and readable as any other registers.
„
Defined by resetting PAB (CONT-3).
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
„
The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
„
The contents of the prescaler counter will be cleared only when TCC register is
written with a value.
5.1.3 R2 (Program Counter) and Stack
„
Depending on the device type, R2 and hardware stack are 10-bit wide. The
structure is depicted in the following figure.
PC (A9 ~ A0)
000H
008H
User Memory Space
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
Reset Vector
Interrupt Vector
On-chip Program
Memory
3FFH
Figure 5-2 Program Counter Organization
„
User must include the initial stack program during OTP programming of
EM78P153A. However, when emulating the EM78P153A with ICE153S, the stack
initial program must not be included. See Application note under APPENDIX C.
„
The configuration structure generates 1024×13 bits on-chip OTP ROM addresses
to the relative programming instruction codes. One program page is 1024 words
long.
„
R2 is set as all "0" when under Reset condition.
„
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows the PC to go to any location within a page.
„
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed onto
the stack. Thus, the subroutine entry address can be located anywhere within a
page.
„
"RET" ("RETLk", "RETI") instruction loads the program counter with the contents
of the top-level stack.
„
"ADD R2,A" allows the contents of ‘A’ to be added to the current PC, and the ninth
and tenth bits of the PC will increase progressively.
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
•5
EM78P153A
8-Bit Microcontroller with OTP ROM
„
"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits
of the PC, and the ninth and tenth bits of the PC will remain unchanged.
„
Any instruction written to R2 (e.g. "MOV R2, A", "BC R2, 6",⋅etc.) will cause the
ninth bit and the tenth bit (A8 ~ A9) of the PC to remain unchanged.
„
All instructions are single instruction cycle (fclk/2 or fclk/4) except for instructions
that would change the contents of R2. Such instructions will need one more
instruction cycle.
„
The Data Memory Configuration is as follows:
Address
IOC PAGE Registers
00
R0
01
R1
(TCC)
02
R2
(PC)
Reserve
03
R3
(Status)
Reserve
04
R4
(RSR)
Reserve
05
R5
(Port 5)
IOC5
(I/O Port Control Register)
06
R6
(Port 6)
IOC6
(I/O Port Control Register)
Reserve
CONT
(Control Register)
07
Reserve
Reserve
08
Reserve
Reserve
09
Reserve
Reserve
0A
Reserve
Reserve
0B
Reserve
IOCB
(Pull-down Register)
0C
Reserve
IOCC
(Open-drain Control)
0D
Reserve
IOCD
(Pull-high Control Register)
0E
Reserve
IOCE
(WDT Control Register)
IOCF
(Interrupt Mask Register)
0F
10
︰
2F
6•
R PAGE Registers
RF
(Interrupt Status)
General Registers
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
5.1.4 R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
GP1
GP0
T
P
Z
DC
C
Bit 0 (C):
Carry flag
Bit 1 (DC): Auxiliary carry flag
Bit 2 (Z):
Zero flag
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 3 (P):
Power down bit
Set to “1” during power on or by a "WDTC" command; and reset to “0” by a
"SLEP" command.
Bit 4 (T):
Time-out bit
Set to “1” with the "SLEP" and "WDTC" commands, or during power up;
and reset to “0” by WDT time-out.
Bits 5 ~6 (GP0 ~ GP1): General-purpose read/write bits
Bit 7 (RST): Bit for reset type
0 : Set to 0 if the device wakes up from other reset type
1 : Set to 1 if the device wakes up from sleep mode on a pin change
5.1.5 R4 (RAM Select Register)
Bits 0 ~ 5 are used to select registers (Address: 00~06, 0F~2F) in indirect addressing
mode.
Bits 6 ~ 7 are general-purpose read bits. Read as “1” at all time.
See the Data Memory Configuration in Figure 5-3.
5.1.6 R5 ~ R6 (Port 5 ~ Port 6)
R5 and R6 are I/O registers.
Only the lower 4 bits of R5 are available.
The upper 4 bits of R5 are fixed to 0.
P63 is input only.
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
•7
EM78P153A
8-Bit Microcontroller with OTP ROM
5.1.7 RF (Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
EXIF
ICIF
TCIF
Note: “ 1 ” means with interrupt request
“ 0 ” means no interrupt occurs
Bit 0 (TCIF): TCC Overflow Interrupt Flag. Set when TCC overflows, reset by
software.
Bit 1 (ICIF): Port 6 input status changed interrupt flag. Set when Port 6 input changes,
reset by software.
Bit 2 (EXIF): External Interrupt Flag. Set by a falling edge on the /INT pin, reset by
software.
Bits 3 ~ 7: Not used.
RF can be cleared by instruction but cannot be set.
IOCF is the interrupt mask register.
NOTE
The result of reading RF is the "logic AND" of RF and IOCF.
5.1.8 R10 ~ R2F
These are all 8-bit general-purpose registers.
8•
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
5.2 Special Function Registers
5.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator, which is not an addressable register.
5.2.2 CONT (Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
/INT
TS
TE
PAB
PSR2
PSR1
PSR0
Bit 0 ~ Bit 2 (PSR0 ~ PSR2): TCC/WDT prescaler bits
PSR2
PSR1
PSR0
TCC Rate
WDT Rate
0
0
0
1:2
1:1
0
0
1
1:4
1:2
0
1
0
1:8
1:4
0
1
1
1:16
1:8
1
0
0
1:32
1:16
1
0
1
1:64
1:32
1
1
0
1:128
1:64
1
1
1
1:256
1:128
Bit 3 (PAB): Prescaler Assigned Bit
0 : TCC
1 : WDT
Bit 4 (TE): TCC signal edge
0 : increment if a transition from low to high takes place on the TCC pin
1 : increment if a transition from high to low takes place on the TCC pin
Bit 5 (TS): TCC signal source
0 : internal instruction cycle clock, P62 is a bidirectional I/O pin
1 : transition on TCC pin
Bit 6 (/INT): Interrupt enable flag
0 : masked by DISI or hardware interrupt
1 : enabled by ENI/RETI instructions
Bit 7:
Not used
The CONT register is both readable and writable.
5.2.3 IOC5 ~ IOC6 (I/O Port Control Register)
0 : defines the relative I/O pin as output
1 : sets the relative I/O pin into high impedance
Only the lower 4 bits of IOC5 are available to be defined.
IOC5 and IOC6 registers are both readable and writable.
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
•9
EM78P153A
8-Bit Microcontroller with OTP ROM
5.2.4 IOCB (Pull-down Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
/PD6
/PD5
/PD4
-
/PD2
/PD1
/PD0
Bit 0 (/PD0): Control bit used to enable pull-down of the 50 pin.
0 : Enable internal pull-down
1 : Disable internal pull-down
Bit 1 (/PD1): Control bit used to enable pull-down of the 51 pin.
Bit 2 (/PD2): Control bit used to enable pull-down of the 52 pin.
Bit 3:
Not used
Bit 4 (/PD4): Control bit used to enable pull-down of the 60 pin.
Bit 5 (/PD5): Control bit used to enable pull-down of the 61 pin.
Bit 6 (/PD6): Control bit used to enable pull-down of the 62 pin.
Bit 7:
Not used
The IOCB Register is both readable and writable.
5.2.5 IOCC (Open-drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD7
OD6
OD5
OD4
-
OD2
OD1
OD0
Bit 0 (OD0): Control bit used to enable open-drain of the P60 pin.
0 : Disable open-drain output
1 : Enable open-drain output
Bit 1 (OD1): Control bit used to enable open-drain of the P61 pin.
Bit 2 (OD2): Control bit used to enable open-drain of the P62 pin.
Bit 3:
Not used
Bit 4 (OD4): Control bit used to enable open-drain of the P64 pin.
Bit 5 (OD5): Control bit used to enable open-drain of the P65 pin.
Bit 6 (OD6): Control bit used to enable open-drain of the P66 pin.
Bit 7 (OD7): Control bit used to enable open-drain of the P67 pin.
The IOCC Register is both readable and writable.
5.2.6 IOCD (Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH7
/PH6
/PH5
/PH4
-
/PH2
/PH1
/PH0
Bit 0 (/PH0): Control bit used to enable pull-high of the P60 pin.
0 : Enable internal pull-high
1 : Disable internal pull-high
Bit 1 (/PH1): Control bit used to enable pull-high of the P61 pin.
10 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
Bit 2 (/PH2): Control bit is used to enable pull-high of the P62 pin.
Bit 3:
Not used
Bit 4 (/PH4): Control bit used to enable pull-high of the P64 pin.
Bit 5 (/PH5): Control bit used to enable pull-high of the P65 pin.
Bit 6 (/PH6): Control bit used to enable pull-high of the P66 pin.
Bit 7 (/PH7): Control bit used to enable pull-high of the P67 pin.
The IOCD Register is both readable and writable.
5.2.7 IOCE (WDT Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
EIS
-
-
-
LVDF
LVDSEL
LVDEN
Bit 0 (LVDEN): LVD function enable bit
0: disable
1: enable
Bit 1 (LVDSEL): LVD level select bit
0: set LVD level to 2.4V (with ± 0.3V allowance for error).
1: set LVD level to 3.6V (with ± 0.3V allowance for error).
Bit 2 (LVDF): Low voltage detector flag
Bits 3~ 5:
Not used
Bit 6 (EIS):
Control bit is used to define the function of the P60 (/INT) pin.
0 : P60, bidirectional I/O pin.
1 : /INT, external interrupt pin. In this case, the I/O control bit of P60
(Bit 0 of IOC6) must be set to "1."
When EIS is "0," the path of /INT is masked. When EIS is "1," the status
of /INT pin can also be read by way of reading Port 6 (R6). See Figure
5-6 under Section 5.4 for reference.
EIS is both readable and writable.
Bit 7 (WDTE): Control bit used to enable the Watchdog timer.
0 : Disable WDT
1 : Enable WDT
WDTE is both readable and writable.
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 11
EM78P153A
8-Bit Microcontroller with OTP ROM
5.2.8 IOCF (Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
EXIE
ICIE
TCIE
Bit 0 (TCIE): TCIF interrupt enable bit
0 : disable TCIF interrupt
1 : enable TCIF interrupt
The IOCF register is both readable and writable.
Bit 1 (ICIE): ICIF interrupt enable bit
0 : disable ICIF interrupt
1 : enable ICIF interrupt
Bit 2 (EXIE): EXIF interrupt enable bit
0 : disable EXIF interrupt
1 : enable EXIF interrupt
Bits 3~7:
Not used
Individual interrupt is enabled by setting its associated control bit in the
IOCF to "1".
Global interrupt is enabled by the ENI instruction and is disabled by the
DISI instruction. Refer to Figure 5-8.
12 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
5.3 TCC/WDT and Prescaler
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is
available for the TCC only or WDT only, one at a time and the PAB bit of the CONT
register is used to determine the prescaler assignment. The PSR0~PSR2 bits
determine the ratio. The prescaler is cleared each time an instruction is written to TCC
in TCC mode. The WDT and prescaler, when assigned to WDT mode, are cleared by
the “WDTC” or “SLEP” instructions. If the prescaler is earlier assigned to TCC and later
assigned to WDT, or vice versa, the contents of the prescaler counter would be cleared
automatically. Figure 5-4 depicts the circuit diagram of TCC/WDT.
„
R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or
external clock input (edge selectable from TCC pin). If the TCC signal source is
from an internal clock, TCC will increase by 1 at every instruction cycle (without
prescaler). Referring to Figure 5-4, CLK=Fosc/2 or CLK=Fosc/4, depends on the
Code Option bit CLK. CLK=Fosc/2 is used if CLK bit is "0", and CLK=Fosc/4 is
used if CLK bit is "1". If the TCC signal source is from an external clock input, TCC
is incremented by 1 at every falling edge or rising edge of the TCC pin.
„
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep
running even when the oscillator driver has been turned off (i.e. in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause
the device to reset. The WDT can be enabled or disabled any time during normal
mode by software programming. Refer to WDTE bit of the IOCE register. Without
1
prescaler, the WDT time-out period is approximately 18 ms (default).
NOTE
During OTP programming of EM78P153A, if the WDT time-out (if enable) or reset pin
input low occurs, it will cause the device to reset. The device reset will result to
programming error of stack function.
5.4 I/O Ports
The I/O registers, both Port 5 and Port 6, are bidirectional tri-state I/O ports. Port 6 can
be pulled-high internally by software except P63. In addition, Port 6 can also have
open-drain output by software except P63. Input status changed interrupt (or wake-up)
function is available from Port 6. P50 ~ P52 and P60 ~ P62 pins can be pulled-down by
software. Each I/O pin can be defined as "input" or "output" pin by the I/O control
register (IOC5 ~ IOC6) except P63. The I/O registers and I/O control registers are both
readable and writable. The I/O interface circuits for Port 5 and Port 6 are shown in
Figures 5-5, 5-6 and 5-7 respectively.
1
Note: Vdd = 5V, set up time period = 16.5ms ± 30% at 25°C
Vdd = 3V, set up time period = 18ms ± 30% at 25°C
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 13
EM78P153A
8-Bit Microcontroller with OTP ROM
Figure 5-4 TCC and WDT Block Diagram
Note: Pull-down is not shown in the figure.
Figure 5-5 I/O Port and I/O Control Register Circuit for Port 5
14 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
Note: Pull-high (down) and open-drain are not shown in the figure.
Figure 5-6 I/O Port and I/O Control Register Circuit for P60 (/INT)
Note: Pull-high (down) and open-drain are not shown in the figure.
Figure 5-7 I/O Port and I/O Control Register Circuit for P61~P67
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 15
EM78P153A
8-Bit Microcontroller with OTP ROM
ICIE
D
P
R
Q
Interrupt
CLK
_
C Q
L
ICIF
ENI Instruction
P
D R Q
P60
P61
P62
P63
CLK
_
C Q
L
P64
P65
P66
P67
Q P
R D
CLK
_
Q C
L
DISI Instruction
Interrupt
(Wake-up from
SLEEP)
/SLEP
Next Instruction
(Wake-up from
SLEEP)
Figure 5-8 Block Diagram of I/O Port 6 with input change interrupt/wake-up
Table 1 Usage of Port 6 Input Change Wake-up/Interrupt Function
Usage of Port 6 Input Status Change Wake-up/Interrupt
(I) Wake-up from Port 6 Input Status Change
(a) Before Sleep
(II) Port 6 Input Status Change Interrupt
1. Read I/O Port 6 (MOV R6,R6)
1. Disable WDT
2. Execute "ENI"
2. Read I/O Port 6 (MOV R6,R6)
3. Enable interrupt (Set IOCF.1)
3. Execute "ENI" or "DISI"
4. IF Port 6 change (interrupt)
4. Enable interrupt (Set IOCF.1)
→ Interrupt vector (008H)
5. Execute "SLEP" instruction
(b) After Wake-up
1. IF "ENI" → Interrupt vector (008H)
2. IF "DISI" → Next instruction
16 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
5.5 Reset and Wake-up
5.5.1 Reset
A Reset is initiated by one of the following events:
1) Power-on reset
2) /RESET pin input "low"
3) WDT time-out (if enabled)
The device is kept under reset condition for a period of approximately 18ms 2 (one
oscillator start-up timer period) after a reset is detected. Once a Reset occurs, the
following functions are performed:
„
The oscillator is running, or will be started.
„
The Program Counter (R2) is set to all "0."
„
All I/O port pins are configured as input mode (high-impedance state)
„
The Watchdog timer and prescaler are cleared.
„
When power is switched on, the upper 3 bits of R3 are cleared.
„
The bits of the CONT register are set to all "1" except for Bit 6 (INT flag).
„
The bits of the IOCB register are set to all "1."
„
The IOCC register is cleared.
„
The bits of the IOCD register are set to all "1."
„
Bit 7 of the IOCE register is set to "1," and Bits 4 and 6 are cleared.
„
Bits 0 ~ 2 of RF and Bits 0 ~ 2 of IOCF registers are cleared.
Sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering Sleep mode, WDT (if enabled) is cleared but keeps on running. The controller
can be awakened by:
1) External reset input on /RESET pin,
2) WDT time-out (if enabled)
3) Port 6 input status change (if enabled)
The first two cases will cause the EM78P153A to reset. The T and P flags of R3 are
used to determine the source of the reset (wake-up). The last case is considered the
continuation of program execution and the global interrupt ("ENI" or "DISI" being
executed) determines whether or not the controller branches to the interrupt vector
after a wake-up. If ENI is executed before SLEP, the instruction will begin to execute
from Address 008H after a wake-up. If DISI is executed before SLEP, the operation will
restart from the succeeding instruction right next to SLEP after a wake-up.
2
Vdd = 5V, set up time period = 16.8ms ± 30%
Vdd = 3V, set up time period = 18ms ± 30%
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 17
EM78P153A
8-Bit Microcontroller with OTP ROM
Only one of Cases 2 and 3 can be enabled before going into Sleep mode. That is,
[a] if Port 6 Input Status Change Interrupt is enabled before SLEP, WDT must be
disabled by software. However, the WDT bit in the option register remains enabled.
Hence, the EM78P153A can be awakened only by Case 1 or Case 3.
[b] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be
disabled. Hence, the EM78P153A can be awakened only by Case 1 or Case 2.
Refer to Section 5.6, Interrupt for further details.
If Port 6 Input Status Change Interrupt is used to wake-up the EM78P153A (Case [a]
above), the following instructions must be executed before SLEP:
MOV A, @xxxx1110b
; Select the WDT prescaler, it must be
; set over 1:1
CONTW
WDTC
; Clear WDT and prescaler
MOV A, @0xxxxxxxb
; Disable WDT
IOW RE
MOV R6, R6
; Read Port 6
MOV A, @00000x1xb
; Enable Port 6 input change interrupt
IOW RF
ENI (or DISI)
SLEP
; Enable (or disable) global interrupt
; Sleep
NOTE
1. After waking up from sleep mode, WDT is automatically enabled. The WDT
enable/disable operation after waking up from sleep mode should be appropriately
defined in the software.
2. To avoid a reset from occurring when the Port 6 Input Status Changed Interrupt
enters into an interrupt vector or is used to wake-up the MCU, the WDT prescaler
must be set above 1:1 ratio.
3. During OTP programming of EM78P153A, if the WDT time-out (if enable) or reset pin
input low occurs, it will cause the device to reset. The device reset will result to
programming error of stack function.
18 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
5.5.2 Summary of Registers Initialized Values
Addr. Name
Reset Type
Bit Name
Power-on
N/A IOC5
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
N/A IOC6
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
0×05 P5
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
0×06 P6
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
N/A CONT
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
R0
0×00 (IAR)
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
R1
0×01 (TCC)
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
R2
0×02 (PC)
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
R3
0×03 (SR)
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
R4
0×04 (RSR)
/RESET and WDT
Wake-up from Pin Change
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
×
0
0
0
C67
1
1
P
×
0
0
0
C66
1
1
P
×
0
0
0
C65
1
1
P
×
0
0
0
C64
1
1
P
×
1
P
P
P67
1
P
P
×
1
P
P
P66
1
P
P
/INT
0
0
0
U
P
P
0
0
P
0
0
P
GP1
0
0
P
GP0
1
1
1
×
1
P
P
P65
1
P
P
TS
1
1
P
U
P
P
0
0
P
0
0
P
GP0
0
0
P
U
P
P
×
1
P
P
P64
1
P
P
TE
1
1
P
U
P
P
0
0
P
0
0
P
T
1
C53
1
1
P
C63
1
1
P
P53
1
P
P
P63
1
P
P
PAB
1
1
P
U
P
P
0
0
P
0
0
P
P
1
*
*
*
*
U
P
P
U
P
P
C52
C51 C50
1
1
1
1
1
1
P
P
P
C62
C61 C60
1
1
1
1
1
1
P
P
P
P52
P51
P50
1
1
1
P
P
P
P
P
P
P62
P61
P60
1
1
1
P
P
P
P
P
P
PSR2 PSR1 PSR0
1
1
1
1
1
1
P
P
P
U
U
U
P
P
P
P
P
P
0
0
0
0
0
0
P
P
P
0
0
0
0
0
0
P
P
P
Z
DC
C
U
U
U
P
P
P
P
P
P
U
U
U
P
P
P
P
P
P
×
1
1
P
U
P
P
0
0
P
0
0
P
RST
0
0
1
GP1
1
1
1
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
Bit 1
Bit 0
• 19
EM78P153A
8-Bit Microcontroller with OTP ROM
Addr. Name
0×0F
0×0B
RF
(ISR)
IOCB
0×0C IOCC
0×0D IOCD
Reset Type
Bit Name
0×0E
Bit 7
Bit Name
×
Power-on
0
/RESET and WDT
0
Wake-up from Pin Change
0
Bit Name
×
Power-on
1
/RESET and WDT
1
Wake-up from Pin Change
P
Bit Name
OD7
Power-on
0
/RESET and WDT
0
Wake-up from Pin Change
P
Bit Name
/PH7
Power-on
1
/RESET and WDT
1
Wake-up from Pin Change
P
Power-on
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
0×0F IOCF
/RESET and WDT
Wake-up from Pin Change
Bit Name
0×10
R10~R Power-on
~
2F
/RESET and WDT
0×2F
Wake-up from Pin Change
IOCE
Legend: ×: Not used
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
×
0
0
0
×
0
0
0
×
0
0
0
×
0
0
0
/PD6
1
1
P
OD6
0
0
P
/PH6
1
1
P
/PD5
1
1
P
OD5
0
0
P
/PH5
1
1
P
/PD4
1
1
P
OD4
0
0
P
/PH4
1
1
P
×
1
1
P
×
1
1
P
EXIF
0
0
P
/PD2
1
1
P
OD2
0
0
P
/PH2
1
1
P
×
×
×
LVDF
0
0
P
EXIE
0
0
P
U
P
P
ICIF
0
0
P
/PD1
1
1
P
OD1
0
0
P
/PH1
1
1
P
LVD
SEL
0
0
P
ICIE
0
0
P
U
P
P
TCIF
0
0
P
/PD0
1
1
P
OD0
0
0
P
/PH0
1
1
P
LVD
EN
0
0
P
TCIE
0
0
P
U
P
P
WDTE EIS
×
0
0
P
1
1
1
0
0
P
1
1
1
1
1
1
1
1
1
×
1
1
1
U
P
P
×
1
1
1
U
P
P
×
1
1
1
U
P
P
×
1
1
1
U
P
P
×
1
1
1
U
P
P
U: Unknown or don’t care
P: Previous value before reset
*Refer to tables provided in the next section (Section 5.5.3), particularly Table 4.
20 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
5.5.3 Status of RST, T, and P of the Status Register
A Reset condition is initiated by the following events
1) A power-on condition
2) A high-low-high pulse on /RESET pin
3) Watchdog timer time-out
The values of T and P listed in the table below are used to check how the processor
wakes up.
Table 2 Values of RST, T, and P after a Reset
Reset Type
RST
T
Power on
/RESET during Operating mode
/RESET wake-up during Sleep mode
WDT during Operating mode
WDT wake-up during Sleep mode
Wake-up on pin change during Sleep mode
0
0
0
0
0
1
1
*P
1
0
0
1
P
1
*P
0
*P
0
0
* P: Previous status before reset
The following table shows the events that may affect the status of T and P.
Table 3 Status of T and P Being Affected by Events
Event
RST
T
P
Power on
WDTC instruction
WDT time-out
SLEP instruction
Wake-up on pin change during Sleep mode
0
*P
0
*P
1
1
1
0
1
1
1
1
*P
0
0
* P: Previous status before reset
Figure 5-9 Controller Reset Block Diagram
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 21
EM78P153A
8-Bit Microcontroller with OTP ROM
5.6 Interrupt
The EM78P153A has three falling-edge interrupts as listed herewith:
1) TCC overflow interrupt
2) Port 6 Input Status Change Interrupt
3) External interrupt [(P60, /INT) pin]
Before the Port 6 Input Status Changed Interrupt is enabled, reading Port 6 (e.g. "MOV
R6, R6") is necessary. Each pin of Port 6 will have this feature if its status changes.
Any pin configured as output or P60 pin configured as /INT, is excluded from this
function. The Port 6 Input Status Changed Interrupt can wake up the EM78P153A from
Sleep mode if Port 6 is enabled prior to going into Sleep mode by executing SLEP
instruction. When the chip wakes-up, the controller will continue to execute the
program in-line if the global interrupt is disabled. If the global interrupt is enabled, it will
branch to the interrupt Vector 008H.
RF is the interrupt status register that records the interrupt requests in the relative
flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the
ENI instruction and is disabled by the DISI instruction. When one of the interrupts
(enabled) occurs, the next instruction will be fetched from Address 008H. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the flag
bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine before interrupts are enabled to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or the execution of ENI. Note that the outcome of RF will be the
logic AND of RF and IOCF (refer to Fig. 5-10). The RETI instruction ends the interrupt
routine and enables the global interrupt (the execution of ENI).
When an interrupt is generated by the INT instruction (enabled), the next instruction will
be fetched from Address 001H.
Figure 5-10 Interrupt Input Circuit
22 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
NOTE
During OTP programming of EM78P153A, if the WDT time-out (if enable) or reset pin
input low occurs, it will cause the device to reset. The device reset will result to
programming error of stack function.
5.7 Oscillator
5.7.1 Oscillator Modes
The EM78P153A can be operated in four different oscillator modes, such as External
RC oscillator mode (ERC), Internal RC oscillator mode (IRC), High Crystal oscillator
mode (HXT), and Low Crystal oscillator mode (LXT). The desired mode can be
selected by programming OSC1 and OSC2 in the Code Option register. The Table
below describes how these four oscillator modes are defined.
Table 4 Oscillator Modes Defined by OSC
Mode
OSC1
OSC2
IRC (Internal RC oscillator mode)
1
1
ERC (External RC oscillator mode)
1
0
HXT (High Crystal oscillator mode)
0
1
LXT (Low Crystal oscillator mode)
0
0
Note: The transient point of system frequency between HXT and LXY is 400kHz.
The maximum operational frequency of the crystal/resonator under different VDDs is as
listed below.
Table 5 Summary of Maximum Operating Speeds
Conditions
Two cycles with two clocks
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
VDD
Max Freq. (MHz)
2.3
4.0
3.0
8.0
5.0
20.0
• 23
EM78P153A
8-Bit Microcontroller with OTP ROM
5.7.2 Crystal Oscillator/Ceramic Resonators (Crystal)
The EM78P153A can be driven by an external clock signal through the OSCI pin as
shown in the following figure.
OSCI
Ext. Clock
OSCO
EM78P153A
Figure 5-11 Circuit for External Clock Input
In most applications, pin OSCI and pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation. Figure 5-12 depicts such a circuit. The
same thing applies whether it is in the HXT mode or in the LXT mode.
In Figure 5-12-1, when the connected resonator in OSCI and OSCO is used in
applications, R1 that is 1 MΩ needs to be shunted with resonator.
C1
OSCI
EM78P153A
Crystal
OSCO
RS
C2
Figure 5-12 Circuit for Crystal/Resonator
24 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
C1
OSCI
Resonator
EM78P153A
R1
OSCO
C2
Fig. 5-12-1 Circuit for Crystal/Resonator
The following table provides the recommended values of C1 and C2. Since each
resonator has its own attribute, refer to its specification for appropriate values of C1 and
C2. RS, a serial resistor, may be necessary for AT strip cut crystal or low frequency
mode.
Table 6 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type
Ceramic Resonators
Frequency Mode
HXT
LXT
Crystal Oscillator
HXT
Frequency
C1 (pF)
C2 (pF)
455kHz
100~150
100~150
2.0 MHz
20~40
20~40
4.0 MHz
10~30
10~30
32.768kHz
25
15
100kHz
25
25
200kHz
25
25
455kHz
20~40
20~150
1.0 MHz
15~30
15~30
2.0 MHz
15
15
4.0 MHz
15
15
Note: The values of Capacitors C1 and C2 are for reference only
5.7.3 External RC Oscillator Mode
For some applications that do not require a very precise timing calculation, the RC
oscillator (Figure 5-15) offers a cost-effective oscillator configuration. Nevertheless, it
should be noted that the frequency of the RC oscillator is influenced by the supply
voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the
operation temperature. Moreover, the frequency also changes slightly from one chip to
another due to manufacturing process variations.
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 25
EM78P153A
8-Bit Microcontroller with OTP ROM
In order to maintain a stable system frequency, the values of the Cext should not be
less than 20pF, and the value of Rext should not be greater than 1 MΩ. If they cannot
be kept in this range, the frequency can be easily affected by noise, humidity, and
leakage.
The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the
contrary, for very low Rext values, for instance, 1 KΩ, the oscillator becomes unstable
because the NMOS cannot discharge the current of the capacitance correctly.
Based on the above reasons, it must be kept in mind that all of the supply voltage, the
operation temperature, the components of the RC oscillator, the package types, the
way the PCB is layout, will affect the system frequency.
Vcc
Rext
OSCI
Cext
EM78P153A
Figure 5-13 External RC Oscillator Mode Circuit
Table 7 RC Oscillator Frequencies
Cext
20pF
100pF
300pF
Rext
Average Fosc
5V, 25°C
Average Fosc
3V, 25°C
3.3k
3.92 MHz
3.65 MHz
5.1k
2.67 MHz
2.60 MHz
10k
1.4 MHz
1.40 MHz
100k
150kHz
156 kHz
3.3k
1.4 MHz
1.33 MHz
5.1k
940kHz
917kHz
10k
476kHz
480kHz
100k
50kHz
52kHz
3.3k
595kHz
570kHz
5.1k
400kHz
384kHz
10k
200kHz
203kHz
100k
20.9kHz
20kHz
1
Note: : Measured based on DIP packages.
2
: The values are for design reference only.
: The frequency drift is ± 30%.
3
26 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
5.7.4 Internal RC Oscillator Mode
EM78P153A offers a versatile internal RC mode with default frequency value of 4MHz.
The Internal RC oscillator mode has other frequencies (1MHz, 8MHz, and 455kHz) that
can be set by Code Option (Word 1), RCM1, and RCM0. All these four main
frequencies can be calibrated by programming the Option Bits CAL0 ~ CAL2. The
table below describes the EM78P153A internal RC drift with variation of voltage,
temperature, and process.
Table 8 Internal RC Drift Rate (Ta=25°C, VDD=5V ± 5%, VSS=0V)
Drift Rate
Internal RC
Temperature
(0°C~70°C)
Voltage
(2.3V~5.5V)
Process
Total
8 MHz
± 3%
± 5%
± 10%
± 18%
4 MHz
± 3%
± 5%
± 5%
± 13%
1 MHz
± 3%
± 5%
± 10%
± 18%
455kHz
± 3%
± 5%
± 10%
± 18%
Note: These are theoretical values provided for reference only. Actual values may vary depending on the
actual process.
5.8 Code Option Register
The EM78P153A has a Code Option word that is not a part of the normal program
memory. The option bits cannot be accessed during normal program execution.
„ Code Option Register and Customer ID Register Arrangement Distribution:
Word 0
Word 1
Word 2
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
5.8.1 Code Option Register (Word 0)
Word 1
Bit
Mne
monic
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
RESETEN ENWDT CLKS OSC1 OCS0 Protect SUT1 SUT0 TYPE RCOUT
Bit 2
Bit 1
Bit 0
C2
C1
C0
1
Disable
Disable 4clocks High
High Disable High High High
High
High High High
0
Enable
Enable 2clocks Low
Low Enable Low
Low
Low
Low
Low
Low
Low
Bit 12 (RESETEN): Define Pin 6.3 as a reset pin
0 : /RESET enable
1 : /RESET disable
Bit 11 (ENWDT): Watchdog timer enable bit
0 : Enable
1 : Disable
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 27
EM78P153A
8-Bit Microcontroller with OTP ROM
Note
This bit must be enabled and the WDTE register (IOCE reg. Bit 6) must be disabled when
Port 6 pin change wake-up function is used.
Bit 10 (CLKS): Instruction period option bit
0 : Two oscillator periods
1 : Four oscillator periods
Refer to the Instruction Set section.
Bit 9 and Bit 8 (OSC1 and OSC0): Oscillator Modes Select bits.
Table 9
Oscillator Modes defined by OSC1 and OSC0
Mode
OSC1
OSC0
IRC (Internal RC oscillator mode)
1
1
ERC (External RC oscillator mode)
1
0
HXT (High Crystal oscillator mode)
0
1
LXT (Low Crystal oscillator mode)
0
0
Note: The transient point of system frequency between HXT and LXY is 400kHz.
Bit 7 (CS): Code Security Bit
0 : Security On
1 : Security Off
Bit 6 and Bit 5 (SUT1 and SUT0): Set-up Time of device bits.
Table 10 Set-up Time of Device Programming
SUT1
SUT0
*Set-up Time
1
1
18 ms
1
0
4.5 ms
0
1
288 ms
0
0
72 ms
* Theoretical values, for reference only
Bit 4 (Type): Type selection for EM78P153A
TYPE
Series
0
EM78P153A
1
×
Bit 3 (RCOUT): Selection bit of Oscillator output or I/O port
RCOUT
Pin Function
0
P64
1
OSCO
Bits 2~ 0 (C2~C 0): Calibrator of internal RC mode Bit 3
C2, C1, C0 must be set to “1” only.
28 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
„
Code Option Register (Word 1)
Word 1
Bit 2
Bit 1
Bit 0
HLP
RCM1
RCM0
Bit 2 (HLP): Power Consumption Selection Bit
0 : Low power consumption
1 : High power consumption
Bit 1 and Bit 0 (RCM1, RCM0): RC mode select bits
„
RCM 1
RCM 0
*Frequency (MHz)
1
1
4
1
0
8
0
1
1
0
0
455kHz
Customer ID Register (Word 2)
Bit 12~Bit 0
XXXXXXXXXXXXX
Bits 12~ 0: Customer’s ID code
5.9 Power-on Considerations
Any microcontroller is not guaranteed to start to operate properly before the power
supply stabilizes at its steady state. Under customer application, when power is OFF,
Vdd must drop to below 1.8V and remains OFF for 10µs before power can be switched
ON again. This way, the EM78P153A will reset and operate normally. The extra
external reset circuit will work well if Vdd can rise at a very fast speed (50 ms or less).
However, under most cases where critical applications are involved, extra devices are
required to assist in solving the power-up problems.
5.10 Programmable Oscillator Set-up Time
The Option word contains SUT0 and SUT1 which can be used to define the oscillator
set-up time. Theoretically, the range is from 4.5 ms to 72 ms. For most of crystal or
ceramic resonators, the lower the operation frequency is, the longer the Set-up time
may be required. Table 12 describes the values of the Oscillator Set-up Time.
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 29
EM78P153A
8-Bit Microcontroller with OTP ROM
5.11 External Power-on Reset Circuit
The circuit shown in Figure
5-14 implements an external
RC to produce the reset
pulse. The pulse width (time
constant) should be kept long
enough for Vdd to reach
minimum operation voltage.
This circuit is used when the
power supply has a slow rise
time.
Fig 5-14 External Power-up Reset Circuit
Since the current leakage from the /RESET pin is ± 5μA, it is recommended that R
should not be greater than 40K. In this way, the /RESET pin voltage is held below 0.2V.
The diode (D) acts as a short circuit at the moment of power down.
The capacitor C will discharge rapidly and fully. Rin, the current-limited resistor, will
prevent high current or ESD (electrostatic discharge) from flowing to pin /RESET.
5.12 Residue-Voltage Protection
When the battery is replaced, the device power (Vdd) is cut off but residue-voltage
remains. The residue-voltage may trip below the minimum Vdd, but not to zero. This
condition may cause a poor power-on reset. The following figures illustrate two
recommended methods on how to build a residue-voltage protection circuit for
EM78P153A.
* Figure 5-15 Residue Voltage Protection Circuit 1
30 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
* Figure 5-16 Residue Voltage Protection Circuit 2
Note: * Figure 5-15 and Figure 5-16 should be designed with their /RESET pin voltage larger
than VIH (min).
5.13 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of two oscillator periods), unless the program counter is
changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or
logic operation on R2 (e.g., "SUB R2,A", "BS(C) R2,6", "CLR R2", etc.). In this case,
the execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try modifying the instruction as follows:
A) Modify one instruction cycle to consist of four oscillator periods.
B) "JMP," "CALL," "RET," "RETL," "RETI," or the conditional skip ("JBS," "JBC," "JZ,"
"JZA," "DJZ,” "DJZA") commands which were tested to be true, are executed within
two instruction cycles. The instructions that are written to the program counter also
take two instruction cycles.
Case (A) is selected by the Code Option bit, called CLK. One instruction cycle consists
of two oscillator clocks if CLK is low; and four oscillator clocks if CLK is high.
Note that once the four oscillator periods within one instruction cycle is selected as in
Case (A), the internal clock source to TCC should be CLK=Fosc/4, instead of Fosc/2.
Moreover, the instruction set has the following features:
1) Every bit of any register can be set, cleared, or tested directly.
2) The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 31
EM78P153A
8-Bit Microcontroller with OTP ROM
The following symbols are used in the Instruction Set table:
Convention:
R = Register designator that specifies which one of the registers (including operation and general
purpose registers) is to be utilized by the instruction.
b = Bit field designator that selects the value for the bit located in the register R and which affects
the operation.
k = 8 or 10-bit constant or literal value
32 •
Binary Instruction
Hex
Mnemonic
Operation
0 0000 0000 0000
0000
NOP
No Operation
0 0000 0000 0001
0001
DAA
Decimal Adjust A
0 0000 0000 0010
0002
CONTW
0 0000 0000 0011
0003
0 0000 0000 0100
Status Affected
None
C
A → CONT
None
SLEP
0 → WDT, Stop oscillator
T, P
0004
WDTC
0 → WDT
T, P
0 0000 0000 rrrr
000r
IOW R
A → IOCR
None 1
0 0000 0001 0000
0010
ENI
Enable Interrupt
None
0 0000 0001 0001
0011
DISI
Disable Interrupt
None
0 0000 0001 0010
0012
RET
[Top of Stack] → PC
None
0 0000 0001 0011
0013
RETI
[Top of Stack] → PC,
Enable Interrupt
None
0 0000 0001 0100
0014
CONTR
CONT → A
None
0 0000 0001 rrrr
001r
IOR R
IOCR → A
None 1
0 0000 01rr rrrr
00rr
MOV R,A
A→R
None
0 0000 1000 0000
0080
CLRA
0→A
Z
0 0000 11rr rrrr
00rr
CLR R
0→R
Z
0 0001 00rr rrrr
01rr
SUB A,R
R-A → A
Z, C, DC
0 0001 01rr rrrr
01rr
SUB R,A
R-A → R
Z, C, DC
0 0001 10rr rrrr
01rr
DECA R
R-1 → A
Z
0 0001 11rr rrrr
01rr
DEC R
R-1 → R
Z
0 0010 00rr rrrr
02rr
OR A,R
A∨R→A
Z
0 0010 01rr rrrr
02rr
OR R,A
A∨R→R
Z
0 0010 10rr rrrr
02rr
AND A,R
A&R→A
Z
0 0010 11rr rrrr
02rr
AND R,A
A&R→R
Z
0 0011 00rr rrrr
03rr
XOR A,R
A⊕R→A
Z
0 0011 01rr rrrr
03rr
XOR R,A
A⊕R→R
Z
0 0011 10rr rrrr
03rr
ADD A,R
A+R→A
Z, C, DC
0 0011 11rr rrrr
03rr
ADD R,A
A+R→R
Z, C, DC
0 0100 00rr rrrr
04rr
MOV A,R
R→A
Z
0 0100 01rr rrrr
04rr
MOV R,R
R→R
Z
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
Binary Instruction
Hex
Mnemonic
0 0100 10rr rrrr
04rr
COMA R
/R → A
Z
0 0100 11rr rrrr
04rr
COM R
/R → R
Z
0 0101 00rr rrrr
05rr
INCA R
R+1 → A
Z
0 0101 01rr rrrr
05rr
INC R
R+1 → R
Z
0 0101 10rr rrrr
05rr
DJZA R
R-1 → A, skip if zero
None
0 0101 11rr rrrr
05rr
DJZ R
R-1 → R, skip if zero
None
0 0110 00rr rrrr
06rr
RRCA R
0 0110 01rr rrrr
06rr
RRC R
0 0110 10rr rrrr
06rr
RLCA R
0 0110 11rr rrrr
06rr
RLC R
0 0111 00rr rrrr
07rr
SWAPA R
0 0111 01rr rrrr
07rr
SWAP R
0 0111 10rr rrrr
07rr
0 0111 11rr rrrr
Operation
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → C, C → R(0)
R(0-3) → A(4-7),
R(4-7) → A(0-3)
Status Affected
C
C
C
C
None
R(0-3) ↔ R(4-7)
None
JZA R
R+1 → A, skip if zero
None
07rr
JZ R
R+1 → R, skip if zero
None
0 100b bbrr rrrr
0xxx
BC R,b
0 → R(b)
None 2
0 101b bbrr rrrr
0xxx
BS R,b
1 → R(b)
None 3
0 110b bbrr rrrr
0xxx
JBC R,b
if R(b)=0, skip
None
0 111b bbrr rrrr
0xxx
JBS R,b
if R(b)=1, skip
None
None
1 00kk kkkk kkkk
1kkk
CALL k
PC+1 → [SP],
(Page, k) → PC
1 01kk kkkk kkkk
1kkk
JMP k
(Page, k) → PC
None
1 1000 kkkk kkkk
18kk
MOV A,k
k→A
None
1 1001 kkkk kkkk
19kk
OR A,k
A∨k→A
Z
1 1010 kkkk kkkk
1Akk
AND A,k
A&k→A
Z
1 1011 kkkk kkkk
1Bkk
XOR A,k
A⊕k→A
Z
1 1100 kkkk kkkk
1Ckk
RETL k
k → A,
[Top of Stack] → PC
1 1101 kkkk kkkk
1Dkk
SUB A,k
1 1110 0000 0001
1E01
INT
1 1111 kkkk kkkk
1Fkk
ADD A,k
k-A → A
PC+1 → [SP],
001H → PC
k+A → A
None
Z, C,DC
None
Z, C, DC
1
Note: This instruction is applicable to IOC5~IOC6, IOCB ~ IOCF only.
2
3
This instruction is not recommended for RF operation.
This instruction cannot operate under RF.
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 33
EM78P153A
8-Bit Microcontroller with OTP ROM
6 Timing Diagrams
AC Test Input/Output Waveform
2.4
2.0
0.8
TEST POINTS
2.0
0.8
0.4
AC Testing : Input is driven at 2.4V for logic "1" and 0.4V for logic "0". Timing measurements are
made at 2.0V for logic "1" and 0.8V for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
Figure 5-17 EM78P153A Timing Diagrams
34 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
7
Absolute Maximum Ratings
Items
Temperature under bias
Rating
0°C to 70°C
Storage temperature
-65°C to 150°C
Input voltage
-0.3V to +6.0V
Output voltage
-0.3V to +6.0V
Note: *These parameters are theoretical values and have not been tested.
8
Electrical Characteristics
8.1 DC Characteristics
Ta=25°C, VDD=5V ± 5%, VSS=0V
Symb
ol
FXT
ERC
IIL
VIH1
VIL1
Parameter
Crystal: VDD to 2.3V
Crystal: VDD to 3V
Crystal: VDD to 5V
ERC: VDD to 5V
Input Leakage Current for input pins
Input High Voltage (VDD=5V)
Input Low Voltage (VDD=5V)
VIHT1 Input High Threshold Voltage (VDD=5V)
VILT1 Input Low Threshold Voltage (VDD=5V)
VIHX1
VILX1
VIH2
VIL2
Clock Input High Voltage (VDD=5V)
Clock Input Low Voltage (VDD=5V)
Input High Voltage (VDD=3V)
Input Low Voltage (VDD=3V)
VIHT2 Input High Threshold Voltage (VDD=3V)
VILT2 Input Low Threshold Voltage (VDD=3V)
Condition
Min.
Two cycles with two clocks
Two cycles with two clocks
Two cycles with two clocks
DC
DC
DC
R: 5.1KΩ, C: 100 pF
VIN = VDD, VSS
Ports 5, 6
Ports 5, 6
/RESET, TCC
(Schmitt trigger)
/RESET, TCC
(Schmitt trigger)
OSCI
OSCI
Ports 5, 6
Ports 5, 6
/RESET, TCC
(Schmitt trigger)
/RESET, TCC
(Schmitt trigger)
OSCI
OSCI
VIHX2 Clock Input High Voltage (VDD=3V)
VILX2 Clock Input Low Voltage (VDD=3V)
Output High Voltage (Port 6)
VOH1
IOH = -12 mA
(P60~P63, P66~P67 are Schmitt trigger)
Output Low Voltage (P50~P53,
VOL1
IOL = 12 mA
P60~P63 P66~P67 are Schmitt trigger)
VOL2 Output Low Voltage (P64, P65)
IOL = 16.0 mA
Pull-high active,
IPH
Pull-high current
Input pin at VSS
Pull-low active,
IPL
Pull-low current
Input pin at VDD
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
Typ.
Max.
4.0
8.0
20.0
F±30% 940 F±30%
±1
2.0
0.8
Unit
MHz
MHz
MHz
kHz
μA
V
V
2.0
-
-
V
-
-
0.8
V
2.5
1.5
-
-
1.0
0. 4
V
V
V
V
1.5
-
-
V
-
-
0.4
V
1.5
-
-
0.6
V
V
2.4
-
-
V
-
-
0.4
V
-
-
0.4
V
–50
–100
–240
μA
20
50
120
μA
• 35
EM78P153A
8-Bit Microcontroller with OTP ROM
Symbol
Parameter
ISB1
Power down current
ISB2
Power down current
ICC1
Operating supply current
at two clocks (VDD=3V)
ICC2
Operating supply current
at two clocks (VDD=3V)
ICC3
Operating supply current at two
clocks (VDD=5.0V)
ICC4
Operating supply current
at two clocks (VDD=5.0V)
Condition
All input and I/O pins at VDD,
Output pin floating,
WDT disabled
All input and I/O pins at VDD,
Output pin floating,
WDT enabled
/RESET= 'High',
Fosc=32.768kHz (Crystal type,
CLKS="0"), Output pin floating,
WDT disabled
/RESET= 'High',
Fosc=32.768kHz (Crystal type,
CLKS="0"), Output pin floating,
WDT enabled
/RESET= 'High', Fosc=4 MHz
(Crystal type, CLKS="0"),
Output pin floating
/RESET= 'High', Fosc=10 MHz
(Crystal type, CLKS="0"),
Output pin floating
Min.
Typ.
Max.
Unit
-
-
1
μA
-
-
10
μA
15
15
30
μA
-
19
35
μA
-
-
2.0
mA
-
-
4.0
mA
Note: *These parameters are theoretical values and have not been tested.
8.2 AC Characteristics
Ta=25°C, VDD=5V ± 5%, VSS=0V
Symbol
Dclk
Ttcc
Parameter
Input CLK duty cycle
Instruction cycle time
(CLKS="0")
TCC input period
Tdrh
Device reset hold time
Trst
/RESET pulse width
Tins
*Twdt1
Watchdog timer period
*Twdt2
Watchdog timer period
*Twdt3
Watchdog timer period
*Twdt4
Watchdog timer period
Tset
Thold
Tdelay
Input pin setup time
Input pin hold time
Output pin delay time
Conditions
Crystal type
RC type
Ta = 25°C, Crystal,
SUT1, SUT0=1, 1
Min.
45
100
500
(Tins+20)/N*
Typ.
50
-
Max.
55
DC
DC
-
Unit
%
ns
ns
ns
17.6-30%
17.6
17.6+30%
ms
Ta = 25°C
Ta = 25°C
SUT1, SUT0=1,1
Ta = 25°C
SUT1, SUT0=1,0
Ta = 25°C
SUT1, SUT0=0,1
Ta = 25°C
SUT1, SUT0=0,0
Cload=20pF
2000
-
-
ns
17.6~30%
17.6
17.6+30%
ms
4.5+30%
4.5
4.5+30%
ms
288~30%
288
288+30%
ms
72~30%
72
72+30%
ms
-
0
20
50
-
ns
ns
ns
Note: These parameters are theoretical values and have not been tested.
The Watchdog Timer duration is determined by Option Code (Bit 6, Bit 5)
*N = selected prescaler ratio
*Twdt1: The Option word (SUT1, SUT0) is used to define the oscillator set-up time. In Crystal mode the
WDT time-out length is the same as set-up time (18ms).
*Twdt2: The Option word (SUT1, SUT0) is used to define the oscillator set-up time. In Crystal mode the
WDT time-out length is the same as set-up time (4.5ms).
*Twdt3: The Option word (SUT1, SUT0) is used to define the oscillator set-up time. In Crystal mode the
WDT time-out length is the same as set-up time (288ms).
*Twdt4: The Option word (SUT1, SUT0) is used to define the oscillator set-up time. In Crystal mode the
WDT time-out length is the same as set-up time (72ms).
36 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
8.3 Device Characteristics
The graphs provided in the following pages were derived based on a limited number of
samples and are shown here for reference only. The device characteristic illustrated
herein are not guaranteed for it accuracy. In some graphs, the data maybe out of the
specified warranted operating range.
P5/P6 Vih vs VDD
2
Vih (V)
1.5
70℃
25℃
1
0℃
0.5
0
2.3
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.50
Figure 8-1 VIH vs. VDD
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 37
EM78P153A
8-Bit Microcontroller with OTP ROM
P5/P6 Vil vs VDD
2
Vil (V)
1.5
70℃
25℃
1
0℃
0.5
0
2.3
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.50
Figure 8-2 VIL vs. VDD
Voh vs Ioh (VDD=3V)
0
-1
Ioh (mA)
-2
-3
70℃
-4
25℃
0℃
-5
-6
-7
-8
0.3
0.6
0.9
1.2
1.5
Voh (V)
1.8
2.1
2.4
2.7
Figure 8-3 VOH vs. IOH, VDD=3V
38 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
Voh vs Ioh (VDD=5V)
0
Ioh (mA)
-5
-10
70℃
25℃
0℃
-15
-20
-25
0.5
1.0
1.5
2.0
2.5
3.0
Voh (V)
3.5
4.0
4.5
Figure 8-4 VOH vs. IOH, VDD=5V
Vol vs Iol (VDD=3V)
40
35
30
Iol (mA)
25
70℃
20
25℃
0℃
15
10
5
0
0.3
0.6
0.9
1.2
1.5
Vol (V)
1.8
2.1
2.4
2.7
Figure 8-5 VOL vs. IOL, VDD=3V
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 39
EM78P153A
8-Bit Microcontroller with OTP ROM
Vol vs Iol (VDD=3V)
80
70
60
Iol (mA)
50
70℃
40
25℃
0℃
30
20
10
0
0.5
1.0
1.5
2.0
2.5
Vol (V)
3.0
3.5
4.0
4.5
Figure 8-6 VOL vs. IOL, VDD=3V
IPH vs Temperature for P60 (VDD=3V&5V)
100
90
80
IPH (uA)
70
60
50
3.0V
5.0V
40
30
20
10
0
-40
-20
0
25
50
Temperature(℃)
70
85
Figure 8-7 IPH of P60 vs. Temperature, VDD=3V&5V
40 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
IPL vs Temperature for P60 (VDD=3V&5V)
60
50
IPL(uA)
40
3.0V
5.0V
30
20
10
0
-40
-20
0
25
50
Temperature(℃)
70
85
Figure 8-8 IPL of P60 vs. Temperature , VDD=3V&5V
IPL vs Temperature for P50 (VDD=3V&5V)
60
50
IPL(uA)
40
3.0V
5.0V
30
20
10
0
-40
-20
0
25
50
Temperature(℃)
70
85
Figure 8-9 IPL of P50 vs. Temperature, VDD=3V&5V
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 41
EM78P153A
8-Bit Microcontroller with OTP ROM
ICC1 and ICC2 vs Temperature (VDD=5V)
45
40
35
Current(uA)
30
Typ. ICC1
Typ. ICC2
Max. ICC1
Max. ICC2
25
20
15
10
5
0
-40
-20
0
25
50
Temperature (℃)
75
85
Figure 8-10 ICC1 and ICC2 vs. Temperature, VDD=5V
ICC1 and ICC2 vsTemperature (VDD=3V)
25
Current(uA)
20
15
Typ. ICC1
Typ. ICC2
Max. ICC1
Max. ICC2
10
5
0
-40
-20
0
25
50
Temperature(℃)
70
85
Figure 8-11 ICC1 and ICC2 vs. Temperature, VDD=3V
42 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
ICC3 and ICC4 vs Temperature (VDD=5V)
3.5
3.0
Current (mA)
2.5
Typ. ICC3
Typ. ICC4
Max. ICC3
Max. ICC4
2.0
1.5
1.0
0.5
0.0
-40
-20
0
25
50
Temperature (℃)
70
85
Figure 8-12 ICC3 and ICC4 vs. Temperature, VDD=5V
ICC3 and ICC4 vs Temperature (VDD=3V)
1.8
1.6
1.4
Current(mA)
1.2
Typ. ICC3
Typ. ICC4
Max. ICC3
Max. ICC4
1.0
0.8
0.6
0.4
0.2
0.0
-40
-20
0
25
50
Temperature(℃)
70
85
Figure 8-13 ICC3 and ICC4 vs. Temperature, VDD=3V
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 43
EM78P153A
8-Bit Microcontroller with OTP ROM
ISB1 and ISB2 vs Temperature (VDD=5V)
10
9
8
Current(uA)
7
6
Typ. ISB1
Typ. ISB2
Max. ISB1
Max. ISB2
5
4
3
2
1
0
-40
-20
0
25
50
Temperature (℃)
70
85
Figure 8-14 ISB1 and ISB2 vs. Temperature, VDD=5V
ISB1 and ISB2 vs Temperature (VDD=3V)
1.8
1.6
Current(uA)
1.4
1.2
Typ. ISB1
Typ. ISB2
Max. ISB1
Max. ISB2
1
0.8
0.6
0.4
0.2
0
-40
-20
0
25
50
Temperature(℃)
70
85
Figure 8-15 ISB1 and ISB2 vs. Temperature, VDD=3V
44 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
Power Consumption in HXT Mode (4MHz)
3.0
2.5
I(mA)
2.0
max
min
1.5
1.0
0.5
0.0
2.2
2.6
3.0
3.4
4.2
3.8
VDD(V)
4.6
5.0
5.4
Figure 8-16 Power Consumption in HXT Mode (4MHz)
Power Consumption in LXT Mode(32.768Hz)
60
50
I(uA)
40
max
min
30
20
10
0
2.2
2.6
3.0
3.4
3.8
4.2
VDD(V)
4.6
5.0
5.4
Figure 8-17 Power Consumption in LXT Mode (32.768KHz)
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 45
EM78P153A
8-Bit Microcontroller with OTP ROM
WDT Timer Time Out in Normal, Crystal & IRC mode (4MHz)
35
30
Time(ms)
25
70℃
20
25℃
15
0℃
10
5
0
2.3
2.5
3.0
3.5
4.0
VDD(Volt)
4.5
5.0
5.5
Figure 8-18 WDT Timer Time Out in Normal, Crystal & IRC mode (4MHz)
WDT Timer Time Out When Sleep to Normal Mode, Crystal & IRC mode
(4MHz)
35
30
Time(ms)
25
20
70℃
25℃
15
0℃
10
5
0
2.3
2.5
3.0
3.5
4.0
VDD(Volt)
4.5
5.0
5.5
Figure 8-19 WDT Timer Time Out when Sleep to Normal, Crystal & IRC mode (4MHz)
46 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
P6 Wake-up Time when Sleep to Normal Mode with XTAL (4MHz)
35
30
Time(ms)
25
70℃
20
25℃
15
0℃
10
5
0
2.2
2.4
3.0
3.5
4.0
VDD(V)
4.5
5.0
5.5
Figure 8-20 P6 Wake-up Time when Sleep to Normal, Crystal mode (4MHz)
1
P6 Wake-up Time when Sleep to Normal Mode with IRC (4MHz)
0.9
0.8
Time(us)
0.7
0.6
70℃
0.5
25℃
0.4
0℃
0.3
0.2
0.1
0
2.2
2.4
3.0
3.5
4.0
VDD(V)
4.5
5.0
5.5
Figure 8-21 P6 Wake-up Time when Sleep to Normal, IRC mode (4MHz)
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 47
EM78P153A
8-Bit Microcontroller with OTP ROM
Power On Reset Time vs VDD in Normal, Crystal & IRC Mode (4MHz)
35
30
Time(ms)
25
20
70℃
25℃
15
0℃
10
5
0
2.3
2.5
3.0
3.5
4.0
VDD(V)
4.5
5.0
5.5
Figure 8-22 Power on Reset Time when Sleep to Normal, Crystal mode (4MHz)
IRC OSC Frequency
1.2
Frequency(MHz)
1
0.8
[email protected]
[email protected]
[email protected]
[email protected]
0.6
0.4
0.2
0
-40
-20
0
25
50
Temperature (℃)
70
85
Figure 8-23 IRC OSC Frequency 1
48 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
IRC OSC Frequency
9
8
Frequency(MHz)
7
6
[email protected]
[email protected]
[email protected]
[email protected]
5
4
3
2
1
0
-40
-20
0
25
50
Temperature (℃)
70
85
Figure 8-24 IRC OSC Frequency 2
ERC OSC Frequency vs Temp.(Cext=100pF, Rext=5.1K)
1.1
1.08
1.06
Frequency(MHz)
1.04
1.02
3V
5V
1
sa
0.98
0.96
0.94
0.92
0.9
-40
-20
0
25
50
Temperature(℃)
70
85
Figure 8-25 ERC OSC Frequency vs. Temp (Cext=100Pf, Rext=5.1K)
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 49
EM78P153A
8-Bit Microcontroller with OTP ROM
APPENDIX
A Package Type
OTP MCU
Package Type
Pin Count
Package Size
EM78P153AD14J
DIP
14
300 mil
EM78P153ASO14J
SOP
14
150 mil
These are Green products which do not contain hazardous substances and comply
with the third edition of Sony SS-00259 standard.
Pb content is less than 100ppm and complies with Sony specifications.
Part No.
Electroplate type
Pure Tin
Ingredient (%)
Sn: 100%
Melting point (°C)
50 •
EM78P153AS/J
232°C
Electrical resistivity (μΩ-cm)
11.4
Hardness (hv)
8~10
Elongation (%)
>50%
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
B Package Information
„
14-Lead Plastic Dual in line (PDIP) — 300 mil
Figure B-1a EM78P15A 14-Lead PDIP Package Type
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 51
EM78P153A
8-Bit Microcontroller with OTP ROM
„
14-Lead Plastic Dual in line (SOP) — 150 mil
Figure B-1b EM78P153A 14-Lead SOP Package Type
52 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
C Application Notes
ELAN MCU Note 1
During OTP programming of the EM78P153A, a WDT time-out (if enabled) or reset pin
input low will cause the device to reset. The device reset will result to programming
error of stack function.
The program must include the initial stack program, because the stack pointer of the
EM78P153A will not point to zero when a WDT time-out (if enabled) or reset pin input
low occurs.
The initial stack program will make the EM78P153A stack pointer point to zero only
when the stack functions normally during OTP programming of the EM78P153A.
When one of the following events occurs, the initial stack program must be
included in the OTP programming of the EM78P153A:
1) WDT time-out
2) Reset pin input low
3) CALL or RET instruction is used
4) Interrupt function is used
Take Note of the following:
1. Initial stack program must insert Address 0x00D~0x0FF in the OTP program. Any
address outside the range will result to stack operation error. You must not modify
the initial stack program.
2. The program requires two SRAM registers for initial stack program use. These
registers are automatically removed after the initial stack program execution is
completed.
3. Stack Initial Program needs 40 words
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 53
EM78P153A
8-Bit Microcontroller with OTP ROM
Initial Stack Program
L_SADR == 0x21
SADR == 0x2F
/* save last stack address */
/* save current stack address*/
ORG 0X0
/* -------------- calibration stack pointer ---------------- */
JMP CAL_SP
CAL_SP:
CLR L_SADR ; CLEAR L_SADR
CLR SADR ; CLEAR SADR
CALL l1
MOV A, 0x2 ; Store Program Counter
JMP CK_SP
l1:
CALL l2
MOV A, 0x2 ; Store Program Counter
JMP CK_SP
l2:
CALL l3
MOV A, 0x2 ; Store Program Counter
JMP CK_SP
l3:
CALL l4
MOV A, 0x2 ; Store Program Counter
JMP CK_SP
l4:
CALL l5
MOV
A, 0x2 ; Store Program Counter
JMP CK_SP
l5:
CALL l6
MOV A, 0x2 ; Store Program Counter
JMP CK_SP
l6:
CALL l7
MOV A, 0x2 ; Store Program Counter
JMP CK_SP
l7:
CALL l8
MOV A, 0x2 ; Store Program Counter
JMP CK_SP
l8:
RET
CK_SP:
MOV SADR, A
;
SUB A, L_SADR ; A = (diff_value) = L_SADR – SADR
JBC 0x3, 0
;
JMP DIFF_LOOP ; C = 1,JMP DIFF_LOOP
Compliment:
; C = 0, A (diff_value) do 2’s compliment
54 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
EM78P153A
8-Bit Microcontroller with OTP ROM
/*********************************************************/
/* 2's compliment
*/
/*********************************************************/
XOR A, @0XFF
ADD A, @0X01
DIFF_LOOP:
XOR A, @0x0C ;diff_value == 0xc
JBC 0x3, 2
;
CALL MAIN
; Z = 1, CALL MAIN
/*label of customer's 1st code*/ ;Z = 0, L_SADR <= SADR, RET STACK
LEVEL*/
MOV A, SADR
MOV L_SADR, A
RET
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)
• 55
EM78P153A
8-Bit Microcontroller with OTP ROM
56 •
Product Specification (V1.3) 04.22.2011
(This specification is subject to change without further notice)