EM78P154N 8-Bit Microcontroller with OTP ROM Product Specification DOC. VERSION 1.1 ELAN MICROELECTRONICS CORP. March 2007 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2006~2007 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: Hong Kong: USA: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Elan (HK) Microelectronics Corporation, Ltd. Elan Information Technology Group (USA) Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon, HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 [email protected] 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8225 Fax: +1 408 366-8220 Shenzhen: Shanghai: Elan Microelectronics Shenzhen, Ltd. Elan Microelectronics Shanghai, Ltd. 3F, SSMEC Bldg., Gaoxin S. Ave. I Shenzhen Hi-tech Industrial Park (South Area) Shenzhen 518057 CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 21 5080-3866 Fax: +86 21 5080-4600 Contents Contents 1 General Description.....................................................................................................1 2 3 4 1.1 Comparison between EM78P154N, EM78P159N, and EM78P157N ................ 1 Features ........................................................................................................................1 Pin Assignment ............................................................................................................2 Pin Description.............................................................................................................2 5 4.1 EM78P154NP and EM78P154NM ...................................................................... 2 Function Description...................................................................................................3 5.1 Operational Registers .......................................................................................... 3 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8 5.1.9 5.1.10 5.2 R0 (Indirect Addressing Register)....................................................................... 3 R1 (Time Clock /Counter) ................................................................................... 3 R2 (Program Counter) & Stack........................................................................... 4 R3 (Status Register) ........................................................................................... 5 R4 (RAM Select Register) .................................................................................. 6 R5 ~ R6 (Port 5 ~ Port 6).................................................................................... 6 RD (Manual Calibration Register)....................................................................... 6 RE (Wake Up Control Register) ......................................................................... 7 RF (Interrupt Status Register)............................................................................. 8 R10 ~ R3F .......................................................................................................... 8 Special Function Registers .................................................................................. 8 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 A (Accumulator) .................................................................................................. 8 CONT (Control Register) .................................................................................... 8 IOC5 ~ IOC6 (I/O Port Control Register)............................................................ 9 IOCA (Prescaler Counter Register) .................................................................... 9 IOCB (Pull-down Control Register)................................................................... 10 IOCC (Open-drain Control Register) ................................................................ 10 IOCD (Pull-high Control Register) .................................................................... 10 IOCE (WDT Control Register) ...........................................................................11 IOCF (Interrupt Mask Register) ........................................................................ 12 5.3 TCC/WDT & Prescaler....................................................................................... 12 5.4 I/O Ports ............................................................................................................. 13 5.4.1 5.5 Usage of Port 6 Input Change Wake-up/Interrupt Function ............................. 15 Reset and Wake-up ........................................................................................... 16 5.5.1 5.5.2 5.5.3 Reset ................................................................................................................ 16 Summary of Registers Initialized Values .......................................................... 19 Status of RST, T, and P of the Status Register ................................................. 21 5.6 Interrupt.............................................................................................................. 22 5.7 Oscillator ............................................................................................................ 23 Product Specification (V1.1) 03.29.2007 • iii Contents 5.7.1 5.7.2 5.7.3 5.7.4 5.8 Code Option Register ........................................................................................ 27 5.8.1 5.8.2 5.8.3 5.9 Oscillator Modes ............................................................................................... 23 Crystal Oscillator/Ceramic Resonators (Crystal) .............................................. 24 External RC Oscillator Mode ............................................................................ 25 Internal RC Oscillator Mode ............................................................................. 26 Code Option Register (Word 0) ........................................................................ 27 Customer ID Register (Word 1) ........................................................................ 28 Customer ID Register (Word 2) ........................................................................ 29 Power-on Considerations .................................................................................. 29 5.10 External Power-on Reset Circuit ....................................................................... 29 5.11 Residue-Voltage Protection ............................................................................... 30 5.12 Instruction Set .................................................................................................... 31 6 7 5.13 Timing Diagrams ................................................................................................ 34 Absolute Maximum Ratings .....................................................................................35 Electrical Characteristics..........................................................................................35 7.1 DC Characteristic............................................................................................... 35 7.2 AC Characteristic ............................................................................................... 36 APPENDIX A B C Package Type .............................................................................................................37 Package Information .................................................................................................37 Quality Assurance and Reliability............................................................................39 C.1 Reliability Test .................................................................................................... 39 C.2 Power-on Reset and Vdd Voltage Drop/Rise Timing Test................................. 40 C.3 Address Trap Detect .......................................................................................... 40 Specification Revision History Doc. Version iv • Revision Description Date 1.0 Initial Release Version 2006/05/19 1.1 Modified the operation voltage of Section 2 2007/03/29 Product Specification (V1.1) 03.29.2007 EM78P154N 8-Bit Microcontroller with OTP ROM 1 General Description EM78P154N is an 8-bit microprocessor designed and developed with low-power, high-speed CMOS technology. It has on-chip 1K×13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides three Protection bits to prevent intrusion of user’s code in the OTP memory as well as from unwanted external accesses. Eight option bits are also available to meet user’s application requirements. With its enhanced OTP-ROM features, the EM78P154N provides a convenient way of developing and verifying user’s programs. Moreover, this OTP device offers the advantages of easy and effective program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his development code. 1.1 Comparison between EM78P154N, EM78P159N, and EM78P157N To find out the similarities and differences between EM78P154N, EM78P159N, and EM78P157N, refer to the following link: AN-001 EM78P154N/159N Introduction and Comparison with EM78P157N 2 Features CPU configuration • 1K×13 bits on chip ROM • 48×8 bits on-chip registers (SRAM, general purpose registers) • 5-level stacks for subroutine nesting Fast set-up time requires only 2ms in high Crystal and 32 CLKS in IRC mode from wake up to operating mode Peripheral configuration • • Less than 2 mA at 5V/4MHz • Typically 20 μA, at 3V/32kHz • Typically 1 μA, during sleep mode I/O port configuration • 2 bidirectional I/O ports • 4 Programmable pull-high I/O pins • 6 programmable pull-down I/O pins • 4 programmable open-drain I/O pins • 2 programmable R-option pins One security register to prevent intrusion of OTP memory codes One configuration register to accommodate user’s requirements Two clocks per instruction cycle Power down (Sleep) mode Operating voltage range: • 2.1V~5.5V at 0°C~70°C • 2.3V~5.5V at -40°C~85°C Operating frequency range (base on 2 clocks): • Crystal mode: DC~20MHz @ 5V, DC~8MHz @ 3V, DC~4MHz @ 2.1V • ERC mode: DC~4MHz @ 5V~2.1V • IRC mode: 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt Three available interrupts: • TCC overflow interrupt • Input-port status changed interrupt (wake-up from sleep mode) • External interrupt Special features • Programmable free running watchdog timer • Single instruction cycle commands Package types: Oscillation mode : 4MHz, 8MHz, 1MHz, 455kHz • 14-pin DIP 300mil : EM78P154NP Process deviation : Typ±3%, Max±5% • 14-pin SOP 150mil : EM78P159NM Temperature deviation : ±5% (-40°C~85°C ) Frequency deviation : ±4.5% after auto trimming (based on Vdd = 5V, Ta = 25°C ) The transient point of system frequency between HXT and LXT is 400kHz. All these four main frequencies can be trimmed by programming with four calibrated bits in the ICE159N Simulator. OTP is auto trimmed by ELAN Writer (DWTR) Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) •1 EM78P154N 8-Bit Microcontroller with OTP ROM 3 Pin Assignment P52 14 P51 13 P50 12 P56/OSCI 11 P55/OSCO 10 VDD 9 P67 8 P66 P53 2 P54/TCC 3 /RESET 4 Vss 5 P60/INT 6 P61 7 EM78P154NP EM78P154NM 1 Figure 3-1a EM78P154NP/M Pin Assignment 4 Pin Description 4.1 EM78P154NP and EM78P154NM Symbol Pin No. Type Function P60, P61 P66, P67 7, 8 13, 14 I/O P60 ~ P67 are bi-directional I/O pins. These can be pulled-high or can be open-drain by software programming. P60 ~ P61 can also be pulled-down by software P56/OSCI 16 I/O General-purpose I/O pin Crystal type: Crystal input terminal or external clock input pin ERC type: RC oscillator input pin General-purpose I/O pin Crystal type: Output terminal for crystal oscillator or external clock input pin RC type: Instruction clock output External clock signal input P55/OSCO 15 I/O P54/TCC 3 I/O P50 ~ P53 17, 18, 1, 2 I/O /RESET 4 I Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain in reset condition. /INT 6 I External interrupt pin triggered by a falling edge VDD 14 - Power supply VSS 5 - Ground General-purpose I/O pin 2• Real time clock/counter (with Schmitt trigger input pin), must be tied to VDD or VSS if not in use. P50 ~ P53 are bidirectional I/O pins, can also be pulled-down by software P50 and P51 can also be defined as R-option pins Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM 5 Function Description OSCO OSCI /RESET TCC WDT Timer Oscillator/Timing Control /INT ROM Prescaler R2 Stack IOCA Interrupt Controller RAM R4 ALU Instruction Register R3 R1 (TCC) Instruction Decoder ACC DATA & CONTROL BUS IOC6 I/O Port 6 R6 P62 P63 P64 P65 P60//INT P61 IOC5 R5 I/O Port 5 P66 P67 P50 P51 P52 P53 P54 P55 P56 Figure 5-1 Function Block Diagram 5.1 Operational Registers 5.1.1 R0 (Indirect Addressing Register) R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4). 5.1.2 R1 (Time Clock /Counter) Incremented by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock. Writable and readable as any other registers. Defined by resetting PAB (CONT-3). The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset. The contents of the prescaler counter will be cleared only when TCC register is written with a value. Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) •3 EM78P154N 8-Bit Microcontroller with OTP ROM 5.1.3 R2 (Program Counter) & Stack Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in the following figure. PC (A9 ~ A0) 000H 008H User Memory Space Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5 Reset Vector Interrupt Vector On-chip Program Memory 3FFH Figure 5-2 Program Counter Organization The configuration structure generates 1024×13 bits on-chip OTP ROM addresses to the relative programming instruction codes. One program page is 1024 words long. R2 is set as all "0" when under RESET condition. "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to go to any location within a page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. "RET" ("RETLk", "RETI") instruction loads the program counter with the contents of the top-level stack. "ADD R2, A" allows a relative address to be added to the current PC, and the ninth and succeeding bits of the PC will increase progressively. "MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged. Any instruction (except “ADD R2,A”) that is written to R2 (e.g., "MOV R2, A", "BC R2, 6",⋅⋅⋅⋅⋅) will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to remain unchanged. All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would change the contents of R2. Such instruction will need one more instruction cycle. 4• Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM The Data Memory Configuration is as follows: Address R PAGE Registers IOC PAGE Registers 00 01 R0 R1 (IAR) (TCC) Reserve CONT 02 03 R2 R3 (PC) (Status) Reserve Reserve 04 05 R4 R5 (RSR) (Port 5) Reserve IOC5 (I/O Port Control Register) 06 R6 (Port 6) IOC6 (I/O Port Control Register) 07 Reserve Reserve 08 Reserve Reserve 09 Reserve Reserve 0A Reserve IOCA (Prescaler Control Register) 0B Reserve IOCB (Pull-down Register) 0C Reserve IOCC (Open-drain Control) 0D RD (Only for simulator) IOCD (Pull-high Control Register) 0E 0F 10 ︰ 3F RE RF (Wake-up control) (Interrupt Status) IOCE IOCF (WDT Control Register) (Interrupt Mask Register) (Control Register) General Registers 5.1.4 R3 (Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GP2 GP1 GP0 T P Z DC C Bit 0 (C): Carry flag Bit 1 (DC): Auxiliary carry flag Bit 2 (Z): Zero flag Set to "1" if the result of an arithmetic or logic operation is zero. Bit 3 (P): Power down bit Set to “1” during power on or by a "WDTC" command; and reset to “0” by a "SLEP" command. Bit 4 (T): Time-out bit Set to “1” with the "SLEP" and "WDTC" commands, or during power up; and reset to “0” by WDT time-out. Bits 5 ~7 (GP0 ~ 2): General-purpose read/write bits Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) •5 EM78P154N 8-Bit Microcontroller with OTP ROM 5.1.5 R4 (RAM Select Register) Bits 0 ~ 5: are used to select registers (Address: 00~06, 0F~3F) in the indirect addressing mode. Bits 6 ~ 7: Not used (read only), but need to set to “1” all the time to avoid possible error. The “Z” flag of R3 will be set to “1” when the R4 content is equal to “3F.” When R4=R4+1, the R4 content will select “R0.” 5.1.6 R5 ~ R6 (Port 5 ~ Port 6) R5 and R6 are I/O registers. Port 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - P56 P55 P54 P53 P52 P51 P50 Bit 7: Not used. Port 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P66 P65 - - - - P61 P60 Bits 2 ~ 5: Not used. 5.1.7 RD (Manual Calibration Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EM78P154N × × × × × × × × ICE159N Simulator - - - - C3 C2 C1 C0 In EM78P154N, the register does not exist in actual chip. In ICE159N Simulator, C3 ~ C0 are IRC calibration bits in MCIRC mode. 6• Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM Bit 3 ~ Bit 0 (C3 ~ C0): calibration bits in internal RC mode C3 C2 C1 C0 Cycle Time (ns) Frequency (MHz) 0 0 0 0 390.6 2.56 0 0 0 1 365.0 2.74 0 0 1 0 342.5 2.92 0 0 1 1 322.6 3.1 0 1 0 0 304.9 3.28 0 1 0 1 289.0 3.46 0 1 1 0 274.7 3.64 0 1 1 1 261.8 3.82 1 1 1 1 250.0 4.00 1 1 1 0 239.2 4.18 1 1 0 1 229.4 4.36 1 1 0 0 220.3 4.54 1 0 1 1 211.9 4.72 1 0 1 0 204.1 4.9 1 0 0 1 196.7 5.08 1 0 0 0 190.1 5.26 NOTE: 1. Frequency values shown are theoretical and taken from an instance of a high frequency mode. Hence they are shown for reference only. Definite values will depend on the actual process. 2. Similar way of calculation is also applicable for Low Frequency mode. Bits 4 ~ 7: Not used 5.1.8 RE (Wake-up Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - - ICWE - Bits 0: Not used. Bit 1 (ICWE): Port 6 input status change wake-up enable bit 0 = Disable Port 6 input status change wake-up 1 = Enable Port 6 input status change wake-up Bits 2 ~ 7: Not used. Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) •7 EM78P154N 8-Bit Microcontroller with OTP ROM 5.1.9 RF (Interrupt Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - EXIF ICIF TCIF Note: “ 1 ” means with interrupt request “ 0 ” means no interrupt occurs Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows. Reset by software. Bit 1 (ICIF): Port 6 input status change interrupt flag. Set when Port 6 input changes. Reset by software. Bit 2 (EXIF): External interrupt flag. Set by a falling edge on /INT pin. Reset by software. Bits 3 ~ 7: Not used RF can be cleared by instruction but cannot be set. IOCF is the interrupt mask register. NOTE The result of reading RF is the "logic AND" of RF and IOCF. 5.1.10 R10 ~ R3F These are all 8-bit general-purpose registers. 5.2 Special Function Registers 5.2.1 A (Accumulator) Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register. 5.2.2 CONT (Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - /INT TS TE PSRE PSR2 PSR1 PSR0 Bit 0 (PSR0) ~ Bit 2 (PSR2): TCC prescaler bits 8• PSR2 PSR1 PSR0 TCC Rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM Bit 3 (PSRE): Prescaler enable bit for TCC 0 = prescaler disabled bit, TCC rate is 1:1 1 = prescaler enabled bit, TCC rate is set as Bit 2~Bit 0 Bit 4 (TE): TCC signal edge 0 = increment if the transition from low to high takes place on the TCC pin 1 = increment if the transition from high to low takes place on the TCC pin Bit 5 (TS): TCC signal source 0 = internal instruction cycle clock, P54 is a bidirectional I/O pin 1 = transition on TCC pin Bit 6 (/INT): Interrupt enable flag 0 = masked by DISI or hardware interrupt 1 = enabled by ENI/RETI instructions Bit 7: Not used CONT register is both readable and writable. 5.2.3 IOC5 ~ IOC6 (I/O Port Control Register) 0 = defines the relative I/O pin as output 1 = puts the relative I/O pin into high impedance Port 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - IOC56 IOC55 IOC54 IOC53 IOC52 IOC51 IOC50 Bit 7 Not used Port 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC66 IOC65 - - - - IOC61 IOC60 Bits 2 ~ 5 Not used. IOC5 and IOC6 registers are both readable and writable. 5.2.4 IOCA (Prescaler Counter Register) The IOCA register is readable. The value of IOCA is equal to the contents of the Prescaler counter. It is a Down counter register. Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) •9 EM78P154N 8-Bit Microcontroller with OTP ROM 5.2.5 IOCB (Pull-down Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - /PD5 /PD4 /PD3 /PD2 /PD1 /PD0 Bit 0 (/PD0): Control bit is used to enable the pull-down of P50 pin. 0 = Enable internal pull-down 1 = Disable internal pull-down Bit 1 (/PD1): Control bit used to enable the P51 pull-down pin Bit 2 (/PD2): Control bit used to enable the P52 pull-down pin Bit 3 (/PD3): Control bit used to enable the P53 pull-down pin Bit 4 (/PD4): Control bit used to enable the P60 pull-down pin Bit 5 (/PD5): Control bit used to enable the P61 pull-down pin Bits 6 ~ 7): Not used The IOCB Register is both readable and writable. 5.2.6 IOCC (Open-drain Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OD7 OD6 - - - - OD1 OD0 Bit 0 (OD0): Control bit used to enable the P60 open-drain pin 0 = Disable open-drain output 1 = Enable open-drain output Bit 1 (OD1): Control bit used to enable the P61 open-drain pin Bit 6 (OD6): Control bit used to enable the P66 open-drain pin Bit 7 (OD7): Control bit used to enable the P67 open-drain pin Bits 2~5: Not used The IOCC Register is both readable and writable. 5.2.7 IOCD (Pull-high Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /PH7 /PH6 - - - - /PH1 /PH0 Bit 0 (/PH0): Control bit used to enable the P60 pull-high pin 0 = Enable internal pull-high 1 = Disable internal pull-high Bit 1 (/PH1): Control bit used to enable the P61 pull-high pin Bit 6 (/PH6): Control bit is used to enable the pull-high of P66 pin. Bit 7 (/PH7): Control bit is used to enable the pull-high of P67 pin. Bits 2~5: Not used The IOCD Register is both readable and writable. 10 • Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM 5.2.8 IOCE (WDT Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTE EIS - ROC PSWE PSW2 PSW1 PSW0 Bit 7 (WDTE): Control bit used to enable the Watchdog timer. 0 = Disable WDT 1 = Enable WDT WDTE is both readable and writable. Bit 6 (EIS): Control bit is used to define the function of P60 (/INT) pin. 0 = P60, bidirectional I/O pin. 1 = /INT, external interrupt pin. In this case, the I/O control bit of P60 (Bit 0 of IOC6) must be set to "1." When EIS is "0," the path of /INT is masked. When EIS is "1," the status of /INT pin can also be read by way of reading Port 6 (R6). See Figure 4-4a under Section 4.4 for reference. EIS is both readable and writable. Bit 5: Not used Bit 4 (ROC): ROC is used for the R-option Setting the ROC to "1" will enable the status of R-option pins (P50∼P51) that are read by the controller. Clearing the ROC will disable the R-option function. If the R-option function is selected, you must connect the P51 pin or/and P50 pin to VSS with a 430KΩ external resistor (Rex). If the Rex is connected/disconnected, the status of P50 (P51) is read as "0" / "1." Refer to Figure 4-5 under Section 4.4 for reference. Bit 3 (PSWE): Prescaler enable bit for WDT 0 = prescaler disable bit, WDT rate is 1:1 1 = prescaler enable bit, WDT rate is set as Bit 4~Bit 2 Bit 2 (PSW2) ~ Bit 0 (PSW0): WDT prescaler bits PSW2 PSW1 PSW0 WDT Rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) • 11 EM78P154N 8-Bit Microcontroller with OTP ROM 5.2.9 IOCF (Interrupt Mask Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - EXIE ICIE TCIE Bit 0 (TCIE): TCIF interrupt enable bit 0 = disable TCIF interrupt 1 = enable TCIF interrupt Bit 1 (ICIE): ICIF interrupt enable bit 0 = disable ICIF interrupt 1 = enable ICIF interrupt Bit 2 (EXIE): EXIF interrupt enable bit 0 = disable EXIF interrupt 1 = enable EXIF interrupt Bits 3~7: Not used Individual interrupt is enabled by setting its associated control bit in the IOCF to "1." Global interrupt is enabled by the ENI instruction and disabled by the DISI instruction. Refer to Figure 5-7 in Section 5.6 for further reference. The IOCF register is both readable and writable. 5.3 TCC/WDT & Prescaler There are two 8-bit counters available as prescalers for TCC and WDT respectively. The PSR0 ~ PSR2 bits of the CONT register are used to determine the ratio of the prescaler of TCC, and the PWR0 ~ PWR2 bits of the IOCE register are used to determine the prescaler of WDT. The prescaler (PSR0 ~ PSR2) will be cleared by the instruction each time it writes to TCC. The WDT and prescaler will be cleared by the “WDTC” and “SLEP” instructions. 1 R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or external clock input (edge selectable from TCC pin). If TCC signal is sourced from internal clock, TCC will increase by 1 at every instruction cycle (without prescaler). CLK=Fosc/2 or CLK=Fosc/4 application is determined by the CODE Option bit CLK status. CLK=Fosc/2 is used if CLK bit is "0," and CLK=Fosc/4 is used if CLK bit is "1." If TCC signal source comes from external clock input, TCC is increased by 1 at every falling edge or rising edge of TCC pin. The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even when the oscillator driver has been turned off (i.e., in Sleep mode). During normal operation or Sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during Normal mode by software programming. Refer to WDTE bit of IOCE register in Section 1 4.2.8. Without prescaler, the WDT time-out period is approximately 18 ms (default). Vdd = 5V, set up time period = 16.8ms ± 30% Vdd = 3V, set up time period = 18ms ± 30% 12 • Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM 5.4 I/O Ports The I/O registers, both Port 5 and Port 6, are bi-directional tri-state I/O ports. Port 6 can be pulled high internally by software. In addition, Port 6 can also features an open-drain output through software and an Input status change interrupt (or wake-up) function. P50 ~ P53 and P60 ~ P61 pins can be pulled down by software. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC6). P50~P51 are the R-option pins enabled by setting the ROC bit in the IOCE register to “1.” When the R-option function is used, it is recommended that P50 ~ P51 are used as output pins. When R-option is in enable state, P50 ~ P51 must be programmed as input pins. In R-option mode, the current/power consumption by Rex should be taken into the consideration to promote energy conservation. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5 and Port 6 are shown in the following figures (Figures 5-3, 5-4a, 5-4b, & 5-5). PCRD Q _ Q PORT P R C L Q P R _ Q C L D CLK PCW R IO D D C LK PDW R PDRD 0 1 M U X Note: Pull-down is not shown in the figure. Figure 5-3 I/O Port and I/O Control Register for Port 5 Circuit Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) • 13 EM78P154N 8-Bit Microcontroller with OTP ROM PC R D Q _ Q P D R C L K C L PC W R Q _ Q P R D C L K C L PD W R P 6 0 /I N T PO R T B it 6 o f I O C E P R C L K C L D 0 Q M U X 1 _ Q IO D T 10 PD R D P R C L K C L D Q _ Q IN T Note: Pull-high (down) and open-drain are not shown in the figure. Figure 5-4a I/O Port and I/O Control Register for P60 (/INT) Circuit PCRD P61~P67 PORT 0 1 Q _ Q P R D CLK C L PCWR Q _ Q P R D CLK C L PDWR IOD M U X TIN PDRD P R CLK C L D Q _ Q Note: Pull-high (down) and open-drain are not shown in the figure. Figure 5-4b I/O Port and I/O Control Register for P61~P67 Circuit 14 • Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM IOCE.1 D P R Q CLK Interrupt _ C Q L RE.1 ENI Instruction P D R Q T10 T11 CLK _ C Q L P Q R D CLK _ Q C L T17 DISI Instruction Interrupt (Wake-up from SLEEP) /SLEP Next Instruction (Wake-up from SLEEP) Figure 5-4c I/O Port 6 with Input Change Interrupt/Wake-up Block Diagram 5.4.1 Usage of Port 6 Input Change Wake-up/Interrupt Function Usage of Port 6 Input Status Changed Wake-up/Interrupt (I) Wake-up (a) Before Sleep (II) Wake-up and interrupt (a) Before Sleep 1. Disable WDT 1. Disable WDT 2. Read I/O Port 6 (MOV R6,R6) 2. Read I/O Port 6 (MOV R6,R6) 3. Execute "ENI" or "DISI" 3. Execute "ENI" or "DISI" 4. Enable wake-up bit (Set RE ICWE =1) 4. Enable wake-up bit (Set RE ICWE =1) 5. Execute "SLEP" instruction 5. Enable interrupt (Set IOCF ICIE =1) (b) After wake-up → Next instruction 6. Execute "SLEP" instruction (b) After wake-up 1. IF "ENI" → Interrupt vector (008H) 2. IF "DISI" → Next instruction (III) Interrupt (a) Before Port 6 pin change 1. Read I/O Port 6 (MOV R6,R6) 2. Execute "ENI" or "DISI" 3. Enable interrupt (Set IOCF0 ICIE =1) (b) After Port 6 pin changed (interrupt) 1. IF "ENI" → Interrupt vector (008H) 2. IF "DISI" → Next instruction Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) • 15 EM78P154N 8-Bit Microcontroller with OTP ROM PCRD ROC VCC Q P R Q C L Q P R Q C L Weakly Pull-up PORT D PCWR CLK D IOD PDWR PDRD 0 1 Rex* M U X *The Rex is 430K ohm external resistor Figure 5-5 I/O Port with R-option (P50,P51) Circuit 5.5 Reset and Wake-up 5.5.1 Reset A Reset is initiated by one of the following events: 1) Power on reset 2) /RESET pin input "low" 3) WDT time-out (if enabled) 2 The device is kept under reset condition for a period of approximately 18ms (one oscillator start-up timer period) after a reset is detected. And if the /Reset pin goes “low” or WDT time-out is active, a reset is generated. Once a Reset occurs, the following functions are performed: 2 The oscillator is running, or will be started. The Program Counter (R2) is set to all "0." All I/O port pins are configured as input mode (high-impedance state) Vdd = 5V, set up time period = 16.8ms ± 30% Vdd = 3V, set up time period = 18ms ± 30% 16 • Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM The Watchdog timer and prescaler are cleared. When power is switched on, the upper 3 bits of R3 are cleared. The bits of the CONT register are set to all "1" except for Bit 6 (INT flag). The bits of the IOCA register are set to all "1." The bits of the IOCB register are set to all "1." The IOCC register is cleared. The bits of the IOCD register are set to all "1." Bit 7 of the IOCE register is set to "1," and Bits 4 and 6 are cleared. Bits 0 ~ 2 of RF and Bits 0 ~ 2 of IOCF registers are cleared. The Sleep (power down) mode is asserted by executing the “SLEP” instruction. While entering Sleep mode, WDT (if enabled) is cleared but keeps on running. The controller can be awakened by1) External reset input on /RESET pin, 2) WDT time-out (if enabled) 3) Port 6 input status change (if enabled) The first two cases will cause the EM78P154N to reset. The T and P flags of R3 are used to determine the source of the reset (wake-up). The last case is considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) decides whether or not the controller branches to the interrupt vector following wake-up. If ENI is executed before SLEP, the instruction will begin to execute from the address 008H after wake-up. If DISI is executed before SLEP, the operation will restart from the succeeding instruction right next to SLEP after wake-up. Wake up time is dependent on oscillator mode. In RC mode, the reset time is 32 clocks, and in High Crystal mode, reset time is 2ms and 32 clocks. In low Crystal mode, the reset time is 500ms. This is applicable only for stable oscillator. Only one of Cases 2 and 3 can be enabled before going into the Sleep mode. That is, [a] if Port 6 Input Status Change Interrupt is enabled before SLEP, WDT must be disabled by software. However, the WDT bit in the option register remains enabled. Hence, the EM78P154N can be awakened only by Case 1 or Case 3. [b] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be disabled. Hence, the EM78P154N can be awakened only by Case 1 or Case 2. Refer to Section 5.6, Interrupt for further details. Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) • 17 EM78P154N 8-Bit Microcontroller with OTP ROM If Port 6 Input Status Change Interrupt is used to wake-up the EM78P154N (Case [a] above), the following instructions must be executed before SLEP: WDTC ; Clear WDT and prescaler MOV A, @0xxxxxxxb ; Disable WDT and Select WDT prescaler IOW IOCE MOV R6, R6 ; Read Port 6 BS RE,1 ; Enable wake up control bit MOV A, @00000x1xb ; Enable Port 6 input change interrupt IOW IOCF ENI (or DISI) ; Enable (or disable) global interrupt SLEP ; Sleep NOP 18 • Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM 5.5.2 Summary of Registers Initialized Values Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C56 C55 C54 C53 C52 C51 C50 Power-on × U 1 1 1 1 1 1 1 /RESET and WDT U 1 1 1 1 1 1 1 Wake-up from Pin Change U P P P P P P P C67 1 C66 1 × U × U × U × U C61 1 C60 1 /RESET and WDT Wake-up from Pin Change 1 P 1 P U U U U U U U U 1 P 1 P Bit Name Power-on × 1 /INT 0 TS 1 TE 1 /RESET and WDT Wake-up from Pin Change 1 P 0 P 1 P 1 P 1 P 1 P 1 P 1 P Bit Name - - - - - - - - Power-on U U U U U U U U /RESET and WDT P P P P P P P P Wake-up from Pin Change P P P P P P P P Bit Name - - - - - - - - Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Bit Name N/A N/A N/A 0x00 0x01 0x02 0x03 0x04 0x05 0x06 IOC5 IOC6 CONT R0 (IAR) R1 (TCC) R2 (PC) R3 (SR) R4 (RSR) P5 P6 Bit Name Power-on PSRE PSR2 PSR1 PSR0 1 1 1 1 Wake-up from Pin Change P P P P P P P P Bit Name Power-on 0 0 0 0 0 0 0 0 /RESET and WDT Wake-up from Pin Change 0 0 0 0 0 0 0 0 *0/P GP2 0 *0/P *0/P GP0 0 *0/P *1/P *0/P *0/P *0/P GP1 0 T 1 P 1 Z U DC U C U 0 P 0 P 0 P ** ** ** ** P P P P P P Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name - - - - - - - - Power-on 1 1 U U U U U U /RESET and WDT 1 1 P P P P P P Wake-up from Pin Change 1 1 P P P P P P Bit Name P56 P55 P54 P53 P52 P51 P50 Power-on × 0 U U U U U U U /RESET and WDT 0 P P P P P P P Wake-up from Pin Change 0 P P P P P P P P67 U P66 U × 0 × 0 × 0 × 0 P61 U P60 U P P P P 0 0 0 0 0 0 0 0 P P P P Bit Name Power-on /RESET and WDT Wake-up from Pin Change Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) • 19 EM78P154N 8-Bit Microcontroller with OTP ROM Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 × U × U × U × U × U ICWE Power-on × U 0 × U /RESET and WDT U U U U U U 0 U Wake-up from Pin Change U U U U U U P U Bit Name Power-on × U × U × U × U × U EXIF 0 ICIF 0 TCIF 0 /RESET and WDT Wake-up from Pin Change U U U U U U U U U U 0 P 0 P 0 P Bit Name Power-on 1 1 1 1 1 1 1 1 /RESET and WDT Wake-up from Pin Change 1 P 1 P 1 P 1 P 1 P 1 P 1 P 1 P Bit Name Power-on × 1 × 1 /PD5 1 /PD4 1 /PD3 1 /PD2 1 /PD1 1 /PD0 1 Bit Name 0x0E 0x0F 0x0A 0x0B 0x0C RE (WUE) RF(ISR) IOCA IOCB IOCC /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P Bit Name OD7 OD6 0 × 0 × 0 × 0 OD0 0 × 0 OD1 Power-on 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change 0x0D 0x0E 0x0F IOCD IOCE IOCF 0x10~0x2F R10~R2F Legend: ×: Not used P P P P P P P P /PH7 1 /PH6 1 × 1 × 1 × 1 × 1 /PH1 1 /PH0 1 1 P 1 P 1 P 1 P 1 P 1 P 1 P 1 P WDTE 1 EIS 0 × U /RESET and WDT Wake-up from Pin Change 1 1 0 P U U 0 P 0 P 0 P 0 P 0 P Bit Name Power-on × U × U × U × U × U EXIE 0 ICIE 0 TCIE 0 /RESET and WDT U U U U U 0 0 0 Wake-up from Pin Change U U U U U P P P Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on ROC PSWE PSW2 PSW1 PSW0 0 0 0 0 0 Bit Name - - - - - - - - Power-on U U U U U U U U /RESET and WDT P P P P P P P P Wake-up from Pin Change P P P P P P P P U: Unknown or don’t care P: Previous value before reset *Jump to Address 0x08, or execute the instruction next to the “SLEP” instruction. ** Refer to tables provided in the next section (Section 5.5.3). 20 • Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM 5.5.3 Status of RST, T, and P of the Status Register A Reset condition is initiated by the following events 1) A power-on condition 2) A high-low-high pulse on /RESET pin 3) Watchdog timer time-out The values of T and P listed in the table below are used to check how the processor wakes up. The Values of RST, T, and P after a Reset Reset Type T Power on /RESET during Operating mode /RESET wake-up during Sleep mode WDT during Operating mode WDT wake-up during Sleep mode Wake-Up on pin change during Sleep mode P 1 *P 1 0 0 1 1 *P 0 *P 0 0 * P: Previous status before reset The following table shows the events that may affect the status of T and P. The Status of T and P Being Affected by Events Event Power on WDTC instruction WDT time-out SLEP instruction Wake-up on pin change during Sleep mode T P 1 1 0 1 1 1 1 *P 0 0 * P: Previous status before reset VDD D CLK Oscillator Q CLK CLR Power-on Reset Voltage Detector WDTE WDT WDT Timeout Setup Time RESET /RESET Figure 5-6 Controller Reset Block Diagram Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) • 21 EM78P154N 8-Bit Microcontroller with OTP ROM 5.6 Interrupt The EM78P154N has three falling-edge interrupts as listed herewith: 1) TCC overflow interrupt 2) Port 6 Input Status Change Interrupt 3) External interrupt [(P60, /INT) pin] Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g., "MOV R6,R6") is necessary. Each Port 6 pin will have this feature if its status changes. Any pin configured as output or P60 pin configured as /INT is excluded from this function. The Port 6 Input Status Changed Interrupt can wake up the EM78P154N from Sleep mode if Port 6 is enabled prior to going into the Sleep mode by executing SLEP. When the chip wakes-up, the controller will continue to execute the succeeding address if the global interrupt is disabled or it will branch into the interrupt vector 008H if the global interrupt is enabled. RF is the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the interrupts (enabled) occurs, the next instruction will be fetched from address 008H. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine and before interrupts are enabled to avoid recursive interrupts. The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the status of its mask bit or the execution of ENI. Note that the outcome of RF will be the logic AND of RF and IOCF (refer to figure below). The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of ENI). When an interrupt is generated by the INT instruction (enabled), the next instruction will be fetched from Address 001H. VCC D /I R Q n P R CLK C L Q IR Q n IN T _ Q RFRD IR Q m RF E N I/D I S I IO C F Q P R _ Q C L IO D D CLK IO C FW R /R E S E T IO C F R D RFW R Figure 5-7 Interrupt Input Circuit 22 • Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM 5.7 Oscillator 5.7.1 Oscillator Modes The EM78P154N can be operated in four different oscillator modes, such as External RC oscillator mode (ERC), Internal RC oscillator mode (IRC), High Crystal oscillator mode (HXT), and Low Crystal oscillator mode (LXT). The desired mode can be selected by programming OSC2, OSC1, and OSC0 in the CODE option register. The Table below describes how these four oscillator modes are defined with OSC2, OSC1, and OSC0. Oscillator Modes Defined by OSC Mode OSC2 OSC1 OSC0 ERC (External RC oscillator mode); P55/OSCO act as P55 0 0 0 ERC (External RC oscillator mode); P55/OSCO act as OSCO 0 0 1 IRC (Internal RC oscillator mode) ; P55/OSCO act as P55 0 1 0 IRC (Internal RC oscillator mode); P55/OSCO act as OSCO 0 1 1 MCIRC (Manual calibration IRC mode); P55/OSCO act as P55 With Simulator MCIRC (Manual calibration IRC mode); P55/OSCO act as OSCO only 1 0 0 1 0 1 LXT (Low Crystal oscillator mode) 1 1 0 HXT (High Crystal oscillator mode) (default) 1 1 1 Note: The transient point of system frequency between HXT and LXY is 400kHz. The maximum operational frequency of the crystal/resonator under different VDDs is as listed below. Summary of Maximum Operating Speeds Conditions Two cycles with two clocks Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) VDD Max Freq. (MHz) 2.1 4.0 3.0 8.0 5.0 20.0 • 23 EM78P154N 8-Bit Microcontroller with OTP ROM 5.7.2 Crystal Oscillator/Ceramic Resonators (Crystal) The EM78P154N can be driven by an external clock signal through the OSCI pin as shown in the following figure. OSCI Ext. Clock OSCO EM78P154N Figure 5-8a External Clock Input Circuit In the most applications, Pins OSCI and OSCO can be connected with a crystal or ceramic resonator to generate oscillation. The Figure below depicts such circuit. The same thing applies whether it is in the HXT mode or in the LXT mode. The following table provides the recommended values of C1 and C2. Since each resonator has its own attribute, refer to its specification for appropriate values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or low frequency mode. C1 OSCI EM78P154N Crystal OSCO RS C2 Figure 5-8b Crystal/Resonator Circuit Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator Oscillator Type Frequency Mode Ceramic Resonators HXT LXT Crystal Oscillator HXT Frequency 455kHz 2.0 MHz 4.0 MHz 32.768kHz 100kHz 200kHz 455kHz 1.0MHz 2.0MHz 4.0MHz C1 (pF) 100~150 20~40 10~30 25 25 25 20~40 15~30 15 15 C2 (pF) 100~150 20~40 10~30 15 25 25 20~150 15~30 15 15 Note: The values of capacitors C1 and C2 are for reference only 24 • Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM 5.7.3 External RC Oscillator Mode For some applications that do not require a very precise timing calculation, the RC oscillator (Figure 5-9 below) offers a cost-effective oscillator configuration. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to manufacturing process variations. In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF, and that the value of Rext should not be greater than 1 MΩ. If they cannot be kept in this range, the frequency can be easily affected by noise, humidity, and leakage. The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 KΩ, the oscillator becomes unstable because the NMOS cannot discharge the current of the capacitance correctly. Based on the above reasons, it must be kept in mind that all of the supply voltage, the operation temperature, the components of the RC oscillator, the package types, the way the PCB is layout, will affect the system frequency. Vcc Rext OSCI Cext EM78P154N Figure 5-9 External RC Oscillator Mode Circuit Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) • 25 EM78P154N 8-Bit Microcontroller with OTP ROM RC Oscillator Frequencies Cext 20 pF 100 pF 300 pF Rext Average Fosc 5V, 25°C Average Fosc 3V, 25°C 3.3k 3.92 MHz 3.65 MHz 5.1k 2.67 MHz 2.60 MHz 10k 1.39MHz 1.40 MHz 100k 149 kHz 156 kHz 3.3k 5.1k 1.39 MHz 940 kHz 1.33 MHz 920 kHz 475 kHz 10k 480 kHz 100k 52 kHz 50 kHz 3.3k 595 kHz 560 kHz 5.1k 400 kHz 390 kHz 10k 200 kHz 200 kHz 100k 21 kHz 20 kHz 1 NOTE: : Measured based on DIP packages. 2 : The values are for design reference only. 3 : The frequency drift is ± 30%. 5.7.4 Internal RC Oscillator Mode EM78P154N offers a versatile internal RC mode with default frequency value of 4MHz. The Internal RC oscillator mode has other frequencies (1MHz, 8MHz, & 455kHz) that can be set by Code Option (Word 1), RCM1, and RCM0. All these four main frequencies can be calibrated by programming the the Option Bits C3 ~ C0. The table below describes a typical instance of the calibration. Internal RC Drift Rate (Ta=25°C, VDD=3.9V± 5%, VSS=0V) Internal RC Frequency Drift Rate Temperature (-40°C ~ +85°C) Voltage (2.3V ~ 5.5V) Process Total 4MHz ±5% ±5% ±4% ±14% 8MHz ±5% ±5% ±4% ±14% 1MHz ±5% ±5% ±4% ±14% 455MHz ±5% ±5% ±4% ±14% Note: These are theoretical values which are provided for reference only. Actual values may vary depending on the actual process. 26 • Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM Calibration Selection for Internal RC Mode C3 C2 C1 C0 Cycle Time (ns) Frequency (MHz) 0 0 0 0 390.6 2.56 0 0 0 1 365.0 2.74 0 0 1 0 342.5 2.92 0 0 1 1 322.6 3.1 0 1 0 0 304.9 3.28 0 1 0 1 289.0 3.46 0 1 1 0 274.7 3.64 0 1 1 1 261.8 3.82 1 1 1 1 250.0 4.00 1 1 1 0 239.2 4.18 1 1 0 1 229.4 4.36 1 1 0 0 220.3 4.54 1 0 1 1 211.9 4.72 1 0 1 0 204.1 4.9 1 0 0 1 196.7 5.08 1 0 0 0 190.1 5.26 Note: These are theoretical values which are provided for reference only. Actual values may vary depending on the actual process. 5.8 Code Option Register The EM78P154N has a Code Option word that is not a part of the normal program memory. The option bits cannot be accessed during normal program execution. Code Option Register and Customer ID Register Arrangement Distribution: Word 0 Word 1 Word 2 Bit 12 ~ Bit 0 Bit 12 ~ Bit 0 Bit 12 ~ Bit 0 5.8.1 Code Option Register (Word 0) Word 0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 - - - - Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CLKS0 ENWDTB OSC2 OSC1 OSC0 HLP PR2 PR1 PR0 Bit 0 ~ Bit 2 (PR0 ~ PR2): Protect bits PR0 ~ PR2 are protect bits. Protect types are as follows: PR2 PR1 PR0 Protect 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Enable Enable Enable Enable Enable Enable Enable Disable Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) • 27 EM78P154N 8-Bit Microcontroller with OTP ROM Power selection Bit 3 (HLP): 0 = Low power 1 = High power Bit 4 ~ Bit 6 (OSC0 ~ OSC2): Oscillator Modes Selection bits Mode OSC2 OSC1 OSC0 ERC (External RC oscillator mode); P55/OSCO act as P55 0 0 0 ERC (External RC oscillator mode); P55/OSCO act as OSCO 0 0 1 IRC (Internal RC oscillator mode) ; P55/OSCO act as P55 0 1 0 IRC (Internal RC oscillator mode); P55/OSCO act as OSCO 0 1 1 MCIRC (Manual calibration IRC mode); P55/OSCO act as P55 With Simulator MCIRC (Manual calibration IRC mode); P55/OSCO act as OSCO only 1 0 0 1 0 1 LXT (Low Crystal oscillator mode) 1 1 0 HXT (High Crystal oscillator mode) (default) 1 1 1 Note: The transient point of system frequency between HXT and LXY is 400kHz. Bit 7 (ENWDTB): Watchdog timer enable bit 0 = Enable 1 = Disable Instruction period option bit Bit 8 (CLKS0): Word 0 CLK0 4 oscillator time periods (default) 1 2 oscillator time periods 0 Refer to Section 4.12, Instruction Set for further details. Not used, but need to be set to “1” all the time to avoid possible error. Bit 9 ~ Bit 12: 5.8.2 Customer ID Register (Word 1) WORD 0 Bit12 Bit11 Bit10 - RCOUT - Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 - - - CYES - - - - Bit1 Bit0 RCM1 RCM0 Bit 0 ~ Bit 1 (RCM0 ~ RCM1): IRC mode selection bits Bit 2 ~ Bit 5: 28 • RCM 1 RCM 0 Frequency (MHz) 1 1 4 1 0 8 0 1 1 0 0 455kHz Not used Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM Bit 6 (CYES): Instruction cycle selection bit 0 = one instruction cycle 1 = two instruction cycles (default) Bit 7 ~ Bit 10: Not used Bit 11 (RCOUT): System clock output enable bit in IRC or ERC mode 0 = OSCO pin is open drain 1 = OSCO output system clock Not used Bit 12: 5.8.3 Customer ID Register (Word 2) Word 0 Bit12 Bit11 Bit10 - - Bit 0 ~ Bit 12: Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 - - - - - - - - - - - User’s ID code 5.9 Power-on Considerations Any microcontroller is not guaranteed to start to operate properly before the power supply has stabilized. The EM78P154N POR voltage range is 1.7V~1.9V. Under customer application, when power is OFF, Vdd must drop to below 1.2V and remains OFF for 10μs before power can be switched ON again. This way, the EM78P154N will reset and operates normally. The extra external reset circuit will work well if Vdd can rise at very fast speed (50 ms or less). However, under most cases where critical applications are involved, extra devices are required to assist in solving the power-up problems. 5.10 External Power-on Reset Circuit The circuit shown in the figure implements an Vdd external RC to produce the R reset pulse. The pulse /RESET D width (time constant) EM78P154N should be kept long enough for Vdd to reached Rin C minimum operation voltage. This circuit is used when the power supply has a slow rise Figure 5-10 External Power-up Reset Circuit time. Since the current leakage from the /RESET pin is about ±5μA, it is recommended that R should not be greater than 40K. In this way, the /RESET pin voltage is held below 0.2V. The diode (D) acts as a short circuit at the moment of power down. The capacitor C will discharge rapidly and fully. Rin, the current-limited resistor, will prevent high current or ESD (electrostatic discharge) from flowing to pin /RESET. Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) • 29 EM78P154N 8-Bit Microcontroller with OTP ROM 5.11 Residue-Voltage Protection When the battery is replaced, the device power (Vdd) is cut off but residue-voltage remains. The residue-voltage may trip below the minimum Vdd, but not to zero. This condition may cause a poor power-on reset. The following figures illustrate two recommended methods on how to build a residue-voltage protection circuit for EM78P154N. Vdd Vdd 33K EM78P154N Q1 10K /RESET 40K 1N4684 Figure 5-11a Residue Voltage Protection Circuit (1) Vdd Vdd R1 EM78P154N Q1 /RESET 40K R2 Figure 5-11b Residue Voltage Protection Circuit (2) 30 • Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM 5.12 Instruction Set Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of two oscillator periods), unless the program counter is changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g., "SUB R2,A", "BS(C) R2,6", "CLR R2", ⋅⋅⋅⋅). In this case, the execution takes two instruction cycles. If for some reasons, the specification of the instruction cycle is not suitable for certain applications, try modifying the instruction as follows: A) Change one instruction cycle to consist of four oscillator periods. B) "JMP," "CALL," "RET," "RETL," "RETI," or the conditional skip ("JBS," "JBC," "JZ," "JZA," "DJZ,” "DJZA") commands which were tested to be true, are executed within two instruction cycles. The instructions that are written to the program counter also take two instruction cycles. Case (A) is selected by the Code Option bit, called CLK. One instruction cycle consists of two oscillator clocks if CLK is low; and four oscillator clocks if CLK is high. Note that once the four oscillator periods within one instruction cycle is selected as in Case (A), the internal clock source to TCC should be CLK=Fosc/4, instead of Fosc/2. Moreover, the instruction set has the following features: 1) Every bit of any register can be set, cleared, or tested directly. 2) The I/O register can be regarded as general register. That is, the same instruction can operate on I/O register. The following symbols are used in the Instruction Set table: Convention: R = Register designator that specifies which one of the registers (including operation and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. b = Bit field designator that selects the value for the bit located in the register R and which affects the operation. k = 8 or 10-bit constant or literal value Binary Instruction Hex Mnemonic 0 0000 0000 0000 0000 NOP No Operation Operation 0 0000 0000 0001 0001 DAA Decimal Adjust A 0 0000 0000 0010 0002 CONTW 0 0000 0000 0011 0003 0 0000 0000 0100 0 0000 0000 rrrr Status Affected None C A → CONT None SLEP 0 → WDT, Stop oscillator T, P 0004 WDTC 0 → WDT T, P 000r IOW R A → IOCR Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) None 1 • 31 EM78P154N 8-Bit Microcontroller with OTP ROM 32 • Binary Instruction Hex Mnemonic Operation Status Affected 0 0000 0001 0000 0010 ENI Enable Interrupt None 0 0000 0001 0001 0011 DISI Disable Interrupt None 0 0000 0001 0010 0012 RET [Top of Stack] → PC None [Top of Stack] → PC, Enable Interrupt None None 0 0000 0001 0011 0013 RETI 0 0000 0001 0100 0014 CONTR CONT → A 0 0000 0001 rrrr 001r IOR R IOCR → A 0 0000 01rr rrrr 00rr MOV R,A A→R None 0 0000 1000 0000 0080 CLRA 0→A Z 0 0000 11rr rrrr 00rr CLR R 0→R Z 0 0001 00rr rrrr 01rr SUB A,R R-A → A Z, C, DC 0 0001 01rr rrrr 01rr SUB R,A R-A → R Z, C, DC 0 0001 10rr rrrr 01rr DECA R R-1 → A Z 0 0001 11rr rrrr 01rr DEC R R-1 → R Z 0 0010 00rr rrrr 02rr OR A,R A∨R→A Z 0 0010 01rr rrrr 02rr OR R,A A∨R→R Z 0 0010 10rr rrrr 02rr AND A,R A&R→A Z 0 0010 11rr rrrr 02rr AND R,A A&R→R Z 0 0011 00rr rrrr 03rr XOR A,R A⊕R→A Z 0 0011 01rr rrrr 03rr XOR R,A A⊕R→R Z 0 0011 10rr rrrr 03rr ADD A,R A+R→A Z, C, DC 0 0011 11rr rrrr 03rr ADD R,A A+R→R Z, C, DC 0 0100 00rr rrrr 04rr MOV A,R R→A Z 0 0100 01rr rrrr 04rr MOV R,R R→R Z 0 0100 10rr rrrr 04rr COMA R /R → A Z 0 0100 11rr rrrr 04rr COM R /R → R Z 0 0101 00rr rrrr 05rr INCA R R+1 → A Z 0 0101 01rr rrrr 05rr INC R R+1 → R Z 0 0101 10rr rrrr 05rr DJZA R R-1 → A, skip if zero None 0 0101 11rr rrrr 05rr DJZ R R-1 → R, skip if zero None 0 0110 00rr rrrr 06rr RRCA R 0 0110 01rr rrrr 06rr RRC R 0 0110 10rr rrrr 06rr RLCA R 0 0110 11rr rrrr 06rr RLC R 0 0111 00rr rrrr 07rr SWAPA R 0 0111 01rr rrrr 07rr SWAP R R(n) → A(n-1), R(0) → C, C → A(7) R(n) → R(n-1), R(0) → C, C → R(7) R(n) → A(n+1), R(7) → C, C → A(0) R(n) → R(n+1), R(7) → C, C → R(0) R(0-3) → A(4-7), R(4-7) → A(0-3) R(0-3) ↔ R(4-7) None 1 C C C C None None Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM Binary Instruction Hex Mnemonic Operation 0 0111 10rr rrrr 07rr JZA R R+1 → A, skip if zero None 0 0111 11rr rrrr 07rr JZ R R+1 → R, skip if zero None 0 100b bbrr rrrr 0xxx BC R,b 0 → R(b) None 2 0 101b bbrr rrrr 0xxx BS R,b 1 → R(b) None 3 0 110b bbrr rrrr 0xxx JBC R,b if R(b)=0, skip None 0 111b bbrr rrrr 0xxx JBS R,b if R(b)=1, skip None 1 00kk kkkk kkkk 1kkk CALL k PC+1 → [SP], (Page, k) → PC None 1 01kk kkkk kkkk 1kkk JMP k (Page, k) → PC None 1 1000 kkkk kkkk 18kk MOV A,k k→A None 1 1001 kkkk kkkk 19kk OR A,k A∨k→A Z 1 1010 kkkk kkkk 1Akk AND A,k A&k→A Z 1 1011 kkkk kkkk 1Bkk XOR A,k A⊕k→A Z 1 1100 kkkk kkkk 1Ckk RETL k k → A, [Top of Stack] → PC 1 1101 kkkk kkkk 1Dkk SUB A,k k-A → A 1 1110 0000 0001 1E01 INT 1 1111 kkkk kkkk 1Fkk ADD A,k PC+1 → [SP], 001H → PC k+A → A Status Affected None Z, C,DC None Z, C, DC 1 Note: This instruction is applicable to IOC5~IOC6, IOCB ~ IOCF only. 2 This instruction is not recommended for RF operation. 3 This instruction cannot operate under RF. Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) • 33 EM78P154N 8-Bit Microcontroller with OTP ROM 5.13 Timing Diagrams AC Test Input/Output Waveform VDD-0.5V 0.75VDD TEST POINTS 0.25VDD 0.75VDD 0.25VDD GND+0.5V AC Testing : Input is driven at VDD-0.5V for logic "1",and GND+0.5V for logic "0".Timing measurements are made at 0.75VDD for logic "1",and 0.25VDD for logic "0". RESET Timing (CLK="0") NOP Instruction 1 Executed CLK /RESET Tdrh TCC Input Timing (CLKS="0") Tins CLK TCC Ttcc Figure 5-12 EM78P154N Timing Diagrams 34 • Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM 6 Absolute Maximum Ratings EM78P154N Items Rating -40°C to 85°C Temperature under bias Storage temperature -65°C to 150°C Working voltage 2.1 to 5.5V Working frequency DC to 20MHz* Input voltage Vss-0.3V to Vdd+0.5V Output voltage Vss-0.3V to Vdd+0.5V Note: *These parameters are theoretical values and have not been tested. 7 Electrical Characteristics 7.1 DC Characteristic Ta=25 °C, VDD=5V±5%, VSS=0V Symbol Parameter Condition FXT Crystal: VDD to 3V Crystal: VDD to 5V ERC IIL ERC: VDD to 5V R: 5.1KΩ, C: 100 pF Input Leakage Current for input pins VIN = VDD, VSS VIH1 VIL1 Input High Voltage (VDD=5V) Input Low Voltage (VDD=5V) Input High Threshold Voltage (VDD=5V) Input Low Threshold Voltage (VDD=5V) Clock Input High Voltage (VDD=5V) VIHT1 VILT1 VIHX1 Two cycle with two clocks Two cycle with two clocks Ports 5, 6 (Schmitt trigger) Ports 5, 6 (Schmitt trigger) /RESET, TCC (Schmitt trigger) /RESET, TCC (Schmitt trigger) OSCI (Schmitt trigger) Min. Typ. Max. Unit 8.0 20.0 MHz MHz kHz 0.75Vdd Vdd-0.3 F±30% ±1 Vdd+0.3 0.25Vdd 0.75Vdd Vdd+0.3 V Vdd-0.3 0.25Vdd V 0.75Vdd Vdd+0.3 V V DC DC F±30% 940 μA V V VILX1 Clock Input Low Voltage (VDD=5V) OSCI (Schmitt trigger) Vdd-0.3 0.25Vdd VIH2 Input High Voltage (VDD=3V) Ports 5, 6 (Schmitt trigger) 0.75Vdd Vdd+0.3 V VIL2 Input Low Voltage (VDD=3V) Input High Threshold Voltage (VDD=3V) Input Low Threshold Voltage (VDD=3V) Clock Input High Voltage (VDD=3V) Clock Input Low Voltage (VDD=3V) Ports 5, 6 (Schmitt trigger) /RESET, TCC (Schmitt trigger) /RESET, TCC (Schmitt trigger) OSCI (Schmitt trigger) OSCI (Schmitt trigger) Vdd-0.3 0.25Vdd V 0.75Vdd Vdd+0.3 V Vdd-0.3 0.25Vdd V 0.75Vdd Vdd-0.3 Vdd+0.3 0.25Vdd V V Output High Voltage (Ports 5) Output High Voltage (Ports 6) (Schmitt trigger) Output Low Voltage(Port5) Output Low Voltage (Ports 6) (Schmitt trigger) IOH = -6 mA 4.5 V IOH = -6 mA 4.5 V VIHT2 VILT2 VIHX2 VILX2 VOH1 VOH1 VOL1 VOL1 IPH Pull-high current IPD Pull-down current IOL = 16.5 mA 0.5 V IOL = 16.5 mA 0.5 V Pull-high active, input pin at VSS Pull-down active, input pin at VDD Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) –50 –70 –100 μA 25 50 120 μA • 35 EM78P154N 8-Bit Microcontroller with OTP ROM Symbol ISB1 Parameter Power down current (VDD=5.0V) Condition Min. Typ. Max. Unit - 1 2 μA - 6 10 μA All input and I/O pins at VDD, output pin floating, WDT disabled All input and I/O pins at VDD, output pin floating, WDT enabled ISB2 Power down current (VDD=5.0V) ICC1 Operating supply current (VDD=3V) at two cycles/four clocks /RESET= 'High', Fosc=32kHz (Crystal type, CLKS="0"), output pin floating, WDT disabled - 20 30 μA ICC2 Operating supply current (VDD=3V) at two cycles/four clocks /RESET= 'High', Fosc=32KHz (Crystal type, CLKS="0"), output pin floating, WDT enabled - 22 32 μA ICC3 Operating supply current (VDD=5.0V) at two cycles/two clocks /RESET= 'High', Fosc=4MHz (Crystal type, CLKS="0"), output pin floating, WDT enabled - 1.7 2.5 mA ICC4 Operating supply current (VDD=5.0V) at two cycles/four clocks /RESET= 'High', Fosc=10MHz (Crystal type, CLKS="0"), output pin floating, WDT enabled - 2.7 3.5 mA Note: *These parameters are theoretical values and have not been tested. 7.2 AC Characteristic Ta=25°C, VDD=5V ± 5%, VSS=0V Symbol Dclk Parameter Conditions Min. Typ. Max. Unit Input CLK duty cycle - 45 50 55 % Tins Instruction cycle time (CLKS="0") Crystal type 100 - DC ns Ttcc TCC input period Tdrh Device reset hold time Trst /RESET pulse width Twdt Watchdog timer period Tset Input pin setup time Thold Input pin hold time Tdelay Output pin delay time RC type 500 - DC ns - (Tins+20)/N* - - ns - 11.8 16.8 21.8 ms Ta = 25°C 2000 - - ns Ta = 25°C 11.8 16.8 21.8 ms - - 0 - ns - - 20 - ns Cload=20pF - 50 - ns NOTE: These parameters are theoretical values and have not been tested. * N = selected prescaler ratio 36 • Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM APPENDIX A Package Type OTP MCU Package Type Pin Count Package Size EM78P154NP DIP 14 300 mil EM78P154NM SOP 14 150 mil B Package Information 14-Lead Plastic Dual in line (PDIP) — 300 mil Figure B-1a EM78P154N 14-Lead PDIP Package Type Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) • 37 EM78P154N 8-Bit Microcontroller with OTP ROM 14-Lead Plastic Dual in line (SOP) — 150 mil Figure B-1b EM78P154N 14-Lead SOP Package Type 38 • Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) EM78P154N 8-Bit Microcontroller with OTP ROM C Quality Assurance and Reliability C.1 Reliability Test Test Category Solderability Test Conditions Remarks Solder temperature = 245±5˚C for 5 seconds up to the stopper using a rosin-type flux Step 1: TCT 65˚C (15mins) ~ 150˚C (15mins), 10 cycles Step 2: bake 125˚C, TD (endurance) = 24 hrs. Pre-condition Step 3: soak 30°C /60%, TD (endurance) = 192hrs. Step 4: IR flow 3cycles (Pkg thickness ≥ 2.5mm or Pkg volume ≥ 350mm3--225±5˚C) (Pkg thickness ≤ 2.5mm or Pkg volume ≤ 350mm3--240±5˚C) Temperature cycle test –65˚C (15mins) ~ 150˚C (15mins), 200 cycles Pressure cooker test TA =121˚C, RH = 100%, pressure = 2atm, TD (endurance) = 96 Hrs. High temperature /high humidity test TA=85˚C , RH=85%, TD (endurance) = 168, 500 Hrs High-temperature storage life TA=150˚C, TD (endurance) = 500, 1000Hrs. High-temperature operating life TA=125˚C, VCC = Max. operating voltage, TD (endurance) = 168,500, 1000Hrs. Latch-up TA=25˚C, VCC = Max. operating voltage, 150mA/20V ESD (HBM) TA=25˚C, ≥ ±3KV For SMD IC (such as SOP, QFP, SOJ, etc.) IP_ND,OP_ND,IO_ND IP_NS,OP_NS,IO_NS IP_PD,OP_PD,IO_PD, ESD (MM) TA=25˚C, ≥ ±300V IP_PS,OP_PS,IO_PS, VDD-VSS(+), VDD_VSS(-)mode Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice) • 39 EM78P154N 8-Bit Microcontroller with OTP ROM C.2 Power-on Reset and Vdd Voltage Drop/Rise Timing Test Vdd /Reset Tvr Tvd Internal POR Tpor Power on Reset Figure C-1 EM78P154N Power-On Reset and Vdd Voltage Drop/Rise Timing Test Timing Diagram Symbol Parameter Condition Min. Typ. Max. Unit Tpor Power on reset time Vdd = 5V, -40℃ to 85℃ 10.5 16.8 22 ms Tvd* Vdd Voltage drop time Vdd = 5V, -40℃ to 85℃ - - 1 μs Tvr** Vdd Voltage rise time Vdd = 5V, -40℃ to 85℃ - - 1 us Note: * Tvd is the period of Vdd voltage lower than POR voltage. ** Tvr is the period of Vdd voltage higher than 5.5V. C.3 Address Trap Detect An address trap detect is one of the fail-safe function that detects CPU malfunction caused by noise or the like. If the CPU attempts to fetch an instruction from a part of RAM, an internal recovery circuit will be auto started. Until CPU got the correct function, it will execute the next program. 40 • Product Specification (V1.1) 03.29.2007 (This specification is subject to change without further notice)