EM78P447S

EM78P447S
8-Bit Microprocessor
with OTP ROM
Product
Specification
DOC. VERSION 1.7
ELAN MICROELECTRONICS CORP.
January 2010
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2003~2010 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes
no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN
Microelectronics makes no commitment to update, or to keep current the information and material contained in
this specification. Such information and material may change to conform to each confirmed order.
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NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR
BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
st
No. 12, Innovation 1 Road
Hsinchu Science Park
Hsinchu, TAIWAN 30076
Tel: +886 3 563-9977
Fax: +886 3 563-9966
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http://www.emc.com.tw
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USA:
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Corporation, Ltd.
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Elan Information
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Shanghai:
Elan Microelectronics
Shenzhen, Ltd.
Elan Microelectronics
Shanghai, Ltd.
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(South Area), Shenzhen
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elan-sh@elanic.com.cn
Contents
Contents
1
2
3
4
General Description ...................................................................................... 1
Features ......................................................................................................... 1
Pin Assignment and Description.................................................................. 2
3.1
EM78P447S Series Pin Assignment .................................................................. 2
3.2
EM78P447SAP and EM78P447SAM Pin Description........................................ 3
3.3
EM78P447SAS Pin Description ......................................................................... 3
3.4
EM78P447SAK Pin Description ......................................................................... 4
3.5
EM78P447SBP, EM78P447SBWM, and EM78P447SBM Pin Description ........ 4
3.6
EM78P447SCK and EM78P447SCM Pin Description ....................................... 5
Function Description..................................................................................... 6
4.1
Operational Registers......................................................................................... 6
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.2
R0 (Indirect Addressing Register) .......................................................................6
R1 (Time Clock/Counter).....................................................................................6
R2 (Program Counter) and Stack........................................................................7
R3 (Status Register) ............................................................................................9
R4 (RAM Select Register)...................................................................................9
R5~R7 (Port 5 ~ Port 7) ......................................................................................9
R8~R1F and R20~R3E (General Purpose Registers) ......................................10
R3F (Interrupt Status Register) .........................................................................10
Special Function Registers............................................................................... 10
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
A (Accumulator).................................................................................................10
CONT (Control Register)...................................................................................10
IOC5 ~ IOC7 (I/O Port Control Register) ..........................................................11
IOCB (Wake-up Control Register for Port 6).....................................................11
IOCE (WDT Control Register) ...........................................................................12
IOCF (Interrupt Mask Register).........................................................................14
4.3
TCC/WDT and Prescaler.................................................................................. 14
4.4
I/O Ports ........................................................................................................... 15
4.5
Reset and Wake-up.......................................................................................... 16
4.5.1
4.5.2
Reset .................................................................................................................16
4.5.1.1 Sleep 2 and Sleep 1 Modes Operation Summary................................18
4.5.1.2 Register Initial Values after Reset ........................................................19
Status of RST, T, and P of Status Register........................................................20
4.6
Interrupt ............................................................................................................ 21
4.7
Oscillator .......................................................................................................... 22
4.7.1
4.7.2
4.8
Oscillator Modes................................................................................................22
Crystal Oscillator/Ceramic Resonators (Crystal)...............................................23
Code Option Register....................................................................................... 25
Product Specification (V1.7) 01.27.2010
iii
Contents
4.9
Power-On Considerations ................................................................................ 26
4.9.1
4.9.2
External Power-on Reset Circuit .......................................................................26
Residue-Voltage Protection...............................................................................27
4.10 Instruction Set .................................................................................................. 28
4.10.1 EM78P447S Instruction Set Table ....................................................................29
5
6
Timing Diagram ........................................................................................... 31
Absolute Maximum Ratings........................................................................ 32
7
Electrical Characteristics............................................................................ 32
7.1
DC Electrical Characteristic.............................................................................. 32
7.2
AC Electrical Characteristic.............................................................................. 33
7.3
Device Characteristic ....................................................................................... 34
7.3.1
7.3.2
7.3.3
Device Operating Voltage Characteristics.........................................................34
Device Operating Temperature Characteristics ................................................37
Device Operation Curve....................................................................................41
APPENDIX
A
Package Type............................................................................................... 44
A.1
B
C
Packaging Configuration ............................................................................ 46
B.1 24-Lead Plastic Skinny Dual In-line Package (SKDIP)
300 mil .................. 46
B.2 28-Lead Plastic Skinny Dual In-line Package (SKDIP)
300 mil .................. 47
B.3 28-Lead Plastic Dual In-line Package (DIP)
600 mil .................................... 47
B.4 32-Lead Plastic Dual In-line Package (DIP)
600 mil .................................... 48
B.5 24-Lead Plastic Small Outline Package (SOP)
300 mil .............................. 48
B.6 28-Lead Plastic Small Outline Package (SOP)
300 mil .............................. 49
B.7 32-Lead Plastic Small Outline Package (SOP)
300 mil .............................. 50
B.8 32-Lead Plastic Small Outline Package (SOP)
450 mil .............................. 51
B.9 28-Lead Shrink Small Outline Package (SSOP)
209 mil ............................ 52
EM78P447S Programming Pin List ............................................................ 53
C.1
iv •
Packaging Material Specification..................................................................... 45
Wiring Diagram for Programming with ELAN DWTR................................... 53
Product Specification (V1.7) 01.27.2010
Contents
Specification Revision History
Doc. Version
Revision Description
Date
1.0
Initial version
1.1
Changed the Power-on reset contents
2003/06/25
1.2
Added device characteristic at Section 6.3
2004/11/05
1.3
Added new package type
2006/04/19
1.4
Added EM78P447SFK and EM78P447SBM package type
on the Features section and other related sections, as well
as on the Appendix section.
2006/07/25
1.5
Updated the EM78P447SAK description.
2006/10/26
1.6
Deleted EM78P447SFK package type on the Features
section and other related sections, as well as on the
Appendix section.
2007/10/31
1.7
1. Modify the SDIP & skinny DIP package information
description into SKDIP.
2 Change the figure of package information.
-
2009/01/27
3. Modify the (A) description of Sleep 2 mode
Product Specification (V1.7) 01.27.2010
v
Contents
vi •
Product Specification (V1.7) 01.27.2010
EM78P447S
8-Bit Microcontroller with OTP ROM
1
General Description
EM78P447S is an 8-bit microprocessor with low-power and high-speed CMOS
technology. It has a built-in 4K×13-bit Electrical One-Time Programmable Read Only
Memory (OTP-ROM). It provides a protection bit to protect user’s OTP memory code
confidentiality.
With its enhanced OTP-ROM feature, the EM78P147N provides a convenient way of
developing and verifying user’s programs. Moreover, this MCU offers the advantages
of easy and effective program updates with the use of ELAN development and
programming tools. You can also avail yourself with ELAN Writer to easily program
your development code.
2
Features
„ CPU configuration:
„
Peripheral configuration:
● 4K×13 bits on-chip ROM
• 8-bit real time clock/counter (TCC) with
● 148×8 bits on-chip registers (SRAM and
selective signal sources, trigger edges, and
overflow interrupt
• Power down (Sleep) mode
general purpose registers)
● 5-level stacks for subroutine nesting
„
One configuration register to accommodate
user’s ID register requirements.
● 30µA Typical at 3V/32kHz
„
Two clocks per instruction cycle
● µA Typical during Sleep mode
„
Single instruction cycle commands
„
Transient point of system frequency between HXT
and LXT is 400kHz
„
Two interrupts available:
• External interrupt (/INT)
• TCC overflow interrupt
„
Programmable free running on-chip watchdog
timer
„
Package types:
• 24-pin Skinny DIP 300 mil:
• 24-pin SOP 300 mil:
• 28-pin DIP 600 mil:
• 28-pin Skinny DIP 300 mil:
• 28-pin SOP 300 mil:
• 28-pin SSOP 209 mil:
• 32-pin DIP 600 mil:
• 32-pin SOP 450 mil:
• 32-pin SOP 300 mil:
„ Low power consumption:
● Less than 2.2 mA at 5V/4MHz
„ I/O port configuration:
● 3 bidirectional I/O ports
● 10 programmable pull-high pins
● 2 programmable open-drain I/O pins
● 2 programmable R-option pins
„ Operating voltage range: 2.3V ~ 5.5V
„ Operating temperature range: 0°C ~70°C
„ Operating frequency range (base on two
clocks):
● Crystal Mode:
DC ~ 20MHz @ 5V
DC ~ 8MHz @ 3V
DC ~ 4MHz @ 2.3V
● RC Mode:
DC ~ 4MHz @ 5V
DC ~ 4MHz @ 3V
DC ~ 4MHz @ 2.3V
EM78P447SCK
EM78P447SCM
EM78P447SAP
EM78P447SAK
EM78P447SAM
EM78P447SAS
EM78P447SBP
EM78P447SBWM
EM78P447SBM
„ One security register to prevent exposure of
OTP memory codes
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
1
EM78P447S
8-Bit Microcontroller with OTP ROM
3
Pin Assignment and Description
3.1 EM78P447S Series Pin Assignment
Figure 3-1 Pin Assignment
2•
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
3.2 EM78P447SAP and EM78P447SAM Pin Description
Symbol Pin No. Type
Function
VDD
2
-
OSCI
27
I
OSCO
26
I/O
TCC
1
I
/RESET
28
I
P50~P53
6~9
I/O
P60~P67
10~17
I/O
P70~P77
18~25
I/O
/INT
5
I
External interrupt pin triggered by a falling edge
VSS
4
-
Ground
NC
3
-
No connection
Power supply
Crystal type: Crystal input terminal or external clock input pin
RC type:
RC oscillator input pin
Crystal type: Output terminal for crystal oscillator or external
clock input pin
RC type:
Instruction clock output
External clock signal input
Real time clock/counter (with Schmitt Trigger input pin) must be
tied to VDD or VSS if not in use.
Input pin with Schmitt Trigger. If this pin remains at logic low,
the controller will also remain in reset condition.
Bidirectional 4-bit input/output pins
Bidirectional 8-bit input/output pins. These can be pulled-high
internally by software control.
Bidirectional 8-bit input/output pins:
P74~P75 can be pulled-high internally by software control
P76~P77 can have open-drain output by software control
P70 and P71 can also be defined as R-option pins
3.3 EM78P447SAS Pin Description
Symbol Pin No. Type
VDD
3
-
OSCI
27
I
OSCO
26
I/O
TCC
2
I
/RESET
28
I
P50~P53
5~8
I/O
P60~P67
9~13,
15~17
I/O
P70~P77 18~25
I/O
Function
Power supply
Crystal type: Crystal input terminal or external clock input pin.
RC type:
RC oscillator input pin
Crystal type: Output terminal for crystal oscillator or external
clock input pin.
RC type:
Instruction clock output
External clock signal input
Real time clock/counter (with Schmitt trigger input pin) must be
tied to VDD or VSS if not in use.
Input pin with Schmitt trigger. If this pin remains at logic low,
the controller will also remain in reset condition.
Bidirectional 4-bit input/output pins
Bidirectional 8-bit input/output pins. These can be pulled-high
internally by software control.
Bidirectional 8-bit input/output pins:
P74~P75 can be pulled-high internally by software control
P76~P77 can have open-drain output by software control
P70 and P71 can also be defined as R-option pins
/INT
4
I
External interrupt pin triggered by a falling edge.
VSS
1, 14
-
Ground
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
3
EM78P447S
8-Bit Microcontroller with OTP ROM
3.4 EM78P447SAK Pin Description
Symbol Pin No. Type
VDD
25
-
OSCI
20
I
OSCO
19
I/O
TCC
24
I
/RESET
21
I
P50~P54
27~28
1~2, 22
I/O
P60~P67
3~10
I/O
P70~P77
11~18
I/O
26
23
I
-
/INT
VSS
Function
Power supply
Crystal type: Crystal input terminal or external clock input pin
RC type:
RC oscillator input pin
Crystal type: Output terminal for crystal oscillator or external
clock input pin.
RC type:
Instruction clock output
External clock signal input
Real time clock/counter (with Schmitt trigger input pin) must be
tied to VDD or VSS if not in use.
Input pin with Schmitt trigger. If this pin remains at logic low,
the controller will also remain in reset condition.
Bidirectional 5-bit input/output pins
Bidirectional 8-bit input/output pins. These can be pulled-high
internally by software control.
Bidirectional 8-bit input/output pins:
P74~P75 can be pulled-high internally by software control
P76~P77 can have open-drain output by software control
P70 and P71 can also be defined as R-option pins
External interrupt pin triggered by a falling edge
Ground
3.5 EM78P447SBP, EM78P447SBWM, and EM78P447SBM
Pin Description
Symbol Pin No. Type
4•
Function
VDD
4
-
Power supply
OSCI
29
I
OSCO
28
I/O
TCC
3
I
/RESET
30
I
P50~P57
8~11,
2~1,
32~31
I/O
P60~P67
12~19
I/O
P70~P77
20~27
I/O
/INT
7
I
External interrupt pin triggered by a falling edge
VSS
6
-
Ground
NC
5
-
No connection
Crystal type: Crystal input terminal or external clock input pin
RC type:
RC oscillator input pin
Crystal type: Output terminal for crystal oscillator or external
clock input pin.
RC type:
Instruction clock output
External clock signal input
Real time clock/counter (with Schmitt trigger input pin), must be
tied to VDD or VSS if not in use.
Input pin with Schmitt trigger. If this pin remains at logic low,
the controller will also remain in reset condition.
Bidirectional 8-bit input/output pins.
Bidirectional 8-bit input/output pins. These can be pulled -high
internally by software control.
Bidirectional 8-bit input/output pins:
P74~P75 can be pulled-high internally by software control
P76~P77 can have open-drain output by software control
P70 and P71 can also be defined as R-option pins
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
3.6 EM78P447SCK and EM78P447SCM Pin Description
Symbol
Pin No. Type
Function
VDD
3
-
OSCI
23
I
OSCO
22
I/O
TCC
2
I
/RESET
24
I
P50~P54
6~9, 1
I/O
P60~P67
10~17
I/O
P74~P77
18~21
I/O
/INT
5
I
External interrupt pin triggered by a falling edge
VSS
4
-
Ground
Power supply
Crystal type: Crystal input terminal or external clock input pin
RC type:
RC oscillator input pin
Crystal type: Output terminal for crystal oscillator or external
clock input pin.
RC type:
Instruction clock output
External clock signal input
Real time clock/counter (with Schmitt trigger input pin), must be
tied to VDD or VSS if not in use.
Input pin with Schmitt trigger. If this pin remains at logic low, the
controller will also remain in reset condition.
Bidirectional 5-bit input/output pins
Bidirectional 8-bit input/output pins. These can be pulled -high
internally by software control.
Bidirectional 4-bit input/output pins:
P74~P75 can be pulled-high internally by software control
P76~P77 can have open-drain output by software control
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
5
EM78P447S
8-Bit Microcontroller with OTP ROM
4
Function Description
OSCI
/RESET
OSCO
TCC /INT
W DT Timer
Oscillator/Timing
Control
Stack 2
Stack 3
Prescale
r
Stack 4
Stack 5
ROM
W DT
Timeout
Interrupt
Control
Instruction
Register
R1(TCC)
Sleep
&
W ake-up
Control
Stack 1
PC
ALU
Instruction
Decoder
RAM
R3
ACC
R4
Data & Control Bus
IOC5
R5
IOC6
R6
PPPPPPPP
55555555
01234567
PPPPPPPP
66666666
01234567
IOC7
R7
PPPPPPPP
77777777
01234567
Figure 4-1 EM78P447S Functional Block Diagram
4.1 Operational Registers
4.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an
indirect addressing pointer. Any instruction using R0 as a pointer actually accesses
data pointed by the RAM Select Register (R4).
4.1.2 R1 (Time Clock/Counter)
„ Incremented by an external signal edge, which is defined by the TE bit (CONT-4)
through the TCC pin, or by the instruction cycle clock.
„ Writable and readable as any other registers.
„ Defined by resetting PAB (CONT-3).
„ The prescaler is assigned to TCC when the PAB bit (CONT-3) is reset.
„ The contents of the prescaler counter will be cleared only when the TCC register
is written with a value.
6•
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
4.1.3 R2 (Program Counter) and Stack
R3
A11 A10 A9 A8
A7
~
A0
00 PAGE0 0000~03FF
01 PAGE1 0400~07FF
10 PAGE2 0800~0BFF
11 PAGE3 0C00~0FFF
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
On-chip Program
Memory
User Memory
Space
CALL
RET
RETL
RETI
Hardware Vector
Software Vector
Reset Vector
Figure 4-2 Program Counter & Stack Structure
„ Depending on the device type, R2 and hardware stack are 10-bit wide. The
structure is depicted in Figure 4-2 above.
„ The configuration structure generates 1024×13 bits on-chip OTP ROM addresses
to the relative programming instruction codes. One program page is 1024 words
long.
„ R2 is set as all "1"s when under RESET condition.
„ "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows the PC to go to any location within a page.
„ "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed
onto the stack. Thus, the subroutine entry address can be located anywhere
within a page.
„ "RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top-level stack.
„ "ADD R2,A" allows the contents of ‘A’ to be added to the current PC, and the ninth
and tenth bits of the PC are cleared.
„ "MOV R2,A" allows loading of an address from the "A" register to the lower 8 bits
of the PC, and the ninth and tenth bits of the PC are cleared.
„ Any instruction that writes to R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6", etc⋅)
will cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the
computed jump is limited to the first 256 locations of a page.
„ All instructions are single instruction cycle (fclk/2 or fclk/4) except for the
instruction that would change the contents of R2. Such instruction will need one
more instruction cycle.
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
7
EM78P447S
8-Bit Microcontroller with OTP ROM
„
Data Memory Configuration
Address
R PAGE Registers
IOC PAGE Registers
00
R0
(Indirect Addressing Register)
Reserve
01
R1
(Time Clock Counter)
02
R2
(Program Counter)
Reserve
03
R3
(Status Register)
Reserve
04
R4
(RAM Select Register)
Reserve
05
R5
(Port 5)
IOC5 (I/O Port Control Register)
06
R6
(Port 6)
IOC6 (I/O Port Control Register)
07
R7
(Port 7)
IOC7 (I/O Port Control Register)
CONT (Control Register)
08
General Register
Reserve
09
General Register
Reserve
0A
General Register
Reserve
0B
General Register
IOCB Wake-up Control Register for Port 6 )
0C
General Register
Reserve
0D
General Register
Reserve
0E
General Register
IOCE (WDT, SLEEP2, Open Drain, R Option
Control Register)
0F
General Register
IOCF (Interrupt Mask Register)
10
General Registers
1F
20
Bank 0
Bank 1
Bank 2
Bank 3
3E
3F
R3F
(Interrupt Status Register)
Figure 4-3 Data Memory Configuration
8•
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
4.1.4 R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
PS1
PS0
T
P
Z
DC
C
Bit 7 (GP): General read/write bit
Bits 6 (PS1) ~ 5 (PS0): Page select bits. PS1~PS0 are used to pre-select a program
memory page. When executing a "JMP", "CALL", or other instructions
which causes the program counter to change (e.g., MOV R2, A), the
PS1~PS0 are loaded into the 11th and 12th bits of the program counter
and select one of the available program memory pages.
NOTE
RET (RETL, RETI) instruction does not change the PS0~PS1 bits. That
is, the program will always return to the page from where the subroutine
was called, regardless of the PS1~PS0 bits current setting.
PS1
PS0
Program Memory Page [Address]
0
0
Page 0 [000-3FF]
0
1
Page 1 [400-7FF]
1
0
Page 2 [800-BFF]
1
1
Page 3 [C00-FFF]
Bit 4 (T):
Time-out bit. Set to “1” with the "SLEP" and "WDTC" commands, or
during power up, and reset to “0” with the WDT time-out.
Bit 3 (P):
Power down bit. Set to “1” during power on or by "WDTC" command and
reset to “0” by "SLEP" command.
Bit 2 (Z):
Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C):
Carry flag
4.1.5 R4 (RAM Select Register)
Bits 7~6:
Determine which bank is activated among the 4 banks.
Bits 5~0:
Are used to select the registers (Address 00~3F) in the indirect
addressing mode.
If no indirect addressing is used, the RSR can be used as an 8-bit general-purpose
read/writer register. See the data memory configuration in Figure 4-3 above
4.1.6 R5~R7 (Port 5 ~ Port 7)
R5, R6, and R7 are I/O registers
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
9
EM78P447S
8-Bit Microcontroller with OTP ROM
4.1.7 R8~R1F and R20~R3E (General Purpose Registers)
R8~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.
4.1.8 R3F (Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
EXIF
-
-
TCIF
Bit 3 (EXIF):
External interrupt flag. Set by a falling edge on the /INT pin. The
flag is cleared by software
Bits 1, 2 & 4~7: Not implemented and are read as “0”.
Bit 0 (TCIF):
TCC overflow interrupt flag. Set when TCC overflows; the flag is
cleared by software.
0: Non-interrupt
1: Interrupt request
R3F can be cleared by instruction, but cannot be set by instruction. IOCF is the
interrupt mask register.
NOTE
Reading R3F obtains the result of the R3F "logic AND" and IOCF.
4.2 Special Function Registers
4.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator, which is not an addressable register.
4.2.2 CONT (Control Register)
The CONT register is both readable and writable.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PHEN
/INT
TS
TE
PAB
PSR2
PSR1
PSR0
Bit 7 (/PHEN): Control bit is used to enable the pull-high of P60~P67, P74, and P75
pins
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/INT):
Interrupt enable flag
0: Masked by DISI or hardware interrupt
1: Enabled by ENI/RETI instructions
10 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
Bit 5 (TS):
TCC signal source
0: Internal instruction cycle clock
1: Transition on TCC pin
Bit 4 (TE):
TCC signal edge
0: Increment if transition is from low to high takes place on TCC pin
1: Increment if transition is from high to low takes place on TCC pin
Bit 3 (PAB): Prescaler assignment bit
0: TCC
1: WDT
Bit 2 (PSR2) ~ Bit 0 (PSR0): TCC/WDT prescaler bits
PSR2
PSR1
PSR0
TCC Rate
WDT Rate
0
0
0
1:2
1:1
0
0
1
1:4
1:2
0
1
0
1:8
1:4
0
1
1
1:16
1:8
1
0
0
1:32
1:16
1
0
1
1:64
1:32
1
1
0
1:128
1:64
1
1
1
1:256
1:128
4.2.3 IOC5 ~ IOC7 (I/O Port Control Register)
0: Defines the relative I/O pin as output
1: Place the relative I/O pin into high impedance
IOC5, IOC6, and IOC7 registers are all readable and writable.
4.2.4 IOCB (Wake-up Control Register for Port 6)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/WUE7
/WUE6
/WUE5
/WUE4
/WUE3
/WUE2
/WUE1
/WUE0
Bit 7 (/WUE7): Control bit used to enable the wake-up function of P67 pin.
Bit 6 (/WUE6): Control bit used to enable the wake-up function of P66 pin.
Bit 5 (/WUE5): Control bit used to enable the wake-up function of P65 pin.
Bit 4 (/WUE4): Control bit used to enable the wake-up function of P64 pin.
Bit 3 (/WUE3): Control bit used to enable the wake-up function of P63 pin.
Bit 2 (/WUE2): Control bit used to enable the wake-up function of P62 pin.
Bit 1 (/WUE1): Control bit used to enable the wake-up function of P61 pin.
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
11
EM78P447S
8-Bit Microcontroller with OTP ROM
Bit 0 (/WUE0): Control bit used to enable the wake-up function of P60 pin.
0: Enable internal wake-up
1: Disable internal wake-up
IOCB Register is readable and writable.
4.2.5 IOCE (WDT Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
ODE
WDTE
SLPC
ROC
-
-
/WUE
Bit 6 (ODE):
Control bit used to enable the open-drain function of P76 and P77 pins
0: Disable open-drain output
1: Enable open-drain output
The ODE bit can be read and written to.
Bit 5 (WDTE): Control bit used to enable Watchdog timer
The WDTE bit is used only when ENWDT, the CODE Option bit, is "0".
It is only when the ENWDT bit is "0" that WDTE bit is able to disable
/enable the WDT.
0: Disable WDT
1: Enable WDT
The WDTE bit is not used if ENWDT, the CODE Option bit ENWDT, is
"1". That is, if the ENWDT bit is "1", WDT is always disabled no
matter what the WDTE bit status is. The WDTE bit can be read and
written.
Bit 4 (SLPC): This bit is set by hardware at the low level trigger of the wake-up
signal and is cleared by software. SLPC is used to control the
oscillator operation. The oscillator is disabled (oscillator is stopped,
and the controller enters into Sleep 2 mode) on the high-to-low
transition and is enabled (controller is awakened from Sleep 2 mode)
on the low-to-high transition. In order to ensure a stable oscillator
output, once the oscillator is enabled again, there should be a delay
for approximately 18ms1 (oscillator start-up timer (OST)) before the
next instruction of the program is executed. The OST is always
activated by a wake-up event from Sleep mode regardless whether
the Code Option bit ENWDT status is "0" or otherwise. After waking
up, the WDT is enabled if the Code Option ENWDT is "1". The block
diagram of Sleep 2 mode and wake-up invoked by an input trigger is
depicted in the following figure (Figure 4-4). The SLPC bit can be
read and written to.
1
Vdd = 5V, set up time period = 16.2ms ± 30%
Vdd = 3V, set up time period = 19.6ms ± 30%
12 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
/WUE0
Oscillator
Enable
Disable
/WUE1
Reset
Q
PR D
CLK
Q
VCC
CL
Clear
Set
8
/WUE7
from S/W
P60~P67
VCC
/WUE
/PHEN
2
P74~P75
Figure 4-4 Block Diagram Showing Sleep Mode and Wake-up Circuits on I/O Ports
Bit 3 (ROC):
ROC is used for the R-option. Setting ROC to "1" enables the status
of the R-option pins (P70, P71) and allows the controller to read.
Clearing ROC disables the R-option function. Otherwise, the R-option
function is introduced. You must connect the P71 pin and/or P70 pin
to VSS with a 430KΩ external resistor (Rex). If Rex is connected
/disconnected to VDD, the status of P70 (P71) will be read as "0"/"1"
(refer to Figure 4-6b of Section 4.4). The ROC bit is readable and
writable.
Bits 1~2, & 7: Not used
Bit 0 (/WUE): Control bit is used to enable the wake-up function of P74 and P75.
0: Enable the wake-up function
1: Disable the wake-up function
The /WUE bit can be read and written to.
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
13
EM78P447S
8-Bit Microcontroller with OTP ROM
4.2.6 IOCF (Interrupt Mask Register)
Bit 7
Bit 6
Bit5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
EXIE
-
-
TCIE
Bit 3 (EXIE):
EXIF interrupt enable bit
0: Disable EXIF interrupt
1: Enable EXIF interrupt
Bits 1,2, &4~7: Not used.
Bit 0 (TCIE):
TCIF interrupt enable bit
0: Disable TCIF interrupt
1: Enable TCIF interrupt
Individual interrupt is enabled by setting its associated control bit in the IOCF to "1".
Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction (refer to Figure4-8 under Section 4.6).
IOCF register is readable and writable.
4.3 TCC/WDT and Prescaler
An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is
available for either the TCC or WDT only at a given time, and the PAB bit of the
CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits
determine the ratio. The prescaler is cleared each time the instruction is written to
TCC under TCC mode. The WDT and prescaler, when assigned to WDT mode, are
cleared by the “WDTC” or “SLEP” instructions. Figure 4-5 below depicts the circuit
diagram of TCC/WDT.
R1 (TCC) is an 8-bit timer/counter. The TCC clock source can be internal or external
clock input (edge selectable from TCC pin). If the TCC signal source is from the
internal clock, TCC is incremented by 1 every time an instruction cycle is executed
(without prescaler). Referring to Figure 4-5 below, CLK=Fosc/2 or CLK=Fosc/4
selection is determined by the Code Option bit CLK status. CLK=Fosc/2 is used if
CLK bit is "0", and CLK=Fosc/4 is used if CLK bit is "1". If the TCC signal source
comes from an external clock input, TCC is incremented by 1 at every falling edge or
rising edge of the TCC pin.
The watchdog timer is a free running on-chip RC oscillator. The WDT keeps on
running even after the oscillator driver has been turned off (i.e., in Sleep mode).
During normal operation or Sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled any time during normal mode
through software programming (refer to WDTE bit of IOCE register in Section 4.2.5
above). Without prescaler, the WDT time-out period is approximately 18 ms2 (default).
2
Vdd = 5V, set up time period = 16.2ms ± 30%
Vdd = 3V, set up time period = 19.6ms ± 30%
14 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
Data Bus
CLK(=Fosc/2)
0
TCC
Pin
1
1
M
U
X
M
U
X
0
SYNC
2 cycles
TE
TS
TCC(R1)
TCC overflow interrupt
PAB
0
WDT
1
M
U
X
8-bit Counter
8-to-1 MUX
WDTE
(in IOCE)
PSR0~PSR2
PAB
0
1
MUX
PAB
WDT timeuot
Figure 4-5 TCC and WDT Block Diagram
4.4 I/O Ports
The I/O registers, Port 5, Port 6, and Port 7, are bidirectional tri-state I/O ports. The
Pull-high, R-option, and Open-drain functions can be performed internally by CONT
and IOCE respectively. Port 6, P74, and P75 feature input status change wake-up
function. Each I/O pin can be defined as "input" or "output" pin by the I/O control
register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable
and writable. The I/O interface circuits for Port 5, Port 6, and Port 7 are illustrated in
the following figures.
PCRD
Q PR D
CLK
Q
PCWR
CL
IOD
Q PR D
PORT
CLK
Q
0
1
M
U
X
PDWR
CL
PDRD
Figure 4-6a I/O Port and I/O Control Register Circuit
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
15
EM78P447S
8-Bit Microcontroller with OTP ROM
PCRD
VCC
ROC
Q PR D
Weak
Pull- up
CLK
Q
Port
Q
PR
Q
CL
IOD
D
CLK
0
Rex*
1
PCWR
CL
PDWR
PDRD
M
U
X
*The Rex is 430K ohm external resistor
Figure 4-6b I/O Port with R-Option (P70, P71) Circuit
4.5 Reset and Wake-up
4.5.1 Reset
A Reset is initiated by one of the following event:
1) Power on reset
2) /RESET pin input “low”
3) WDT timeout (if enabled)
The device is kept in a Reset condition for a period of approximately 18ms3 (one
oscillator start-up timer period) after the reset is detected. Once a Reset occurs, the
following functions are performed (see next figure):
„ The oscillator starts or is running
„ The Program Counter (R2) is set to all "1"
„ When power is switched on, Bits 5~6 of R3 and the upper 2 bits of R4 are cleared.
„ All I/O port pins are configured as input mode (high-impedance state).
„ The Watchdog timer and prescaler are cleared.
„ At power on, Bits 5~6 of R3 are cleared.
„ At power on, the upper 2 bits of R4 are cleared.
„ The CONT register bits are set to all "1" except Bit 6 (INT flag).
„ IOCB register is set to “1” (disable P60 ~ P67 wake-up function).
„ Bits 3 and 6 of IOCE register are cleared, and Bits 0, 4, and 5 are set to "1".
„ Bits 0 and 3 of R3F register and Bits 0 and 3 of IOCF registers are cleared.
3
Vdd = 5V, set up time period = 16.2ms ± 30%
Vdd = 3V, set up time period = 19.6ms ± 30%
16 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
The Sleep (power down) mode is asserted by executing the “SLEP” instruction.
While entering Sleep mode, WDT (if enabled) is cleared but keeps on running. The
controller is awakened by one of the following events:
1) External reset input on /RESET pin;
2) WDT time-out (if enabled)
The above two events will cause the microcontroller EM78P447S to reset. The T and
P flags of R3 are used to determine the source of the reset (wake-up).
In addition to the basic Sleep 1 mode, EM78P447S has another Sleep mode
(designated as Sleep 2 mode) and is invoked by clearing the IOCE register “SLPC”
bit. Under the Sleep 2 mode, the controller can be awakened by one of the following
events:
1) Any of the wake-up pins is “0” as illustrated in Figure 4-4 under Section 4.2.5.
Upon waking, the controller will continue to execute the next instruction. In this
case, before entering Sleep 2 Mode, the wake-up function of the trigger sources
(P60~P67 and P74~P75) should be defined (i.e., as input pin) and enabled (i.e.,
pull-high and wake-up controlled). It should be noted that after waking up, the
WDT will be enabled regardless what the Code Option bit ENWDT status is (“0” or
“1”). The WDT operation (to be enabled or disabled) should be properly defined
in software after waking up. See the Sleep 2 mode details operation in Section
4.5.1.1 below.
2) WDT time-out (if enabled) or external reset input on /RESET pin will trigger a
controller reset.
VDD
D
Q
CLK
CLR
Oscillator
CLK
Power-on
Reset
Voltage
Detector
WDTE
WDT
WDT
Timeout
Setup Time
RESET
/RESET
Figure 4-7 Controller Reset Block Diagram
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
17
EM78P447S
8-Bit Microcontroller with OTP ROM
4.5.1.1
Sleep 2 and Sleep 1 Modes Operation Summary
Sleep 2 Mode
Sleep 1 Mode
a) Before Sleep
a) Before Sleep
1. Execute SLEP instruction
1. Set Port 6, P74 or P75 as Input
2. Enable Pull-high and set WDT
prescaler over 1:1 (Set CONT.7 and
CONT.3 ~ CONT.0)
3. Enable Wake-up (Set IOCB or IOCE.0)
4. Execute Sleep 2 (Set IOCE.4)
b) After Wake-up
b) After Wake-up
1. Reset
1. Next instruction
2. Disable Wake-up
3. Disable WDT (Set IOCE.5)
If Port 6 (Input Status Change Wake-up) is used (Sleep 2 Mode, case ‘a’ in the above
table) to wake-up the EM78P447S from Sleep 1 mode, the following instructions must
be executed before entering Sleep 2 mode:
MOV
IOW
MOV
CONTW
MOV
IOW
MOV
IOW
After Wake-up
NOP
MOV
IOW
MOV
IOW
A, @11111111b
R6
A, @0xxx1010b
;Set Port6 input
A, @00000000b
RB
A, @xx00xxx1b
RE
;Enable Port 6 wake-up function
A, @11111111b
RB
A, @ xx01xxx1b
RE
;Disable Port 6 wake-up function
;Set Port 6 pull-high, WDT
prescaler.
;Prescaler must be set at 1:1
;Enable SLEEP 2
;Disable WDT
NOTE
„ After waking up from Sleep 2 mode, WDT is automatically enabled. The WDT
enabled/disabled operation after waking up from Sleep 2 mode should be properly
defined in the software.
„ To avoid reset from occurring when the Port 6 status change interrupt enters into
interrupt vector, or is used to wake-up the MCU, the WDT prescaler must be set
above 1:1 ratio.
18 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
4.5.1.2
Register Initial Values after Reset
Legend X: Not used U: Unknown or don’t care --: Not defined.
P: Previous value before reset
t: Check Table 8
Address
Name
N/A
IOC5
N/A
IOC6
N/A
IOC7
N/A
CONT
0x00
0x01
R1(TCC)
0x02
R2(PC)
0x03
R3(SR)
0x04
R4
(RSR)
0x05
R5(P5)
Reset Type
Bit 7
Bit Name
C57
Type
A B
Power-On
0 1
/RESET and WDT
0 1
Wake-Up from Pin Change 0 P
Bit Name
C67
Power-On
1
/RESET and WDT
1
Wake-Up from Pin Change
P
Bit Name
C77
Power-On
1
/RESET and WDT
1
Wake-Up from Pin Change
P
Bit Name
/PHEN
Power-On
1
/RESET and WDT
1
Wake-Up from Pin Change
P
Bit Name
-Power-On
U
/RESET and WDT
P
Wake-Up from Pin Change
P
Bit Name
-Power-On
0
/RESET and WDT
0
Wake-Up from Pin Change
P
Bit Name
-Power-On
1
/RESET and WDT
1
Wake-Up from Pin Change 0/P*
Bit Name
GP
Power-On
0
/RESET and WDT
0
Wake-Up from Pin Change
P
Bit Name
RSR.1
Power-On
0
/RESET and WDT
0
Wake-Up from Pin Change
P
Bit Name
P57
Power-On
U
/RESET and WDT
P
Wake-Up from Pin Change
P
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C56
A B
0 1
0 1
0 P
C66
1
1
P
C76
1
1
P
/INT
0
P
P
-U
P
P
-0
0
P
-1
1
C55
A B
0 1
0 1
0 P
C65
1
1
P
C75
1
1
P
TS
1
1
P
-U
P
P
-0
0
P
-1
1
C54
A B
0 1
0 1
0 P
C64
1
1
P
C74
1
1
P
TE
1
1
P
-U
P
P
-0
0
P
-1
1
C53
-1
1
P
C63
1
1
P
C73
1
1
P
PAB
1
1
P
-U
P
P
-0
0
P
-1
1
C52
-1
1
P
C62
1
1
P
C72
1
1
P
PSR2
1
1
P
-U
P
P
-0
0
P
-1
1
C51
-1
1
P
C61
1
1
P
C71
1
1
P
PSR1
1
1
P
-U
P
P
-0
0
P
-1
1
C50
-1
1
P
C60
1
1
P
C70
1
1
P
PSR0
1
1
P
-U
P
P
-0
0
P
-1
1
0/P*
PS1
0
0
P
RSR.0
0
0
P
P56
U
P
P
0/P*
PS0
0
0
P
-U
P
P
P55
U
P
P
0/P*
T
1
t
t
-U
P
P
P54
U
P
P
0/P*
P
1
t
t
-U
P
P
P53
U
P
P
0/P*
Z
U
P
P
-U
P
P
P52
U
P
P
0/P*
DC
U
P
P
-U
P
P
P51
U
P
P
0/P*
C
U
P
P
-U
P
P
P50
U
P
P
* Execute the next instruction after the ”SLPC” bit status of the IOCE register goes on high-to-low transition.
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
19
EM78P447S
8-Bit Microcontroller with OTP ROM
(Continuation)
Address Name
0x06
R6(P6)
0x07
R7(P7)
0x3F
R3F(ISR)
0x0B
IOCB
0x0E
IOCE
0x0F
IOCF
0x08
R8
0x09~
R9~R3E
0x3E
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit Name
P67
P66
P65
P64
Power-On
U
U
U
U
/RESET and WDT
P
P
P
P
Wake-Up from Pin Change
P
P
P
P
Bit Name
P77
P76
P75
P74
Power-On
U
U
U
U
/RESET and WDT
P
P
P
P
Wake-Up from Pin Change
P
P
P
P
Bit Name
X
X
X
X
Power-On
U
U
U
U
/RESET and WDT
U
U
U
U
Wake-Up from Pin Change
U
U
U
U
Bit Name
/WUE7 /WUE6 /WUE5 /WUE4
Power-On
1
1
1
1
/RESET and WDT
1
1
1
1
Wake-Up from Pin Change
P
P
P
P
Bit Name
X
ODE WDTE SLPC
Power-On
U
0
1
1
/RESET and WDT
U
0
1
1
Wake-Up from Pin Change
U
P
1
1
Bit Name
X
X
X
X
Power-On
U
U
U
U
/RESET and WDT
U
U
U
U
Wake-Up from Pin Change
U
U
U
U
Bit Name
----Power-On
0
0
0
0
/RESET and WDT
0
0
0
0
Wake-Up from Pin Change
P
P
P
P
Bit Name
----Power-On
U
U
U
U
/RESET and WDT
P
P
P
P
Wake-Up from Pin Change
P
P
P
P
Bit 3
Bit 2
Bit 1
Bit 0
P63
P62
P61
P60
U
U
U
U
P
P
P
P
P
P
P
P
P73
P72
P71
P70
U
U
U
U
P
P
P
P
P
P
P
P
EXIF
X
X
TCIF
0
U
U
0
0
U
U
0
P
U
U
P
/WUE3 /WUE2 /WUE1 /WUE0
1
1
1
1
1
1
1
1
P
P
P
P
ROC
X
X
/WUE
0
U
U
1
0
U
U
1
P
U
U
P
EXIE
X
X
TCIE
0
U
U
0
0
U
U
0
P
U
U
P
----0
0
0
0
0
0
0
0
P
P
P
P
----U
U
U
U
P
P
P
P
P
P
P
P
4.5.2 Status of RST, T, and P of Status Register
A Reset condition is initiated by one of the following events:
1) A power-on condition
2) A high-low-high pulse on the /RESET pin
3) Watchdog timer time-out
20 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
The values of T and P as listed in table below, are used to verify the event that
triggered the processor to wake up.
Reset Type
T
P
Power on
1
1
/RESET during Operating mode
*P
*P
/RESET wake-up during Sleep 1 mode
1
0
/RESET wake-up during Sleep 2 mode
*P
*P
WDT during Operating mode
0
*P
WDT wake-up during Sleep 1 mode
0
0
WDT wake-up during Sleep 2 mode
0
*P
Wake-up on pin change during Sleep 2 mode
*P
*P
*P: Previous status before Reset
The following shows the events that may affect the T and P Status
Event
T
P
Power on
1
1
WDTC instruction
1
1
WDT time-out
0
*P
SLEP instruction
1
0
Wake-up on pin change during Sleep 2 mode
*P
*P
*P: Previous value before Reset
4.6 Interrupt
The following are the two interrupts of EM78P447S:
1) TCC overflow interrupt
2) External interrupt (/INT pin)
R3F is the interrupt status register that records the interrupt requests in the relative
flags/bits. IOCF is the interrupt mask register. The global interrupt is enabled by the
ENI instruction and is disabled by the DISI instruction. When one of the interrupts
(enabled) occurs, the next instruction will be fetched from address 001H. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the
flag bits in R3F. The interrupt flag bit must be cleared by instructions before leaving
the interrupt service routine and before interrupts are enabled to avoid recursive
interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (R3F) is set regardless of
the status of its mask bit or the execution of ENI. Note that the outcome of R3F is the
logic AND of R3F and IOCF (refer to Figure 4-8 below). The RETI instruction ends
the interrupt routine and enables the global interrupt (the execution of ENI).
When an interrupt is generated by the INT instruction (enabled), the next instruction
will be fetched from Address 002H.
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
21
EM78P447S
8-Bit Microcontroller with OTP ROM
VCC
P
R
D
/IRQn
CLK
C
L
Q
IRQn
INT
_
Q
IRQm
RFRD
RF
ENI/DISI
Q
IOCF
_
Q
P
R
C
L
IOD
D
CLK
IOCFWR
/RESET
IOCFRD
RFWR
Figure 4-8 Interrupt Input Circuit
4.7 Oscillator
4.7.1 Oscillator Modes
The EM78P447S can operate in three different oscillator modes:
„ High Crystal (HXT) oscillator mode
„ Low Crystal (LXT) oscillator mode
„ External RC (ERC) oscillator mode
You can select one of them by programming MS, HLF, and HLP in the Code Option
Register. The following table shows how these three modes are defined.
Mode
MS
HLF
HLP
ERC External RC oscillator mode)
0
*×
*×
HXT (High Crystal oscillator mode)
1
1
*×
LXT (Low Crystal oscillator mode)
1
0
0
*x: Don’t Care
NOTE
The transient point of the system frequency between HXT and LXY is 400kHz.
The maximum limit for operational frequencies of crystal/resonator under different
VDDs is shown below.
Conditions
Two cycles with two clocks
22 •
VDD
Fxt Max. (MHz)
2.3
4.0
3.0
8.0
5.0
20.0
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
4.7.2 Crystal Oscillator/Ceramic Resonators (Crystal)
The EM78P447S can be driven by an external clock signal through the OSCI pin as
illustrated in Figure 4-9a below.
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation as indicated in the Figure 4-9b. The same
thing applies whether it is in the HXT mode or in the LXT mode.
E x t. C lo c k
OSCI
OSCO
E M 78P 447S
Figure 4-9a Crystal/Resonator Circuit
C1
OSCI
EM78P447S
Crystal
OSCO
RS
C2
Figure 4-9b Crystal/Resonator Circuit
The following table provides the recommended values of C1 and C2. Since each
resonator has its own attribute, you should refer to its specification for appropriate
values of C1 and C2. RS which is a serial resistor may be necessary for AT strip cut
crystal or low frequency mode.
Oscillator Type
Ceramic Resonators
Frequency Mode
HXT
LXT
Crystal Oscillator
HXT
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
Frequency
C1 (pF)
C2 (pF)
455 kHz
100~150
100~150
2.0 MHz
20~40
20~40
4.0 MHz
10~30
10~30
32.768 kHz
25
15
100 kHz
25
25
200 kHz
25
25
455 kHz
20~40
20~150
1.0 MHz
15~30
15~30
2.0 MHz
15
15
4.0 MHz
15
15
23
EM78P447S
8-Bit Microcontroller with OTP ROM
For some applications that do not need a very precise timing calculation, the RC
oscillator (Figure 4-9c bellow) offers a lot of cost savings. Nevertheless, it should be
noted that the frequency of the RC oscillator is influenced by the supply voltage, the
values of the resistor (Rext), the capacitor (Cext), and even by the operation
temperature. Moreover, the frequency also changes slightly from one chip to another
due to the manufacturing process variation.
In order to maintain a stable system frequency, the values of the Cext should not be
less than 20pF, and the value of Rext should not be greater than 1 MΩ. If they
cannot be kept in this range, the frequency is easily affected by noise, humidity, and
leakage.
The smaller the Rext in the RC
oscillator is, the faster its frequency
will be. On the contrary, for very low
Rext values, for instance; 1 KΩ, the
oscillator becomes unstable because
the NMOS cannot discharge the
current of the capacitance correctly.
VCC
Rext
O SCI
EM 78P447S
Cext
Based on the above reasons, it must
be kept in mind that all of the supply
voltage, the operation temperature,
the components of the RC oscillator,
Figure 4-9c External RC Oscillator Mode Circuit
the RC oscillator, the package type,
and the way the PCB is layout, will affect the system frequency.
The following are the typical RC oscillator frequencies:
Cext
20 pF
100 pF
300 pF
24 •
Rext
Average Fosc 5V,
25°C
Average Fosc 3V,
25°C
3.3k
4.32 MHz
3.56 MHz
5.1k
2.83 MHz
2.8 MHz
10k
1.62 MHz
1.57 MHz
100k
184 kHz
187 kHz
3.3k
1.39 MHz
1.35 MHz
5.1k
950 kHz
930 kHz
10k
500 kHz
490 kHz
100k
54 kHz
55 kHz
3.3k
580 kHz
550 kHz
5.1k
390 kHz
380 kHz
10k
200 kHz
200 kHz
100k
21 kHz
21 kHz
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
NOTE
1. Measured on DIP packages
2. This is for design reference only
3. The frequency drift is ± 30%
4.8 Code Option Register
The EM78P447S has a Code Option word that is not a part of the normal program
memory. The option bits cannot be accessed during normal program execution.
Bit
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Mnemonic
MS
/ENWDT
CLK
CS
HLF
HLP
TYPE
1
XTAL
Disable
4clock
Off
>400kHz
High
A
0
RC
Enable
2clock
On
<=400kHz
Low
B
Bit 12 (MS):
Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
-
-
-
-
-
-
Oscillator type selection
0: RC type
1: Crystal type (Crystal 1 and Crystal 2)
Bit 11 (/ENWDT): Watchdog timer enable bit
0: Enable
1: Disable
Bit 10 (CLK):
Instruction period option bit
0: Two oscillator periods
1: Four oscillator periods
Refer to the Instruction Set, Section 4.10.
Bit 9 (CS):
Code Security Bit
0: Security On
1: Security Off
Bit 8 (HLF):
Crystal frequency selection
0: Crystal 2 type (low frequency, 32.768kHz)
1: Crystal 1 type (high frequency)
This bit will affect the system oscillation only when Bit 12 (MS) is “1”. When MS is”0”,
HLF must be “0”.
NOTE
The transient point of the system frequency between HXT and LXY is 400 kHz.
Bit 7 (HLP):
Power selection
0: Low power
1: High power
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
25
EM78P447S
8-Bit Microcontroller with OTP ROM
Bit 6 (TYPE):
Type selection for EM78P447SA or SB
0: EM78P447SB
1: EM78P447SA
Bit 5 & Bit 4:
Reserved
0: Bit 5 is set to “1” all the time
1: Bit 4 is set to “0” all the time
Bits 3~0:
Customer’s ID code
4.9 Power-On Considerations
Any microcontroller is not guaranteed to start and operate properly before the power
supply remains at its steady state.
The EM78P447S POR voltage range is 1.2V~1.8V. For customer applications, when
power is OFF, Vdd must drop to below 1.2V and remains OFF for 10µs before power
can be switched ON again. This way, the EM78P447S will reset and work normally.
The extra external reset circuit will work well if Vdd can rise at very fast speed (50 ms
or less). However, in most cases where critical applications are involved, extra
devices are required to assist in solving the power-up problems.
4.9.1 External Power-on Reset Circuit
The circuit illustrated below implements an external RC to produce the reset pulse.
The pulse width (time constant) should be kept long enough for Vdd to achieve the
minimum operating voltage. This circuit is applicable when the power supply has a
slow rise time. As the current leakage from the /RESET pin is about ±5µA, it is
recommended that R should not be greater than 40 KΩ. In this way, the /RESET pin
voltage is held below 0.2V. The diode (D) acts as a short circuit at the moment of
power down. The capacitor C will discharge rapidly and fully. Rin, the current-limited
resistor, will prevent high current or ESD (electrostatic discharge) from flowing into
the Pin /RESET.
Vdd
R
/RESET
D
EM78P447S
Rin
C
Figure 4-10 External Power-Up Reset Circuit
26 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
4.9.2 Residue-Voltage Protection
When the battery is replaced, device power (Vdd) is taken off but the residue-voltage
remains. The residue-voltage may trip below Vdd minimum, but not to zero. This
condition may cause a poor power-on reset. The following two figures show how to
build the residue-voltage protection circuit.
Vdd
Vdd
33K
EM78P447S
Q1
10K
/RESET
40K
1N4684
Figure 4-11a Residue Voltage Protection Circuit 1
Vdd
Vdd
R1
EM78P447S
Q1
/RESET
40K
R2
Figure 4-11b Residue Voltage Protection Circuit 2
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
27
EM78P447S
8-Bit Microcontroller with OTP ROM
4.10 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and
one or more operands. Normally, all instructions are executed within one single
instruction cycle (one instruction consists of 2 oscillator periods), unless the program
counter is changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of
arithmetic or logic operation on R2 (e.g., "SUB R2,A", "BS (C) R2,6", "CLR R2", etc⋅).
In this case, the execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try modifying the instruction as follows:
1) Change one instruction cycle to consist of four oscillator periods.
2) Execute within two instruction cycles, "JMP", "CALL", "RET", "RETL", "RETI", or
the conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") instructions which
were tested to be true. Also execute within two instruction cycles the instructions
that are written to the program counter.
Case 1 above is selected by the Code Option bit, called CLK. One instruction cycle
consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is high.
NOTE
Once the four oscillator periods within one instruction cycle is selected as in Case 1,
the internal clock source to TCC should be CLK=Fosc/4, NOT Fosc/2 as indicated in
Figure 4-5 of Section 4-3.
In addition, the instruction set has the following features:
1) Every bit of any register can be set, cleared, or tested directly.
2) The I/O register can be regarded as general register. That is, the same instruction
can operate on the I/O register.
28 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
4.10.1 EM78P447S Instruction Set Table
The following symbols are use:
R = Register designator that specifies which one of the registers (including operation and
general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine
the selected register bank.
b = Bit field designator that selects the value for the bit located in the Register “R” and which
affects the operation.
k = 8 or 10-bit constant or literal value
Binary Instruction
Hex
Mnemonic
Operation
0 0000 0000 0000
0000
NOP
No Operation
0 0000 0000 0001
0001
DAA
Decimal Adjust A
0 0000 0000 0010
0002
CONTW
0 0000 0000 0011
0003
0 0000 0000 0100
Status
Affected
None
C
A → CONT
None
SLEP
0 → WDT, Stop oscillator
T, P
0004
WDTC
0 → WDT
T, P
0 0000 0000 rrrr
000r
IOW R
A → IOCR
None
0 0000 0001 0000
0010
ENI
Enable Interrupt
None
0 0000 0001 0001
0011
DISI
Disable Interrupt
None
0 0000 0001 0010
0012
RET
[Top of Stack] → PC
None
0 0000 0001 0011
0013
RETI
[Top of Stack] → PC,
Enable Interrupt
None
0 0000 0001 0100
0014
CONTR
CONT → A
None
0 0000 0001 rrrr
001r
IOR R
IOCR → A
None
0 0000 0010 0000
0020
TBL
0 0000 01rr rrrr
00rr
MOV R,A
A→R
None
0 0000 1000 0000
0080
CLRA
0→A
Z
0 0000 11rr rrrr
00rr
CLR R
0→R
Z
0 0001 00rr rrrr
01rr
SUB A,R
R-A → A
Z,C, DC
0 0001 01rr rrrr
01rr
SUB R,A
R-A → R
Z,C, DC
0 0001 10rr rrrr
01rr
DECA R
R-1 → A
Z
0 0001 11rr rrrr
01rr
DEC R
R-1 → R
Z
0 0010 00rr rrrr
02rr
OR A,R
A∨R→A
Z
0 0010 01rr rrrr
02rr
OR R,A
A∨R→R
Z
0 0010 10rr rrrr
02rr
AND A,R
A&R→A
Z
0 0010 11rr rrrr
02rr
AND R,A
A&R→R
Z
0 0011 00rr rrrr
03rr
XOR A,R
A⊕R→A
Z
0 0011 01rr rrrr
03rr
XOR R,A
A⊕R→R
Z
0 0011 10rr rrrr
03rr
ADD A,R
A+R→A
Z, C, DC
0 0011 11rr rrrr
03rr
ADD R,A
A+R→R
Z, C, DC
0 0100 00rr rrrr
04rr
MOV A,R
R→A
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
R2+A → R2,
Bits 8~9 of R2 unchanged
1
1
Z,C, DC
Z
29
EM78P447S
8-Bit Microcontroller with OTP ROM
(Continuation)
1
2
3
30 •
Operation
Status
Affected
Binary Instruction
Hex
Mnemonic
0 0100 01rr rrrr
04rr
MOV R,R
R→R
Z
0 0100 10rr rrrr
04rr
COMA R
/R → A
Z
0 0100 11rr rrrr
04rr
COM R
/R → R
Z
0 0101 00rr rrrr
05rr
INCA R
R+1 → A
Z
0 0101 01rr rrrr
05rr
INC R
R+1 → R
Z
0 0101 10rr rrrr
05rr
DJZA R
R-1 → A, skip if zero
None
0 0101 11rr rrrr
05rr
DJZ R
R-1 → R, skip if zero
None
0 0110 00rr rrrr
06rr
RRCA R
R(n) → A(n-1),
R(0) → C, C → A(7)
C
0 0110 01rr rrrr
06rr
RRC R
R(n) → R(n-1),
R(0) → C, C → R(7)
C
0 0110 10rr rrrr
06rr
RLCA R
R(n) → A(n+1),
R(7) → C, C → A(0)
C
0 0110 11rr rrrr
06rr
RLC R
R(n) → R(n+1),
R(7) → C, C → R(0)
C
0 0111 00rr rrrr
07rr
SWAPA R
R(0-3) → A(4-7),
R(4-7) → A(0-3)
None
0 0111 01rr rrrr
07rr
SWAP R
R(0-3) ↔ R(4-7)
None
0 0111 10rr rrrr
07rr
JZA R
R+1 → A, skip if zero
None
0 0111 11rr rrrr
07rr
JZ R
R+1 → R, skip if zero
None
0 100b bbrr rrrr
0xxx
BC R,b
0 → R(b)
None
0 101b bbrr rrrr
0xxx
BS R,b
1 → R(b)
None
0 110b bbrr rrrr
0xxx
JBC R,b
if R(b)=0, skip
None
0 111b bbrr rrrr
0xxx
JBS R,b
if R(b)=1, skip
None
1 00kk kkkk kkkk
1kkk
CALL k
PC+1 → [SP],
(Page, k) → PC
None
1 01kk kkkk kkkk
1kkk
JMP k
(Page, k) → PC
None
1 1000 kkkk kkkk
18kk
MOV A,k
k→A
None
1 1001 kkkk kkkk
19kk
OR A,k
A∨k→A
Z
1 1010 kkkk kkkk
1Akk
AND A,k
A&k→A
Z
1 1011 kkkk kkkk
1Bkk
XOR A,k
A⊕k→A
Z
1 1100 kkkk kkkk
1Ckk
RETL k
k → A, [Top of Stack] → PC
1 1101 kkkk kkkk
1Dkk
SUB A,k
k-A → A
1 1110 0000 0010
1E02
INT
1 1111 kkkk kkkk
1Fkk
ADD A,k
PC+1 → [SP], 002H → PC
k+A → A
2
3
None
Z, C, DC
None
Z, C, DC
This instruction is applicable to IOC5~IOC7, IOCB, IOCE, and IOCF only.
This instruction is not recommended for R3F operation.
This instruction cannot operate under R3F
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
5
Timing Diagram
AC Test Input/Output W aveform
2.4
2.0
0.8
TEST POINTS
2.0
0.8
0.4
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Tim ing m easurem ents are
m ade at 2.0V for logic "1",and 0.8V for logic "0".
RESET Tim ing (CLK="0")
NO P
Instruction 1
Executed
CLK
/RESET
Tdrh
TCC Input Tim ing (CLKS="0")
Tins
CLK
TCC
Ttcc
Figure 5-1 EM78P447S Timing Diagram
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
31
EM78P447S
8-Bit Microcontroller with OTP ROM
6
Absolute Maximum Ratings
Items
Temperature under bias
-40°C
to
85°C
Storage temperature
-65°C
to
150°C
Input voltage
VSS-0.3V
to
VDD+0.5V
Output voltage
VSS-0.3V
to
VDD+0.5V
Operating Frequency (2clks)
32.768kHz
to
20 MHz
2.5V
to
5.5V
Operating Voltage
7
Rating
Electrical Characteristics
7.1 DC Electrical Characteristic
„ Ta= 25°C, VDD= 5.0V±5%, VSS= 0V
Symbol
FXT
ERC
IIL
VIH1
VIL1
VIHX2
VILX2
VOH1
VOL1
VOL2
Input Leakage Current for input pins
Input High Voltage (VDD=5V)
Input Low Voltage (VDD=5V)
Input High Threshold Voltage
(VDD=5V)
Input Low Threshold Voltage
(VDD=5V)
Clock Input High Voltage (VDD=5V)
Clock Input Low Voltage (VDD=5V)
Input High Voltage (VDD=3V)
Input Low Voltage (VDD=3V)
Input High Threshold Voltage
(VDD=3V)
Input Low Threshold Voltage
(VDD=3V)
Clock Input High Voltage (VDD=3V)
Clock Input Low Voltage (VDD=3V)
Output High Voltage (Ports 5, 6, 7)
Output Low Voltage (Ports 5, 6)
Output Low Voltage (Port 7)
IPH
Pull-high current
ISB1
Power down current
VIHT1
VILT1
VIHX1
VILX1
VIH2
VIL2
VIHT2
VILT2
ISB2
32 •
Parameter
Crystal: VDD to 3V
Crystal: VDD to 5V
ERC: VDD to 5V
Power down current
Condition
Two cycles with two clocks
Two cycles with two clocks
R: 5.1KΩ, C: 100 pF
VIN = VDD, VSS
Ports 5, 6, 7
Ports 5, 6, 7
Min
DC
DC
Typ. Max
8.0
20.0
F±30% 950 F±30%
±1
2.0
0.8
Unit
MHz
MHz
KHz
µA
V
V
/RESET, TCC, INT
2.0
-
-
V
/RESET, TCC, INT
-
-
0.8
V
OSCI
OSCI
Ports 5, 6, 7
Ports 5, 6, 7
3.5
1.5
-
-
1.5
0.4
V
V
V
V
/RESET, TCC, INT
1.5
-
-
V
/RESET, TCC, INT
-
-
0.4
V
2.1
2.4
-
-
0.9
0.4
0.4
V
V
V
V
V
-50
-100
-240
µA
-
-
1
µA
-
-
7
µA
OSCI
OSCI
IOH = -10.0 mA
IOL = 9.0 mA
IOL = 14.0 mA
Pull-high active,
Input pin at VSS
All input and I/O pins at
VDD, Output pin floating,
WDT disabled
All input and I/O pins at
VDD, Output pin floating,
WDT enabled
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
(Continuation)
Symbol
Condition
Min
Typ.
Operating supply current (VDD=3V)
Two cycles/four clocks
/RESET= 'High',
Fosc=32kHz (Crystal type,
CLKS="0"),
Output pin floating,
WDT disabled
−
25
30
µA
ICC2
Operating supply current (VDD=3V)
Two cycles/four clocks
/RESET= 'High',
Fosc=32kHz (Crystal type,
CLKS="0"),
Output pin floating,
WDT enabled
-
30
35
µA
ICC3
Operating supply current
(VDD=5V)
Two cycles/two clocks
/RESET= 'High',
Fosc=4MHz (Crystal type,
CLKS="0"),
Output pin floating,
WDT enabled
-
1.6
2.2
mA
ICC4
Operating supply current
(VDD=5V)
Two cycles/four clocks
/RESET= 'High',
Fosc=10MHz (Crystal
type, CLKS="0"),
Output pin floating,
WDT enabled
-
2.8
5.0
mA
ICC1
Parameter
Max Unit
7.2 AC Electrical Characteristic
„ Ta=-40°C ~ 85 °C, VDD=5V±5%, VSS=0V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
45
50
55
%
Dclk
Input CLK duty cycle
−
Tins
Instruction cycle time
(CLKS="0")
Crystal type
100
−
DC
ns
RC type
500
−
DC
ns
Ttcc
TCC input period
(Tins+20)/N*
−
−
ns
Tdrh
Device reset hold time
Ta = 25°C
11.3
16.2
21.6
ms
−
Trst
/RESET pulse width
Ta = 25°C
2000
−
−
ns
Twdt
Watchdog timer period
Ta = 25°C
11.3
16.2
21.6
ms
Tset
Input pin setup time
−
0
−
ns
−
−
Thold
Input pin hold time
15
20
25
ns
Tdelay
Output pin delay time
Cload=20pF
45
50
55
ns
Tiod
I/O delay for EMI enable
Cload=150pF
Cload=150pF
4
5
6
ns
Ttrr1
Rising time for EMI enable
Ttrf1
Falling time for EMI enable
Ttrr2
Rising time for EMI enable
Ttrf2
Falling time for EMI enable
Tdrc
ERC delay time
190
200
210
ns
Cload=150pF
Cload=300pF
190
200
210
ns
380
400
420
ns
Cload=300pF
Ta = 25°C
380
400
420
ns
1
3
5
ns
*N = Selected prescaler ratio
NOTE
Data under Typ. column are measured at 5V, 25°C
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
33
EM78P447S
8-Bit Microcontroller with OTP ROM
7.3 Device Characteristic
The graphic provided in the following pages were derived based on a limited number
of samples and are shown here for reference only. The device characteristics
illustrated herein are not guaranteed for its accuracy. In some graphics, the data
maybe out of the specified warranted operating range.
Device Operating Voltage Characteristics
7.3.1
Vih/Vil (Input pins with Schmitt Inverter)
2
Vih max (-40
Vih typ 25
Vih min (-40
to 85
)
to 85 )
Vih Vil (Volt)
1.5
1
Vil max (-40 to 85 )
Vil typ 25
Vil min (-40 to 85 )
0.5
0
2.5
3
3.5
4
Vdd (Volt)
4.5
5
5.5
Figure 7-1a Vih, Vil of TCC, /INT, /RESET Pin
Vth (Input thershold voltage) of I/O pins
1.8
1.6
1.4
Max (-40
to 85
)
Typ 25
Vth (Volt)
1.2
1
Min (-40
0.8
to 85
)
0.6
0.4
0.2
0
2.5
3
3.5
4
VDD (Volt)
4.5
5
5.5
Figure 7-1b Vth (Threshold Voltage) of P60~P67, P70~P77 vs. VDD
34 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
Voh/Ioh (VDD=5V)
Voh/Ioh (VDD=3V)
0
0
-5
-10
Ioh (mA)
Ioh (mA)
-2
Min 85
-15
-4
Min 85
Typ 25
-20
Typ 25
-6
Max -40
Max -40
-8
-25
0
1
2
3
Voh (Volt)
4
0
5
0.5
1
1.5
2
2.5
3
Voh (Volt)
Figure 7-1c Port 5, Port 6, and Port 7 Voh vs. Ioh,
VDD=5V
Figure 7-1d Port 5, Port 6, and Port 7 Voh vs. Ioh,
VDD=3V
Vol/Iol (VDD=5V)
Vol/Iol (VDD=3V)
50
25
40
20
30
Typ 25
Iol (mA)
Iol (mA)
Max -40
Min 85
20
10
15
Max -40
Typ 25
10
Min 85
5
0
0
0
1
2
3
4
5
Vol (Volt)
Figure 7-1e Port 5 and Port 6 Vol vs. Iol, VDD=5V
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
0
0.5
1
1.5
2
2.5
3
Vol (Volt)
Figure 7-1f Port 5 and Port 6 Vol vs. Iol, VDD=3V
35
EM78P447S
8-Bit Microcontroller with OTP ROM
Vol/Iol (5V)
Vol/Iol (3V)
60
25
Max -40
50
Max -40
Typ 25
20
Typ 25
Min 85
40
Min 85
Iol (mA)
Iol (mA)
15
30
10
20
5
10
0
0
0
1
2
3
4
5
0
0.5
1
1.5
2
2.5
3
Vol (Volt)
Vol (Volt)
Figure 7-1g Port 7 Vol vs. Iol, VDD=5V
Figure 7-1h Port 7 Vol vs. Iol, VDD=3V
WDT Time-out
30
WDT Time-out Period (ms
25
Max 85
20
Typ 25
15
Min -40
10
5
0
2
3
4
VDD (Volt)
5
6
Figure 7-1i WDT Time Out Period vs. VDD, Prescaler Set to 1:1
36 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
Cext=100pF, Typical RC OSC Frequency
1.4
R = 3.3 k
Frequency (M Hz)
1.2
1
R = 5.1 k
0.8
0.6
R = 10 k
0.4
0.2
R = 100 k
0
2.5
3
3.5
4
4.5
VDD (Volt)
5
5.5
Figure 7-1j Typical RC OSC Frequency vs. VDD (Cext=100pF, Temperature at 25°C)
7.3.2
Device Operating Temperature Characteristics
ERC OSC Frequency vs Temp. (Cext=100pF, Rext=5.1K)
1.01
Fosc/Fosc (25℃)
1.005
1
5V
0.995
3V
0.99
0.985
0.98
-40
-20
0
20
40
60
80
Temperature (℃)
Figure 7-2a Typical RC OSC Frequency vs. Temperature (R and C are Ideal Components)
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
37
EM78P447S
8-Bit Microcontroller with OTP ROM
„ Operating Current ICC1 to ICC4
Four conditions exist with the operating current ICC1 to ICC4. These conditions are
as follows
● ICC1: VDD=3V, Fosc=32 kHz, 2clocks, WDT disable
● ICC2: VDD=3V, Fosc=32 kHz, 2clocks, WDT enable
● ICC3: VDD=5V, Fosc=4 MHz, 2clocks, WDT enable
● ICC4: VDD=5V, Fosc=10 MHz, 2clocks, WDT enable
Typical ICC1 and ICC2 vs. Temperature
Current (uA)
21
18
Typ ICC2
15
Typ ICC1
12
9
-40
-20
0
20
40
Temperature (
60
80
)
Figure 7-2b Typical Operating Current (ICC1 and ICC2) vs. Temperature
Maximum ICC1 and ICC2 vs. Temperature
27
Max ICC2
Current (µA)
24
21
Max ICC1
18
15
-40
-20
0
20
40
Temperature (
60
80
)
Figure 7-2c Maximum Operating Current (ICC1 and ICC2) vs. Temperature
38 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
Typical ICC3 and ICC4 vs. Temperature
4
Current (mA)
3.5
Typ ICC4
3
2.5
Typ ICC3
2
1.5
1
0.5
-40
-20
0
20
40
60
80
Temperature (℃)
Figure 7-2d Typical Operating Current (ICC3 and ICC4) vs. Temperature
Maximum ICC3 and ICC4 vs. Temperature
4.5
Max ICC4
Current (mA)
4
3.5
3
2.5
Max ICC3
2
1.5
1
-40
-20
0
20
40
60
80
Temperature (℃)
Figure 7-2e Maximum Operating Current (ICC3 and ICC4) vs. Temperature
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
39
EM78P447S
8-Bit Microcontroller with OTP ROM
„ Standby Current ISB1 AND ISB2
Two conditions exist with the standby current ISB1 and ISB2. These conditions are
as follows:
● ISB1: VDD=5V, WDT disable
● ISB2: VDD=5V, WDT enable
Typical ISB1 and ISB2 vs. Temperature
12
Current (µA)
9
Typ ISB2
6
3
Typ ISB1
0
-40
-20
0
20
40
Temperature (
60
80
)
Figure 7-2f Typical Standby Current (ISB1 and ISB2) vs. Temperature
Maximum ISB1 and ISB2 vs. Temperature
15
Current (µA)
12
9
Max ISB2
6
3
Max ISB1
0
-40
-20
0
20
40
60
80
Temperature (
Figure 7-2g Maximum Standby Current (ISB1 and ISB2) vs. Temperature
40 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
„ Operating Voltage at –40°C to 85°C
Operating voltage (-40
25
Frequency (M Hz)
20
15
10
5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (Volt)
Figure 7-2h Operating Voltage at Temperature Range of –40°C to 85 °C
Device Operation Curve
7.3.3
EM78P447S HXT I-V
2.5
I (mA)
2
1.5
max
1
min
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Volt (V)
Figure 7-3a EM78P447S I-V Operating Curve at 4MHz
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
41
EM78P447S
8-Bit Microcontroller with OTP ROM
EM78P447S-G HXT I-V
2.5
I (mA)
2
1.5
max
min
1
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Volt (V)
Figure 7-3b EM78P447S-G I-V Operating Curve at 4MHz
EM78P447S LXT I-V
50
I (µA)
40
30
20
max
min
10
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Volt (V)
Figure 7-3c EM78P447S I-V Operating Curve at 32.768 kHz
42 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
EM78P447S-G LXT I-V
50
I (µA)
40
30
max
20
min
10
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Volt (V)
Figure 7-3d EM78P447S-G I-V Operating Curve at 32.768 kHz
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
43
EM78P447S
8-Bit Microcontroller with OTP ROM
APPENDIX
A Package Type
OTP MCU
44 •
Package Type
Pin Count
Package Size
EM78P447SAP
DIP
28
600 mil
EM78P447SAM
SOP
28
300 mil
EM78P447SAK
Skinny DIP
28
300 mil
EM78P447SAS
SSOP
28
209 mil
EM78P447SBP
DIP
32
600 mil
EM78P447SBWM
SOP
32
450 mil
EM78P447SBM
SOP
32
300 mil
EM78P447SCK
Skinny DIP
24
300 mil
EM78P447SAPS
DIP
28
600 mil
EM78P447SAMS
SOP
28
300 mil
EM78P447SAKS
Skinny DIP
28
300 mil
EM78P447SASS
SSOP
28
209 mil
EM78P447SBPS
DIP
32
600 mil
EM78P447SBWMS
SOP
32
450 mil
EM78P447SBMS
SOP
32
300 mil
EM78P447SCKS
Skinny DIP
24
300 mil
EM78P447SCMS
SOP
24
300 mil
EM78P447SAPJ
DIP
28
600 mil
EM78P447SAMJ
SOP
28
300 mil
EM78P447SAKJ
Skinny DIP
28
300 mil
EM78P447SASJ
SSOP
28
209 mil
EM78P447SBPJ
DIP
32
600 mil
EM78P447SBWMJ
SOP
32
450 mil
EM78P447SBMJ
SOP
32
300 mil
EM78P447SCKJ
Skinny DIP
24
300 mil
EM78P447SCMJ
SOP
24
300 mil
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
NOTE
„ All the above MCUs, are Green products and do not contain hazardous
substances.
„ These MCUs comply with the third edition of Sony SS-00259 standard.
„ The Pb content of the device complies with Sony specifications of less than
100ppm.
A.1 Packaging Material Specification
Category
Electroplate type
Ingredient (%)
Melting point (°C)
Specification
Pure Tin
Sn :100%
232°C
Electrical Resistivity (µΩ-cm)
11.4
Hardness (hv)
8~10
Elongation (%)
>50%
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
45
EM78P447S
8-Bit Microcontroller with OTP ROM
B Packaging Configuration
B.1 24-Lead Plastic Skinny Dual In-line Package
(SKDIP)
300 mil
Symbal Min Normal
Max
A
A1
A2
c
0.203
0.254
0.356
D
E1
E
e
B
0.356
0.457
0.559
B1
1.520
L
3.302
3.556
e
2.540(TYP)
46 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
B.2 28-Lead Plastic Skinny Dual In-line Package
(SKDIP)
300 mil
Symbal
A
A1
A2
c
D
E1
E
e
B
B1
L
e
Min
Normal
0.254
0.457
1.524
2.540(TYP)
B.3 28-Lead Plastic Dual In-line Package (DIP)
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
Max
600 mil
47
EM78P447S
8-Bit Microcontroller with OTP ROM
B.4 32-Lead Plastic Dual In-line Package (DIP)
600 mil
B.5 24-Lead Plastic Small Outline Package
(SOP)
300 mil
48 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
B.6 28-Lead Plastic Small Outline Package
(SOP)
300 mil
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
49
EM78P447S
8-Bit Microcontroller with OTP ROM
B.7 32-Lead Plastic Small Outline Package
(SOP)
300 mil
50 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
B.8 32-Lead Plastic Small Outline Package
(SOP)
450 mil
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
51
EM78P447S
8-Bit Microcontroller with OTP ROM
B.9 28-Lead Shrink Small Outline Package
(SSOP)
209 mil
52 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
EM78P447S
8-Bit Microcontroller with OTP ROM
C EM78P447S Programming Pin List
ELAN’s DWTR is used to program the EM78P447S MCUs. The connector of DWTR
is selected by CON3 (EM78P447S). The software is selected by EM78P447S.
Program Pin Name
IC Pin Name
28-DIP Pin No.
32-DIP Pin No.
/RESET
28
30
ACLK
OSCO
26
28
DINCK
P77
25
27
DATAIN
P76
24
26
/PGMB
P75
23
25
/OEB
P74
22
24
VDD
VDD
2
4
VSS
VSS
4
6
VPP
C.1 Wiring Diagram for Programming with ELAN DWTR
TCC
1
28
/RESET
P55
1
32
VDD
2
27
OSCI
P54
2
31
P56
P57
NC
3
26
OSCO
TCC
3
30
/RESET
Vss
4
25
P77
VDD
4
29
OSCI
24
P76
NC
5
28
OSCO
6
23
P75
Vss
6
27
P77
P51
7
22
P74
/INT
7
26
P76
P52
8
21
P73
P50
8
25
P75
20
P72
P51
9
P71
P52
10
P53
9
P60
10
P61
11
18
P70
P62
12
17
P67
P63
13
16
P66
P64
14
15
19
P65
EM78P447SBP
EM78P447SBWM
5
P50
EM78P447SAP
EM78P447SAM
/INT
24
P74
23
P73
P53
11
22
P72
P60
12
21
P71
P61
13
20
P70
P62
14
19
P67
P63
15
18
P66
P64
16
17
P65
Figure C-1 EM78P447S Wiring Diagram for DWTR Interface
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)
53
EM78P447S
8-Bit Microcontroller with OTP ROM
54 •
Product Specification (V1.7) 01.27.2010
(This specification is subject to change without further notice)