Datasheet R8C/38T-A Group RENESAS MCU 1. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Overview 1.1 Features The R8C/38T-A Group of single-chip microcontrollers (MCUs) incorporates the R8C CPU core, which provides sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, the CPU core is capable of executing instructions at high speed. In addition, it features a multiplier for high-speed arithmetic processing. Power consumption is low, and additional power control is possible by selecting the operating mode. The R8C/38TA Group is also designed to maximize EMI/EMS performance. Integration of many peripheral functions, including multifunction timer and serial interface on the same chip, reduces the number of system components. The R8C/38T-A Group integrates a touch sensor control unit, which enables detection of the floating capacitance of the electrostatic capacitive touch electrode. This group also has on-chip data flash (1 KB × 4 blocks) with background operation (BGO) function. 1.1.1 Applications Electronic household appliances, office equipment, audio equipment, consumer equipment, etc. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 1 of 60 R8C/38T-A Group 1.1.2 1. Overview Specifications Tables 1.1 and 1.2 outline Specifications. Table 1.1 Item CPU Specifications (1) Function Central processing unit Memory Description R8C CPU core • Number of fundamental instructions: 89 • Minimum instruction execution time: 50 ns (CPU clock = 20 MHz, VCC = 2.7 V to 5.5 V) 200 ns (CPU clock = 5 MHz, VCC = 1.8 V to 5.5 V) • Multiplier: 16 bits × 16 bits 32 bits • Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits 32 bits • Operating mode: Single-chip mode (address space: 1 Mbyte) Refer to Table 1.3 Product List. ROM, RAM, data flash Voltage Voltage detection • Power-on reset detection circuit • Voltage detection with three check points (the detection levels for voltage detection 0 and voltage detection 1 can be selected.) I/O ports Programmable • Input only: 1 I/O ports • CMOS I/O: 75, selectable pull-up resistor • High current drive ports: 75 Clock Clock generation • 4 circuits: XIN clock oscillation circuit, XCIN clock oscillation circuit, circuits high-speed on-chip oscillator (with frequency adjustment function), low-speed on-chip oscillator • Oscillation stop detection: XIN clock oscillation stop detection function • Frequency divider circuit: Divided by 1, 2, 4, 8, or 16 can be selected • Low-power mode: Standard operating mode (high-speed clock, low-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode Interrupts • Number of interrupt vectors: 69 • External interrupt inputs: 9 (INT × 5, key input × 4) • Priority levels: 7 Event link controller (ELC) • Events output from peripheral functions can be linked to events input to different peripheral functions. (30 sources × 10 types of event link operations) • Events can be handled independently from interrupt requests. Watchdog timer • 14 bits × 1 • Selectable reset start function • Selectable low-speed on-chip oscillator for the watchdog timer DTC (data transfer controller) • 1 channel • Activation sources: 27 • Transfer modes: 2 (normal mode, repeat mode) Timer Timers RJ_0 16 bits × 1: 1 circuit integrated on-chip Timer mode (periodic timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode Timer RB2_0 16 bits × 1: 1 circuit integrated on-chip Timer mode (periodic timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait one-shot generation mode Timers RC_0 16 bits (with 4 capture/compare registers) × 1: 1 circuit integrated on-chip Timer mode (input capture function, output compare function), PWM mode (output: 3 pins), PWM2 mode (PWM output: 1 pin) Timer RE2 8 bits × 1 Compare match timer mode, real-time clock mode R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 2 of 60 R8C/38T-A Group Table 1.2 1. Overview Specifications (2) Item Function Serial interface UART0_0 and UART0_1 UART2 Description 2 channels Clock synchronous serial I/O mode, clock asynchronous serial I/O mode 1 channel Clock synchronous serial I/O mode, clock asynchronous serial I/O mode, I2C mode (I2C-bus), multiprocessor communication mode Clock Synchronous serial interface (SSU) SSU_0 1 channel (also used for the I2C bus) (I2C bus) I2C_0 HW-LIN_0 1 channel (also used for the SSU) LIN module A/D converter Comparator B Touch sensor control unit (TSCU) CRC calculator Flash memory Operating frequency/ Power supply voltage Current consumption Operating ambient temperature Package Hardware LIN 1 channel (timer RJ_0, UART0_0, or UART0_1 used) Resolution: 10 bits × 20 channels, sample and hold function, sweep mode 2 circuits System CH × 4, electrostatic capacitive touch detection × 36 CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant • Program/erase voltage: VCC = 2.7 V to 5.5 V • Program/erase endurance:10,000 times (data flash) 1,000 times (program ROM) • Program security: ROM code protect, ID code check • Debug functions: On-chip debug, on-board flash rewrite function • BGO (background operation) function (data flash) CPU clock = 20 MHz (VCC = 2.7 V to 5.5 V) CPU clock = 5 MHz (VCC = 1.8 V to 5.5 V) Typ. 6.5 mA (VCC = 5.0 V, f(XIN) = 20 MHz) Typ. 3.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 4.0 A (VCC = 3.0 V, wait mode f(XCIN) = 32 kHz) Typ. 2.2 A (VCC = 3.0 V, stop mode) -20C to 85C (N version) -40C to 85C (D version) (1) 80-pin LQFP Package code: PLQP0080KB-A (previous code: 80P6Q-A) Note: 1. Specify the D version if it is to be used. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 3 of 60 R8C/38T-A Group 1.2 1. Overview Product List Table 1.3 lists product information. Figure 1.1 shows the Product Part Number Structure. Table 1.3 Product List Part No. R5F21388SNFP R5F2138ASNFP R5F2138CSNFP R5F21388SDFP R5F2138ASDFP R5F2138CSDFP Current of Dec 2011 Internal ROM Capacity Program ROM Data Flash 64 Kbytes 1 Kbyte × 4 96 Kbytes 128 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes Internal RAM Capacity 6 Kbytes 8 Kbytes 10 Kbytes 6 Kbytes 8 Kbytes 10 Kbytes Package Type Remarks PLQP0080KB-A N version PLQP0080KB-A D version Part No. R 5 F 21 38 C S N FP Package type: FP: PLQP0080KB-A (0.5 mm pin pitch, 12 12 mm square body) Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 8: 64 KB A: 96 KB C: 128 KB R8C/38T-A Group R8C/3xT-A Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.1 Product Part Number Structure R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 4 of 60 R8C/38T-A Group 1.3 1. Overview Block Diagram Figure 1.2 shows the Block Diagram. I/O ports 8 8 8 8 Port P0 Port P1 Port P2 Port P3 5 1 8 8 Port P4 Port P5 Port P6 System clock generation circuit Peripheral functions XIN-XOUT XCIN-XCOUT High-speed on-chip oscillator Low-speed on-chip oscillator Low-speed on-chip oscillator (for watchdog timer) A/D converter (10 bits 20 channels) Timers Timer RJ (16 bits 1) Timer RB2 (16 bits 1) Timer RC (16 bits 1) Timer RE2 (8 bits 1) DTC Event link controller UART0 (8 bits 2 channels) Voltage detection circuit UART2 (8 bits 1 channel) Comparator B Synchronous serial communication unit (SSU/I2C) (8 bits 1 channel) TSCU (36 channels) LIN module (1 channel) Watchdog timer (14 bits) R0H R1H CRC calculator Memory R8C CPU core R0L R1L R2 R3 A0 A1 FB ROM (1) SB USP ISP INTB PC FLG RAM (2) Multiplier Port P9 Port P8 Port P7 6 8 8 Notes: 1. ROM size varies with the product. 2. RAM size varies with the product. Figure 1.2 Block Diagram R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 5 of 60 R8C/38T-A Group 1.4 1. Overview Pin Assignment P6_6/INT2(/TXD2/SDA2/TRCIOC_0/CH04) P6_7(/INT3/TRCIOD_0/CH05) P8_0/CH06 P8_1/CH07 P8_2/CHxA0 P8_3/CHxA1 46 45 43 42 41 P1_7/IVCMP1/INT1(/CH01) 49 44 P1_6/IVREF1(/CLK_0/CH00) 50 P4_5/ADTRG/INT0(/RXD2/SCL2/CH02) P1_5(/INT1/RXD_0/TRJIO_0) 51 P6_5/INT4(/CLK_1/CLK2/TRCIOB_0/CH03) P1_4(/TXD_0/TRCCLK_0) 52 47 P1_3/AN11/KI3/TRBO_0(/TRCIOC_0) 53 48 P1_0/AN8/KI0(/TRCIOD_0) P1_2/AN10/KI2(/TRCIOB_0) 54 P7_7/AN19 57 55 P7_6/AN18 58 P1_1/AN9/KI1(/TRCIOA_0/TRCTRG_0) P7_5/AN17 59 56 P7_4/AN16 60 Figure 1.3 shows Pin Assignment (Top View). Tables 1.4 to 1.9 list the Pin Name Information by Pin Number. P7_3/AN15 61 40 P8_4/CHxB P7_2/AN14 62 39 P8_5/CHxC P7_1/AN13 63 38 P8_6/CH08 P7_0/AN12 64 37 P8_7/CH09 P0_7/AN0(/TRCIOC_0) 65 36 P3_1/CH10 P0_6/AN1(/TRCIOD_0) 66 35 P3_6/CH11 P0_5/AN2(/TRCIOB_0) 67 34 P9_0/CH12 P0_4/AN3/TMRE2O(/TRCIOB_0) 68 33 P9_1/CH13 P0_3/AN4(/CLK_1/TRCIOB_0) 69 32 P9_2/CH14 P0_2/AN5(/RXD_1/TRCIOA_0/TRCTRG_0) 70 31 P9_3/CH15 P0_1/AN6(/TXD_1/TRCIOA_0/TRCTRG_0) 71 30 P2_0(/INT1/TRCIOB_0/CH16) P0_0/AN7(/TRCIOA_0/TRCTRG_0) 72 29 P2_1(/TRCIOC_0/CH17) P6_4(/RXD_1/CH35) 73 28 P2_2(/TRCIOD_0/CH18) P6_3(/TXD_1/CH34) 74 27 P2_3(/CH19) P6_2(/CLK_1/CH33) 75 26 P2_4(/CH20) P6_1(/CH32) 76 25 P2_5(/CH21) P6_0(/TMRE2O/CH31) 77 24 P2_6(/CH22) P9_5(/CH30) 78 23 P2_7(/CH23) P9_4(/CH29) 79 22 P3_3/IVCMP3/INT3/SCS_0(/CTS2/RTS2/TRCCLK_0) P5_7(/CH28) 80 21 P3_4/IVREF3/SSI_0(/RXD2/SCL2/TXD2/SDA2/TRCIOC_0) Figure 1.3 R8C/38T-A Group 13 14 VCC/AVCC P5_4(/TRCIOD_0) 20 12 P4_6/XIN P3_5/SCL_0/SSCK_0(/CLK2/TRCIOD_0) 11 VSS/AVSS 19 10 P4_7/XOUT P3_7/SDA_0/SSO_0(/RXD2/SCL2/TXD2/SDA2) 9 RESET 18 8 P4_4(/XCOUT) P5_0(/TRCCLK_0) 7 P4_3(/XCIN) 16 6 MODE 15 5 P4_2/VREF 17 4 P3_0(/TRJIO_0/CH24) P5_2(/TRCIOB_0) 3 P3_2(/INT1/INT2/TRJIO_0/CH25) P5_3(/TRCIOC_0) 2 P5_1(/TRCIOA_0/TRCTRG_0) 1 P5_6(/CH27) P5_5(/TRJIO_0/CH26) PLQP0080KB-A (80P6Q-A) (Top view) Pin Assignment (Top View) R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 6 of 60 R8C/38T-A Group Table 1.4 Port Pin No. P0_0 72 1. Overview Pin Name Information by Pin Number (INT, URAT0, and UART2) (1) INT INT0 INT1 P0_1 71 P0_2 70 P0_3 69 P0_4 68 P0_5 67 P0_6 66 P0_7 65 P1_0 56 P1_1 55 P1_2 54 P1_3 53 P1_4 52 P1_5 51 P1_6 50 P1_7 49 INT1 P2_0 30 INT1 P2_1 29 P2_2 28 P2_3 27 P2_4 26 P2_5 25 P2_6 24 P2_7 23 P3_0 4 P3_1 36 P3_2 3 P3_3 22 P3_4 21 P3_5 20 P3_6 35 P3_7 19 P4_2 5 P4_3 7 P4_4 8 P4_5 48 P4_6 12 P4_7 10 P5_0 18 P5_1 17 P5_2 16 P5_3 15 P5_4 14 P5_5 2 P5_6 1 P5_7 80 P6_0 77 P6_1 76 P6_2 75 P6_3 74 P6_4 73 P6_5 47 P6_6 46 P6_7 45 P7_0 64 P7_1 63 P7_2 62 P7_3 61 P7_4 60 P7_5 59 P7_6 58 P7_7 57 INT2 UART0 INT3 INT4 TXD_0 TXD_1 RXD_0 RXD_1 UART2 CLK_0 CLK_1 TXD2 RXD2 TXD2 RXD2 CTS2 RTS2 CTS2 RTS2 SDA2 SCL2 SDA2 SCL2 CLK2 TXD_1 RXD_1 CLK_1 TXD_0 INT1 RXD_0 CLK_0 INT1 INT2 INT3 CLK2 TXD2 INT0 RXD2 SDA2 RXD2 SCL2 SCL2 CLK_1 TXD_1 RXD_1 INT4 INT2 R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 CLK_1 CLK2 TXD2 SDA2 INT3 Page 7 of 60 R8C/38T-A Group Table 1.5 Port Pin No. P8_0 44 P8_1 43 P8_2 42 P8_3 41 P8_4 40 P8_5 39 P8_6 38 P8_7 37 P9_0 34 P9_1 33 P9_2 32 P9_3 31 P9_4 79 P9_5 78 1. Overview Pin Name Information by Pin Number (INT, URAT0, and UART2) (2) INT INT0 INT1 INT2 R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 UART0 INT3 INT4 TXD_0 TXD_1 RXD_0 RXD_1 UART2 CLK_0 CLK_1 TXD2 RXD2 CTS2 RTS2 SDA2 SCL2 CLK2 Page 8 of 60 R8C/38T-A Group Table 1.6 Port 1. Overview Pin Name Information by Pin Number (SSU/I2C, Timer RJ, and Timer RB2) (1) SSU/I2C Pin No. SCL_0 P0_0 SDA_0 SSI_0 Timer RJ SCS_0 SSCK_0 SSO_0 TRJO_0 Timer RB2 TRJIO_0 TRBO_0 72 P0_1 71 P0_2 70 P0_3 69 P0_4 68 P0_5 67 P0_6 66 P0_7 65 P1_0 56 P1_1 55 P1_2 54 P1_3 53 P1_4 52 P1_5 51 P1_6 50 P1_7 49 P2_0 30 P2_1 29 P2_2 28 P2_3 27 P2_4 26 P2_5 25 P2_6 24 P2_7 23 P3_0 4 P3_1 36 P3_2 3 P3_3 22 P3_4 21 P3_5 20 P3_6 35 P3_7 19 P4_2 5 P4_3 7 P4_4 8 P4_5 48 P4_6 12 P4_7 10 P5_0 18 P5_1 17 P5_2 16 P5_3 15 P5_4 14 P5_5 2 P5_6 1 P5_7 80 P6_0 77 P6_1 76 P6_2 75 P6_3 74 P6_4 73 P6_5 47 P6_6 46 P6_7 45 P7_0 64 P7_1 63 P7_2 62 P7_3 61 P7_4 60 P7_5 59 P7_6 58 P7_7 57 TRBO_0 TRJIO_0 TRJO_0 TRJIO_0 SCS_0 SSI_0 SCL_0 SSCK_0 SDA_0 R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 SSO_0 TRJIO_0 Page 9 of 60 R8C/38T-A Group Table 1.7 Port 1. Overview Pin Name Information by Pin Number (SSU/I2C, Timer RJ, and Timer RB2) (2) SSU/I2C Pin No. SCL_0 P8_0 44 P8_1 43 P8_2 42 P8_3 41 P8_4 40 P8_5 39 P8_6 38 P8_7 37 P9_0 34 P9_1 33 P9_2 32 P9_3 31 P9_4 79 P9_5 78 SDA_0 R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 SSI_0 Timer RJ SCS_0 SSCK_0 SSO_0 TRJO_0 Timer RB2 TRJIO_0 TRBO_0 Page 10 of 60 R8C/38T-A Group Table 1.8 Port Pin No. 1. Overview Pin Name Information by Pin Number (Timer RC, Timer RE2, and Others) (1) Timer RC TRCCLK_0 TRCIOA_0 TRCIOB_0 TRCIOC_0 Timer RE2 TRCIOD_0 TRCTRG_0 Others TMRE2O P0_0 72 TRCIOA_0 TRCTRG_0 AN7 P0_1 71 TRCIOA_0 TRCTRG_0 AN6 P0_2 70 TRCIOA_0 TRCTRG_0 AN5 P0_3 69 TRCIOB_0 P0_4 68 TRCIOB_0 P0_5 67 TRCIOB_0 P0_6 66 P0_7 65 P1_0 56 P1_1 55 P1_2 54 P1_3 53 AN4 TMRE2O AN3 AN2 TRCIOD_0 AN1 TRCIOD_0 AN8 KI0 AN9 KI1 TRCIOC_0 AN0 TRCIOA_0 TRCTRG_0 TRCIOB_0 TRCIOC_0 AN10 KI2 AN11 KI3 P1_4 52 P1_5 51 TRCCLK_0 P1_6 50 IVREF1 P1_7 49 IVCMP1 P2_0 30 TRCIOB_0 CH00 CH01 CH16 P2_1 29 P2_2 28 TRCIOC_0 CH17 P2_3 27 CH19 P2_4 26 CH20 P2_5 25 CH21 P2_6 24 CH22 P2_7 23 CH23 P3_0 4 CH24 P3_1 36 CH10 P3_2 3 P3_3 22 TRCIOD_0 CH18 CH25 TRCCLK_0 IVCMP3 P3_4 21 P3_5 20 P3_6 35 P3_7 19 P4_2 5 P4_3 7 XCIN P4_4 8 XCOUT P4_5 48 ADTRG P4_6 12 XIN P4_7 10 P5_0 18 P5_1 17 P5_2 16 TRCIOC_0 IVREF3 TRCIOD_0 CH11 VREF CH02 XOUT TRCCLK_0 TRCIOA_0 TRCTRG_0 TRCIOB_0 P5_3 15 P5_4 14 P5_5 2 CH26 P5_6 1 CH27 P5_7 80 P6_0 77 P6_1 76 CH32 P6_2 75 CH33 P6_3 74 CH34 P6_4 73 P6_5 47 P6_6 46 P6_7 45 P7_0 64 AN12 P7_1 63 AN13 P7_2 62 AN14 P7_3 61 AN15 P7_4 60 AN16 P7_5 59 AN17 P7_6 58 AN18 P7_7 57 AN19 R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 TRCIOC_0 TRCIOD_0 CH28 TMRE2O CH31 CH35 TRCIOB_0 CH03 TRCIOC_0 CH04 TRCIOD_0 CH05 Page 11 of 60 R8C/38T-A Group Table 1.9 1. Overview Pin Name Information by Pin Number (Timer RC, Timer RE2, and Others) (2) Timer RC Timer RE2 Port Pin No. P8_0 44 P8_1 43 CH07 P8_2 42 CHxA0 P8_3 41 CHxA1 P8_4 40 CHxB P8_5 39 CHxC P8_6 38 CH08 P8_7 37 CH09 P9_0 34 CH12 P9_1 33 CH13 P9_2 32 CH14 P9_3 31 CH15 P9_4 79 CH29 P9_5 78 CH30 TRCCLK_0 TRCIOA_0 R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 TRCIOB_0 TRCIOC_0 TRCIOD_0 TRCTRG_0 TMRE2O Others CH06 Page 12 of 60 R8C/38T-A Group 1.5 1. Overview Pin Functions Tables 1.10 and 1.11 list Pin Functions. Table 1.10 Pin Functions (1) Item Power supply input Pin Name VCC, VSS I/O — Analog power supply input Reset input AVCC, AVSS — I Description Apply 1.8 V through 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Power supply input for the A/D converter. Connect a capacitor between pins AVCC and AVSS. Applying a low level to this pin resets the MCU. MODE XIN clock input XIN clock output RESET MODE XIN XOUT I I I/O XCIN clock input XCIN clock output XCIN XCOUT I I/O INT interrupt input Key input interrupt INT0 to INT4 I KI0 to KI3 TRJIO_0 TRJO_0 TRBO_0 TRCCLK_0 TRCTRG_0 TRCIOA_0, TRCIOB_0, TRCIOC_0, TRCIOD_0 TMRE2O CLK_0, CLK_1 RXD_0, RXD_1 TXD_0, TXD_1 I INT interrupt input. Key input interrupt input. I/O O O I I I/O Input/output for timer RJ. Output for timer RJ. Output for timer RB2. External clock input. External trigger input. Input/output for timer RC. O I/O I O I Divided clock output. Transfer clock input/output. Serial data input. Serial data output. Input for transmission control. Timer RJ_0 Timer RB2_0 Timer RC_0 Timer RE2 Serial interface (UART0) Serial interface (UART2) Synchronous serial communication unit (SSU_0) I2C bus (I2C_0) CTS2 Connect this pin to the VCC pin via a resistor. I/O for the XIN clock generation circuit. Connect a ceramic resonator or a crystal oscillator between pins XIN and XOUT. (1) To use an external clock, input it to the XIN pin and leave the XOUT pin open. I/O for the XCIN clock generation circuit. Connect a crystal oscillator between pins XCIN and XCOUT. (1) To use an external clock, input it to the XCOUT pin and leave the XCIN pin open. RTS2 SCL2 O Output for reception control. I/O I2C mode clock input/output. SDA2 I/O RXD2 TXD2 CLK2 SSI_0 I O I/O I/O I/O I2C mode data input/output. Serial data input. Serial data output. Transfer clock input/output. Data input/output. Chip-select input/output. I/O I/O I/O I/O I Clock input/output. Data input/output. Clock input/output. Data input/output. Reference voltage input for the A/D converter. SCS_0 SSCK_0 SSO_0 SCL_0 SDA_0 VREF Reference voltage input Note: 1. Contact the oscillator manufacturer for oscillation characteristics. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 13 of 60 R8C/38T-A Group Table 1.11 1. Overview Pin Functions (2) Item A/D converter Comparator B Touch sensor control unit I/O ports Input port Pin Name AN0 to AN19 ADTRG IVCMP1, IVCMP3 IVREF1, IVREF3 CHxA0, CHxA1, CHxB, CHxC CH00 to CH35 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_3 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_5 P4_2 R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 I/O I I Description Analog input for the A/D converter. External trigger input for the A/D converter. I I I/O Analog voltage input for comparator B. Reference voltage input for comparator B. Control pins for electrostatic capacitive touch detection. I I/O Electrostatic capacitive touch detection pins. 8-bit CMOS input/output ports. Each port has an I/O select direction register, enabling switching input and output for each pin. For input ports, the presence or absence of a pull-up resistor can be selected by a program. All ports can be used as LED drive (high drive) ports. I Input-only port. Page 14 of 60 R8C/38T-A Group 2. 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the 13 CPU Registers. The registers R0, R1, R2, R3, A0, A1, and FB form a single register bank. The CPU has two register banks. b31 b15 b8 b7 b0 R2 R0H (R0 high-order byte) R0L (R0 low-order byte) R3 R1H (R1 high-order byte) R1L (R1 low-order byte) R2 Data registers (1) R3 A0 Address registers (1) A1 Frame base register (1) FB b19 b15 b0 INTBH INTBL Interrupt table register The higher 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL. b19 b0 PC Program counter b15 b0 USP User stack pointer ISP Interrupt stack pointer SB Static base register b15 b0 FLG b15 b8 IPL b7 U Flag register b0 I O B S Z D C Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bits Processor interrupt priority level Reserved bit Note: 1. These registers form a single register bank. The CPU has two register banks. Figure 2.1 CPU Registers R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 15 of 60 R8C/38T-A Group 2.1 2. Central Processing Unit (CPU) Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 through R3. R0 can be split into high-order (R0H) and low-order (R0L) registers to be used separately as 8-bit data registers. The same applies to R1H and R1L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). Similarly, R3 and R1 can be used as a 32-bit data register. 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 functions in the same manner as A0. A1 can be combined with A0 and used as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table. 2.5 Program Counter (PC) PC is a 20-bit register that indicates the address of the next instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of the FLG register is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register used for SB relative addressing. 2.8 Flag Register (FLG) FLG is an 11-bit register that indicates the CPU state. 2.8.1 Carry Flag (C) The C flag retains carry, borrow, or shift-out bits that have been generated in the arithmetic and logic unit. 2.8.2 Debug Flag (D) The D flag is for debugging only. It must only be set to 0. 2.8.3 Zero Flag (Z) The Z flag is set to 1 when an arithmetic operation results in 0. Otherwise it is set to 0. 2.8.4 Sign Flag (S) The S flag is set to 1 when an arithmetic operation results in a negative value. Otherwise it is set to 0. 2.8.5 Register Bank Select Flag (B) Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1. 2.8.6 Overflow Flag (O) The O flag is set to 1 when an operation results in an overflow. Otherwise it is set to 0. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 16 of 60 R8C/38T-A Group 2.8.7 2. Central Processing Unit (CPU) Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1. The I flag is set to 0 when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is 0. USP is selected when the U flag is 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction for a software interrupt numbered from 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide and assigns eight processor interrupt priority levels from 0 to 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled. 2.8.10 Reserved Bit The write value must be 0. The read value is undefined. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 17 of 60 R8C/38T-A Group 3. 3. Address Space Address Space 3.1 Memory Map Figure 3.1 shows the Memory Map. The R8C/38T-A Group has a 1-Mbyte address space from addresses 00000h to FFFFFh. Up to 32 Kbytes of the internal ROM (program ROM) is allocated at lower addresses, beginning with address 0FFFFh. The area in excess of 32 Kbytes is allocated at higher addresses, beginning with address 10000h. For example, a 64-Kbyte internal ROM is allocated at addresses 08000h to 17FFFh. The fixed interrupt vector table is allocated at addresses 0FFDCh to 0FFFFh. The start address of each interrupt routine is stored here. The internal ROM (data flash) is allocated at addresses 07000h to 07FFFh. The internal RAM is allocated at higher addresses, beginning with address 00400h. For example, a 6-Kbyte internal RAM is allocated at addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. Special function registers (SFRs) are allocated at addresses 00000h to 02FFFh and addresses 06800h to 06FFFh. Peripheral function control registers are allocated here. All unallocated locations within the SFRs are reserved and cannot be accessed by users. 00000h SFR 002FFh 00400h Internal RAM 0XXXXh 06800h SFR (2) 0FFDCh 06FFFh 07000h Undefined instruction Overflow Internal ROM (data flash) (1) BRK instruction Address match 07FFFh Single-step 0YYYYh Watchdog timer, oscillation stop detection, voltage monitor Address break Internal ROM (program ROM) (Reserved) Reset 0FFFFh 0FFFFh Internal ROM (program ROM) ZZZZZh FFFFFh Notes: 1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte). 2. Addresses 06800h to 06FFFh are used for the ELC, DTC, and TSCU SFR areas. 3. The blank areas are reserved. No access is allowed. Part Number Internal RAM Internal ROM Capacity Address 0YYYYh Address ZZZZZh Capacity Address 0XXXXh 01BFFh R5F21388SNFP, R5F21388SDFP 64 Kbytes 08000h 17FFFh 6 Kbytes R5F21388SNFP, R5F21388SDFP 96 Kbytes 08000h 1FFFFh 8 Kbytes 023FFh R5F21388SNFP, R5F21388SDFP 128 Kbytes 08000h 27FFFh 10 Kbytes 02BFFh Figure 3.1 Memory Map R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 18 of 60 R8C/38T-A Group 3.2 3. Address Space Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 3.1 to 3.16 list the SFR Information. Table 3.17 lists the ID code Area, Option Function Select Area. SFR Information (1) (1) Table 3.1 Address 00000h 00001h 00002h 00003h 00004h 00005h 00006h 00007h 00008h 00009h 0000Ah 0000Bh 0000Ch 0000Dh 0000Eh 0000Fh 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h 00019h 0001Ah 0001Bh 0001Ch 0001Dh 0001Eh 0001Fh 00020h 00021h 00022h 00023h 00024h 00025h 00026h 00027h 00028h 00029h 0002Ah 0002Bh 0002Ch 0002Dh 0002Eh 0002Fh 00030h 00031h 00032h 00033h 00034h 00035h 00036h 00037h 00038h Symbol Register Name After Reset PM0 PM1 Processor Mode Register 0 Processor Mode Register 1 00h 10000000b PRCR CM0 CM1 OCD CM3 CM4 Protect Register System Clock Control Register 0 System Clock Control Register 1 Oscillation Stop Detection Register System Clock Control Register 3 System Clock Control Register 4 00h 00101000b 00100000b 00h 00h 00000001b CPSRF Clock Prescaler Reset Flag 00h FRA0 High-Speed On-Chip Oscillator Control Register 0 00h FRA2 High-Speed On-Chip Oscillator Control Register 2 00h RISR Reset Interrupt Select Register WDTR WDTS WDTC CSPR Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Count Source Protection Mode Register 10000000b or 00000000b FFh FFh 01111111b 10000000b or 00000000b RSTFR Reset Source Determination Register 00XXXXXXb SVDC STBY VDC Power Control Register 00h CMPA VCAC OCVREFCR Voltage Monitor Circuit Control Register Voltage Monitor Circuit Edge Select Register On-Chip Reference Voltage Control Register 00h 00h 00h VCA2 Voltage Detection Register 2 00000000b or 00100000b VD1LS Voltage Detection 1 Level Select Register 00000111b VW0C Voltage Monitor 0 Circuit Control Register 1100XX10b or 1100XX11b 10001010b 00039h VW1C Voltage Monitor 1 Circuit Control Register X: Undefined Notes: 1. The blank areas are reserved. No access is allowed. 2. Depends on the CSPROINI bit in the OFS register. 3. Depends on the LVDASI bit in the OFS register. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Remarks (Note 2) (Note 2) (Note 3) (Note 3) Page 19 of 60 R8C/38T-A Group Table 3.2 3. Address Space SFR Information (2) (1) Address Symbol Register Name 0003Ah VW2C Voltage Monitor 2 Circuit Control Register 0003Bh 0003Ch 0003Dh 0003Eh 0003Fh 00040h 00041h FMRDYIC Interrupt Control Register 00042h 00043h 00044h 00045h 00046h INT4IC Interrupt Control Register 00047h TRCIC_0 Interrupt Control Register 00048h 00049h 0004Ah TRE2IC Interrupt Control Register 0004Bh U2TIC Interrupt Control Register 0004Ch U2RIC Interrupt Control Register 0004Dh KUPIC Interrupt Control Register 0004Eh ADIC Interrupt Control Register 0004Fh SSUIC_0/IICIC_0 Interrupt Control Register 00050h 00051h U0TIC_0 Interrupt Control Register 00052h U0RIC_0 Interrupt Control Register 00053h U0TIC_1 Interrupt Control Register 00054h U0RIC_1 Interrupt Control Register 00055h INT2IC Interrupt Control Register 00056h TRJIC_0 Interrupt Control Register 00057h 00058h TRB2IC_0 Interrupt Control Register 00059h INT1IC Interrupt Control Register 0005Ah INT3IC Interrupt Control Register 0005Bh 0005Ch 0005Dh INT0IC Interrupt Control Register 0005Eh U2BCNIC Interrupt Control Register 0005Fh 00060h 00061h 00062h 00063h 00064h 00065h 00066h 00067h 00068h 00069h 0006Ah 0006Bh 0006Ch 0006Dh 0006Eh 0006Fh 00070h 00071h 00072h VCMP1IC Interrupt Control Register 00073h VCMP2IC Interrupt Control Register 00074h 00075h TSCUIC Interrupt Control Register 00076h 00077h 00078h 00079h Note: 1. The blank areas are reserved. No access is allowed. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 After Reset 10001010b Remarks 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Page 20 of 60 R8C/38T-A Group Table 3.3 3. Address Space SFR Information (3) (1) Address Symbol Register Name 0007Ah 0007Bh 0007Ch 0007Dh 0007Eh 0007Fh 00080h U0MR_0 UART0_0 Transmit/Receive Mode Register 00081h U0BRG_0 UART0_0 Bit Rate Register 00082h U0TB_0 UART0_0 Transmit Buffer Register 00083h 00084h U0C0_0 UART0_0 Transmit/Receive Control Register 0 00085h U0C1_0 UART0_0 Transmit/Receive Control Register 1 00086h U0RB_0 UART0_0 Receive Buffer Register 00087h 00088h U0IR_0 UART0_0 Interrupt Flag and Enable Register 00089h 0008Ah 0008Bh 0008Ch LINCR2_0 LIN_0 Special Function Register 0008Dh 0008Eh LINCT_0 LIN_0 Control Register 0008Fh LINST_0 LIN_0 Status Register 00090h U0MR_1 UART0_1 Transmit/Receive Mode Register 00091h U0BRG_1 UART0_1 Bit Rate Register 00092h U0TB_1 UART0_1 Transmit Buffer Register 00093h 00094h U0C0_1 UART0_1 Transmit/Receive Control Register 0 00095h U0C1_1 UART0_1 Transmit/Receive Control Register 1 00096h U0RB_1 UART0_1 Receive Buffer Register 00097h 00098h U0IR_1 UART0_1 Interrupt Flag and Enable Register 00099h 0009Ah 0009Bh 0009Ch 0009Dh 0009Eh 0009Fh 000A0h 000A1h 000A2h 000A3h 000A4h 000A5h 000A8h 000A9h 000AAh 000ABh 000ACh 000ADh 000AEh 000AFh 000B0h 000B1h 000B4h 000B5h 000B8h 000B9h X: Undefined Note: 1. The blank areas are reserved. No access is allowed. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 After Reset Remarks 00h XXh XXh XXh 00001000b 00000010b XXXXh 00h 00h 00h 00h 00h XXh XXh XXh 00001000b 00000010b XXXXh 00h Page 21 of 60 R8C/38T-A Group Table 3.4 3. Address Space SFR Information (4) (1) Address Symbol Register Name 000BAh 000BBh 000BCh 000BDh 000BEh 000BFh 000C0h U2MR UART2 Transmit/Receive Mode Register 000C1h U2BRG UART2 Bit Rate Register 000C2h U2TB UART2 Transmit Buffer Register 000C3h 000C4h U2C0 UART2 Transmit/Receive Control Register 0 000C5h U2C1 UART2 Transmit/Receive Control Register 1 000C6h U2RB UART2 Receive Buffer Register 000C7h 000C8h U2RXDF UART2 Digital Filter Function Select Register 000C9h 000CAh 000CBh 000CCh 000CDh 000CEh 000CFh 000D0h U2SMR5 UART2 Special Mode Register 5 000D1h 000D2h 000D3h 000D4h U2SMR4 UART2 Special Mode Register 4 000D5h U2SMR3 UART2 Special Mode Register 3 000D6h U2SMR2 UART2 Special Mode Register 2 000D7h U2SMR UART2 Special Mode Register 000D8h 000D9h 000DAh 000DBh 000DCh 000DDh 000DEh 000DFh 000E0h IICCR_0 I2C_0 Control Register 000E1h SSBR_0 SS_0 Bit Counter Register 000E2h SITDR_0 SI_0 Transmit Data Register 000E3h 000E4h SIRDR_0 SI_0 Receive Data Register 000E5h 000E6h SICR1_0 SI_0 Control Register 1 000E7h SICR2_0 SI_0 Control Register 2 000E8h SIMR1_0 SI_0 Mode Register 1 000E9h SIER_0 SI_0 Interrupt Enable Register 000EAh SISR_0 SI_0 Status Register 000EBh SIMR2_0 SI_0 Mode Register 2 000ECh 000EDh 000EEh 000EFh 000F0h 000F1h 000F2h 000F3h 000F4h 000F5h 000F6h 000F7h 000F8h 000F9h Note: 1. The blank areas are reserved. No access is allowed. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 After Reset Remarks 00h 00h 00h 00h 00001000b 00000010b 0000h 00h 00h 00h 00h 00h 00h 00001110b 11111000b FFh FFh FFh FFh 00h 01111101b 00010000b 00h 00h 00h Page 22 of 60 R8C/38T-A Group Table 3.5 3. Address Space SFR Information (5) (1) Address Symbol Register Name 000FAh 000FBh 000FCh 000FDh 000FEh 000FFh 00100h 00101h 00102h 00103h 00104h 00105h 00106h 00107h 00108h 00109h 0010Ah 0010Bh 0010Ch 0010Dh 0010Eh 0010Fh 00110h TRJ_0 Timer RJ_0 Counter Register 00111h 00112h TRJCR_0 Timer RJ_0 Control Register 00113h TRJIOC_0 Timer RJ_0 I/O Control Register 00114h TRJMR_0 Timer RJ_0 Mode Register 00115h TRJISR_0 Timer RJ_0 Event Pin Select Register 00116h 00117h 00118h 00119h 0011Ah 0011Bh 0011Ch 0011Dh 0011Eh 0011Fh 00120h 00121h 00122h 00123h 00124h 00125h 00126h 00127h 00128h 00129h 0012Ah 0012Bh 0012Ch 0012Dh 0012Eh 0012Fh 00130h TRBCR_0 Timer RB2_0 Control Register 00131h TRBOCR_0 Timer RB2_0 One-Shot Control Register 00132h TRBIOC_0 Timer RB2_0 I/O Control Register 00133h TRBMR_0 Timer RB2_0 Mode Register 00134h TRBPRE_0 Timer RB2_0 Prescaler Register 00135h TRBPR_0 Timer RB2_0 Primary Register 00136h TRBSC_0 Timer RB2_0 Secondary Register 00137h TRBIR_0 Timer RB2_0 Interrupt Request Register 00138h TRCCNT_0 Timer RC_0 Counter 00139h Note: 1. The blank areas are reserved. No access is allowed. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 After Reset Remarks FFFFh 00h 00h 00h 00h 00h 00h 00h 00h FFh FFh FFh 00h 0000h Page 23 of 60 R8C/38T-A Group Table 3.6 Address 0013Ah 0013Bh 0013Ch 0013Dh 0013Eh 0013Fh 00140h 00141h 00142h 00143h 00144h 00145h 00146h 00147h 00148h 00149h 0014Ah 0014Bh 0014Ch 0014Dh 0014Eh 0014Fh 00150h 00151h 00152h 00153h 00154h 00155h 00156h 00157h 00158h 00159h 0015Ah 0015Bh 0015Ch 0015Dh 0015Eh 0015Fh 00160h 00161h 00162h 00163h 00164h 00165h 00166h 00167h 00168h 00169h 0016Ah 0016Bh 0016Ch 0016Dh 0016Eh 0016Fh 00170h 00171h 3. Address Space SFR Information (6) (1) Symbol TRCGRA_0 Register Name Timer RC_0 General Register A FFFFh TRCGRB_0 Timer RC_0 General Register B FFFFh TRCGRC_0 Timer RC_0 General Register C FFFFh TRCGRD_0 Timer RC_0 General Register D FFFFh TRCMR_0 TRCCR1_0 TRCIER_0 TRCSR_0 TRCIOR0_0 TRCIOR1_0 TRCCR2_0 TRCDF_0 TRCOER_0 TRCADCR_0 TRCOPR_0 TRCELCCR_0 Timer RC_0 Mode Register Timer RC_0 Control Register 1 Timer RC_0 Interrupt Enable Register Timer RC_0 Status Register Timer RC_0 I/O Control Register 0 Timer RC_0 I/O Control Register 1 Timer RC_0 Control Register 2 Timer RC_0 Digital Filter Function Select Register Timer RC_0 Output Enable Register Timer RC_0 A/D Conversion Trigger Control Register Timer RC_0 Output Waveform Manipulation Register Timer RC_0 ELC Cooperation Control Register 01001000b 00h 01110000b 01110000b 10001000b 10001000b 00011000b 00h 01111111b 11110000b 00h 00h TRESEC Timer RE2 Counter Data Register Timer RE2 Second Data Register Timer RE2 Compare Data Register Timer RE2 Minute Data Register Timer RE2 Hour Data Register Timer RE2 Day-of-the-Week Data Register Timer RE2 Day Data Register Timer RE2 Month Data Register Timer RE2 Year Data Register Timer RE2 Control Register Timer RE2 Count Source Select Register Timer RE2 Clock Error Correction Register 00h TREMIN 00172h TREHR 00173h TREWK 00174h TREDY 00175h TREMON 00176h TREYR 00177h TRECR 00178h TRECSR 00179h TREADJ Note: 1. The blank areas are reserved. No access is allowed. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 After Reset Remarks 00h 00h 00h 00000001b 00000001b 00h 00000100b 00001000b 00h Page 24 of 60 R8C/38T-A Group Table 3.7 3. Address Space SFR Information (7) (1) Address Symbol Register Name 0017Ah TREIFR Timer RE2 Interrupt Flag Register 0017Bh TREIER Timer RE2 Interrupt Enable Register 0017Ch TREAMN Timer RE2 Alarm Minute Register 0017Dh TREAHR Timer RE2 Alarm Hour Register 0017Eh TREAWK Timer RE2 Alarm Day-of-the-Week Register 0017Fh TREPRC Timer RE2 Protect Register 00180h to 001FFh 00200h AD0 A/D Register 0 00201h 00202h AD1 A/D Register 1 00203h 00204h AD2 A/D Register 2 00205h 00206h AD3 A/D Register 3 00207h 00208h AD4 A/D Register 4 00209h 0020Ah AD5 A/D Register 5 0020Bh 0020Ch AD6 A/D Register 6 0020Dh 0020Eh AD7 A/D Register 7 0020Fh 00210h 00211h 00212h 00213h 00214h ADMOD A/D Mode Register 00215h ADINSEL A/D Input Select Register 00216h ADCON0 A/D Control Register 0 00217h ADCON1 A/D Control Register 1 00218h 00219h 0021Ah 0021Bh 0021Ch 0021Dh 0021Eh 0021Fh 00220h 00221h 00222h 00223h 00224h 00225h 00226h 00227h 00228h INTCMP Comparator B Control Register 0 00229h 0022Ah 0022Bh 0022Ch 0022Dh 0022Eh 0022Fh 00230h INTEN External Input Enable Register 0 00231h INTEN1 External Input Enable Register 1 00232h INTF INT Input Filter Select Register 0 00233h INTF1 INT Input Filter Select Register 1 00234h INTPOL INT Input Polarity Switch Register 00235h 00236h KIEN Key Input Interrupt Enable Register 00237h 00238h MSTCR0 Module Standby Control Register 0 00239h MSTCR1 Module Standby Control Register 1 Note: 1. The blank areas are reserved. No access is allowed. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 After Reset Remarks 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 11000000b 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Page 25 of 60 R8C/38T-A Group Table 3.8 3. Address Space SFR Information (8) (1) Address Symbol Register Name 0023Ah MSTCR2 Module Standby Control Register 2 0023Bh MSTCR3 Module Standby Control Register 3 0023Ch MSTCR4 Module Standby Control Register 4 0023Dh 0023Eh 0023Fh 00240h 00241h 00242h 00243h 00244h 00245h 00246h 00247h 00248h 00249h 0024Ah 0024Bh 0024Ch 0024Dh 0024Eh 0024Fh 00250h 00251h 00252h FST Flash Memory Status Register 00253h 00254h FMR0 Flash Memory Control Register 0 00255h FMR1 Flash Memory Control Register 1 00256h FMR2 Flash Memory Control Register 2 00257h 00258h 00259h 0025Ah 0025Bh 0025Ch 0025Dh 0025Eh 0025Fh 00260h AIADR0L Address Match Interrupt Address 0L Register 00261h 00262h AIADR0H Address Match Interrupt Address 0H Register 00263h AIEN0 Address Match Interrupt Enable 0 Register 00264h AIADR1L Address Match Interrupt Address 1L Register 00265h 00266h AIADR1H Address Match Interrupt Address 1H Register 00267h AIEN1 Address Match Interrupt Enable 1 Register 00268h 00269h 0026Ah 0026Bh 0026Ch 0026Dh 0026Eh 0026Fh 00270h 00271h 00272h 00273h 00274h 00275h 00276h 00277h 00278h 00279h 0027Ah 0027Bh 0027Ch 0027Dh 0027Eh 0027Fh X: Undefined Note: 1. The blank areas are reserved. No access is allowed. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 After Reset Remarks 00h 00h 00h 10000X00b 00h 00h 00h XXXXh 0000XXXXb 00h XXXXh 0000XXXXb 00h Page 26 of 60 R8C/38T-A Group Table 3.9 3. Address Space SFR Information (9) (1) Address Symbol Register Name 00280h DTCTL DTC Activation Control Register 00281h 00282h 00283h 00284h 00285h 00286h 00287h 00288h DTCEN0 DTC Activation Enable Register 0 00289h DTCEN1 DTC Activation Enable Register 1 0028Ah DTCEN2 DTC Activation Enable Register 2 0028Bh DTCEN3 DTC Activation Enable Register 3 0028Ch 0028Dh DTCEN5 DTC Activation Enable Register 5 0028Eh DTCEN6 DTC Activation Enable Register 6 0028Fh 00290h CRCSAR SFR Snoop Address Register 00291h 00292h CRCMR CRC Control Register 00293h 00294h CRCD CRC Data Register 00295h 00296h CRCIN CRC Input Register 00297h 00298h 00299h 0029Ah 0029Bh 0029Ch 0029Dh 0029Eh 0029Fh 002A0h TRJ_0SR Timer RJ_0 Pin Select Register 002A1h 002A2h 002A3h 002A4h 002A5h TRCCLKSR Timer RCCLK Pin Select Register 002A6h TRC_0SR0 Timer RC_0 Pin Select Register 0 002A7h TRC_0SR1 Timer RC_0 Pin Select Register 1 002A8h 002A9h 002AAh 002ABh 002ACh 002ADh TIMSR Timer Pin Select Register 002AEh U_0SR UART0_0 Pin Select Register 002AFh U_1SR UART0_1 Pin Select Register 002B0h 002B1h 002B2h U2SR0 UART2 Pin Select Register 0 002B3h U2SR1 UART2 Pin Select Register 1 002B4h 002B5h 002B6h INTSR0 INT Interrupt Input Pin Select Register 0 002B7h 002B8h 002B9h PINSR I/O Function Pin Select Register 002BAh 002BBh 002BCh 002BDh 002BEh PMCSEL Pin Assignment Select Register 002BFh Note: 1. The blank areas are reserved. No access is allowed. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 After Reset Remarks 00h 00h 00h 00h 00h 00h 00h 0000h 00h 0000h 00h 08h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Page 27 of 60 R8C/38T-A Group Table 3.10 3. Address Space SFR Information (10) (1) Address Symbol Register Name 002C0h PUR0 Pull-Up Control Register 0 002C1h PUR1 Pull-Up Control Register 1 002C2h PUR2 Pull-Up Control Register 2 002C3h 002C4h 002C5h 002C6h 002C7h 002C8h P1DRR Port P1 Drive Capacity Control Register 002C9h P2DRR Port P2 Drive Capacity Control Register 002CAh 002CBh 002CCh DRR0 Drive Capacity Control Register 0 002CDh DRR1 Drive Capacity Control Register 1 002CEh DRR2 Drive Capacity Control Register 2 002CFh 002D0h VLT0 Input Threshold Control Register 0 002D1h VLT1 Input Threshold Control Register 1 002D2h VLT2 Input Threshold Control Register 2 002D3h 002D4h 002D5h 002D6h 002D7h 002D8h 002D9h 002DAh 002DBh 002DCh 002DDh 002DEh 002DFh 002E0h PORT0 Port P0 Register 002E1h PORT1 Port P1 Register 002E2h PD0 Port P0 Direction Register 002E3h PD1 Port P1 Direction Register 002E4h PORT2 Port P2 Register 002E5h PORT3 Port P3 Register 002E6h PD2 Port P2 Direction Register 002E7h PD3 Port P3 Direction Register 002E8h PORT4 Port P4 Register 002E9h PORT5 Port P5 Register 002EAh PD4 Port P4 Direction Register 002EBh PD5 Port P5 Direction Register 002ECh PORT6 Port P6 Register 002EDh PORT7 Port P7 Register 002EEh PD6 Port P6 Direction Register 002EFh PD7 Port P7 Direction Register 002F0h PORT8 Port P8 Register 002F1h PORT9 Port P9 Register 002F2h PD8 Port P8 Direction Register 002F3h PD9 Port P9 Direction Register 002F4h 002F5h 002F6h 002F7h 002F8h 002F9h 002FAh 002FBh 002FCh 002FDh 002FEh 002FFh 00300h to 003FFh Note: 1. The blank areas are reserved. No access is allowed. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 After Reset Remarks 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h Page 28 of 60 R8C/38T-A Group Table 3.11 3. Address Space SFR Information (11) (1) Address Symbol Register Name 00400h On-chip RAM On-chip RAM to 053FFh 05400h to 069FFh 06A00h ELSELR0 Event Output Destination Select Register 0 06A01h ELSELR1 Event Output Destination Select Register 1 06A02h ELSELR2 Event Output Destination Select Register 2 06A03h ELSELR3 Event Output Destination Select Register 3 06A04h ELSELR4 Event Output Destination Select Register 4 06A05h 06A06h 06A07h 06A08h ELSELR8 Event Output Destination Select Register 8 06A09h ELSELR9 Event Output Destination Select Register 9 06A0Ah 06A0Bh ELSELR11 Event Output Destination Select Register 11 06A0Ch ELSELR12 Event Output Destination Select Register 12 06A0Dh ELSELR13 Event Output Destination Select Register 13 06A0Eh ELSELR14 Event Output Destination Select Register 14 06A0Fh ELSELR15 Event Output Destination Select Register 15 06A10h ELSELR16 Event Output Destination Select Register 16 06A11h 06A12h 06A13h 06A14h 06A15h 06A16h 06A17h 06A18h 06A19h 06A1Ah 06A1Bh 06A1Ch 06A1Dh 06A1Eh 06A1Fh 06A20h 06A21h 06A22h 06A23h 06A24h 06A25h 06A26h 06A27h 06A28h 06A29h 06A2Ah 06A2Bh 06A2Ch 06A2Dh 06A2Eh 06A2Fh 06A30h 06A31h to 06AFFh Note: 1. The blank areas are reserved. No access is allowed. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 After Reset Remarks 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Page 29 of 60 R8C/38T-A Group Table 3.12 3. Address Space SFR Information (12) (1) Address Symbol Register Name 06B00h TSCUCR0 TSCU Control Register 0 06B01h 06B02h TSCUCR1 TSCU Control Register 1 06B03h 06B04h TSCUMR TSCU Mode Register 06B05h 06B06h TSCUTCR0A TSCU Timing Control Register 0A 06B07h 06B08h TSCUTCR0B TSCU Timing Control Register 0B 06B09h 06B0Ah TSCUTCR1 TSCU Timing Control Register 1 06B0Bh 06B0Ch TSCUTCR2 TSCU Timing Control Register 2 06B0Dh 06B0Eh TSCUTCR3 TSCU Timing Control Register 3 06B0Fh 06B10h TSCUCHC TSCU Channel Control Register 06B11h 06B12h TSCUFR TSCU Flag Register 06B13h 06B14h TSCUSTC TSCU Status Counter Register 06B15h 06B16h TSCUSCS TSCU Secondary Counter Set Register 06B17h 06B18h TSCUSCC TSCU Secondary Counter 06B19h 06B1Ah TSCUDBR TSCU Data Buffer Register 06B1Bh 06B1Ch TSCUPRC TSCU Primary Counter 06B1Dh 06B1Eh TSCURVR0 TSCU Random Value Store Register 0 06B1Fh 06B20h TSCURVR1 TSCU Random Value Store Register 1 06B21h 06B22h TSCURVR2 TSCU Random Value Store Register 2 06B23h 06B24h TSCURVR3 TSCU Random Value Store Register 3 06B25h 06B26h TSIE0 TSCU Input Enable Register 0 06B27h 06B28h TSIE1 TSCU Input Enable Register 1 06B29h 06B2Ah TSIE2 TSCU Input Enable Register 2 06B2Bh 06B2Ch TSCHSEL0 TSCUCHXA Select Register 0 06B2Dh 06B2Eh TSCHSEL1 TSCUCHXA Select Register 1 06B2Fh 06B30h TSCHSEL2 TSCUCHXA Select Register 2 06B31h 06B32h to 06BFFh 06C00h Area for storing DTC transfer vector 0 06C01h Area for storing DTC transfer vector 1 06C02h Area for storing DTC transfer vector 2 06C03h Area for storing DTC transfer vector 3 06C04h Area for storing DTC transfer vector 4 06C05h 06C06h 06C07h 06C08h Area for storing DTC transfer vector 8 06C09h Area for storing DTC transfer vector 9 X: Undefined Note: 1. The blank areas are reserved. No access is allowed. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 After Reset Remarks 0000h 0000000000010000b 0000000010000000b 0000000001111111b 0000000001111111b 0000000000000001b 0000h 0000h 0011111100000000b 0000h 0000h 0000000000100000b 0000000000100000b 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h XXh XXh XXh XXh XXh XXh XXh Page 30 of 60 R8C/38T-A Group Table 3.13 3. Address Space SFR Information (13) (1) Address Symbol Register Name 06C0Ah Area for storing DTC transfer vector 10 06C0Bh Area for storing DTC transfer vector 11 06C0Ch Area for storing DTC transfer vector 12 06C0Dh Area for storing DTC transfer vector 13 06C0Eh Area for storing DTC transfer vector 14 06C0Fh Area for storing DTC transfer vector 15 06C10h Area for storing DTC transfer vector 16 06C11h Area for storing DTC transfer vector 17 06C12h Area for storing DTC transfer vector 18 06C13h Area for storing DTC transfer vector 19 06C14h 06C15h 06C16h Area for storing DTC transfer vector 22 06C17h Area for storing DTC transfer vector 23 06C18h Area for storing DTC transfer vector 24 06C19h Area for storing DTC transfer vector 25 06C1Ah 06C1Bh 06C1Ch 06C1Dh 06C1Eh 06C1Fh 06C20h 06C21h 06C22h 06C23h 06C24h 06C25h 06C26h 06C27h 06C28h 06C29h 06C2Ah Area for storing DTC transfer vector 42 06C2Bh 06C2Ch 06C2Dh 06C2Eh 06C2Fh 06C30h 06C31h Area for storing DTC transfer vector 49 06C32h 06C33h Area for storing DTC transfer vector 51 06C34h Area for storing DTC transfer vector 52 06C35h Area for storing DTC transfer vector 53 06C36h Area for storing DTC transfer vector 54 06C37h 06C38h 06C39h 06C3Ah 06C3Bh 06C3Ch 06C3Dh 06C3Eh 06C3Fh 06C40h DTCCR0 DTC Control Register 0 06C41h DTBLS0 DTC Block Size Register 0 06C42h DTCCT0 DTC Transfer Count Register 0 06C43h DTRLD0 DTC Transfer Count Reload Register 0 06C44h DTSAR0 DTC Source Address Register 0 06C45h 06C46h DTDAR0 DTC Destination Address Register 0 06C47h 06C48h DTCCR1 DTC Control Register 1 06C49h DTBLS1 DTC Block Size Register 1 X: Undefined Note: 1. The blank areas are reserved. No access is allowed. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 After Reset Remarks XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh Page 31 of 60 R8C/38T-A Group Table 3.14 3. Address Space SFR Information (14) (1) Address Symbol Register Name 06C4Ah DTCCT1 DTC Transfer Count Register 1 06C4Bh DTRLD1 DTC Transfer Count Reload Register 1 06C4Ch DTSAR1 DTC Source Address Register 1 06C4Dh 06C4Eh DTDAR1 DTC Destination Address Register 1 06C4Fh 06C50h DTCCR2 DTC Control Register 2 06C51h DTBLS2 DTC Block Size Register 2 06C52h DTCCT2 DTC Transfer Count Register 2 06C53h DTRLD2 DTC Transfer Count Reload Register 2 06C54h DTSAR2 DTC Source Address Register 2 06C55h 06C56h DTDAR2 DTC Destination Address Register 2 06C57h 06C58h DTCCR3 DTC Control Register 3 06C59h DTBLS3 DTC Block Size Register 3 06C5Ah DTCCT3 DTC Transfer Count Register 3 06C5Bh DTRLD3 DTC Transfer Count Reload Register 3 06C5Ch DTSAR3 DTC Source Address Register 3 06C5Dh 06C5Eh DTDAR3 DTC Destination Address Register 3 06C5Fh 06C60h DTCCR4 DTC Control Register 4 06C61h DTBLS4 DTC Block Size Register 4 06C62h DTCCT4 DTC Transfer Count Register 4 06C63h DTRLD4 DTC Transfer Count Reload Register 4 06C64h DTSAR4 DTC Source Address Register 4 06C65h 06C66h DTDAR4 DTC Destination Address Register 4 06C67h 06C68h DTCCR5 DTC Control Register 5 06C69h DTBLS5 DTC Block Size Register 5 06C6Ah DTCCT5 DTC Transfer Count Register 5 06C6Bh DTRLD5 DTC Transfer Count Reload Register 5 06C6Ch DTSAR5 DTC Source Address Register 5 06C6Dh 06C6Eh DTDAR5 DTC Destination Address Register 5 06C6Fh 06C70h DTCCR6 DTC Control Register 6 06C71h DTBLS6 DTC Block Size Register 6 06C72h DTCCT6 DTC Transfer Count Register 6 06C73h DTRLD6 DTC Transfer Count Reload Register 6 06C74h DTSAR6 DTC Source Address Register 6 06C75h 06C76h DTDAR6 DTC Destination Address Register 6 06C77h 06C78h DTCCR7 DTC Control Register 7 06C79h DTBLS7 DTC Block Size Register 7 06C7Ah DTCCT7 DTC Transfer Count Register 7 06C7Bh DTRLD7 DTC Transfer Count Reload Register 7 06C7Ch DTSAR7 DTC Source Address Register 7 06C7Dh 06C7Eh DTDAR7 DTC Destination Address Register 7 06C7Fh 06C80h DTCCR8 DTC Control Register 8 06C81h DTBLS8 DTC Block Size Register 8 06C82h DTCCT8 DTC Transfer Count Register 8 06C83h DTRLD8 DTC Transfer Count Reload Register 8 06C84h DTSAR8 DTC Source Address Register 8 06C85h 06C86h DTDAR8 DTC Destination Address Register 8 06C87h 06C88h DTCCR9 DTC Control Register 9 06C89h DTBLS9 DTC Block Size Register 9 06C8Ah DTCCT9 DTC Transfer Count Register 9 06C8Bh DTRLD9 DTC Transfer Count Reload Register 9 06C8Ch DTSAR9 DTC Source Address Register 9 06C8Dh 06C8Eh DTDAR9 DTC Destination Address Register 9 06C8Fh X: Undefined Note: 1. The blank areas are reserved. No access is allowed. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 After Reset XXh XXh XXXXh Remarks XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh Page 32 of 60 R8C/38T-A Group Table 3.15 3. Address Space SFR Information (15) (1) Address Symbol Register Name 06C90h DTCCR10 DTC Control Register 10 06C91h DTBLS10 DTC Block Size Register 10 06C92h DTCCT10 DTC Transfer Count Register 10 06C93h DTRLD10 DTC Transfer Count Reload Register 10 06C94h DTSAR10 DTC Source Address Register 10 06C95h 06C96h DTDAR10 DTC Destination Address Register 10 06C97h 06C98h DTCCR11 DTC Control Register 11 06C99h DTBLS11 DTC Block Size Register 11 06C9Ah DTCCT11 DTC Transfer Count Register 11 06C9Bh DTRLD11 DTC Transfer Count Reload Register 11 06C9Ch DTSAR11 DTC Source Address Register 11 06C9Dh 06C9Eh DTDAR11 DTC Destination Address Register 11 06C9Fh 06CA0h DTCCR12 DTC Control Register 12 06CA1h DTBLS12 DTC Block Size Register 12 06CA2h DTCCT12 DTC Transfer Count Register 12 06CA3h DTRLD12 DTC Transfer Count Reload Register 12 06CA4h DTSAR12 DTC Source Address Register 12 06CA5h 06CA6h DTDAR12 DTC Destination Address Register 12 06CA7h 06CA8h DTCCR13 DTC Control Register 13 06CA9h DTBLS13 DTC Block Size Register 13 06CAAh DTCCT13 DTC Transfer Count Register 13 06CABh DTRLD13 DTC Transfer Count Reload Register 13 06CACh DTSAR13 DTC Source Address Register 13 06CADh 06CAEh DTDAR13 DTC Destination Address Register 13 06CAFh 06CB0h DTCCR14 DTC Control Register 14 06CB1h DTBLS14 DTC Block Size Register 14 06CB2h DTCCT14 DTC Transfer Count Register 14 06CB3h DTRLD14 DTC Transfer Count Reload Register 14 06CB4h DTSAR14 DTC Source Address Register 14 06CB5h 06CB6h DTDAR14 DTC Destination Address Register 14 06CB7h 06CB8h DTCCR15 DTC Control Register 15 06CB9h DTBLS15 DTC Block Size Register 15 06CBAh DTCCT15 DTC Transfer Count Register 15 06CBBh DTRLD15 DTC Transfer Count Reload Register 15 06CBCh DTSAR15 DTC Source Address Register 15 06CBDh 06CBEh DTDAR15 DTC Destination Address Register 15 06CBFh 06CC0h DTCCR16 DTC Control Register 16 06CC1h DTBLS16 DTC Block Size Register 16 06CC2h DTCCT16 DTC Transfer Count Register 16 06CC3h DTRLD16 DTC Transfer Count Reload Register 16 06CC4h DTSAR16 DTC Source Address Register 16 06CC5h 06CC6h DTDAR16 DTC Destination Address Register 16 06CC7h 06CC8h DTCCR17 DTC Control Register 17 06CC9h DTBLS17 DTC Block Size Register 17 06CCAh DTCCT17 DTC Transfer Count Register 17 06CCBh DTRLD17 DTC Transfer Count Reload Register 17 06CCCh DTSAR17 DTC Source Address Register 17 06CCDh 06CCEh DTDAR17 DTC Destination Address Register 17 06CCFh X: Undefined Note: 1. The blank areas are reserved. No access is allowed. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 After Reset XXh XXh XXh XXh XXXXh Remarks XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh Page 33 of 60 R8C/38T-A Group Table 3.16 3. Address Space SFR Information (16) (1) Address Symbol Register Name 06CD0h DTCCR18 DTC Control Register 18 06CD1h DTBLS18 DTC Block Size Register 18 06CD2h DTCCT18 DTC Transfer Count Register 18 06CD3h DTRLD18 DTC Transfer Count Reload Register 18 06CD4h DTSAR18 DTC Source Address Register 18 06CD5h 06CD6h DTDAR18 DTC Destination Address Register 18 06CD7h 06CD8h DTCCR19 DTC Control Register 19 06CD9h DTBLS19 DTC Block Size Register 19 06CDAh DTCCT19 DTC Transfer Count Register 19 06CDBh DTRLD19 DTC Transfer Count Reload Register 19 06CDCh DTSAR19 DTC Source Address Register 19 06CDDh 06CDEh DTDAR19 DTC Destination Address Register 19 06CDFh 06CE0h DTCCR20 DTC Control Register 20 06CE1h DTBLS20 DTC Block Size Register 20 06CE2h DTCCT20 DTC Transfer Count Register 20 06CE3h DTRLD20 DTC Transfer Count Reload Register 20 06CE4h DTSAR20 DTC Source Address Register 20 06CE5h 06CE6h DTDAR20 DTC Destination Address Register 20 06CE7h 06CE8h DTCCR21 DTC Control Register 21 06CE9h DTBLS21 DTC Block Size Register 21 06CEAh DTCCT21 DTC Transfer Count Register 21 06CEBh DTRLD21 DTC Transfer Count Reload Register 21 06CECh DTSAR21 DTC Source Address Register 21 06CEDh 06CEEh DTDAR21 DTC Destination Address Register 21 06CEFh 06CF0h DTCCR22 DTC Control Register 22 06CF1h DTBLS22 DTC Block Size Register 22 06CF2h DTCCT22 DTC Transfer Count Register 22 06CF3h DTRLD22 DTC Transfer Count Reload Register 22 06CF4h DTSAR22 DTC Source Address Register 22 06CF5h 06CF6h DTDAR22 DTC Destination Address Register 22 06CF7h 06CF8h DTCCR23 DTC Control Register 23 06CF9h DTBLS23 DTC Block Size Register 23 06CFAh DTCCT23 DTC Transfer Count Register 23 06CFBh DTRLD23 DTC Transfer Count Reload Register 23 06CFCh DTSAR23 DTC Source Address Register 23 06CFDh 06CFEh DTDAR23 DTC Destination Address Register 23 06CFFh 06D00h to 06FFFh X: Undefined Note: 1. The blank areas are reserved. No access is allowed. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 After Reset XXh XXh XXh XXh XXXXh Remarks XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh XXh XXh XXh XXh XXXXh XXXXh Page 34 of 60 R8C/38T-A Group Table 3.17 3. Address Space ID code Area, Option Function Select Area Address Symbol Area Name After Reset Address size : 0FFDBh OFS2 Option Function Select Register 2 (Note 1) : 0FFDFh ID1 (Note 2) : 0FFE3h ID2 (Note 2) : 0FFEBh ID3 (Note 2) : 0FFEFh ID4 (Note 2) : 0FFF3h ID5 (Note 2) : 0FFF7h ID6 (Note 2) : 0FFFBh ID7 (Note 2) : 0FFFFh OFS Option Function Select Register (Note 1) Notes: 1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. Do not perform any additional writes to the option function select area. Erasing the block including the option function select area sets the option function select area to FFh. 2. The ID code area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. Do not perform any additional writes to the ID code area. Erasing the block including the ID code area sets the ID code area to FFh. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 35 of 60 R8C/38T-A Group 4. 4. Electrical Characteristics Electrical Characteristics 4.1 Absolute Maximum Ratings Table 4.1 Absolute Maximum Ratings Symbol Vcc/AVcc ICEVcc VI VO Pd Topr Parameter Supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Tstg Storage temperature R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Condition 40°C Topr 85°C Rated Value 0.3 to 6.5 Unit V 0.3 to Vcc + 0.3 0.3 to Vcc + 0.3 500 20 to 85 (N version)/ 40 to 85 (D version) 65 to 150 V V mW °C °C Page 36 of 60 R8C/38T-A Group 4.2 4. Electrical Characteristics Recommended Operating Conditions Table 4.2 Recommended Operating Conditions (1) (Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/40°C to 85°C (D version), unless otherwise specified) Symbol Parameter VCC/AVCC Supply voltage VSS/AVSS Supply voltage VIH Input high Other than CMOS input voltage CMOS Input level input switching function (I/O port) Conditions Input level selection: 0.35VCC Input level selection: 0.5VCC Input level selection: 0.7VCC VIL Input low voltage External clock input (XOUT) Other than CMOS input CMOS Input level Input level input switching selection: function 0.35VCC (I/O port) Input level selection: 0.5VCC Input level selection: 0.7VCC f(XIN) External clock input (XOUT) Peak sum output high Sum of all pins IOH(peak) current Average sum output high Sum of all pins IOH(avg) current Peak output high current When drive capacity is low When drive capacity is high Average output high When drive capacity is low current When drive capacity is high Peak sum output low Sum of all pins IOL(peak) current Average sum output low Sum of all pins IOL(avg) current Peak output low current When drive capacity is low When drive capacity is high Average output low When drive capacity is low current When drive capacity is high XIN clock input oscillation frequency f(XCIN) fHOCO fHOCO-F XCIN clock input oscillation frequency Count source for timer RC fHOCO-F frequency — System clock frequency f(BCLK) CPU clock frequency IOH(sum) IOH(sum) IOH(peak) IOH(avg) IOL(sum) IOL(sum) IOL(peak) IOL(avg) 4.0 V VCC 5.5 V 2.7 V VCC 4.0 V 1.8 V VCC 2.7 V 4.0 V VCC 5.5 V 2.7 V VCC 4.0 V 1.8 V VCC 2.7 V 4.0 V VCC 5.5 V 2.7 V VCC 4.0 V 1.8 V VCC 2.7 V 4.0 V VCC 5.5 V 2.7 V VCC 4.0 V 1.8 V VCC 2.7 V 4.0 V VCC 5.5 V 2.7 V VCC 4.0 V 1.8 V VCC 2.7 V 4.0 V VCC 5.5 V 2.7 V VCC 4.0 V 1.8 V VCC 2.7 V Min. 1.8 ― 0.8VCC 0.5VCC 0.55VCC 0.65VCC 0.65VCC 0.7VCC 0.8VCC 0.85VCC 0.85VCC 0.85VCC 1.2 0 0 0 0 0 0 0 0 0 0 0 ― Standard Typ. ― 0 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― Max. 5.5 ― VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 0.2VCC 0.2VCC 0.2VCC 0.2VCC 0.4VCC 0.3VCC 0.2VCC 0.55VCC 0.45VCC 0.35VCC 0.4 80 ― ― 40 mA ― ― ― ― ― ― ― ― ― ― 10 40 5 20 80 mA mA mA mA mA ― ― 40 mA ― ― ― ― ― ― ― 32 ― ― ― ― ― ― ― ― ― ― ― ― 32.768 ― ― ― ― ― ― ― 10 40 5 20 20 5 50 40 20 5 20 5 20 5 mA mA mA mA MHz MHz kHz MHz MHz MHz MHz MHz MHz MHz 2.7 V VCC 5.5 V 1.8 V VCC 2.7 V 1.8 V VCC 5.5 V 2.7 V VCC 5.5 V 2.7 V VCC 5.5 V 1.8 V VCC 2.7 V 2.7 V VCC 5.5 V 1.8 V VCC 2.7 V 2.7 V VCC 5.5 V 1.8 V VCC 2.7 V Unit V V V V V V V V V V V V V V V V V V V V V V V V mA Note: 1. The average output current indicates the average value of current measured during 100 ms. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 37 of 60 R8C/38T-A Group 4. Electrical Characteristics P0, P1, P2 P3 P4_2 to P4_7 P5, P6, P7, P8 P9_0 to P9_5 Figure 4.1 30 pF Timing Measurement Circuit for Ports P0, P1, P2, P3, P4_2 to P4_7, P5, P6, P7, P8, and P9_0 to P9_5 R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 38 of 60 R8C/38T-A Group 4.3 4. Electrical Characteristics Peripheral Function Characteristics Table 4.3 A/D Converter Characteristics (Vcc/AVcc = Vref = 2.2 V to 5.5 V, Vss = 0 V, Topr = 20°C to 85°C (N version)/ 40°C to 85°C (D version), unless otherwise specified) Symbol ― ― Resolution Absolute accuracy 10-bit mode 8-bit mode AD ― Ivref tCONV tSAMP Vref VIA Min. ― ― ― ― ― ― ― ― ― Standard Typ. ― ― ― ― ― ― ― ― ― Max. 10 ±3 ±5 ±5 ±5 ±2 ±2 ±2 ±2 Bit LSB LSB LSB LSB LSB LSB LSB LSB 4.0 V Vref = AVcc 5.5 V (1) 2 ― 20 MHz 3.2 V Vref = AVcc 5.5 V (1) 2 ― 16 MHz 2.7 V Vref = AVcc 5.5 V (1) 2 ― 10 MHz 2.2 V Vref = AVcc 5.5 V (1) 2 ― 5 MHz ― ― 2.2 2.2 0.8 2.2 3 45 ― ― ― ― ― ― ― ― ― AVcc kΩ μA μs μs μs V 0 1.19 ― 1.34 Vref 1.49 V V Parameter A/D conversion clock Tolerance level impedance Vref current Conversion time 10-bit mode 8-bit mode Sampling time Reference voltage Analog input voltage (2) OCVREF On-chip reference voltage Conditions Vref = AVcc Vref = AVcc = 5.0 V Vref = AVcc = 3.3 V Vref = AVcc = 3.0 V Vref = AVcc = 2.2 V Vref = AVcc = 5.0 V Vref = AVcc = 3.3 V Vref = AVcc = 3.0 V Vref = AVcc = 2.2 V AN0 to AN19 input AN0 to AN19 input AN0 to AN19 input AN0 to AN19 input AN0 to AN19 input AN0 to AN19 input AN0 to AN19 input AN0 to AN19 input Vcc = 5 V, XIN = f1 = fAD = 20 MHz Vref = AVcc = 5.0 V, AD = 20 MHz Vref = AVcc = 5.0 V, AD = 20 MHz AD = 20 MHz 2MHz AD 4MHz Unit Notes: 1. If the CPU and the flash memory stop, the A/D conversion result will be undefined. 2. When the analog input voltage exceeds the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode. Table 4.4 Symbol Vref VI ― td ICMP Comparator B Characteristics (Vcc/AVcc = 2.2 V to 5.5 V, Topr = 20°C to 85°C (N version)/40°C to 85°C (D version), unless otherwise specified) Parameter Conditions IVREF1, IVREF3 input reference voltage IVCMP1, IVCMP3 input voltage Offset Comparator output delay time (1) Comparator operating current VI = Vref ±100 mV Vcc = 5.0 V Min. 0 Standard Typ. ― Max. Vcc 1.4 0.3 ― ― ― 5 0.1 Vcc + 0.3 100 ― V mV μs ― 17.5 ― μA Unit V Note: 1. When the digital filter is not selected. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 39 of 60 R8C/38T-A Group Table 4.5 Symbol ― ― ― ― ― ― ― td(SR-SUS) ― ― 4. Electrical Characteristics Flash Memory (Program ROM) Characteristics (Vcc = 2.7 V to 5.5 V, Topr =20°C to 85°C (N version)/40°C to 85°C (D version), unless otherwise specified) Parameter Program/erase endurance (1) Byte program time (Program and erase endurance 100 times) Byte program time (Program and erase endurance 1,000 times) Word program time (Program and erase endurance 100 times) Word program time (Program and erase endurance 100 times) Word program time (Program and erase endurance 1,000 times) Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Time from suspend until erase restart Conditions Topr = 25°C, VCC = 5.0 V Data hold time (6) Ambient temperature = 55°C (7) Standard Typ. ― Unit Max. ― times ― ― μs ― ― ― μs ― 100 200 μs ― 100 400 μs ― 100 650 μs ― ― 0.3 ― s ms 0 ― 4 5 + CPU clock × 3 cycles ― ― ― μs ― ― 2.7 1.8 20 (N ver.) 40 (D ver.) 20 ― ― ― 30 + CPU clock × 1 cycle 30 + CPU clock × 1 cycle 5.5 5.5 85 V V °C ― ― year 1,000 (2) ― td(CMDRST Time from when command is forcibly -READY) terminated until reading is enabled ― Program, erase voltage ― Read voltage ― Program, erase temperature ― Min. μs μs Notes: 1. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. For example, if 1,024 1byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 6. The data hold time includes time that the power supply is off or the clock is not supplied. 7. The data hold time includes 7,000 hours under an environment of ambient temperature 85°C. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 40 of 60 R8C/38T-A Group Table 4.6 Symbol ― ― ― ― ― td(SR-SUS) ― ― 4. Electrical Characteristics Flash Memory (Data flash Block A to Block D) Characteristics (Vcc = 2.7 V to 5.5 V, Topr = 20°C to 85°C (N version)/40°C to 85°C (D version), unless otherwise specified) Parameter Program/erase endurance (1) Byte program time (Program and erase endurance 1,000 times) Byte program time (Program and erase endurance > 1,000 times) Block erase time (Program and erase endurance 1,000 times) Block erase time (Program and erase endurance > 1,000 times) Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Time from suspend until erase restart ― ― ― Time from when command is forcibly terminated until reading is enabled Program, erase voltage Read voltage Program, erase temperature ― Data hold time (6) td(CMDRST -READY) Conditions Standard Typ. ― Max. ― times 160 950 μs ― 300 950 μs ― 0.2 1 s ― 0.3 1 s ― ― ms 0 ― 3 + CPU clock × 3 cycles ― ― ― μs ― ― 2.7 1.8 20 (N ver.) 40 (D ver.) 20 ― ― ― 30 + CPU clock × 1 cycle 30 + CPU clock × 1 cycle 5.5 5.5 85 V V °C ― ― year Min. 10,000 (2) ― Ambient temperature = 55°C (7) Unit μs μs Notes: 1. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100, 1,000 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 6. The data hold time includes time that the power supply is off or the clock is not supplied. 7. The data hold time includes 7,000 hours under an environment of ambient temperature 85°C. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 41 of 60 R8C/38T-A Group 4. Electrical Characteristics Suspend request (FMR21 bit) FST6 bit Clock-dependent time Fixed time Access restart td(SR-SUS) FST6: Bit in FST register FMR21: Bit in FMR2 register Figure 4.2 Table 4.7 Symbol Time Delay from Suspend Request until Suspend Voltage Detection 0 Circuit Characteristics (Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/ 40°C to 85°C (D version)) Parameter Conditions Standard Typ. 1.90 Max. 2.05 Unit Voltage detection level Vdet0_0 (1) When Vcc falls Min. 1.80 Voltage detection level Vdet0_1 (1) When Vcc falls 2.15 2.35 2.55 V Voltage detection level Vdet0_2 (1) When Vcc falls 2.70 2.85 3.05 V Voltage detection level Vdet0_3 (1) When Vcc falls 3.55 3.80 4.05 V ― Voltage detection 0 circuit response time (2) ― 6 150 μs ― Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts (3) At the falling of Vcc from 5 V to (Vdet0 0.1) V VCA25 = 1, Vcc = 5.0 V ― 1.5 ― μA ― ― 100 μs Vdet0 td(E-A) V Notes: 1. The voltage detection level must be selected with bits VDSEL0 and VDSEL1 in the OFS register. 2. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 42 of 60 R8C/38T-A Group Table 4.8 Symbol 4. Electrical Characteristics Voltage Detection 1 Circuit Characteristics (Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/ 40°C to 85°C (D version)) Parameter Vdet1 ― Conditions Max. 2.40 Unit Voltage detection level Vdet1_0 (1) When Vcc falls Voltage detection level Vdet1_1 (1) When Vcc falls 2.15 2.35 2.55 V Voltage detection level Vdet1_2 (1) When Vcc falls 2.30 2.50 2.70 V Voltage detection level Vdet1_3 (1) When Vcc falls 2.45 2.65 2.85 V Voltage detection level Vdet1_4 (1) When Vcc falls 2.60 2.80 3.00 V Voltage detection level Vdet1_5 (1) When Vcc falls 2.75 2.95 3.15 V Voltage detection level Vdet1_6 (1) When Vcc falls 2.80 3.10 3.40 V Voltage detection level Vdet1_7 (1) When Vcc falls 2.95 3.25 3.55 V Voltage detection level Vdet1_8 (1) When Vcc falls 3.10 3.40 3.70 V Voltage detection level Vdet1_9 (1) When Vcc falls 3.25 3.55 3.85 V Voltage detection level Vdet1_A (1) When Vcc falls 3.40 3.70 4.00 V Voltage detection level Vdet1_B (1) When Vcc falls 3.55 3.85 4.15 V Voltage detection level Vdet1_C (1) When Vcc falls 3.70 4.00 4.30 V Voltage detection level Vdet1_D (1) When Vcc falls 3.85 4.15 4.45 V Voltage detection level Vdet1_E (1) When Vcc falls 4.00 4.30 4.60 V Voltage detection level Vdet1_F (1) Hysteresis width at the rising of Vcc in voltage detection 1 circuit When Vcc falls 4.15 4.45 4.75 V ― 0.07 ― V ― 0.10 ― V ― 60 150 μs ― 1.7 ― μA ― ― 100 μs ― Voltage detection 1 circuit response time (2) ― Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts (3) td(E-A) Standard Typ. 2.20 Min. 2.00 Vdet1_0 to Vdet1_5 selected Vdet1_6 to Vdet1_F selected At the falling of Vcc from 5 V to (Vdet1 0.1) V VCA26 = 1, Vcc = 5.0 V V Notes: 1. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register. 2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. Table 4.9 Symbol Voltage Detection 2 Circuit Characteristics (Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/ 40°C to 85°C (D version)) Parameter Conditions Vdet2 ― Voltage detection level Vdet2_0 Hysteresis width at the rising of Vcc in voltage detection 2 circuit When Vcc falls ― Voltage detection 2 circuit response time (1) ― Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts (2) At the falling of Vcc from 5 V to (Vdet2_0 0.1) V VCA27 = 1, Vcc = 5.0 V td(E-A) Min. 3.70 ― Standard Typ. 4.00 0.1 Max. 4.30 ― ― 20 150 μs ― 1.7 ― μA ― ― 100 μs Unit V μs Notes: 1. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 43 of 60 R8C/38T-A Group 4. Electrical Characteristics Power-On Reset Circuit Characteristics (1) (Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/ 40°C to 85°C (D version)) Table 4.10 Symbol Parameter trth Conditions External power VCC rise gradient Min. 0 Standard Typ. ― Max. 50,000 Unit mV/msec Note: 1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0. Vdet0 (1) Vdet0 (1) trth trth External Power VCC 0.5 V Voltage detection 0 circuit response time tw(por) (2) Internal reset signal 1 32 fOCO-S 1 32 fOCO-S Notes: 1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to the Voltage Detection Circuit chapter of User’s Manual: Hardware for details. 2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain tw(por) for 1 ms or more. Figure 4.3 Power-on Reset Circuit Characteristics Table 4.11 Symbol ― High-Speed On-Chip Oscillator Circuit Characteristics Parameter High-speed on-chip oscillator frequency after reset High-speed on-chip oscillator frequency when 01b or 10b is written to bits FRA25 and FRA24 in the FRA2 register Conditions Vcc = 1.8 V to 5.5 V, 20°C Topr 85°C (N version) 40°C Topr 85°C (D version) Min. ― Standard Typ. 40 Max. ― MHz — 36.864 — MHz — 32 — MHz 1.5 ― 1.5 % ― ― 250 500 ― ― μs μA Unit (1) ― ― High-speed on-chip oscillator frequency when 10b is written to bits FRA25 and FRA24 in the FRA2 register High-speed on-chip oscillator frequency dependence on temperature and power supply voltage (2) Oscillation stability time Vcc = 5.0 V, Topr = 25°C Self power consumption at oscillation Vcc = 5.0 V, Topr = 25°C Notes: 1. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in UART mode. 2. This indicates the precision error for the oscillation frequency of the high-speed on-chip oscillator. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 44 of 60 R8C/38T-A Group Table 4.12 Symbol Low-speed on-chip oscillator frequency Oscillation stability time Self power consumption at oscillation Table 4.13 td(P-R) Low-Speed On-Chip Oscillator Circuit Characteristics (Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/ 40°C to 85°C (D version)) Parameter fLOCO ― ― Symbol 4. Electrical Characteristics Conditions Vcc = 5.0 V, Topr = 25°C Vcc = 5.0 V, Topr = 25°C Min. 60 ― ― Standard Typ. 125 30 3 Max. 250 100 ― Unit kHz μs μA Power Supply Circuit Characteristics (Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/ 40°C to 85°C (D version)) Parameter Time for internal power supply stabilization during power-on (1) Conditions Min. ― Standard Typ. ― Max. 2,000 Unit μs Note: 1. Waiting time until the internal power supply generation circuit stabilizes during power-on. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 45 of 60 R8C/38T-A Group 4.4 4. Electrical Characteristics DC Characteristics Table 4.14 DC Characteristics (1) [4.2 V Vcc 5.5 V] (Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/ 40°C to 85°C (D version)) Symbol VOH VOL Output high Other than XOUT voltage Output low voltage XOUT Other than XOUT XOUT VT+-VT- IIH IIL RPULLUP RfXIN RfXCIN VRAM Standard Min. Typ. Vcc 2.0 ― Max. Vcc Vcc 2.0 Vcc 0.3 1.0 ― — — — ― Vcc Vcc Vcc 2.0 V V V V — — — 0.1 — — — 1.2 2.0 0.45 0.5 ― V V V V Vcc = 5.0 V 0.1 1.2 ― V VI = 5.0 V VI = 0 V VI = 0 V ― ― 25 ― ― ― 50 0.3 1.0 1.0 100 ― μA μA kΩ MΩ ― 8 ― MΩ 1.8 ― ― V Parameter Hysteresis Conditions Drive capacity is IOH = 20 mA high Drive capacity is low IOH = 5 mA IOH = 200 A IOH = 200 A Drive capacity is IOL= 20 mA high Drive capacity is low IOL = 5 mA IOL = 200 A IOL = 200 A INT0 to INT4, KI0 to KI3, TRJIO_0, TRCCLK_0, TRCTRG_0, TRCIOA_0, TRCIOB_0, TRCIOC_0, TRCIOD_0, CLK_0, CLK_1, RXD_0, RXD_1, CTS2, SCL2, SDA2, CLK2, RXD2, SCL_0, SDA_0, SSI_0, SCS_0, SSCK_0, SSO_0 RESET Input high current Input low current Pull-up resistance Feedback XIN resistance Feedback XCIN resistance RAM hold voltage R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 During stop mode Unit V Page 46 of 60 R8C/38T-A Group Table 4.15 4. Electrical Characteristics DC Characteristics (2) [3.3 V Vcc 5.5 V] (Topr = 20°C to 85°C (N version)/40°C to 85°C (D version), unless otherwise specified) Standard (4) Conditions Symbol ICC Oscillation Power supply current (1) On-Chip Oscillator XIN (2) XCIN HighSpeed LowSpeed CPU Clock Low-PowerConsumption Setting 20 MHz Off Off 125 kHz No division ― ― 6.5 15 mA 16 MHz Off Off 125 kHz No division ― ― 5.3 12.5 mA 10 MHz Off Off 125 kHz No division ― ― 3.6 ― mA 20 MHz Off Off 125 kHz Divide-by-8 ― ― 3.0 ― mA 16 MHz Off Off 125 kHz Divide-by-8 ― ― 2.2 ― mA 10 MHz Off Off 125 kHz Divide-by-8 ― ― 1.5 ― mA Off Off 20 MHz (3) 125 kHz No division ― ― 7.0 15 mA Off Off 20 MHz (3) 125 kHz Divide-by-8 ― ― 3.0 ― mA Off Off 4 MHz (3) 125 kHz Divide-by-16 MSTIIC = 1 MSTTRC = 1 ― 1 ― mA Lowspeed onchip oscillator mode Off Off Off 125 kHz Divide-by-8 FMR27 = 1 SVC0 = 0 ― 90 400 μA Lowspeed clock mode Off 32 kHz Off Off ― FMR27 = 1 SVC0 = 0 ― 85 400 μA Off 32 kHz Off Off ― FMSTP = 1 SVC0 = 0 Program operation on RAM Flash memory off ― 47 ― μA Off Off Off 125 kHz ― VCA27 = 0 VCA26 = 0 VCA25 = 0 SVC0 = 1 While a WAIT instruction is executed Peripheral clock operation ― 15 100 μA Off Off Off 125 kHz ― VCA27 = 0 VCA26 = 0 VCA25 = 0 SVC0 = 1 While a WAIT instruction is executed Peripheral clock off ― 4 90 μA Off 32 kHz Off Off ― VCA27 = 0 VCA26 = 0 VCA25 = 0 SVC0 = 1 While a WAIT instruction is executed Peripheral clock off ― 3.5 ― μA Off Off Off Off ― VCA27 = 0 VCA26 = 0 VCA25 = 0 CM10 = 1 Topr = 25°C Peripheral clock off ― 2.2 6.0 μA Off Off Off Off ― VCA27 = 0 VCA26 = 0 VCA25 = 0 CM10 = 1 Topr = 85°C Peripheral clock off ― 30 ― μA Parameter Highspeed clock mode Highspeed onchip oscillator mode Wait mode Stop mode Other Min. Typ. Max. Unit Notes: 1. Vcc = 3.3 V to 5.5 V, single-chip mode, output pins are open, and other pins are Vss. 2. XIN is set to square wave input. 3. fHOCO-F 4. The typical value (Typ.) indicates the current value when the CPU and the memory operate. The maximum value (Max.) indicates the current value when the CPU, the memory, and the peripheral functions operate and the flash memory is programmed/erased. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 47 of 60 R8C/38T-A Group Table 4.16 4. Electrical Characteristics DC Characteristics (3) [2.7 V Vcc 4.2 V] (Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/ 40°C to 85°C (D version)) Symbol VOH VOL Output high Other than XOUT voltage Output low voltage XOUT Other than XOUT XOUT VT+-VT- IIH IIL RPULLUP RfXIN RfXCIN VRAM Standard Min. Typ. Vcc 0.5 ― Max. Vcc Vcc 0.5 1.0 ― — — ― Vcc Vcc 0.5 V V V — — 0.1 — — 0.4 0.5 0.5 ― V V V Vcc = 3.0 V 0.1 0.5 ― V VI = 3.0 V VI = 0 V VI = 0 V ― ― 42 ― ― ― 84 0.3 1.0 1.0 168 ― μA μA kΩ MΩ ― 8 ― MΩ 1.8 ― ― V Parameter Hysteresis Conditions Drive capacity is IOH = 5 mA high Drive capacity is low IOH = 1 mA IOH = 200 A Drive capacity is IOL = 5 mA high Drive capacity is low IOL = 1 mA IOL = 200 A INT0 to INT4, KI0 to KI3, TRJIO_0, TRCCLK_0, TRCTRG_0, TRCIOA_0, TRCIOB_0, TRCIOC_0, TRCIOD_0, CLK_0, CLK_1, RXD_0, RXD_1, CTS2, SCL2, SDA2, CLK2, RXD2, SCL_0, SDA_0, SSI_0, SCS_0, SSCK_0, SSO_0 RESET Input high current Input low current Pull-up resistance Feedback XIN resistance Feedback XCIN resistance RAM hold voltage R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 During stop mode Unit V Page 48 of 60 R8C/38T-A Group Table 4.17 4. Electrical Characteristics DC Characteristics (4) [2.7 V Vcc 3.3 V] (Topr = 20°C to 85°C (N version)/40°C to 85°C (D version), unless otherwise specified)) Standard (4) Conditions Symbol ICC Oscillation Parameter Power supply current (1) Highspeed clock mode On-Chip Oscillator CPU Clock Low-PowerConsumption Setting 125 kHz No division ― ― 3.5 10 mA 125 kHz Divide-by-8 ― ― 1.5 7.5 mA XIN (2) XCIN HighSpeed LowSpeed 10 MHz Off Off 10 MHz Off Off Other Min. Typ. Max. Unit Off Off 20 MHz (3) 125 kHz No division ― ― 7.0 15 mA Off Off 20 MHz (3) 125 kHz Divide-by-8 ― ― 3.0 ― mA Off Off 10 MHz (3) 125 kHz No division ― ― 4.0 ― mA Off Off 10 MHz (3) 125 kHz Divide-by-8 ― ― 1.5 ― mA Off Off 4 MHz (3) 125 kHz Divide-by-16 MSTIIC = 1 MSTTRC = 1 ― 1 ― mA Lowspeed onchip oscillator mode Off Off Off 125 kHz Divide-by-8 FMR27 = 1 SVC0 = 0 ― 90 390 μA Lowspeed clock mode Off 32 kHz Off Off No division FMR27 = 1 SVC0 = 0 ― 80 400 μA Off 32 kHz Off Off No division FMSTP = 1 SVC0 = 0 Program operation on RAM Flash memory off ― 40 ― μA Wait mode Off Off Off 125 kHz ― VCA27 = 0 VCA26 = 0 VCA25 = 0 SVC0 = 1 While a WAIT instruction is executed Peripheral clock operation ― 15 90 μA Off Off Off 125 kHz ― VCA27 = 0 VCA26 = 0 VCA25 = 0 SVC0 = 1 While a WAIT instruction is executed Peripheral clock off ― 4 80 μA Off 32 kHz Off Off ― VCA27 = 0 VCA26 = 0 VCA25 = 0 SVC0 = 1 While a WAIT instruction is executed Peripheral clock off ― 3.5 ― μA Off Off Off Off ― VCA27 = 0 VCA26 = 0 VCA25 = 0 CM10 = 1 Topr = 25°C Peripheral clock off ― 2.2 6.0 μA Off Off Off Off ― VCA27 = 0 VCA26 = 0 VCA25 = 0 CM10 = 1 Topr = 85°C Peripheral clock off ― 30 ― μA Highspeed onchip oscillator mode Stop mode Notes: 1. Vcc = 2.7 V to 3.3 V, single-chip mode, output pins are open, and other pins are Vss. 2. XIN is set to square wave input. 3. fHOCO-F 4. The typical value (Typ.) indicates the current value when the CPU and the memory operate. The maximum value (Max.) indicates the current value when the CPU, the memory, and the peripheral functions operate and the flash memory is programmed/erased. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 49 of 60 R8C/38T-A Group Table 4.18 4. Electrical Characteristics DC Characteristics (5) [1.8 V Vcc 2.7 V] (Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/ 40°C to 85°C (D version)) Symbol VOH VOL Output high Other than XOUT voltage Output low voltage XOUT Other than XOUT XOUT VT+-VT- IIH IIL RPULLUP RfXIN RfXCIN VRAM Standard Min. Typ. Vcc 0.5 ― Max. Vcc Vcc 0.5 1.0 ― — — ― Vcc Vcc 0.5 V V V — — 0.05 — — 0.2 0.5 0.5 ― V V V VCC = 2.2 V 0.05 0.2 ― V VI = 2.2 V VI = 0 V VI = 0 V ― ― 100 ― ― ― 200 0.3 1.0 1.0 400 ― μA μA kΩ MΩ ― 8 ― MΩ 1.8 ― ― V Parameter Hysteresis Conditions Drive capacity is IOH = 2 mA high Drive capacity is low IOH = 1 mA IOH = 200 A Drive capacity is IOL = 2 mA high Drive capacity is low IOL = 1 mA IOL = 200 A INT0 to INT4, KI0 to KI3, TRJIO_0, TRCCLK_0, TRCTRG_0, TRCIOA_0, TRCIOB_0, TRCIOC_0, TRCIOD_0, CLK_0, CLK_1, RXD_0, RXD_1,CTS2, SCL2, SDA2, CLK2, RXD2, SCL_0, SDA_0,SSI_0, SCS_0, SSCK_0,SSO_0 RESET Input high current Input low current Pull-up resistance Feedback XIN resistance Feedback XCIN resistance RAM hold voltage R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 During stop mode Unit V Page 50 of 60 R8C/38T-A Group Table 4.19 4. Electrical Characteristics DC Characteristics (6) [1.8 V Vcc 2.7 V] (Topr = 20°C to 85°C (N version)/40°C to 85°C (D version), unless otherwise specified) Standard (4) Conditions Symbol Oscillation Parameter XIN (2) ICC Power supply current (1) Highspeed clock mode XCIN On-Chip Oscillator HighSpeed LowSpeed CPU Clock Low-PowerConsumption Setting Other Min. Typ. Max. Unit 5 MHz Off Off 125 kHz No division ― ― 2.2 ― mA 5 MHz Off Off 125 kHz Divide-by-8 ― ― 0.8 ― mA mA Off Off 5 MHz (3) 125 kHz No division ― ― 2.5 10 Off Off 5 MHz (3) 125 kHz Divide-by-8 ― ― 1.7 ― mA Off Off 4 MHz (3) 125 kHz Divide-by-16 MSTIIC = 1 MSTTRC = 1 ― 1 ― mA Lowspeed onchip oscillator mode Off Off Off 125 kHz Divide-by-8 FMR27 = 1 SVC0 = 0 ― 90 300 μA Lowspeed clock mode Off 32 kHz Off Off No division FMR27 = 1 SVC0 = 0 ― 80 350 μA Wait mode Off Off Off 125 kHz ― VCA27 = 0 VCA26 = 0 VCA25 = 0 SVC0 = 1 While a WAIT instruction is executed Peripheral clock operation ― 15 90 μA Off Off Off 125 kHz ― VCA27 = 0 VCA26 = 0 VCA25 = 0 SVC0 = 1 While a WAIT instruction is executed Peripheral clock off ― 4 80 μA Off 32 kHz Off Off ― VCA27 = 0 VCA26 = 0 VCA25 = 0 SVC0 = 1 While a WAIT instruction is executed Peripheral clock off ― 3.5 ― μA Off Off Off Off ― VCA27 = 0 VCA26 = 0 VCA25 = 0 CM10 = 1 Topr = 25°C Peripheral clock off ― 2.2 6 μA Off Off Off Off ― VCA27 = 0 VCA26 = 0 VCA25 = 0 CM10 = 1 Topr = 85°C Peripheral clock off ― 30 ― μA Highspeed onchip oscillator mode Stop mode Notes: 1. Vcc = 1.8 V to 2.7 V, single-chip mode, output pins are open, and other pins are Vss. 2. XIN is set to square wave input. 3. fHOCO-F 4. The typical value (Typ.) indicates the current value when the CPU and the memory operate. The maximum value (Max.) indicates the current value when the CPU, the memory, and the peripheral functions operate and the flash memory is programmed/erased. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 51 of 60 R8C/38T-A Group 4.5 4. Electrical Characteristics AC Characteristics Table 4.20 Timing Requirements of Clock Synchronous Serial I/O with Chip Select (during Master Operation) (Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/ 40°C to 85°C (D version)) Symbol Parameter Conditions Standard Typ. ― tSUCYC SSCK clock cycle time tHI tLO tRISE SSCK clock high width SSCK clock low width SSCK clock rising time 2.7 V Vcc 5.5 V 0.40 0.40 ― ― ― ― 0.60 0.60 0.50 tCYC (1) 1.8 V Vcc 2.7 V ― ― 1.00 tCYC (1) 2.7 V Vcc 5.5 V ― ― 0.50 tCYC (1) 1.8 V Vcc 2.7 V ― ― 1.00 4.5 V Vcc 5.5 V 2.7 V Vcc 4.5 V 1.8 V Vcc 2.7 V 2.7 V Vcc 5.5 V 60 70 100 2.00 ― ― ― ― ― ― ― ― tCYC (1) ns ns ns 1.8 V Vcc 2.7 V 2.00 ― ― ― ― tCYC (1) ns tFALL SSCK clock falling time tSU SSI, SSO data input setup time tH SSI, SSO data input hold time Max. ― Unit Min. 4.00 tCYC (1) tSUCYC tSUCYC tCYC (1) tLEAD SCS-SCK output delay time 0.5 tSUCYC - 1 tCYC tLAG SCK -SCS output valid time SSO data output delay time 0.5 tSUCYC - 1 tCYC ― ― ns ― ― ― ― 30.00 1.00 tCYC (1) tOD 2.7 V Vcc 5.5 V 1.8 V Vcc 2.7 V ns Note: 1. 1tCYC = 1/f1 (s) R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 52 of 60 R8C/38T-A Group Table 4.21 4. Electrical Characteristics Timing Requirements of Clock Synchronous Serial I/O with Chip Select (during Slave Operation) (Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/ 40°C to 85°C (D version)) Symbol Parameter Conditions Standard Typ. ― Unit tSUCYC SSCK clock cycle time Min. 4.00 tHI tLO tRISE tFALL tSU tH SSCK clock high width SSCK clock low width SSCK clock rising time SSCK clock falling time SSO data input setup time SSO data input hold time 0.40 0.40 ― ― 10.00 2.00 ― ― ― ― ― ― 0.60 0.60 1.00 1.00 ― ― tLEAD SCS setup time 1tCYC + 50 ― ― tCYC (1) ns ― ― ns tOD SCS hold time SSI, SSO data output delay time 1tCYC + 50 tSA SSI slave access time tOR SSI slave out open time ― ― ― ― ― ― ― ― ― ― ― ― ― ― 60 70 100.00 1.5tCYC + 100 1.5tCYC + 200 1.5tCYC + 100 1.5tCYC + 200 ns ns ns ns ns ns ns tLAG 4.5 V Vcc 5.5 V 2.7 V Vcc 4.5 V 1.8 V Vcc 2.7 V 2.7 V Vcc 5.5 V 1.8 V Vcc 2.7 V 2.7 V Vcc 5.5 V 1.8 V Vcc 2.7 V Max. ― tCYC (1) tSUCYC tSUCYC μs μs ns Note: 1. 1tCYC = 1/f1 (s) R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 53 of 60 R8C/38T-A Group 4. Electrical Characteristics 4-Wire Bus Communication Mode, Master, CPHS = 1 VIH or VOH SCS (output) VIL or VOL tHI tFALL tRISE SSCK (output) (CPOS = 1) tLO tHI SSCK (output) (CPOS = 0) tLO tSUCYC SSO (output) tOD SSI (input) tSU tH 4-Wire Bus Communication Mode, Master, CPHS = 0 VIH or VOH SCS (output) VIL or VOL tLEAD tLAG tHI tFALL tRISE SSCK (output) (CPOS = 1) tLO tHI SSCK (output) (CPOS = 0) tLO tSUCYC SSO (output) tOD SSI (input) tSU tH CPHS, CPOS: Bits in SIMR1 register Figure 4.4 I/O Timing of Synchronous Serial Communication Unit (SSU) (Master) R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 54 of 60 R8C/38T-A Group 4. Electrical Characteristics 4-Wire Bus Communication Mode, Slave, CPHS = 1 VIH or VOH SCS (input) VIL or VOL tLEAD tHI tFALL tRISE tLAG SSCK (input) (CPOS = 1) tLO tHI SSCK (input) (CPOS = 0) tLO tSUCYC SSO (input) tSU tH SSI (output) tSA tOD tOR 4-Wire Bus Communication Mode, Slave, CPHS = 0 VIH or VOH SCS (input) VIL or VOL tLEAD tHI tFALL tRISE tLAG SSCK (input) (CPOS = 1) tLO tHI SSCK (input) (CPOS = 0) tLO tSUCYC SSO (input) tSU tH SSI (output) tSA tOD tOR CPHS, CPOS: Bits in SIMR1 register Figure 4.5 I/O Timing of Synchronous Serial Communication Unit (SSU) (Slave) R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 55 of 60 R8C/38T-A Group 4. Electrical Characteristics tHI VIH or VOH SSCK VIL or VOL tLO tSUCYC SSO (output) tOD SSI (input) tSU Figure 4.6 tH I/O Timing of Synchronous Serial Communication Unit (SSU) (Clock Synchronous Communication Mode) R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 56 of 60 R8C/38T-A Group Table 4.22 Symbol tc(XOUT) tWH(XOUT) tWL(XOUT) tc(XCIN) tWH(XCIN) tWL(XCIN) 4. Electrical Characteristics External Clock Input (XOUT, XCIN) Parameter XOUT input cycle time XOUT input high width XOUT input low width XCIN input cycle time XCIN input high width XCIN input low width Vcc = 2.2 V, Topr = 25°C Min. Max. 200 ― 90 ― 90 ― 14 ― 7 ― 7 ― Standard Vcc = 3 V, Topr = 25°C Min. Max. 50 ― 24 ― 24 ― 14 ― 7 ― 7 ― Vcc = 5 V, Topr = 25°C Min. Max. 50 ― 24 ― 24 ― 14 ― 7 ― 7 ― Unit Vcc = 5 V, Topr = 25°C Min. Max. 100 ― 40 ― 40 ― Unit ns ns ns μs μs μs tC(XOUT), tC(XCIN) tWH(XOUT), tWH(XCIN) External Clock Input tWL(XOUT), tWL(XCIN) Figure 4.7 External Clock Input Timing Diagram Table 4.23 Symbol tc(TRJIO) tWH(TRJIO) tWL(TRJIO) Timing Requirements of TRJIO Parameter TRJIO input cycle time TRJIO input high width TRJIO input low width Vcc = 2.2 V, Topr = 25°C Min. Max. 500 ― 200 ― 200 ― Standard Vcc = 3 V, Topr = 25°C Min. Max. 300 ― 120 ― 120 ― ns ns ns tC(TRJIO) tWH(TRJIO) TRJIO input tWL(TRJIO) Figure 4.8 Input Timing of TRJIO R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 57 of 60 R8C/38T-A Group Table 4.24 Symbol 4. Electrical Characteristics Timing Requirements of Serial Interface (Internal clock selected as transfer clock (master communication)) Parameter td(C-Q) TXDi output delay time tsu(D-C) RXDi input setup time (1) RXDi input hold time th(C-D) Vcc = 2.2 V, Topr = 25°C Min. Max. ― 150 90 Standard Vcc = 3 V, Topr = 25°C Min. Max. ― 120 90 200 ― ― 30 ― ― Vcc = 5 V, Topr = 25°C Min. Max. ― 90 90 10 ― ― Unit ns ns ns i = 0 or 1 Note: 1. External pin load condition CL = 30 pF Table 4.25 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) tsu(D-C) th(C-D) Timing Requirements of Serial Interface (External clock selected as transfer clock (slave communication)) Parameter Vcc = 2.2 V, Topr = 25°C Min. Max. 800 ― 400 ― 400 ― ― 200 150 ― 90 ― CLKi input cycle time CLKi input high width CLKi input low width TXDi output delay time RXDi input setup time RXDi input hold time Standard Vcc = 3 V, Topr = 25°C Min. Max. 300 ― 150 ― 150 ― ― 120 30 ― 90 ― Vcc = 5 V, Topr = 25°C Min. Max. 200 ― 100 ― 100 ― ― 90 10 ― 90 ― Unit ns ns ns ns ns ns i = 0 or 1 tC(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi Figure 4.9 Input and Output Timing of Serial Interface (i = 0 or 1) R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 58 of 60 R8C/38T-A Group Table 4.26 4. Electrical Characteristics Timing Requirements of External Interrupt INTi (i = 0 to 4) and Key Input Interrupt KIj (j = 0 to 3) Standard Symbol Parameter Vcc = 2.2 V, Topr = 25°C Vcc = 3 V, Topr = 25°C Vcc = 5 V, Topr = 25°C Min. Max. Min. Max. Min. Max. Unit tW(INH) INTi input high width, KIj input high width 1000 (1) ― 380 (1) ― 250 (1) ― ns tW(INL) INTi input low width, KIj input low width 1000 (2) ― 380 (2) ― 250 (2) ― ns Notes: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input high pulse width of either (1/digital filter sampling frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input low pulse width of either (1/digital filter sampling frequency × 3) or the minimum value of standard, whichever is greater. tW(INL) INTi input KIj input Figure 4.10 tW(INH) Input Timing of External Interrupt INTi and Key Input Interrupt KIj (i = 0 to 4; j = 0 to 3) R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Page 59 of 60 R8C/38T-A Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Electronics website. JEITA Package Code P-LQFP80-12x12-0.50 RENESAS Code PLQP0080KB-A Previous Code 80P6Q-A MASS[Typ.] 0.5g HD *1 D 60 41 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 40 61 bp E c *2 HE c1 b1 Reference Dimension in Millimeters Symbol ZE Terminal cross section 80 21 1 20 ZD Index mark F bp c A *3 A1 y S e A2 S L x L1 Detail F R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Min Nom Max 11.9 12.0 12.1 11.9 12.0 12.1 1.4 13.8 14.0 14.2 13.8 14.0 14.2 1.7 0.1 0.2 0 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 10° 0.5 0.08 0.08 1.25 1.25 0.3 0.5 0.7 1.0 Page 60 of 60 REVISION HISTORY Rev. Date R8C/38T-A Group User’s Manual: Datasheet Description Page 0.01 Feb 23, 2011 — 1.00 Dec 09, 2011 All pages 2, 3 Summary First Edition issued “Preliminary”, “Under development” deleted, “sensor control unit” “touch sensor control unit” Tables 1.1 and 1.2 revised 6 Figure 1.3 revised 16 2.1 revised 19, 20, 22 to 25, 27 to31 35 36 to 59 Tables 3.1, 3.2, 3.4 to 3.7, 3.9 to 3.13 Table 3.17 revised, Note 2 added “4. Electrical Characteristics” added All trademarks and registered trademarks are the property of their respective owners. C-1 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. 4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. 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Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. 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Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. 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