RENESAS R5F6411EDFP

R32C/111 Group Datasheet
R32C/111 Group
RENESAS MCU
1.
REJ03B0227-0110
Rev.1.10
Sep 17, 2009
Overview
1.1
Features
The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM
code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing
in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from
low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral
functions, provides support for a vast range of application fields.
The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory
space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture,
multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of onchip peripheral devices — UART, CRC, DMAC, A/D and D/A converters, timers, I2C, and WDT enables to
minimize external components.
The R32C/100 Series, in particular, provides the R32C/111 Group as a standard product. This product,
provided as 100-pin plastic molded LGA, and 100-/80-/64-pin plastic molded LQFP package, configures a
maximum of nine channels of serial interface.
1.1.1
Applications
Audio, cameras, television, home appliance, printer, meter, office/industrial equipment, communication/
portable devices
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 1 of 99
R32C/111 Group
1.1.2
1. Overview
Performance Overview
Table 1.1 to Table 1.6 show the performance overview of the R32C/111 Group.
Table 1.1
R32C/111 Group Performance for the 100-pin Package (1/2)
Unit
CPU
Function
Central
processing unit
Memory
Performance
R32C/100 Series CPU Core
• Basic instructions: 108
• Minimum instruction execution time: 20 ns (f(CPU) = 50 MHz)
• Multiplier: 32-bit × 32-bit 64-bit
• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit 64-bit
• IEEE-754 floating point standard: Single precision
• 32-bit barrel shifter
• Operating mode: Single-chip mode, memory expansion mode,
microprocessor mode (optional (1))
Flash memory: 256 to 512 Kbytes
RAM: 32 to 63 Kbytes
Data flash: 4 Kbytes × 2 blocks
Refer to Table 1.7 for memory size of each product group
Voltage
Detector
Low voltage
detector
Optional (1)
Low voltage detection interrupt
Clock
Clock generator
• 4 circuits (main clock, sub clock, PLL, on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/re-oscillation
detection
• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable
• Low power modes: Wait mode, stop mode
External Bus
Expansion
Bus and memory
expansion
• Address space: 4 Gbytes (of which up to 64 Mbytes is user
accessible)
• External bus Interface: Support for wait-state insertion, 4 chip select
outputs, 3V/5V interface
• Bus format: Separate bus/Multiplexed bus selectable, data bus width
selectable (8/16 bits)
Interrupts
Interrupt vectors: 261
External interrupt inputs: NMI, INT × 6, key input × 4
Interrupt priority levels: 7 levels
Watchdog Timer
15 bits × 1 (selectable input frequency from prescaler output)
DMA
DMAC
4 channels
• Cycle-steal transfer mode
• Request sources: 51
• 2 transfer modes: Single transfer, repeat transfer
DMAC II
• Can be activated by any peripheral interrupt source
• 3 transfer functions: Immediate data transfer, calculation transfer,
chained transfer
Programmable
I/O ports
• 2 input-only ports
• 82 CMOS inputs/outputs
• 2 N-channel open drain ports
• A pull-up resistor is selectable for every 4 input ports
I/O Ports
Note:
1. Please contact a Renesas sales office to use the optional feature.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 2 of 99
R32C/111 Group
Table 1.2
1. Overview
R32C/111 Group Performance for the 100-pin Package (2/2)
Unit
Timer
Serial
Interface
Function
Performance
Timer A
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (twophase encoder input) × 3
Timer B
16-bit timer × 6
Timer mode, event counter mode, pulse frequency measurement
mode, pulse-width measurement mode
Three-phase
motor control
timer
Three-phase motor control timer ×1 (timers A1, A2, A4, and B2 used)
8-bit programmable dead time timer
UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels
• I2C-bus (UART0 to UART6)
• Special mode 2 (UART0 to UART6)
• IEBus (1) (optional (2)) (UART0 to UART6)
A/D Converter
10-bit resolution × 26 channels
Sample and hold functionality integrated
D/A Converter
8-bit resolution × 2
CRC Calculator
CRC-CCITT (X16 + X12 + X5 + 1)
X-Y Converter
16 bits × 16 bits
Intelligent I/O
Time measurement (input capture): 16 bits × 16
Waveform generation (output compare): 16 bits × 19
Serial interface: Variable-length synchronous serial I/O mode, IEBus (1)
mode (optional (2))
Flash Memory
Programming and erasure supply voltage:
VCC1 = VCC2 = 3.0 to 5.5 V
Minimum endurance: 1,000 program/erase cycles
Security protection: ROM code protect, ID code protect
Debugging: On-chip debug, on-board flash programming
Operating Frequency/Supply
Voltage
50 MHz/VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 V to VCC1
Operating Temperature
-20°C to 85°C (version N)
-40°C to 85°C (version D)
Current Consumption
32 mA (VCC1 = VCC2 = 5.0 V, f(CPU) = 50 MHz)
8 µA (VCC1 = VCC2 = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)
Package
100-pin plastic molded LQFP (PLQP0100KB-A)
100-pin plastic molded TFLGA (PTLG0100KA-A)
Notes:
1. IEBus is a trademark of NEC Electronics Corporation.
2. Please contact a Renesas sales office to use the optional feature.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 3 of 99
R32C/111 Group
Table 1.3
1. Overview
R32C/111 Group Performance for the 80-pin Package (1/2)
Unit
CPU
Function
Central
processing unit
Memory
Performance
R32C/100 Series CPU Core
• Basic instructions: 108
• Minimum instruction execution time: 20 ns (f(CPU) = 50 MHz)
• Multiplier: 32-bit × 32-bit 64-bit
• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit 64-bit
• IEEE-754 floating point standard: Single precision
• 32-bit barrel shifter
• Operating mode: Single-chip mode, memory expansion mode,
microprocessor mode (optional (1))
Flash memory: 128/256 Kbytes
RAM: 32 Kbytes
Data flash: 4 Kbytes × 2 blocks
Refer to Table 1.7 for memory size of each product group
Voltage
Detector
Low voltage
detector
Optional (1)
Low voltage detection interrupt
Clock
Clock generator
• 4 circuits (main clock, sub clock, PLL, on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/re-oscillation
detection
• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable
• Low power modes: Wait mode, stop mode
Interrupts
Interrupt vectors: 261
External interrupt inputs: NMI, INT × 6, key input × 4
Interrupt priority levels: 7 levels
Watchdog Timer
15 bits × 1 (selectable input frequency from prescaler output)
DMA
DMAC
4 channels
• Cycle-steal transfer mode
• Request sources: 47
• 2 transfer modes: Single transfer, repeat transfer
DMAC II
• Can be activated by any peripheral interrupt source
• 3 transfer functions: Immediate data transfer, calculation transfer,
chained transfer
Programmable
I/O ports
• 1 input-only port
• 65 CMOS inputs/outputs
• 2 N-channel open drain ports
• A pull-up resistor is selectable for every 4 input ports
I/O Ports
Note:
1. Please contact a Renesas sales office to use the optional feature.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 4 of 99
R32C/111 Group
Table 1.4
1. Overview
R32C/111 Group Performance for the 80-pin Package (2/2)
Unit
Timer
Serial
Interface
Function
Performance
Timer A
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (twophase encoder input) × 3
Timer B
16-bit timer × 6 (1)
Timer mode, event counter mode, pulse frequency measurement
mode, pulse-width measurement mode
Three-phase
motor control
timer
Three-phase motor control timer ×1 (timers A1, A2, A4, and B2 used)
8-bit programmable dead time timer
UART0 to
UART5, UART8
Asynchronous/synchronous serial interface × 7 channels
• I2C-bus (UART0 to UART5)
• Special mode 2 (UART0 to UART3, UART5)
• IEBus (2) (optional (3)) (UART0 to UART5)
A/D Converter
10-bit resolution × 26 channels
Sample and hold functionality integrated
D/A Converter
8-bit resolution × 1
CRC Calculator
CRC-CCITT (X16 + X12 + X5 + 1)
X-Y Converter
16 bits × 16 bits
Intelligent I/O
Time measurement (input capture): 16 bits × 16
Waveform generation (output compare): 16 bits × 19
Serial interface: Variable-length synchronous serial I/O mode, IEBus (2)
mode (optional (3))
Flash Memory
Programming and erasure supply voltage: VCC1 = 3.0 to 5.5 V
Minimum endurance: 1,000 program/erase cycles
Security protection: ROM code protect, ID code protect
Debugging: On-chip debug, on-board flash programming
Operating Frequency/Supply
Voltage
50 MHz/VCC1 = 3.0 to 5.5 V
Operating Temperature
-20°C to 85°C (version N)
-40°C to 85°C (version D)
Current Consumption
32 mA (VCC1 = 5.0 V, f(CPU) = 50 MHz)
8 µA (VCC1 = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)
Package
80-pin plastic molded LQFP (PLQP0080KB-A)
Notes:
1. Timer B4 is available in timer mode only.
2. IEBus is a trademark of NEC Electronics Corporation.
3. Please contact a Renesas sales office to use the optional feature.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 5 of 99
R32C/111 Group
Table 1.5
1. Overview
R32C/111 Group Performance for the 64-pin Package (1/2)
Unit
CPU
Function
Central
processing unit
Memory
Performance
R32C/100 Series CPU Core
• Basic instructions: 108
• Minimum instruction execution time: 20 ns (f(CPU) = 50 MHz)
• Multiplier: 32-bit × 32-bit 64-bit
• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit 64-bit
• IEEE-754 floating point standard: Single precision
• 32-bit barrel shifter
• Operating mode: Single-chip mode, memory expansion mode,
microprocessor mode (optional (1))
Flash memory: 128/256 Kbytes
RAM: 32 Kbytes
Data flash: 4 Kbytes × 2 blocks
Refer to Table 1.7 for memory size of each product group
Voltage
Detector
Low voltage
detector
Optional (1)
Low voltage detection interrupt
Clock
Clock generator
• 4 circuits (main clock, sub clock, PLL, on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/re-oscillation
detection
• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable
• Low power modes: Wait mode, stop mode
Interrupts
Interrupt vectors: 261
External interrupt inputs: NMI, INT × 6, key input × 4
Interrupt priority levels: 7 levels
Watchdog Timer
15 bits × 1 (selectable input frequency from prescaler output)
DMA
DMAC
4 channels
• Cycle-steal transfer mode
• Request sources: 45
• 2 transfer modes: Single transfer, repeat transfer
DMAC II
• Can be activated by any peripheral interrupt source
• 3 transfer functions: Immediate data transfer, calculation transfer,
chained transfer
Programmable
I/O ports
• 1 input-only port
• 49 CMOS inputs/outputs
• 2 N-channel open drain ports
• A pull-up resistor is selectable for every 4 input ports
I/O Ports
Note:
1. Please contact a Renesas sales office to use the optional feature.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 6 of 99
R32C/111 Group
Table 1.6
1. Overview
R32C/111 Group Performance for the 64-pin Package (2/2)
Unit
Timer
Serial
Interface
Function
Performance
Timer A
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (twophase encoder input) × 3
Timer B
16-bit timer × 6 (1)
Timer mode, event counter mode, pulse frequency measurement
mode, pulse-width measurement mode
Three-phase
motor control
timer
Three-phase motor control timer ×1 (timers A1, A2, A4, and B2 used)
8-bit programmable dead time timer
UART0 to
UART3, UART5,
UART8
Asynchronous/synchronous serial interface × 6 channels
• I2C-bus (UART0 to UART3, UART5)
• Special mode 2 (UART0 to UART3, UART5)
• IEBus (2) (optional (3)) (UART0 to UART3, UART5)
A/D Converter
10-bit resolution × 20 channels
Sample and hold functionality integrated
D/A Converter
8-bit resolution × 1
CRC Calculator
CRC-CCITT (X16 + X12 + X5 + 1)
X-Y Converter
16 bits × 16 bits
Intelligent I/O
Time measurement (input capture): 16 bits × 16
Waveform generation (output compare): 16 bits × 19
Serial interface: Variable-length synchronous serial I/O mode, IEBus (2)
mode (optional (3))
Flash Memory
Programming and erasure supply voltage: VCC1 = 3.0 to 5.5 V
Minimum endurance: 1,000 program/erase cycles
Security protection: ROM code protect, ID code protect
Debugging: On-chip debug, on-board flash programming
Operating Frequency/Supply
Voltage
50 MHz/VCC1 = 3.0 to 5.5 V
Operating Temperature
-20°C to 85°C (version N)
-40°C to 85°C (version D)
Current Consumption
32 mA (VCC1 = 5.0 V, f(CPU) = 50 MHz)
8 µA (VCC1 = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)
Package
64-pin plastic molded LQFP (PLQP0080KB-A)
Notes:
1. Timer B4 is available in timer mode only.
2. IEBus is a trademark of NEC Electronics Corporation.
3. Please contact a Renesas sales office to use the optional feature.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 7 of 99
R32C/111 Group
1.2
1. Overview
Product Information
Table 1.7 lists the product information and Figure 1.1 shows the details of the part number.
Table 1.7
R32C/111 Group Product List
Package Code (1) ROM Capacity (2) RAM Capacity
Part Number
R5F64110NFB
(P)
(P)
384 Kbytes
+8 Kbytes
R5F64111DFB
R5F64112NFB
(P)
R5F64112DFB
R5F64114NFB
(P)
R5F64115NFB
(P)
384 Kbytes
+8 Kbytes
(P)
R5F64112NLG
R5F64112DLG
(P)
(P)
R5F6411ENFP
(P)
R5F6411EDFP
(P)
R5F6411FNFP
(P)
R5F6411FDFP
(P)
R5F6411ENFN
(P)
R5F6411EDFN
(D)
R5F6411FNFN
(P)
-40°C to 85°C (version D)
40 Kbytes
PTLG0100KA-A
-20°C to 85°C (version N)
32 Kbytes
-20°C to 85°C (version N)
-40°C to 85°C (version D)
-40°C to 85°C (version D)
256 Kbytes
+8 Kbyts
-20°C to 85°C (version N)
128 Kbytes
+8 Kbyts
-20°C to 85°C (version N)
-40°C to 85°C (version D)
32 Kbytes
256 Kbytes
+8 Kbyts
(D): Under development (P): On planning phase
Notes:
1. The old package codes are as follows:
PLQP0100KB-A: 100P6Q-A
PTLG0100KA-A: 100F0M
PLQP0080KB-A: 80P6Q-A
PLQP0064KB-A: 64P6Q-A
2. Data flash memory provides an additional 8 Kbytes of ROM capacity.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 8 of 99
-20°C to 85°C (version N)
-20°C to 85°C (version N)
32 Kbytes
PLQP064KB-A
R5F6411FDFN
-40°C to 85°C (version D)
-40°C to 85°C (version D)
128 Kbytes
+8 Kbyts
PLQP080KB-A
-40°C to 85°C (version D)
-40°C to 85°C (version D)
512 Kbytes
+8 Kbytes
256 Kbytes
+8 Kbytes
-20°C to 85°C (version N)
-20°C to 85°C (version N)
63 Kbytes
R5F6411FNLG
R5F6411FDLG
-20°C to 85°C (version N)
384 Kbytes
+8 Kbytes
(P)
-40°C to 85°C (version D)
-40°C to 85°C (version D)
512 Kbytes
+8 Kbytes
R5F64111NLG
-20°C to 85°C (version N)
-20°C to 85°C (version N)
256 Kbytes
+8 Kbytes
R5F64116DFB
R5F64111DLG
63 Kbytes
PLQP0100KB-A
R5F64115DFB
R5F64116NFB
-40°C to 85°C (version D)
512 Kbytes
+8 Kbytes
R5F64114DFB
Remarks
-20°C to 85°C (version N)
256 Kbytes
+8 Kbyts
R5F64110DFB
R5F64111NFB
As of September, 2009
-40°C to 85°C (version D)
-20°C to 85°C (version N)
-40°C to 85°C (version D)
R32C/111 Group
1. Overview
Part Number
R5 F 64 11 6 N XXX FB
Package Code
FB : PLQP0100KB-A
FP : PLQP0080KB-A
FN : PLQP0064KB-A
LG : PTLG0100KA-A
ROM Number
Omitted in the flash memory version
Temperature Code
N : -20°C to 85°C
D : -40°C to 85°C
ROM/RAM Capacity
0 : 256 KB/63 KB
1 : 384 KB/63 KB
2 : 512 KB/63 KB
4 : 256 KB/40 KB
5 : 384 KB/40 KB
6 : 512 KB/40 KB
E : 128 KB/32 KB
F : 256 KB/32 KB
R32C/111 Group
R32C/100 Series
Memory Type
F : Flash memory version
Figure 1.1
Part Numbering of Product
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 9 of 99
R32C/111 Group
1.3
1. Overview
Block Diagram
Figure 1.2 to Figure 1.4 show block diagram of the R32C/111 Group.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
16 bits × 5 timers
16 bits × 6 timers
Three-phase motor
controller
A/D converter:
Clock generator:
10 bits × 1 circuit
Standard: 10 inputs
Maximum: 26 inputs
4 circuits
- XIN-XOUT
- XCIN-XCOUT
- On-chip oscillator
- PLL frequency synthesizer
D/A converter:
8 bits × 2 channels
VCC1
DMAC
9 channels
Watchdog timer:
DMAC II
15 bits
X-Y converter:
CRC calculator (CCITT)
X16 + X12 + X5 + 1
ROM
Multiplier
Floating-point unit
Note:
1. IEBus is a trademark of NEC Electronics Corporation.
Figure 1.2
R32C/111 Group Block Diagram for the 100-pin Package
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 10 of 99
8
RAM
5
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT
Memory
Port P10
Time measurement: 16
Wave generation: 19
Serial interface:
- Variable-length
synchronous serial I/O
- IEBus (1)
R2R0
R2R0
R3R1
R3R1
R6R4
R6R4
R7R5
R7R5
A0
A0
A1
A1
A2
A2
A3
A3
FB
FB
SB
SB
Port P9
Intelligent I/O
R32C/100 Series CPU Core
P9_1
16 bits × 16 bits
P8_5
Serial interface:
7
Timer:
Timer A
Timer B
8
Peripheral functions
Port P8
VCC1
Port P7
VCC2
R32C/111 Group
1. Overview
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P6
Port P7
Timer:
16 bits × 5 timers
16 bits × 6 timers
Three-phase motor
controller
A/D converter:
Clock generator:
10 bits × 1 circuit
Standard: 10 inputs
Maximum: 26 inputs
4 circuits
- XIN-XOUT
- XCIN-XCOUT
- On-chip oscillator
- PLL frequency synthesizer
P8_5
D/A converter:
X-Y converter:
8 bits × 1 channel
DMAC
16 bits × 16 bits
7
Timer A
Timer B
Port P8
Peripheral functions
Watchdog timer:
Serial interface:
DMAC II
15 bits
7 channels
X +X +X +1
Intelligent I/O
Time measurement: 16
Wave generation: 19
Serial interface:
- Variable-length
synchronous serial I/O
- IEBus (1)
Memory
R32C/100 Series CPU Core
R2R0
R2R0
R3R1
R3R1
R6R4
R6R4
R7R5
R7R5
A0
A0
A1
A1
A2
A2
A3
A3
FB
FB
SB
SB
ROM
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT
RAM
Multiplier
Floating-point unit
Note:
1. IEBus is a trademark of NEC Electronics Corporation.
Figure 1.3
R32C/111 Group Block Diagram for the 80-pin Package
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 11 of 99
8
5
4
12
Port P10
16
Port P9
CRC calculator (CCITT)
R32C/111 Group
1. Overview
4
3
8
4
8
8
Port P0
Port P1
Port P2
Port P3
Port P6
Port P7
Timer:
16 bits × 5 timers
16 bits × 6 timers
Three-phase motor
controller
A/D converter:
Clock generator:
10 bits × 1 circuit
Standard: 8 inputs
Maximum: 20 inputs
4 circuits
- XIN-XOUT
- XCIN-XCOUT
- On-chip oscillator
- PLL frequency synthesizer
P8_5
D/A converter:
X-Y converter:
8 bits × 1 channel
DMAC
16 bits × 16 bits
7
Timer A
Timer B
Port P8
Peripheral functions
Watchdog timer:
Serial interface:
DMAC II
15 bits
6 channels
16
12
5
X +X +X +1
Intelligent I/O
ROM
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT
RAM
Multiplier
Floating-point unit
Note:
1. IEBus is a trademark of NEC Electronics Corporation.
Figure 1.4
R32C/111 Group Block Diagram for the 64-pin Package
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 12 of 99
8
R2R0
R2R0
R3R1
R3R1
R6R4
R6R4
R7R5
R7R5
A0
A0
A1
A1
A2
A2
A3
A3
FB
FB
SB
SB
Port P10
Time measurement: 16
Wave generation: 19
Serial interface:
- Variable-length
synchronous serial I/O
- IEBus (1)
Memory
R32C/100 Series CPU Core
P9_3
CRC calculator (CCITT)
R32C/111 Group
1.4
1. Overview
Pin Assignments
Figure 1.5 to Figure 1.8 show the pin assignments (top view) and Table 1.8 to Table 1.14 show the pin
characteristics.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
76
50
77
49
VCC2
78
48
79
47
80
46
81
45
82
44
83
43
84
42
R32C/111 GROUP
85
86
41
40
87
39
88
38
PLQP0100KB-A
(100P6Q-A)
(Top view)
89
90
91
92
93
37
36
35
34
33
94
32
95
31
96
30
97
29
98
28
VCC1
99
27
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
26
P4_2 / A18 / RXD3 / SCL3 / STXD3 / ISRXD2 / IEIN
P4_3 / A19 / TXD3 / SDA3 / SRXD3 / OUTC2_0 / ISTXD2 / IEOUT
P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6
P4_5 / CS2 / A21 / CLK6
P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6
P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6
P5_0 / WR0 / WR
P5_1 / WR1 / BC1
P5_2 / RD
R5_3 / CLKOUT / BCLK
P5_4 / HLDA / CS1 / TXD7
P5_5 / HOLD / CLK7
P5_6 / ALE / CS2 / RXD7
P5_7 / RDY / CS3 / CTS7 / RTS7
P6_0 / TB0IN / CTS0 / RTS0 / SS0
P6_1 / TB1IN / CLK0
P6_2 / TB2IN / RXD0 / SCL0 / STXD0
P6_3 / TXD0 / SDA0 / SRXD0
P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2
P6_5 / CLK1
P6_6 / RXD1 / SCL1 / STXD1
P6_7 / TXD1 / SDA1 / SRXD1
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT (Note 2)
P7_1 / TB5IN / TA0IN / RXD2 / SCL2 / STXD2 / IIO1_7 / OUTC2_2 / ISRXD2 / IEIN
(Note 2)
P7_2 / TA1OUT / V / CLK2
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P9_4
TB3IN / DA0 / P9_3
VDC0
P9_1
VDC1
NSD
CNVSS
XCIN / P8_7
XCOUT / P8_6
RESET
XOUT
VSS
XIN
VCC1
NMI / P8_5
INT2 / P8_4
INT1 / P8_3
INT0 / P8_2
UD0B / UD1B / IIO1_5 / RTS5 / CTS5 / SS5 / U / TA4IN / P8_1
UD0A / UD1A / RXD5 / SCL5 / STXD5 / U / TA4OUT / P8_0
UD0B / UD1B / IIO1_4 / CLK5 / TA3IN / P7_7
UD0A / UD1A / IIO1_3 / RTS8 / CTS8 / TXD5 / SDA5 / SRXD5 / TA3OUT / P7_6
IIO1_2 / RXD8 / W / TA2IN / P7_5
IIO1_1 / CLK8 / W / TA2OUT / P7_4
IIO1_0 / TXD8 / SS2 / RTS2 / CTS2 / V / TA1IN / P7_3
(Note 3)
2
100
1
IIO0_2 / IIO1_2 / D10 / P1_2
IIO0_1 / IIO1_1 / D9 / P1_1
IIO0_0 / IIO1_0 / D8 / P1_0
AN0_7 / D7 / P0_7
AN0_6 / D6 / P0_6
AN0_5 / D5 / P0_5
AN0_4 / D4 / P0_4
AN0_3 / D3 / P0_3
AN0_2 / D2 / P0_2
AN0_1 / D1 / P0_1
AN0_0 / D0 / P0_0
KI3 / AN_7 / P10_7
KI2 / AN_6 / P10_6
KI1 / AN_5 / P10_5
KI0 / AN_4 / P10_4
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AVSS
AN_0 / P10_0
VREF
AVCC
STXD4 / SCL4 / RXD4 / ADTRG / P9_7
SRXD4 / SDA4 / TXD4 / ANEX1 / P9_6
CLK4 / ANEX0 / P9_5
74
75
P1_3 / D11 / IIO0_3 / IIO1_3
P1_4 / D12 / IIO0_4 / IIO1_4
P1_5 / D13 / INT3 / IIO0_5 / IIO1_5
P1_6 / D14 / INT4 / IIO0_6 / IIO1_6
P1_7 / D15 / INT5 / IIO0_7 / IIO1_7
P2_0 / A0 / [A0/D0] / BC0 / [BC0/D0] / AN2_0
P2_1 / A1 / [A1/D1] / AN2_1
P2_2 / A2 / [A2/D2] / AN2_2
P2_3 / A3 / [A3/D3] / AN2_3
P2_4 / A4 / [A4/D4] / AN2_4
P2_5 / A5 / [A5/D5] / AN2_5
P2_6 / A6 / [A6/D6] / AN2_6
P2_7 / A7 / [A7/D7] / AN2_7
VSS
P3_0 / A8 / [A8/D8] / TA0OUT / UD0A / UD1A
VCC2
P3_1 / A9 / [A9/D9] / TA3OUT / UD0B / UD1B
P3_2 / A10 / [A10/D10] / TA1OUT / V
P3_3 / A11 / [A11/D11] / TA1IN / V
P3_4 / A12 / [A12/D12] / TA2OUT / W
P3_5 / A13 / [A13/D13] / TA2IN / W
P3_6 / A14 / [A14/D14] / TA4OUT / U
P3_7 / A15 / [A15/D15] / TA4IN / U
P4_0 / A16 / CTS3 / RTS3 / SS3
P4_1 / A17 / CLK3
(Note 1)
Notes:
1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.
2. Pins P7_0 and P7_1 are open drain outputs.
3. The position of pin number 1 varies by product. Refer to the index mark attached “Package Dimensions”.
Figure 1.5
Pin Assignment for the 100-pin Package (top view)
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 13 of 99
R32C/111 Group
1. Overview
R32C/111 GROUP
PTLG0100KA-A (100F0M)
(Top view)
VCC1
VCC2
10
9
8
7
6
5
4
3
2
1
K
P4_2
P4_3
P5_0
P5_1
P5_4
P6_0
P6_3
P6_6
P7_1
(Note 1)
P7_2
K
J
P4_1
P4_0
P4_6
P5_2
P5_5
P6_1
P6_4
P7_0
(Note 1)
P7_3
P7_4
J
H
P3_6
P3_7
P4_5
P5_3
P5_6
P6_2
P6_7
P7_5
P7_7
P8_0
H
G
P3_2
P3_3
P4_4
P4_7
P5_7
P6_5
P7_6
P8_3 /
INT1
P8_5 /
NMI
P8_2 /
INT0
G
F
P3_0
VCC2
P3_1
P3_4
P3_5
P8_4 /
INT2
P8_1
VSS
XIN
VCC1
F
E
P2_6
P2_7
VSS
P2_5
P1_6 /
INT4
P0_0
P9_3
P8_6 /
XCOUT
RESET
XOUT
E
D
P2_2
P2_1
P2_3
P2_4
P0_5
P10_7
P10_0
P9_1
CNVSS
P8_7 /
XCIN
D
C
P2_0
P1_7 /
INT5
P1_1
P1_0
P0_1
P10_3
AVSS
P9_7
VDC1
NSD
C
B
P1_4
P1_5 /
INT3
P0_6
P0_4
P0_2
P10_5
P10_2
AVCC
P9_6
VDC0
B
A
P1_3
P1_2
P0_7
P0_3
P10_6
P10_4
P10_1
VREF
P9_5
P9_4
A
10
9
8
7
6
5
4
3
2
1
VCC2
VCC1
Notes:
1. P7_0 and P7_1 as output are open drain outputs.
2. The pin position A1 varies by product. Refer to the index mark attached
“Package Dimensions”.
Figure 1.6
Pin Assignment for the 100-pin LGA Package (top view)
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 14 of 99
(Note 2)
R32C/111 Group
Table 1.8
1. Overview
Pin Characteristics for the 100-pin Package (1/3)
Pin No.
Control
Pin
QFP LGA
Port
Interrupt
Pin
Timer Pin
1
A1
P9_4
TB4IN
2
E4
P9_3
TB3IN
3
B1
4
D3
5
C2
VDC1
6
C1
NSD
7
D2
CNVSS
8
D1
XCIN
9
E3
XCOUT P8_6
10
E2
RESET
11
E1
XOUT
12
F3
VSS
13
F2
XIN
14
F1
VCC1
15
G2
UART Pin
Intelligent I/O Pin
CTS4/RTS4/SS4
Analog
Pin
Bus Control
Pin
DA1
DA0
VDC0
P9_1
P8_7
P8_5
NMI
16
F5
P8_4
INT2
17
G3
P8_3
INT1
18
G1
P8_2
INT0
19
F4
P8_1
20
H1
P8_0
TA4OUT/U RXD5/SCL5/STXD5 UD0A/UD1A
21
H2
P7_7
TA3IN
CLK5
22
G4
P7_6
TA3OUT
TXD5/SDA5/
IIO1_3/UD0A/UD1A
SRXD5/CTS8/RTS8
23
H3
P7_5
TA2IN/W
RXD8
IIO1_2
24
J1
P7_4
TA2OUT/W CLK8
IIO1_1
25
J2
P7_3
TA1IN/V
26
K1
P7_2
TA1OUT/V CLK2
27
K2
P7_1
TB5IN/
TA0IN
RXD2/SCL2/STXD2 IIO1_7/OUTC2_2/
ISRXD2/IEIN
28
J3
P7_0
TA0OUT
TXD2/SDA2/SRXD2 IIO1_6/OUTC2_0/
ISTXD2/IEOUT
29
H4
P6_7
TXD1/SDA1/SRXD1
30
K3
P6_6
RXD1/SCL1/STXD1
31
G5
P6_5
CLK1
TA4IN/U
CTS5/RTS5/SS5
CTS2/RTS2/SS2/
TXD8
32
J4
P6_4
CTS1/RTS1/SS1
33
K4
P6_3
TXD0/SDA0/SRXD0
34
H5
P6_2
TB2IN
RXD0/SCL0/STXD0
35
J5
P6_1
TB1IN
CLK0
TB0IN
IIO1_5/UD0B/UD1B
IIO1_4/UD0B/UD1B
IIO1_0
OUTC2_1/ISCLK2
CTS0/RTS0/SS0
36
K5
P6_0
37
G6
P5_7
CTS7/RTS7
RDY/CS3
38
H6
P5_6
RXD7
ALE/CS2
39
J6
P5_5
CLK7
HOLD
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 15 of 99
R32C/111 Group
Table 1.9
1. Overview
Pin Characteristics for the 100-pin Package (2/3)
Pin No.
Control
Pin
QFP LGA
Port
Interrupt
Pin
Timer Pin
UART Pin
Intelligent I/O Pin
Analog
Pin
Bus Control
Pin
HLDA/CS1
40
K6
P5_4
TXD7
41
H7
P5_3
CLKOUT/
BCLK
42
J7
P5_2
RD
43
K7
P5_1
WR1/BC1
44
K8
P5_0
WR0/WR
45
G7
P4_7
TXD6/SDA6/SRXD6
CS0/A23
46
J8
P4_6
RXD6/SCL6/STXD6
CS1/A22
47
H8
P4_5
CLK6
CS2/A21
48
G8
P4_4
CTS6/RTS6/SS6
CS3/A20
49
K9
P4_3
TXD3/SDA3/SRXD3 OUTC2_0/ISTXD2/
IEOUT
A19
50
K10
P4_2
RXD3/SCL3/STXD3 ISRXD2/IEIN
A18
51
J10
P4_1
CLK3
A17
52
J9
P4_0
CTS3/RTS3/SS3
A16
53
H9
P3_7
TA4IN/U
A15(/D15)
54
H10
P3_6
TA4OUT/U
A14(/D14)
55
F6
P3_5
TA2IN/W
A13(/D13)
56
F7
P3_4
TA2OUT/W
A12(/D12)
57
G9
P3_3
TA1IN/V
A11(/D11)
58
G10
P3_2
TA1OUT/V
A10(/D10)
59
F8
P3_1
TA3OUT
UD0B/UD1B
A9(/D9)
60
F9
P3_0
TA0OUT
UD0A/UD1A
A8(/D8)
VCC2
61
F10
62
E8
63
E9
P2_7
AN2_7
A7(/D7)
64
E10
P2_6
AN2_6
A6(/D6)
65
E7
P2_5
AN2_5
A5(/D5)
66
D7
P2_4
AN2_4
A4(/D4)
67
D8
P2_3
AN2_3
A3(/D3)
68
D10
P2_2
AN2_2
A2(/D2)
69
D9
P2_1
AN2_1
A1(/D1)
70
C10
P2_0
AN2_0
A0(/D0)/
BC0(/D0)
71
C9
P1_7
VSS
INT5
IIO0_7/IIO1_7
D15
72
E6
P1_6
INT4
IIO0_6/IIO1_6
D14
73
B9
P1_5
INT3
IIO0_5/IIO1_5
D13
74
B10
P1_4
IIO0_4/IIO1_4
D12
75
A10
P1_3
IIO0_3/IIO1_3
D11
76
A9
P1_2
IIO0_2/IIO1_2
D10
77
C8
P1_1
IIO0_1/IIO1_1
D9
78
C7
P1_0
IIO0_0/IIO1_0
D8
79
A8
P0_7
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 16 of 99
AN0_7
D7
R32C/111 Group
Table 1.10
1. Overview
Pin Characteristics for the 100-pin Package (3/3)
Pin No.
Control
Pin
QFP LGA
Port
Interrupt
Pin
Timer Pin
UART Pin
Intelligent I/O Pin
Analog
Pin
Bus Control
Pin
80
B8
P0_6
AN0_6
D6
81
D6
P0_5
AN0_5
D5
82
B7
P0_4
AN0_4
D4
83
A7
P0_3
AN0_3
D3
84
B6
P0_2
AN0_2
D2
85
C6
P0_1
AN0_1
D1
86
E5
P0_0
AN0_0
D0
87
D5
P10_7 KI3
AN_7
88
A6
P10_6 KI2
AN_6
89
B5
P10_5 KI1
AN_5
90
A5
P10_4 KI0
AN_4
91
C5
P10_3
AN_3
92
B4
P10_2
AN_2
93
A4
P10_1
AN_1
94
C4
P10_0
AN_0
AVSS
95
D4
96
A3
VREF
97
B3
AVCC
98
C3
P9_7
RXD4/SCL4/STXD4
99
B2
P9_6
TXD4/SDA4/SRXD4
ANEX1
100 A2
P9_5
CLK4
ANEX0
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 17 of 99
ADTRG
1. Overview
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
61
40
62
39
63
38
64
37
65
36
66
35
67
34
R32C/111 GROUP
68
69
33
32
70
31
71
30
PLQP0080KB-A
(80P6Q-A)
(Top view)
72
73
74
75
29
28
27
26
P7_3 / TA1IN / V / CTS2 / RTS2 / SS2 / TXD8 / IIO1_0
P7_4 / TA2OUT / W / CLK8 / IIO1_1
P7_5 / TA2IN / W / RXD8 / IIO1_2
P7_6 / TA3OUT / TXD5 / SDA5 / SRXD5 / RTS8 / CTS8 / IIO1_3 / UD0A / UD1A
20
19
18
17
16
15
14
13
12
11
9
10
P6_3 / TXD0 / SDA0 / SRXD0
P3_0 / TA0OUT / UD0A / UD1A / CLK3
P3_1 / TA3OUT / UD0B / UD1B / RXD3 / SCL3 / STXD3
P3_2 / TA1OUT / V / TXD3 / SDA3 / SRXD3
P3_3 / TA1IN / V / CTS3 / RTS3 / SS3
P3_4 / TA2OUT / W
P3_5 / TA2IN / W
P3_6 / TA4OUT / U
P3_7 / TA4IN / U
P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2
P6_5 / CLK1
P6_6 / RXD1 / SCL1 / STXD1
P6_7 / TXD1 / SDA1 / SRXD1
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT (Note 1)
P7_1 / TB5IN / TA0IN / RXD2 / SCL2 / STXD2 / IIO1_7 / OUTC2_2 / ISRXD2 / IEIN
(Note 1)
P7_2 / TA1OUT / V / CLK2
CLK4 / ANEX0 / P9_5
TB3IN / DA0 / P9_3
VDC0
VDC1
NSD
CNVSS
XCIN / P8_7
XCOUT / P8_6
RESET
XOUT
VSS
XIN
VCC1
NMI / P8_5
INT2 / P8_4
INT1 / P8_3
INT0 / P8_2
UD0B / UD1B / IIO1_5 / RTS5 / CTS5 / SS5 / U / TA4IN / P8_1
UD0A / UD1A / RXD5 / SCL5 / STXD5 / U / TA4OUT / P8_0
UD0B / UD1B / IIO1_4 / CLK5 / TA3IN / P7_7
8
21
7
80
(Note 2)
6
22
5
23
79
4
24
78
3
25
77
2
76
1
AN0_6 / P0_6
AN0_5 / P0_5
AN0_4 / P0_4
AN0_3 / P0_3
AN0_2 / P0_2
AN0_1 / P0_1
AN0_0 / P0_0
KI3 / AN_7 / P10_7
KI2 / AN_6 / P10_6
KI1 / AN_5 / P10_5
KI0 / AN_4 / P10_4
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AVSS
AN_0 / P10_0
VREF
AVCC
STXD4 / SCL4 / RXD4 / ADTRG / P9_7
SRXD4 / SDA4 / TXD4 / ANEX1 / P9_6
59
60
P0_7 / AN0_7
P1_0 / IIO0_0 / IIO1_0
P1_1 / IIO0_1 / IIO1_1
P1_2 / IIO0_2 / IIO1_2
P1_3 / IIO0_3 / IIO1_3
P1_4 / IIO0_4 / IIO1_4
P1_5 / INT3 / IIO0_5 / IIO1_5 / ADTRG
P1_6 / INT4 / IIO0_6 / IIO1_6
P1_7 / INT5 / IIO0_7 / IIO1_7
P2_0 / AN2_0 / IIO0_0
P2_1 / AN2_1 / IIO0_1
P2_2 / AN2_2 / IIO0_2
P2_3 / AN2_3 / IIO0_3
P2_4 / AN2_4 / IIO0_4
P2_5 / AN2_5 / IIO0_5
P2_6 / AN2_6 / IIO0_6
P2_7 / AN2_7 / IIO0_7
P6_0 / TB0IN / CTS0 / RTS0 / SS0
P6_1 / TB1IN / CLK0
P6_2 / TB2IN / RXD0 / SCL0 / STXD0
R32C/111 Group
Notes:
1. Pins P7_0 and P7_1 are open drain outputs.
2. The position of pin number 1 varies by product. Refer to the index mark attached “Package Dimensions”.
Figure 1.7
Pin Assignment for the 80-pin Package (top view)
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 18 of 99
R32C/111 Group
Table 1.11
1. Overview
Pin Characteristics for the 80-pin Package (1/2)
Pin No. Control Pin
Port
1
P9_5
2
P9_3
3
VDC0
4
VDC1
5
NSD
6
CNVSS
7
XCIN
P8_7
8
XCOUT
P8_6
9
RESET
10
XOUT
11
VSS
12
XIN
13
VCC1
Interrupt Pin
Timer Pin
UART Pin
Intelligent I/O Pin
CLK4
ANEX0
TB3IN
DA0
14
P8_5
NMI
15
P8_4
INT2
16
P8_3
INT1
17
P8_2
INT0
18
P8_1
TA4IN/U
CTS5/RTS5/SS5
IIO1_5/UD0B/UD1B
19
P8_0
TA4OUT/U
RXD5/SCL5/STXD5
UD0A/UD1A
20
P7_7
TA3IN
CLK5
IIO1_4/UD0B/UD1B
21
P7_6
TA3OUT
TXD5/SDA5/SRXD5/
CTS8/RTS8
IIO1_3/UD0A/UD1A
22
P7_5
TA2IN/W
RXD8
IIO1_2
23
P7_4
TA2OUT/W
CLK8
IIO1_1
24
P7_3
TA1IN/V
CTS2/RTS2/SS2/TXD8 IIO1_0
25
P7_2
TA1OUT/V
CLK2
26
P7_1
TB5IN/TA0IN RXD2/SCL2/STXD2
IIO1_7/OUTC2_2/
ISRXD2/IEIN
27
P7_0
TA0OUT
IIO1_6/OUTC2_0/
ISTXD2/IEOUT
28
P6_7
TXD1/SDA1/SRXD1
29
P6_6
RXD1/SCL1/STXD1
30
P6_5
CLK1
31
P6_4
CTS1/RTS1/SS1
32
P3_7
TA4IN/U
33
P3_6
TA4OUT/U
34
P3_5
TA2IN/W
35
P3_4
TA2OUT/W
36
P3_3
TA1IN/V
CTS3/RTS3/SS3
37
P3_2
TA1OUT/V
TXD3/SDA3/SRXD3
38
P3_1
TA3OUT
RXD3/SCL3/STXD3
UD0B/UD1B
39
P3_0
TA0OUT
CLK3
UD0A/UD1A
40
P6_3
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 19 of 99
Analog Pin
TXD2/SDA2/SRXD2
TXD0/SDA0/SRXD0
OUTC2_1/ISCLK2
R32C/111 Group
Table 1.12
1. Overview
Pin Characteristics for the 80-pin Package (2/2)
Pin No. Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Intelligent I/O Pin
Analog Pin
41
P6_2
TB2IN
RXD0/SCL0/STXD0
42
P6_1
TB1IN
CLK0
43
P6_0
TB0IN
CTS0/RTS0/SS0
44
P2_7
IIO0_7
AN2_7
45
P2_6
IIO0_6
AN2_6
46
P2_5
IIO0_5
AN2_5
47
P2_4
IIO0_4
AN2_4
48
P2_3
IIO0_3
AN2_3
49
P2_2
IIO0_2
AN2_2
50
P2_1
IIO0_1
AN2_1
51
P2_0
IIO0_0
AN2_0
52
P1_7
INT5
IIO0_7/IIO1_7
53
P1_6
INT4
IIO0_6/IIO1_6
54
P1_5
INT3
IIO0_5/IIO1_5
55
P1_4
IIO0_4/IIO1_4
56
P1_3
IIO0_3/IIO1_3
57
P1_2
IIO0_2/IIO1_2
58
P1_1
IIO0_1/IIO1_1
59
P1_0
IIO0_0/IIO1_0
60
P0_7
AN0_7
61
P0_6
AN0_6
62
P0_5
AN0_5
63
P0_4
AN0_4
64
P0_3
AN0_3
65
P0_2
AN0_2
66
P0_1
AN0_1
67
P0_0
AN0_0
68
P10_7 KI3
AN_7
ADTRG
69
P10_6 KI2
AN_6
70
P10_5 KI1
AN_5
71
P10_4 KI0
AN_4
72
P10_3
AN_3
73
P10_2
AN_2
74
P10_1
AN_1
P10_0
AN_0
75
AVSS
76
77
VREF
78
AVCC
79
P9_7
RXD4/SCL4/STXD4
ADTRG
80
P9_6
TXD4/SDA4/SRXD4
ANEX1
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 20 of 99
1. Overview
33
34
35
36
37
38
39
40
41
42
43
44
45
46
49
32
50
31
51
30
52
29
53
54
55
R32C/111 GROUP
56
28
27
26
25
57
24
PLQP0064KB-A
(64P6Q-A)
(Top view)
58
59
60
61
23
22
21
20
P7_3 / TA1IN / V / CTS2 / RTS2 / SS2 / TXD8 / IIO1_0
P7_4 / TA2OUT / W / CLK8 / IIO1_1
P7_5 / TA2IN / W / RXD8 / IIO1_2
P7_6 / TA3OUT / TXD5 / SDA5 / SRXD5 / RTS8 / CTS8 / IIO1_3 / UD0A / UD1A
P7_7 / TA3IN / CLK5 / IIO1_4 / UD0B / UD1B
16
15
14
13
12
11
10
9
8
7
6
P3_0 / TA0OUT / UD0A / UD1A / CLK3
P3_1 / TA3OUT / UD0B / UD1B / RXD3 / SCL3 / STXD3
P3_2 / TA1OUT / V / TXD3 / SDA3 / SRXD3
P3_3 / TA1IN / V / CTS3 / RTS3 / SS3
P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2
P6_5 / CLK1
P6_6 / RXD1 / SCL1 / STXD1
P6_7 / TXD1 / SDA1 / SRXD1
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT (Note 1)
P7_1 / TB5IN / TA0IN / RXD2 / SCL2 / STXD2 / IIO1_7 / OUTC2_2 / ISRXD2 / IEIN
(Note 1)
P7_2 / TA1OUT / V / CLK2
VDC1
NSD
CNVSS
XCIN / P8_7
XCOUT / P8_6
RESET
XOUT
VSS
XIN
VCC1
NMI / P8_5
INT2 / P8_4
INT1 / P8_3
INT0 / P8_2
UD0B / UD1B / IIO1_5 / RTS5 / CTS5 / SS5 / U / TA4IN / P8_1
UD0A / UD1A / RXD5 / SCL5 / STXD5 / U / TA4OUT / P8_0
(Note 2)
5
17
4
18
64
3
19
63
2
62
1
AN0_2 / P0_2
AN0_1 / P0_1
AN0_0 / P0_0
KI3 / AN_7 / P10_7
KI2 / AN_6 / P10_6
KI1 / AN_5 / P10_5
KI0 / AN_4 / P10_4
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AVSS
AN_0 / P10_0
VREF
AVCC
TB3IN / DA0 / P9_3
VDC0
47
48
P0_3 / AN0_3
P1_5 / INT3 / IIO0_5 / IIO1_5 / ADTRG
P1_6 / INT4 / IIO0_6 / IIO1_6
P1_7 / INT5 / IIO0_7 / IIO1_7
P2_0 / AN2_0 / IIO0_0
P2_1 / AN2_1 / IIO0_1
P2_2 / AN2_2 / IIO0_2
P2_3 / AN2_3 / IIO0_3
P2_4 / AN2_4 / IIO0_4
P2_5 / AN2_5 / IIO0_5
P2_6 / AN2_6 / IIO0_6
P2_7 / AN2_7 / IIO0_7
P6_0 / TB0IN / CTS0 / RTS0 / SS0
P6_1 / TB1IN / CLK0
P6_2 / TB2IN / RXD0 / SCL0 / STXD0
P6_3 / TXD0 / SDA0 / SRXD0
R32C/111 Group
Notes:
1. P7_0 and P7_1 are open drain outputs.
2. The position of pin number 1 varies by product. Refer to the index mark attached “Package Dimensions”.
Figure 1.8
Pin Assignment for the 64-pin Package (top view)
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 21 of 99
R32C/111 Group
Table 1.13
1. Overview
Pin Characteristics for the 64-pin Package (1/2)
Pin No. Control Pin
Port
1
VDC1
2
NSD
3
CNVSS
4
XCIN
P8_7
5
XCOUT
P8_6
6
RESET
7
XOUT
8
VSS
9
XIN
10
VCC1
Interrupt Pin
Timer Pin
UART Pin
Intelligent I/O Pin
11
P8_5
NMI
12
P8_4
INT2
13
P8_3
INT1
14
P8_2
INT0
15
P8_1
TA4IN/U
CTS5/RTS5/SS5
IIO1_5/UD0B/UD1B
16
P8_0
TA4OUT/U
RXD5/SCL5/STXD5
UD0A/UD1A
17
P7_7
TA3IN
CLK5
IIO1_4/UD0B/UD1B
18
P7_6
TA3OUT
TXD5/SDA5/SRXD5/
CTS8/RTS8
IIO1_3/UD0A/UD1A
19
P7_5
TA2IN/W
RXD8
IIO1_2
IIO1_1
20
P7_4
TA2OUT/W
CLK8
21
P7_3
TA1IN/V
CTS2/RTS2/SS2/TXD8 IIO1_0
22
P7_2
TA1OUT/V
CLK2
23
P7_1
TB5IN/
TA0IN
RXD2/SCL2/STXD2
IIO1_7/OUTC2_2/
ISRXD2/IEIN
24
P7_0
TA0OUT
TXD2/SDA2/SRXD2
IIO1_6/OUTC2_0/
ISTXD2/IEOUT
25
P6_7
TXD1/SDA1/SRXD1
26
P6_6
RXD1/SCL1/STXD1
27
P6_5
CLK1
28
P6_4
CTS1/RTS1/SS1
29
P3_3
TA1IN/V
30
P3_2
TA1OUT/V
TXD3/SDA3/SRXD3
31
P3_1
TA3OUT
RXD3/SCL3/STXD3
UD0B/UD1B
32
P3_0
TA0OUT
CLK3
UD0A/UD1A
33
P6_3
Analog Pin
OUTC2_1/ISCLK2
CTS3/RTS3/SS3
TXD0/SDA0/SRXD0
34
P6_2
TB2IN
RXD0/SCL0/STXD0
35
P6_1
TB1IN
CLK0
36
P6_0
TB0IN
CTS0/RTS0/SS0
37
P2_7
IIO0_7
AN2_7
38
P2_6
IIO0_6
AN2_6
39
P2_5
IIO0_5
AN2_5
40
P2_4
IIO0_4
AN2_4
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 22 of 99
R32C/111 Group
Table 1.14
1. Overview
Pin Characteristics for the 64-pin Package (2/2)
Pin No. Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Intelligent I/O Pin
Analog Pin
41
P2_3
IIO0_3
AN2_3
42
P2_2
IIO0_2
AN2_2
43
P2_1
IIO0_1
AN2_1
44
P2_0
IIO0_0
AN2_0
45
P1_7
INT5
IIO0_7/IIO1_7
46
P1_6
INT4
IIO0_6/IIO1_6
47
P1_5
INT3
IIO0_5/IIO1_5
48
P0_3
AN0_3
49
P0_2
AN0_2
50
P0_1
AN0_1
51
P0_0
AN0_0
52
P10_7 KI3
AN_7
53
P10_6 KI2
AN_6
54
P10_5 KI1
AN_5
55
P10_4 KI0
AN_4
56
P10_3
AN_3
57
P10_2
AN_2
58
P10_1
AN_1
P10_0
AN_0
59
AVSS
60
61
VREF
62
AVCC
63
64
ADTRG
P9_3
TB3IN
VDC0
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 23 of 99
DA0
R32C/111 Group
1.5
1. Overview
Pin Definitions and Functions
Table 1.15 to Table 1.21 show the pin definitions and functions.
Table 1.15
Pin Definitions and Functions for the 100-pin Package (1/4)
Function
Symbol
Power supply
VCC1, VCC2,
VSS
Connecting pins
for decoupling
capacitor
VDC0, VDC1
Analog power
supply
AVCC, AVSS
Reset input
I/O
Power
Supply
I
—
—
—
Description
Applicable as follows: VCC1 and VCC2 = 3.0 to
5.5 V (VCC1 ≥ VCC2), VSS = 0 V
A decoupling capacitor for internal voltage should
be connected between VDC0 and VDC1
I
VCC1
Power supply for the A/D converter. AVCC and
AVSS should be connected to VCC1 and VSS,
respectively
RESET
I
VCC1
The MCU is reset when this pin is driven low
CNVSS
CNVSS
I
VCC1
This pin should be connected to VSS via a resistor
Debug port
NSD
I/O
VCC1
This pin is to communicate with a debugger. It
should be connected to VCC1 via a resistor of 1 to
4.7 kΩ
I
VCC1
O
VCC1
I
VCC1
Main clock input
XIN
Main clock output XOUT
Input/output for the main clock oscillator. A crystal,
or a ceramic resonator should be connected
between pins XIN and XOUT. An external clock
should be input at the XIN while leaving the XOUT
open
Sub clock input
XCIN
Sub clock output
XCOUT
O
VCC1
BCLK output
BCLK
O
VCC2
BCLK output
Clock output
CLKOUT
O
VCC2
Output of the clock with the same frequency as fC,
f8, or f32
I
VCC1
VCC2
Input for external interrupts
P8_5/NMI
I
VCC1
Input for NMI
Key input interrupt KI0 to KI3
I
VCC1
Input for the key input interrupt
I/O
VCC2
Input/output of data (D0 to D7) while accessing an
external memory space with a separate bus
I/O
VCC2
Input/output of data (D8 to D15) while accessing
an external memory space with 16-bit separate
bus
O
VCC2
Output of address bits A0 to A23
External interrupt INT0 to INT5
input
NMI input
Bus control pins
D0 to D7
D8 to D15
A0 to A23
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 24 of 99
Input/output for the sub clock oscillator. A crystal
oscillator should be connected between pins XCIN
and XCOUT. An external clock should be input at
the XCIN while leaving the XCOUT open
R32C/111 Group
Table 1.16
1. Overview
Pin Definitions and Functions for the 100-pin Package (2/4)
Function
Bus control pins
Symbol
I/O
Power
Supply
Description
I/O
VCC2
Output of address bits (A0 to A7) and input/output
of data (D0 to D7) by time-division while accessing
an external memory space with multiplexed bus
VCC2
Output of address bits (A8 to A15) and input/
output of data (D8 to D15) by time-division while
accessing an external memory space with 16-bit
multiplexed bus
I/O
VCC2
Output of byte control (BC0) and input/output of
data (D0) by time-division while accessing an
external memory space with multiplexed bus
O
VCC2
Chip select output
A0/D0 to A7/D7
A8/D8 to
A15/D15
I/O
BC0/D0
CS0 to CS3
WR0/WR1/WR/
BC0/BC1/RD
Output of write, byte control, and read signals.
Either WRx or WR and BCx can be selected by a
program.
Data is read when RD is low.
O
VCC2
• When WR0, WR1, and RD are selected,
data is written to the following address:
an even address, when WR0 is low
an odd address, when WR1 is low
on 16-bit external data bus
• When WR, BC0, BC1, and RD are selected,
data is written, when WR is low
and
the following address is accessed:
an even address, when BC0 is low
an odd address, when BC1 is low
on 16-bit external data bus
ALE
HOLD
HLDA
RDY
O
VCC2
Latch enable signal in multiplexed bus format
I
VCC2
The MCU is in a hold state while this pin is held
low
O
VCC2
This pin is driven low while the MCU is held in a
hold state
I
VCC2
Bus cycle is extended by the CPU if this pin is low
on the falling edge of the BCLK
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 25 of 99
R32C/111 Group
Table 1.17
1. Overview
Pin Definitions and Functions for the 100-pin Package (3/4)
Function
I/O port
Symbol
Power
Supply
Description
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_0 to P4_7
P5_0 to P5_7
I/O
VCC2
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_4
P8_6, P8_7
P9_3 to P9_7
P10_0 to
P10_7
I/O
VCC1
I
VCC1
Input port in CMOS. Pull-up resistors are
selectable for P9_1 and P9_3
I/O
VCC1
VCC2
Timers A0 to A4 input/output.
TA0OUT output assigned for port P7_0 is Nchannel open drain
I
VCC1
VCC2
I
VCC1
O
VCC1
VCC2
I
VCC1
VCC2
Handshake input
O
VCC1
VCC2
Handshake output
I/O
VCC1
VCC2
Transmit/receive clock input/output
I
VCC1
VCC2
Serial data input
O
VCC1
VCC2
Serial data output.
TXD2 output is N-channel open drain
I/O
VCC1
VCC2
Serial data input/output.
SDA2 output is N-channel open drain
I/O
VCC1
VCC2
Transmit/receive clock input/output.
SCL2 output is N-channel open drain
Input port
P9_1
Timer A
TA0OUT to
TA4OUT
TA0IN to TA4IN
Timer B
TB0IN to
TB5IN
Three-phase
motor control
timer output
U,U,V,V,W,W
Serial interface
CTS0 to CTS8
RTS0 to RTS8
CLK0 to CLK8
RXD0 to RXD8
TXD0 to TXD8
I2C bus
(simplified)
I/O
SDA0 to SDA6
SCL0 to SCL6
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 26 of 99
I/O ports in CMOS. Each port can be programmed
to input or output under the control of the direction
register.
Pull-up resistors are selected for following 4-pin
units, but are enabled only for the input pins: Pi_0
to Pi_3 and Pi_4 to Pi_7 (i = 0 to 10).
P7_0 and P7_1 outputs are N-channel open drain
Timers A0 to A4 input
Timers B0 to B5 input
Three-phase motor control timer output
R32C/111 Group
Table 1.18
1. Overview
Pin Definitions and Functions for the 100-pin Package (4/4)
Function
Serial interface
special functions
I/O
Power
Supply
STXD0 to
STXD6
O
VCC1
VCC2
Serial data output in slave mode.
STXD2 is N-channel open drain
SRXD0 to
SRXD6
I
VCC1
VCC2
Serial data input in slave mode
I
VCC1
VCC2
Input to control serial interface special functions
AN_0 to AN_7
I
VCC1
Analog input for the A/D converter
AN0_0 to
AN0_7
AN2_0 to
AN2_7
I
VCC2
ADTRG
I
VCC1
External trigger input for the A/D converter
I/O
VCC1
Expanded analog input for the A/D converter and
output in external op-amp connection mode
ANEX1
I
VCC1
Expanded analog input for the A/D converter
DA0, DA1
O
VCC1
Output for the D/A converter
I
−
Reference voltage input for the A/D converter and
D/A converter
I/O
VCC1
VCC2
Input/output for the Intelligent I/O group 0. Either
input capture or output compare is selectable
I/O
VCC1
VCC2
Input/output for the Intelligent I/O group 1. Either
input capture or output compare is selectable.
IIO1_6 and IIO1_7 outputs assigned for ports
P7_0 and P7_1 are N-channel open drain
I
VCC1
VCC2
Symbol
SS0 to SS6
A/D converter
ANEX0
D/A converter
Reference voltage VREF
input
Intelligent I/O
IIO0_0 to
IIO0_7
IIO1_0 to
IIO1_7
UD0A, UD0B,
UD1A, UD1B
OUTC2_0 to
OUTC2_2
O
ISCLK2
I/O
ISRXD2
I
ISTXD2
VCC1
VCC2
VCC1
VCC2
O
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 27 of 99
Output for OC (output compare) of the Intelligent I/
O group 2.
OUTC2_0 and OUTC2_2 assigned for ports P7_0
and P7_1 are N-channel open drain
Receive data input for the serial interface
Transmit data output for the serial interface.
ISTXD2 assigned for port P7_0 is N-channel open
drain
Receive data input for the serial interface
I
IEOUT
Input for the two-phase encoder
Clock input/output for the serial interface
O
IEIN
Description
VCC1
VCC2
Transmit data output for the serial interface.
IEOUT assigned for port P7_0 is N-channel open
drain
R32C/111 Group
Table 1.19
1. Overview
Pin Definitions and Functions for the 80-/64-pin Package (1/3)
Function
Symbol
Power supply
VCC1, VSS
Connecting pins
for decoupling
capacitor
VDC0, VDC1
Analog power
supply
AVCC, AVSS
Reset input
I/O
I
—
Description
Applicable as follows: VCC1 = 3.0 to 5.5 V, VSS = 0 V
A decoupling capacitor for internal voltage should be
connected between VDC0 and VDC1
I
Power supply for the A/D converter. AVCC and AVSS should
be connected to VCC and VSS, respectively
RESET
I
The MCU is reset when this pin is driven low
CNVSS
CNVSS
I
This pin should be connected to VSS via a resistor
Debug port
NSD
Main clock input
XIN
Main clock output XOUT
Sub clock input
XCIN
Sub clock output
XCOUT
External interrupt INT0 to INT5
input
I/O
I
O
I
O
I
This pin is to communicate with a debugger. It should be
connected to VCC1 via a resistor of 1 to 4.7 kΩ
Input/output for the main clock oscillator. A crystal, or a
ceramic resonator should be connected between pins XIN
and XOUT. An external clock should be input at the XIN while
leaving the XOUT open
Input/output for the sub clock oscillator. A crystal oscillator
should be connected between pins XCIN and XCOUT. An
external clock should be input at the XCIN while leaving the
XCOUT open
Input for external interrupts
P8_5/NMI
I
Input for NMI
Key input interrupt KI0 to KI3
I
Input for the key input interrupt
NMI input
I/O port
(1)
Timer A
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_4
P8_6, P8_7
P9_3,
P9_5 to P9_7,
P10_0 to P10_7
TA0OUT to
TA4OUT
I/O
I/O
TA0IN to TA4IN
I
Timer B
TB0IN to
TB3IN, TB5IN
I
Three-phase
motor control
timer output
U,U,V,V,W,W
I/O ports in CMOS. Each port can be programmed to input or
output under the control of the direction register.
Pull-up resistors are selected for following 4-pin units, but are
enabled only for the input pins: Pi_0 to Pi_3 and Pi_4 to Pi_7
(i = 0 to 3, 6 to 10).
P7_0 and P7_1 outputs are N-channel open drain
Timers A0 to A4 input/output.
TA0OUT output assigned for port P7_0 is N-channel open
drain
Timers A0 to A4 input
Timers B0 to B3, and B5 input
Three-phase motor control timer output
O
Note:
1. Ports P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, and P9_5 to P9_7 are available in the 80-pin
package only.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 28 of 99
R32C/111 Group
Table 1.20
1. Overview
Pin Definitions and Functions for the 80-/64-pin Package (2/3)
Function
Symbol
I/O
Description
Serial interface (1) CTS0 to CTS3,
CTS5, CTS8
I
RTS0 to RTS3,
RTS5, RTS8
O
CLK0 to CLK5,
CLK8
I/O
RXD0 to RXD5,
RXD8
I
TXD0 to TXD5,
TXD8
O
Serial data output.
TXD2 output is N-channel open drain
I/O
Serial data input/output.
SDA2 output is N-channel open drain
I/O
Transmit/receive clock input/output.
SCL2 output is N-channel open drain
O
Serial data output in slave mode.
STXD2 is N-channel open drain
I2C bus
(simplified) (1)
SDA0 to SDA5
SCL0 to SCL5
Handshake input
Handshake output
Transmit/receive clock input/output
Serial data input
Serial interface
special functions
STXD0 to STXD5
(1)
SRXD0 to SRXD5
I
Serial data input in slave mode
SS0 to SS3, SS5
I
Input to control serial interface special functions
AN_0 to AN_7
AN0_0 to AN0_7
AN2_0 to AN2_7
I
ADTRG
I
A/D converter (2)
ANEX0
D/A converter
Analog input for the A/D converter
I/O
External trigger input for the A/D converter
Expanded analog input for the A/D converter and output in
external op-amp connection mode
ANEX1
I
Expanded analog input for the A/D converter
DA0
O
Output for the D/A converter
I
Reference voltage input for the A/D converter and D/A
converter
Reference voltage VREF
input
Notes:
1. Pins CLK4, RXD4, TXD4, SDA4, SCL4, SRXD4, and STXD4 are available in the 80-pin package
only.
2. Pins AN0_4 to AN0_7, ANEX0 and ANEX1 are available in the 80-pin package only.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 29 of 99
R32C/111 Group
Table 1.21
1. Overview
Pin Definitions and Functions for the 80-/64-pin Package (3/3)
Function
Intelligent I/O
Symbol
IIO0_0 to IIO0_7
I/O
I/O
Input/output for the Intelligent I/O group 0. Either input
capture or output compare is selectable
I/O
Input/output for the Intelligent I/O group 1. Either input
capture or output compare is selectable. IIO1_6 and IIO1_7
outputs assigned for ports P7_0 and P7_1 are N-channel
open drain
IIO1_0 to IIO1_7
UD0A, UD0B,
UD1A, UD1B
OUTC2_0 to
OUTC2_2
Description
I
Input for the two-phase encoder
O
Output for OC (output compare) of the Intelligent I/O group
2.
OUTC2_0 and OUTC2_2 assigned for ports P7_0 and
P7_1 are N-channel open drain
ISCLK2
I/O
Clock input/output for the serial interface
ISRXD2
I
Receive data input for the serial interface
O
Transmit data output for the serial interface. ISTXD2
assigned for port P7_0 is N-channel open drain
I
Receive data input for the serial interface
O
Transmit data output for the serial interface. IEOUT
assigned for port P7_0 is N-channel open drain
ISTXD2
IEIN
IEOUT
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
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R32C/111 Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
The CPU contains registers as shown below. There are two register banks each consisting of registers
R2R0, R3R1, R6R4, R7R5, A0 to A3, SB, and FB.
General purpose
registers
b31
R2R0
R2H
R3R1
R3H
b23
R6R4
R6
R7R5
R7
b15
b7
R2L
R0H
R3L
R1H
b0
R0L
R1L
Data registers (1)
R4
R5
A0
A1
Address registers (1)
A2
A3
SB
Static base register (1)
FB
Frame base register (1)
USP
User stack pointer
ISP
Interrupt stack pointer
Interrupt vector table base register
INTB
b31
PC
Program counter
FLG
Flag register
b24 b23
b16 b15
RND
b8 b7
IPL
DP
FU
FO
Fast interrupt
registers
DMAC-associated
registers (2)
b31
b31
Blank fields represent reserved.
b0
SVF
Save flag register
SVP
Save PC register
VCT
Vector register
b0
b23
DMD0
DMD0
DMD0
DMD0
DCT0
DCT0
DCT0
DCT0
DCR0
DCR0
DCR0
DCR0
DSA0
DSA0
DSA0
DSA0
DSR0
DSR0
DSR0
DSR0
DDA0
DDA0
DDA0
DDA0
DDR0
DDR0
DDR0
DDR0
DMA mode register
DMA terminal count register
DMA terminal count reload register
DMA source address register
DMA source address reload register
DMA destination address register
DMA destination address reload register
Notes:
1. There are two banks of these registers.
2. There are four identical sets of DMAC-associated registers.
Figure 2.1
b0
U I O B S Z D C
CPU Registers
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Page 31 of 99
R32C/111 Group
2.1
2. Central Processing Unit (CPU)
General Purpose Registers
2.1.1
Data Registers (R2R0, R3R1, R6R4, and R7R5)
These 32-bit registers are primarily used for transfers and arithmetic/logic operations.
Each of the registers can be divided into upper and lower 16-bit registers, e.g. R2R0 can be divided into
R2 and R0, R3R0 can be divided into R3 and R1, etc.
Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: upper (R2H and
R3H), mid-upper (R2L and R3L), mid-lower (R0H and R1H), and lower (R0L and R1L).
2.1.2
Address Registers (A0, A1, A2, and A3)
These 32-bit registers have functions similar to data registers. They are also used for address register
indirect addressing and address register relative addressing.
2.1.3
Static Base Register (SB)
This 32-bit register is used for SB relative addressing.
2.1.4
Frame Base Register (FB)
This 32-bit register is used for FB relative addressing.
2.1.5
Program Counter (PC)
This 32-bit counter indicates the address of the instruction to be executed next.
2.1.6
Interrupt Vector Table Base Register (INTB)
This 32-bit register indicates the start address of a relocatable vector table.
2.1.7
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack
pointer (ISP).
Use the stack pointer select flag (U flag) to select either the user stack pointer (USP) or the interrupt
stack pointer (ISP). The U flag is bit 7 in the flag register (FLG). Refer to 2.1.8 “Flag Register (FLG)” for
details.
To minimize the overhead of interrupt sequence due to less memory access, set the user stack pointer
(USP) or the interrupt stack pointer (ISP) to a multiple of 4.
2.1.8
Flag Register (FLG)
This 32-bit register indicates the CPU status.
2.1.8.1
Carry Flag (C flag)
This flag becomes 1 when any of the carry, borrow, shifted-out bit, etc. is generated in the arithmetic
logic unit (ALU).
2.1.8.2
Debug Flag (D flag)
This flag is only for debugging. Only set this bit to 0.
2.1.8.3
Zero Flag (Z flag)
This flag becomes 1 when the result of an operation is 0; otherwise it is 0.
2.1.8.4
Sign Flag (S flag)
This flag becomes 1 when the result of an operation is a negative value; otherwise it is 0.
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R32C/111 Group
2.1.8.5
2. Central Processing Unit (CPU)
Register Bank Select Flag (B flag)
This flag selects a register bank. It indicates 0 when the register bank 0 is selected, and 1 when the
register bank 1 is selected.
2.1.8.6
Overflow Flag (O flag)
This flag becomes 1 if an overflow occurs in an operation; otherwise it is 0.
2.1.8.7
Interrupt Enable Flag (I flag)
This flag enables maskable interrupts. To disable maskable interrupts, set this flag to 0. To enable
them, set this flag to 1. When an interrupt is accepted, the flag becomes 0.
2.1.8.8
Stack Pointer Select Flag (U flag)
To select the interrupt stack pointer (ISP), set this flag to 0. To select the user stack pointer (USP), set
this flag to 1.
It becomes 0 when a hardware interrupts is accepted or when an INT instruction designated by a
software interrupt number from 0 to 127 is executed.
2.1.8.9
Floating-point Underflow Flag (FU flag)
This flag becomes 1 when an underflow occurs in a floating-point operation; otherwise it is 0. It also
becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.10
Floating-point Overflow Flag (FO flag)
This flag becomes 1 when an overflow occurs in a floating-point operation; otherwise it is 0. It also
becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.11
Processor Interrupt Priority Level (IPL)
The processor interrupt priority level (IPL), consisting of three bits, selects a processor interrupt priority
level from level 0 to 7. An interrupt is acceptable when the interrupt request level is higher than the
selected IPL.
When the processor interrupt priority level (IPL) is set to 111b (level 7), all interrupts are disabled.
2.1.8.12
Fixed-point Radix Point Designation Bit (DP bit)
This bit designates the radix point. It also specifies which portion of the fixed-point multiplication result
to take. It is used in the MULX instruction.
2.1.8.13
Floating-point Rounding Mode (RND)
The 2-bit floating-point rounding mode selects a rounding mode for floating-point calculation results.
2.1.8.14
Reserved
Only set this bit to 0. The read value is undefined.
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R32C/111 Group
2.2
2. Central Processing Unit (CPU)
Fast Interrupt Registers
The following three registers are provided to minimize the overhead of interrupt sequence.
2.2.1
Save Flag Register (SVF)
This 32-bit register is used to save the flag register when a fast interrupt is generated.
2.2.2
Save PC Register (SVP)
This 32-bit register is used to save the program counter when a fast interrupt is generated.
2.2.3
Vector Register (VCT)
This 32-bit register is used to indicate a jump address when a fast interrupt is generated.
2.3
DMAC-associated Registers
There are seven types of DMAC-associated registers.
2.3.1
DMA Mode Registers (DMD0, DMD1, DMD2, and DMD3)
These 32-bit registers are used to set DMA transfer mode, bit rate etc.
2.3.2
DMA Terminal Count Registers (DCT0, DCT1, DCT2, and DCT3)
These 24-bit registers are used to set DMA transfer counting.
2.3.3
DMA Terminal Count Reload Registers (DCR0, DCR1, DCR2, and DCR3)
These 24-bit registers are used to set the reloaded values for DMA terminal count registers.
2.3.4
DMA Source Address Registers (DSA0, DSA1, DSA2, and DSA3)
These 32-bit registers are used to set DMA source addresses.
2.3.5
DMA Source Address Reload Registers (DSR0, DSR1, DSR2, and DSR3)
These 32-bit registers are used to set the reloaded value for DMA source address register.
2.3.6
DMA Destination Address Registers (DDA0, DDA1, DDA2, and DDA3)
These 32-bit registers are used to set DMA destination address.
2.3.7
DMA Destination Address Reload Registers (DDR0, DDR1, DDR2, and
DDR3)
These 32-bit registers are used to set reloaded values for DMA destination address registers.
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R32C/111 Group
3.
3. Memory
Memory
Figure 3.1 shows the memory map of the R32C/111 Group.
The R32C/111 Group provides a 4-Gbyte address space from 00000000h to FFFFFFFFh.
The internal ROM is mapped to the end of the memory map with the ending address fixed at FFFFFFFFh.
Therefore, the 512-Kbyte internal ROM is mapped from FFF80000h to FFFFFFFFh.
The fixed interrupt vector table which contains each start address of interrupt handlers is mapped from
FFFFFFDCh to FFFFFFFFh.
The internal RAM is mapped to the beginning of the memory map with the starting address fixed at
00000400h. Therefore, the 63-Kbyte internal RAM is mapped from 00000400h to 0000FFFFh. Besides
being used for data storage, the internal RAM functions as a stack(s) for subroutines and/or interrupt
handlers.
Special Function Registers (SFRs), which are control registers for peripheral functions, are mapped from
00000000h to 000003FFh, and from 00040000h to 0004FFFFh. Unoccupied SFR locations are reserved.
No access is allowed.
In memory expansion mode or microprocessor mode, some spaces are reserved for internal use and should
not be accessed.
00000000h
SFR1
00000400h
Internal RAM
Internal RAM
XXXXXXXXh
Capacity
XXXXXXXXh
32 Kbytes
00008400h
Reserved
40 Kbytes
0000A400h
00040000h
SFR2
63 Kbytes
00010000h
00050000h
Reserved
00060000h
Internal ROM
(Data space) (1)
00062000h
Reserved
Internal ROM
Capacity
YYYYYYYYh
128 Kbytes
FFFE0000h
256 Kbytes
FFFC0000h
384 Kbytes
FFFA0000h
512 Kbytes
FFF80000h
00080000h
External space (2)
FFE00000h
Reserved (3)
YYYYYYYYh
Internal ROM (4)
FFFFFFFFh
FFFFFFDCh Undefined instruction
Overflow
BRK instruction
Reserved
Reserved
Watchdog timer (5)
Reserved
NMI
Reset
FFFFFFFFh
Notes:
1. Additional two 4-Kbyte spaces (blocks A and B) for storing data are provided in the flash memory version.
2. This space can be used in memory expansion mode or microprocessor mode. Addresses from 02000000h
to FDFFFFFFh are inaccessible.
3. This space is reserved in memory expansion mode. It becomes external space in microprocessor mode.
4. This space can be used in single-chip mode or memory expansion mode. It becomes external space in
microprocessor mode.
5. The watchdog timer interrupt shares the vector table with the oscillator stop detection interrupt and low
voltage detection interrupt.
Figure 3.1
Memory Map
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
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R32C/111 Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
SFRs are memory-mapped peripheral registers that control the operation of peripherals. Table 4.1 SFR List
(1) to Table 4.24 SFR List (24) list the SFR details.
Table 4.1
SFR List (1)
Address
Register
000000h
000001h
000002h
000003h
000004h Clock Control Register
000005h
000006h Flash Memory Control Register
000007h Protect Release Register
000008h
000009h
00000Ah
00000Bh
00000Ch
00000Dh
00000Eh
00000Fh
000010h External Bus Control Register 3/Flash Memory Rewrite Bus
000011h Control Register 3
000012h Chip Selects 2 and 3 Boundary Setting Register
000013h
000014h External Bus Control Register 2
000015h
000016h Chip Selects 1 and 2 Boundary Setting Register
000017h
000018h External Bus Control Register 1
000019h
00001Ah Chip selects 0 and 1 Boundary Setting Register
00001Bh
00001Ch External Bus Control Register 0/Flash Memory Rewrite Bus
00001Dh Control Register 0
00001Eh Peripheral Bus Control Register
00001Fh
000020h to
00005Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 36 of 99
Symbol
Reset Value
CCR
0001 1000b
FMCR
PRR
0000 0001b
00h
EBC3/FEBC3
0000h
CB23
00h
EBC2
0000h
CB12
00h
EBC1
0000h
CB01
00h
EBC0/FEBC0
0000h
PBC
0504h
R32C/111 Group
Table 4.2
Address
000060h
000061h
000062h
000063h
000064h
000065h
000066h
000067h
000068h
000069h
00006Ah
00006Bh
00006Ch
00006Dh
00006Eh
00006Fh
000070h
000071h
000072h
000073h
000074h
000075h
000076h
000077h
000078h
000079h
00007Ah
00007Bh
00007Ch
00007Dh
00007Eh
00007Fh
000080h
000081h
000082h
000083h
000084h
000085h
000086h
000087h
4. Special Function Registers (SFRs)
SFR List (2)
Register
Symbol
Reset Value
Timer B5 Interrupt Control Register
UART5 Transmit/NACK Interrupt Control Register
UART2 Receive/ACK Interrupt Control Register
UART6 Transmit/NACK Interrupt Control Register
UART3 Receive/ACK Interrupt Control Register
UART5/6 Bus Collision, Start Condition/Stop Condition
Detection Interrupt Control Register
UART4 Receive/ACK Interrupt Control Register
DMA0 Transfer Complete Interrupt Control Register
UART0/3 Bus Collision, Start Condition/Stop Condition
Detection Interrupt Control Register
DMA2 Transfer Complete Interrupt Control Register
A/D Converter 0 Convert Completion Interrupt Control Register
Timer A0 Interrupt Control Register
Intelligent I/O Interrupt Control Register 0
Timer A2 Interrupt Control Register
Intelligent I/O Interrupt Control Register 2
Timer A4 Interrupt Control Register
Intelligent I/O Interrupt Control Register 4
UART0 Receive/ACK Interrupt Control Register
Intelligent I/O Interrupt Control Register 6
UART1 Receive/ACK Interrupt Control Register
Intelligent I/O Interrupt Control Register 8
Timer B1 Interrupt Control Register
Intelligent I/O Interrupt Control Register 10
Timer B3 Interrupt Control Register
TB5IC
S5TIC
S2RIC
S6TIC
S3RIC
BCN5IC/BCN6IC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
S4RIC
DM0IC
BCN0IC/BCN3IC
XXXX X000b
XXXX X000b
XXXX X000b
DM2IC
AD0IC
TA0IC
IIO0IC
TA2IC
IIO2IC
TA4IC
IIO4IC
S0RIC
IIO6IC
S1RIC
IIO8IC
TB1IC
IIO10IC
TB3IC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
INT5 Interrupt Control Register
INT5IC
XX00 X000b
INT3 Interrupt Control Register
INT3IC
XX00 X000b
INT1 Interrupt Control Register
INT1IC
XX00 X000b
UART2 Transmit/NACK Interrupt Control Register
UART5 Receive/ACK Interrupt Control Register
UART3 Transmit/NACK Interrupt Control Register
UART6 Receive/ACK Interrupt Control Register
UART4 Transmit/NACK Interrupt Control Register
S2TIC
S5RIC
S3TIC
S6RIC
S4TIC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
UART2 Bus Collision, Start Condition/Stop Condition Detection BCN2IC
Interrupt Control Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 37 of 99
XXXX X000b
R32C/111 Group
Table 4.3
4. Special Function Registers (SFRs)
SFR List (3)
Address
Register
000088h DMA1 Transfer Complete Interrupt Control Register
000089h UART1/4 Bus Collision, Start Condition/Stop Condition
Detection Interrupt Control Register
00008Ah DMA3 Transfer Complete Interrupt Control Register
00008Bh Key Input Interrupt Control Register
00008Ch Timer A1 Interrupt Control Register
00008Dh Intelligent I/O Interrupt Control Register 1
00008Eh Timer A3 Interrupt Control Register
00008Fh Intelligent I/O Interrupt Control Register 3
000090h UART0 Transmit/NACK Interrupt Control Register
000091h Intelligent I/O Interrupt Control Register 5
000092h UART1 Transmit/NACK Interrupt Control Register
000093h Intelligent I/O Interrupt Control Register 7
000094h Timer B0 Interrupt Control Register
000095h Intelligent I/O Interrupt Control Register 9
000096h Timer B2 Interrupt Control Register
000097h Intelligent I/O Interrupt Control Register 11
000098h Timer B4 Interrupt Control Register
000099h
00009Ah INT4 Interrupt Control Register
00009Bh
00009Ch INT2 Interrupt Control Register
00009Dh
00009Eh INT0 Interrupt Control Register
00009Fh
0000A0h Intelligent I/O Interrupt Request Register 0
0000A1h Intelligent I/O Interrupt Request Register 1
0000A2h Intelligent I/O Interrupt Request Register 2
0000A3h Intelligent I/O Interrupt Request Register 3
0000A4h Intelligent I/O Interrupt Request Register 4
0000A5h Intelligent I/O Interrupt Request Register 5
0000A6h Intelligent I/O Interrupt Request Register 6
0000A7h Intelligent I/O Interrupt Request Register 7
0000A8h Intelligent I/O Interrupt Request Register 8
0000A9h Intelligent I/O Interrupt Request Register 9
0000AAh Intelligent I/O Interrupt Request Register 10
0000ABh Intelligent I/O Interrupt Request Register 11
0000ACh
0000ADh
0000AEh
0000AFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 38 of 99
Symbol
DM1IC
BCN1IC/BCN4IC
Reset Value
XXXX X000b
XXXX X000b
DM3IC
KUPIC
TA1IC
IIO1IC
TA3IC
IIO3IC
S0TIC
IIO5IC
S1TIC
IIO7IC
TB0IC
IIO9IC
TB2IC
IIO11IC
TB4IC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
INT4IC
XX00 X000b
INT2IC
XX00 X000b
INT0IC
XX00 X000b
IIO0IR
IIO1IR
IIO2IR
IIO3IR
IIO4IR
IIO5IR
IIO6IR
IIO7IR
IIO8IR
IIO9IR
IIO10IR
IIO11IR
0000 0XX1b
0000 0XX1b
0000 0X01b
0000 XXX1b
000X 0XX1b
000X 0XX1b
000X 0XX1b
X00X 0XX1b
XX0X 0XX1b
0000 0XX1b
0000 0XX1b
0000 0XX1b
R32C/111 Group
Table 4.4
4. Special Function Registers (SFRs)
SFR List (4)
Address
Register
0000B0h Intelligent I/O Interrupt Enable Register 0
0000B1h Intelligent I/O Interrupt Enable Register 1
0000B2h Intelligent I/O Interrupt Enable Register 2
0000B3h Intelligent I/O Interrupt Enable Register 3
0000B4h Intelligent I/O Interrupt Enable Register 4
0000B5h Intelligent I/O Interrupt Enable Register 5
0000B6h Intelligent I/O Interrupt Enable Register 6
0000B7h Intelligent I/O Interrupt Enable Register 7
0000B8h Intelligent I/O Interrupt Enable Register 8
0000B9h Intelligent I/O Interrupt Enable Register 9
0000BAh Intelligent I/O Interrupt Enable Register 10
0000BBh Intelligent I/O Interrupt Enable Register 11
0000BCh
0000BDh
0000BEh
0000BFh
0000C0h
0000C1h
0000C2h
0000C3h
0000C4h
0000C5h
0000C6h
0000C7h
0000C8h
0000C9h
0000CAh
0000CBh
0000CCh
0000CDh
0000CEh
0000CFh
0000D0h
0000D1h
0000D2h
0000D3h
0000D4h
0000D5h
0000D6h
0000D7h
0000D8h
0000D9h
0000DAh
0000DBh
0000DCh
0000DDh UART7 Transmit Interrupt Control Register
0000DEh
0000DFh UART8 Transmit Interrupt Control Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 39 of 99
Symbol
IIO0IE
IIO1IE
IIO2IE
IIO3IE
IIO4IE
IIO5IE
IIO6IE
IIO7IE
IIO8IE
IIO9IE
IIO10IE
IIO11IE
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Reset Value
S7TIC
XXXX X000b
S8TIC
XXXX X000b
R32C/111 Group
Table 4.5
4. Special Function Registers (SFRs)
SFR List (5)
Address
Register
0000E0h
0000E1h
0000E2h
0000E3h
0000E4h
0000E5h
0000E6h
0000E7h
0000E8h
0000E9h
0000EAh
0000EBh
0000ECh
0000EDh
0000EEh
0000EFh
0000F0h
0000F1h
0000F2h
0000F3h
0000F4h
0000F5h
0000F6h
0000F7h
0000F8h
0000F9h
0000FAh
0000FBh
0000FCh
0000FDh UART7 Receive Interrupt Control Register
0000FEh
0000FFh UART8 Receive Interrupt Control Register
000100h Group 1 Time Measurement/Waveform Generation Register 0
000101h
000102h Group 1 Time Measurement/Waveform Generation Register 1
000103h
000104h Group 1 Time Measurement/Waveform Generation Register 2
000105h
000106h Group 1 Time Measurement/Waveform Generation Register 3
000107h
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 40 of 99
Symbol
Reset Value
S7RIC
XXXX X000b
S8RIC
G1TM0/G1PO0
XXXX X000b
XXXXh
G1TM1/G1PO1
XXXXh
G1TM2/G1PO2
XXXXh
G1TM3/G1PO3
XXXXh
R32C/111 Group
Table 4.6
4. Special Function Registers (SFRs)
SFR List (6)
Address
Register
000108h Group 1 Time Measurement/Waveform Generation Register 4
000109h
00010Ah Group 1 Time Measurement/Waveform Generation Register 5
00010Bh
00010Ch Group 1 Time Measurement/Waveform Generation Register 6
00010Dh
00010Eh Group 1 Time Measurement/Waveform Generation Register 7
00010Fh
000110h Group 1 Waveform Generation Control Register 0
000111h Group 1 Waveform Generation Control Register 1
000112h Group 1 Waveform Generation Control Register 2
000113h Group 1 Waveform Generation Control Register 3
000114h Group 1 Waveform Generation Control Register 4
000115h Group 1 Waveform Generation Control Register 5
000116h Group 1 Waveform Generation Control Register 6
000117h Group 1 Waveform Generation Control Register 7
000118h Group 1 Time Measurement Control Register 0
000119h Group 1 Time Measurement Control Register 1
00011Ah Group 1 Time Measurement Control Register 2
00011Bh Group 1 Time Measurement Control Register 3
00011Ch Group 1 Time Measurement Control Register 4
00011Dh Group 1 Time Measurement Control Register 5
00011Eh Group 1 Time Measurement Control Register 6
00011Fh Group 1 Time Measurement Control Register 7
000120h Group 1 Base Timer Register
000121h
000122h Group 1 Base Timer Control Register 0
000123h Group 1 Base Timer Control Register 1
000124h Group 1 Timer Measurement Prescaler Register 6
000125h Group 1 Timer Measurement Prescaler Register 7
000126h Group 1 Function Enable Register
000127h Group 1 Function Select Register
000128h
000129h
00012Ah
00012Bh
00012Ch
00012Dh
00012Eh
00012Fh
000130h to
00013Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 41 of 99
Symbol
G1TM4/G1PO4
Reset Value
XXXXh
G1TM5/G1PO5
XXXXh
G1TM6/G1PO6
XXXXh
G1TM7/G1PO7
XXXXh
G1POCR0
G1POCR1
G1POCR2
G1POCR3
G1POCR4
G1POCR5
G1POCR6
G1POCR7
G1TMCR0
G1TMCR1
G1TMCR2
G1TMCR3
G1TMCR4
G1TMCR5
G1TMCR6
G1TMCR7
G1BT
0000 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
00h
00h
00h
00h
00h
00h
00h
00h
XXXXh
G1BCR0
G1BCR1
G1TPR6
G1TPR7
G1FE
G1FS
00h
0000 0000b
00h
00h
00h
00h
R32C/111 Group
Table 4.7
4. Special Function Registers (SFRs)
SFR List (7)
Address
Register
000140h Group 2 Waveform Generation Register 0
000141h
000142h Group 2 Waveform Generation Register 1
000143h
000144h Group 2 Waveform Generation Register 2
000145h
000146h Group 2 Waveform Generation Register 3
000147h
000148h Group 2 Waveform Generation Register 4
000149h
00014Ah Group 2 Waveform Generation Register 5
00014Bh
00014Ch Group 2 Waveform Generation Register 6
00014Dh
00014Eh Group 2 Waveform Generation Register 7
00014Fh
000150h Group 2 Waveform Generation Control Register 0
000151h Group 2 Waveform Generation Control Register 1
000152h Group 2 Waveform Generation Control Register 2
000153h Group 2 Waveform Generation Control Register 3
000154h Group 2 Waveform Generation Control Register 4
000155h Group 2 Waveform Generation Control Register 5
000156h Group 2 Waveform Generation Control Register 6
000157h Group 2 Waveform Generation Control Register 7
000158h
000159h
00015Ah
00015Bh
00015Ch
00015Dh
00015Eh
00015Fh
000160h Group 2 Base Timer Register
000161h
000162h Group 2 Base Timer Control Register 0
000163h Group 2 Base Timer Control Register 1
000164h Base Timer Start Register
000165h
000166h Group 2 Function Enable Register
000167h Group 2 RTP Output Buffer Register
000168h
000169h
00016Ah Group 2 Serial Interface Mode Register
00016Bh Group 2 Serial Interface Control Register
00016Ch Group 2 SI/O Transmit Buffer Register
00016Dh
00016Eh Group 2 SI/O Receive Buffer Register
00016Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 42 of 99
Symbol
G2PO0
Reset Value
XXXXh
G2PO1
XXXXh
G2PO2
XXXXh
G2PO3
XXXXh
G2PO4
XXXXh
G2PO5
XXXXh
G2PO6
XXXXh
G2PO7
XXXXh
G2POCR0
G2POCR1
G2POCR2
G2POCR3
G2POCR4
G2POCR5
G2POCR6
G2POCR7
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
G2BT
XXXXh
G2BCR0
G2BCR1
BTSR
00h
0000 0000b
XXXX 0000b
G2FE
G2RTP
00h
00h
G2MR
G2CR
G2TB
00XX X000b
0000 X110b
XXXXh
G2RB
XXXXh
R32C/111 Group
Table 4.8
4. Special Function Registers (SFRs)
SFR List (8)
Address
Register
000170h Group 2 IE Bus Address Register
000171h
000172h Group 2 IE Bus Control Register
000173h Group 2 IE Bus Transmit Interrupt Source Detect Register
000174h Group 2 IE Bus Receive Interrupt Source Detect Register
000175h
000176h
000177h
000178h
000179h
00017Ah
00017Bh
00017Ch
00017Dh
00017Eh
00017Fh
000180h Group 0 Time Measurement/Waveform Generation Register 0
000181h
000182h Group 0 Time Measurement/Waveform Generation Register 1
000183h
000184h Group 0 Time Measurement/Waveform Generation Register 2
000185h
000186h Group 0 Time Measurement/Waveform Generation Register 3
000187h
000188h Group 0 Time Measurement/Waveform Generation Register 4
000189h
00018Ah Group 0 Time Measurement/Waveform Generation Register 5
00018Bh
00018Ch Group 0 Time Measurement/Waveform Generation Register 6
00018Dh
00018Eh Group 0 Time Measurement/Waveform Generation Register 7
00018Fh
000190h Group 0 Waveform Generation Control Register 0
000191h Group 0 Waveform Generation Control Register 1
000192h Group 0 Waveform Generation Control Register 2
000193h Group 0 Waveform Generation Control Register 3
000194h Group 0 Waveform Generation Control Register 4
000195h Group 0 Waveform Generation Control Register 5
000196h Group 0 Waveform Generation Control Register 6
000197h Group 0 Waveform Generation Control Register 7
000198h Group 0 Time Measurement Control Register 0
000199h Group 0 Time Measurement Control Register 1
00019Ah Group 0 Time Measurement Control Register 2
00019Bh Group 0 Time Measurement Control Register 3
00019Ch Group 0 Time Measurement Control Register 4
00019Dh Group 0 Time Measurement Control Register 5
00019Eh Group 0 Time Measurement Control Register 6
00019Fh Group 0 Time Measurement Control Register 7
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 43 of 99
IEAR
Symbol
Reset Value
XXXXh
IECR
IETIF
IERIF
00XX X000b
XXX0 0000b
XXX0 0000b
G0TM0/G0PO0
XXXXh
G0TM1/G0PO1
XXXXh
G0TM2/G0PO2
XXXXh
G0TM3/G0PO3
XXXXh
G0TM4/G0PO4
XXXXh
G0TM5/G0PO5
XXXXh
G0TM6/G0PO6
XXXXh
G0TM7/G0PO7
XXXXh
G0POCR0
G0POCR1
G0POCR2
G0POCR3
G0POCR4
G0POCR5
G0POCR6
G0POCR7
G0TMCR0
G0TMCR1
G0TMCR2
G0TMCR3
G0TMCR4
G0TMCR5
G0TMCR6
G0TMCR7
0000 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
00h
00h
00h
00h
00h
00h
00h
00h
R32C/111 Group
Table 4.9
4. Special Function Registers (SFRs)
SFR List (9)
Address
Register
0001A0h Group 0 Base Timer Register
0001A1h
0001A2h Group 0 Base Timer Control Register 0
0001A3h Group 0 Base Timer Control Register 1
0001A4h Group 0 Timer Measurement Prescaler Register 6
0001A5h Group 0 Timer Measurement Prescaler Register 7
0001A6h Group 0 Function Enable Register
0001A7h Group 0 Function Select Register
0001A8h
0001A9h
0001AAh
0001ABh
0001ACh
0001ADh
0001AEh
0001AFh
0001B0h
0001B1h
0001B2h
0001B3h
0001B4h
0001B5h
0001B6h
0001B7h
0001B8h
0001B9h
0001BAh
0001BBh
0001BCh
0001BDh
0001BEh
0001BFh
0001C0h
0001C1h
0001C2h
0001C3h
0001C4h UART5 Special Mode Register 4
0001C5h UART5 Special Mode Register 3
0001C6h UART5 Special Mode Register 2
0001C7h UART5 Special Mode Register
0001C8h UART5 Transmit/Receive Mode Register
0001C9h UART5 Bit Rate Register
0001CAh UART5 Transmit Buffer Register
0001CBh
0001CCh UART5 Transmit/Receive Control Register 0
0001CDh UART5 Transmit/Receive Control Register 1
0001CEh UART5 Receive Buffer Register
0001CFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 44 of 99
G0BT
Symbol
Reset Value
XXXXh
G0BCR0
G0BCR1
G0TPR6
G0TPR7
G0FE
G0FS
00h
0000 0000b
00h
00h
00h
00h
U5SMR4
U5SMR3
U5SMR2
U5SMR
U5MR
U5BRG
U5TB
00h
00h
00h
00h
00h
XXh
XXXXh
U5C0
U5C1
U5RB
0000 1000b
0000 0010b
XXXXh
R32C/111 Group
Table 4.10
4. Special Function Registers (SFRs)
SFR List (10)
Address
Register
0001D0h
0001D1h
0001D2h
0001D3h
0001D4h UART6 Special Mode Register 4
0001D5h UART6 Special Mode Register 3
0001D6h UART6 Special Mode Register 2
0001D7h UART6 Special Mode Register
0001D8h UART6 Transmit/Receive Mode Register
0001D9h UART6 Bit Rate Register
0001DAh UART6 Transmit Buffer Register
0001DBh
0001DCh UART6 Transmit/Receive Control Register 0
0001DDh UART6 Transmit/Receive Control Register 1
0001DEh UART6 Receive Buffer Register
0001DFh
0001E0h UART7 Transmit/Receive Mode Register
0001E1h UART7 Bit Rate Register
0001E2h UART7 Transmit Buffer Register
0001E3h
0001E4h UART7 Transmit/Receive Control Register 0
0001E5h UART7 Transmit/Receive Control Register 1
0001E6h UART7 Receive Buffer Register
0001E7h
0001E8h UART8 Transmit/Receive Mode Register
0001E9h UART8 Bit Rate Register
0001EAh UART8 Transmit Buffer Register
0001EBh
0001ECh UART8 Transmit/Receive Control Register 0
0001EDh UART8 Transmit/Receive Control Register 1
0001EEh UART8 Receive Buffer Register
0001EFh
0001F0h UART7, UART8 Transmit/Receive Control Register 2
0001F1h
0001F2h
0001F3h
0001F4h
0001F5h
0001F6h
0001F7h
0001F8h
0001F9h
0001FAh
0001FBh
0001FCh
0001FDh
0001FEh
0001FFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 45 of 99
Symbol
Reset Value
U6SMR4
U6SMR3
U6SMR2
U6SMR
U6MR
U6BRG
U6TB
00h
00h
00h
00h
00h
XXh
XXXXh
U6C0
U6C1
U6RB
0000 1000b
0000 0010b
XXXXh
U7MR
U7BRG
U7TB
00h
XXh
XXXXh
U7C0
U7C1
U7RB
00X0 1000b
XXXX 0010b
XXXXh
U8MR
U8BRG
U8TB
00h
XXh
XXXXh
U8C0
U8C1
U8RB
00X0 1000b
XXXX 0010b
XXXXh
U78CON
X000 0000b
R32C/111 Group
Table 4.11
4. Special Function Registers (SFRs)
SFR List (11)
Address
Register
000200h to
0002BFh
0002C0h X0 Register/Y0 Register
0002C1h
0002C2h X1 Register/Y1 Register
0002C3h
0002C4h X2 Register/Y2 Register
0002C5h
0002C6h X3 Register/Y3 Register
0002C7h
0002C8h X4 Register/Y4 Register
0002C9h
0002CAh X5 Register/Y5 Register
0002CBh
0002CCh X6 Register/Y6 Register
0002CDh
0002CEh X7 Register/Y7 Register
0002CFh
0002D0h X8 Register/Y8 Register
0002D1h
0002D2h X9 Register/Y9 Register
0002D3h
0002D4h X10 Register/Y10 Register
0002D5h
0002D6h X11 Register/Y11 Register
0002D7h
0002D8h X12 Register/Y12 Register
0002D9h
0002DAh X13 Register/Y13 Register
0002DBh
0002DCh X14 Register/Y14 Register
0002DDh
0002DEh X15 Register/Y15 Register
0002DFh
0002E0h XY Control Register
0002E1h
0002E2h
0002E3h
0002E4h UART1 Special Mode Register 4
0002E5h UART1 Special Mode Register 3
0002E6h UART1 Special Mode Register 2
0002E7h UART1 Special Mode Register
0002E8h UART1 Transmit/Receive Mode Register
0002E9h UART1 Bit Rate Register
0002EAh UART1 Transmit Buffer Register
0002EBh
0002ECh UART1 Transmit/Receive Control Register 0
0002EDh UART1 Transmit/Receive Control Register 1
0002EEh UART1 Receive Buffer Register
0002EFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 46 of 99
Symbol
Reset Value
X0R/Y0R
XXXXh
X1R/Y1R
XXXXh
X2R/Y2R
XXXXh
X3R/Y3R
XXXXh
X4R/Y4R
XXXXh
X5R/Y5R
XXXXh
X6R/Y6R
XXXXh
X7R/Y7R
XXXXh
X8R/Y8R
XXXXh
X9R/Y9R
XXXXh
X10R/Y10R
XXXXh
X11R/Y11R
XXXXh
X12R/Y12R
XXXXh
X13R/Y13R
XXXXh
X14R/Y14R
XXXXh
X15R/Y15R
XXXXh
XYC
XXXX XX00b
U1SMR4
U1SMR3
U1SMR2
U1SMR
U1MR
U1BRG
U1TB
00h
00h
00h
00h
00h
XXh
XXXXh
U1C0
U1C1
U1RB
0000 1000b
0000 0010b
XXXXh
R32C/111 Group
Table 4.12
4. Special Function Registers (SFRs)
SFR List (12)
Address
Register
0002F0h
0002F1h
0002F2h
0002F3h
0002F4h UART4 Special Mode Register 4
0002F5h UART4 Special Mode Register 3
0002F6h UART4 Special Mode Register 2
0002F7h UART4 Special Mode Register
0002F8h UART4 Transmit/Receive Mode Register
0002F9h UART4 Bit Rate Register
0002FAh UART4 Transmit Buffer Register
0002FBh
0002FCh UART4 Transmit/Receive Control Register 0
0002FDh UART4 Transmit/Receive Control Register 1
0002FEh UART4 Receive Buffer Register
0002FFh
000300h Count Start Register for Timers B3, B4 and B5
000301h
000302h Timer A1-1 Register
000303h
000304h Timer A2-1 Register
000305h
000306h Timer A4-1 Register
000307h
000308h Three-phase PWM Control Register 0
000309h Three-phase PWM Control Register 1
00030Ah Three-phase Output Buffer Register 0
00030Bh Three-phase Output Buffer Register 1
00030Ch Dead Time Timer
00030Dh Timer B2 Interrupt Generating Frequency Set Counter
00030Eh
00030Fh
000310h Timer B3 Register
000311h
000312h Timer B4 Register
000313h
000314h Timer B5 Register
000315h
000316h
000317h
000318h
000319h
00031Ah
00031Bh Timer B3 Mode Register
00031Ch Timer B4 Mode Register
00031Dh Timer B5 Mode Register
00031Eh
00031Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 47 of 99
Symbol
Reset Value
U4SMR4
U4SMR3
U4SMR2
U4SMR
U4MR
U4BRG
U4TB
00h
00h
00h
00h
00h
XXh
XXXXh
U4C0
U4C1
U4RB
0000 1000b
0000 0010b
XXXXh
TBSR
000X XXXXb
TA11
XXXXh
TA21
XXXXh
TA41
XXXXh
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
00h
00h
XX11 1111b
XX11 1111b
XXh
XXh
TB3
XXXXh
TB4
XXXXh
TB5
XXXXh
TB3MR
TB4MR
TB5MR
00XX 0000b
00XX 0000b
00XX 0000b
R32C/111 Group
Table 4.13
4. Special Function Registers (SFRs)
SFR List (13)
Address
Register
000320h
000321h
000322h
000323h
000324h UART3 Special Mode Register 4
000325h UART3 Special Mode Register 3
000326h UART3 Special Mode Register 2
000327h UART3 Special Mode Register
000328h UART3 Transmit/Receive Mode Register
000329h UART3 Bit Rate Register
00032Ah UART3 Transmit Buffer Register
00032Bh
00032Ch UART3 Transmit/Receive Control Register 0
00032Dh UART3 Transmit/Receive Control Register 1
00032Eh UART3 Receive Buffer Register
00032Fh
000330h
000331h
000332h
000333h
000334h UART2 Special Mode Register 4
000335h UART2 Special Mode Register 3
000336h UART2 Special Mode Register 2
000337h UART2 Special Mode Register
000338h UART2 Transmission/Receive Mode Register
000339h UART2 Bit Rate Register
00033Ah UART2 Transmit Buffer Register
00033Bh
00033Ch UART2 Transmit/Receive Control Register 0
00033Dh UART2 Transmit/Receive Control Register 1
00033Eh UART2 Receive Buffer Register
00033Fh
000340h Count Start Register
000341h Clock Prescaler Reset Register
000342h One-shot Start Register
000343h Trigger Select Register
000344h Increment/Decrement Counting Select Register
000345h
000346h Timer A0 Register
000347h
000348h Timer A1 Register
000349h
00034Ah Timer A2 Register
00034Bh
00034Ch Timer A3 Register
00034Dh
00034Eh Timer A4 Register
00034Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 48 of 99
Symbol
Reset Value
U3SMR4
U3SMR3
U3SMR2
U3SMR
U3MR
U3BRG
U3TB
00h
00h
00h
00h
00h
XXh
XXXXh
U3C0
U3C1
U3RB
0000 1000b
0000 0010b
XXXXh
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
00h
00h
00h
00h
00h
XXh
XXXXh
U2C0
U2C1
U2RB
0000 1000b
0000 0010b
XXXXh
TABSR
CPSRF
ONSF
TRGSR
UDF
00h
0XXX XXXXb
00h
00h
0000 0000b
TA0
XXXXh
TA1
XXXXh
TA2
XXXXh
TA3
XXXXh
TA4
XXXXh
R32C/111 Group
Table 4.14
4. Special Function Registers (SFRs)
SFR List (14)
Address
Register
000350h Timer B0 Register
000351h
000352h Timer B1 Register
000353h
000354h Timer B2 Register
000355h
000356h Timer A0 Mode Register
000357h Timer A1 Mode Register
000358h Timer A2 Mode Register
000359h Timer A3 Mode Register
00035Ah Timer A4 Mode Register
00035Bh Timer B0 Mode Register
00035Ch Timer B1 Mode Register
00035Dh Timer B2 Mode Register
00035Eh Timer B2 Special Mode Register
00035Fh Count Source Prescaler Register
000360h
000361h
000362h
000363h
000364h UART0 Special Mode Register 4
000365h UART0 Special Mode Register 3
000366h UART0 Special Mode Register 2
000367h UART0 Special Mode Register
000368h UART0 Transmit/Receive Mode Register
000369h UART0 Bit Rate Register
00036Ah UART0 Transmit Buffer Register
00036Bh
00036Ch UART0 Transmit/Receive Control Register 0
00036Dh UART0 Transmit/Receive Control Register 1
00036Eh UART0 Receive Buffer Register
00036Fh
000370h
000371h
000372h
000373h
000374h
000375h
000376h
000377h
000378h
000379h
00037Ah
00037Bh
00037Ch CRC Data Register
00037Dh
00037Eh CRC Input Register
00037Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 49 of 99
TB0
Symbol
Reset Value
XXXXh
TB1
XXXXh
TB2
XXXXh
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
TCSPR
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
00XX 0000b
00XX 0000b
00XX 0000b
XXXX XXX0b
0000 0000b
U0SMR4
U0SMR3
U0SMR2
U0SMR
U0MR
U0BRG
U0TB
00h
00h
00h
00h
00h
XXh
XXXXh
U0C0
U0C1
U0RB
0000 1000b
0000 0010b
XXXXh
CRCD
XXXXh
CRCIN
XXh
R32C/111 Group
Table 4.15
4. Special Function Registers (SFRs)
SFR List (15)
Address
Register
000380h A/D0 Register 0
000381h
000382h A/D0 Register 1
000383h
000384h A/D0 Register 2
000385h
000386h A/D0 Register 3
000387h
000388h A/D0 Register 4
000389h
00038Ah A/D0 Register 5
00038Bh
00038Ch A/D0 Register 6
00038Dh
00038Eh A/D0 Register 7
00038Fh
000390h
000391h
000392h A/D0 Control Register 4
000393h
000394h A/D0 Control Register 2
000395h A/D0 Control Register 3
000396h A/D0 Control Register 0
000397h A/D0 Control Register 1
000398h D/A Register 0
000399h
00039Ah D/A Register 1
00039Bh
00039Ch D/A Control Register
00039Dh
00039Eh
00039Fh
0003A0h
0003A1h
0003A2h
0003A3h
0003A4h
0003A5h
0003A6h
0003A7h
0003A8h
0003A9h
0003AAh
0003ABh
0003ACh
0003ADh
0003AEh
0003AFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 50 of 99
AD00
Symbol
Reset Value
00XXh
AD01
00XXh
AD02
00XXh
AD03
00XXh
AD04
00XXh
AD05
00XXh
AD06
00XXh
AD07
00XXh
AD0CON4
XXXX 00XXb
AD0CON2
AD0CON3
AD0CON0
AD0CON1
DA0
X00X X000b
XXXX X000b
00h
00h
XXh
DA1
XXh
DACON
XXXX XX00b
R32C/111 Group
Table 4.16
4. Special Function Registers (SFRs)
SFR List (16)
Address
Register
0003B0h
0003B1h
0003B2h
0003B3h
0003B4h
0003B5h
0003B6h
0003B7h
0003B8h
0003B9h
0003BAh
0003BBh
0003BCh
0003BDh
0003BEh
0003BFh
0003C0h Port P0 Register
0003C1h Port P1 Register
0003C2h Port P0 Direction Register
0003C3h Port P1 Direction Register
0003C4h Port P2 Register
0003C5h Port P3 Register
0003C6h Port P2 Direction Register
0003C7h Port P3 Direction Register
0003C8h Port P4 Register
0003C9h Port P5 Register
0003CAh Port P4 Direction Register
0003CBh Port P5 Direction Register
0003CCh Port P6 Register
0003CDh Port P7 Register
0003CEh Port P6 Direction Register
0003CFh Port P7 Direction Register
0003D0h Port P8 Register
0003D1h Port P9 Register
0003D2h Port P8 Direction Register
0003D3h Port P9 Direction Register
0003D4h Port P10 Register
0003D5h
0003D6h Port P10 Direction Register
0003D7h
0003D8h
0003D9h
0003DAh
0003DBh
0003DCh
0003DDh
0003DEh
0003DFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 51 of 99
Symbol
Reset Value
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
XXh
XXh
0000 0000b
0000 0000b
XXh
XXh
0000 0000b
0000 0000b
XXh
XXh
0000 0000b
0000 0000b
XXh
XXh
0000 0000b
0000 0000b
XXh
XXh
00X0 0000b
0000 0000b
XXh
PD10
0000 0000b
R32C/111 Group
Table 4.17
4. Special Function Registers (SFRs)
SFR List (17)
Address
Register
0003E0h
0003E1h
0003E2h
0003E3h
0003E4h
0003E5h
0003E6h
0003E7h
0003E8h
0003E9h
0003EAh
0003EBh
0003ECh
0003EDh
0003EEh
0003EFh
0003F0h Pull-up Control Register 0
0003F1h Pull-up Control Register 1
0003F2h Pull-up Control Register 2
0003F3h Pull-up Control Register 3
0003F4h
0003F5h
0003F6h
0003F7h
0003F8h
0003F9h
0003FAh
0003FBh
0003FCh
0003FDh
0003FEh
0003FFh Port Control Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 52 of 99
Symbol
Reset Value
PUR0
PUR1
PUR2
PUR3
0000 0000b
XXXX 0000b
0000 0000b
XXXX XX00b
PCR
XXXX XXX0b
R32C/111 Group
Table 4.18
4. Special Function Registers (SFRs)
SFR List (18)
Address
Register
040000h Flash Memory Control Register 0
040001h Flash Memory Status Register 0
040002h
040003h
040004h
040005h
040006h
040007h
040008h Flash Register Protection Unlock Register 0
040009h Flash Memory Control Register 1
04000Ah Block Protect Bit Monitor Register 0
04000Bh Block Protect Bit Monitor Register 1
04000Ch
04000Dh
04000Eh
04000Fh
040010h
040011h
040012h
040013h
040014h
040015h
040016h
040017h
040018h
040019h
04001Ah
04001Bh
04001Ch
04001Dh
04001Eh
04001Fh
040020h PLL Control Register 0
040021h PLL Control Register 1
040022h
040023h
040024h
040025h
040026h
040027h
040028h
040029h
04002Ah
04002Bh
04002Ch
04002Dh
04002Eh
04002Fh
X: Undefined
Blanks are reserved. No access is allowed.
Note:
1. The status of protect bit of each block in flash memory is reflected.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 53 of 99
Symbol
FMR0
FMSR0
Reset Value
0X01 XX00b
1000 0000b
FPR0
FMR1
FBPM0
FBPM1
00h
0000 0010b
??X? ????b (1)
XXX? ????b (1)
PLC0
PLC1
0000 0001b
0001 1111b
R32C/111 Group
Table 4.19
4. Special Function Registers (SFRs)
SFR List (19)
Address
Register
040030h to
04003Fh
040040h
040041h
040042h
040043h
040044h Processor Mode Register 0 (1)
040045h
040046h System Clock Control Register 0
040047h System Clock Control Register 1
040048h Processor Mode Register 3
040049h
04004Ah Protect Register
04004Bh
04004Ch Protect Register 3
04004Dh Oscillator Stop Detection Register
04004Eh
04004Fh
040050h
040051h
040052h
040053h Processor Mode Register 2
040054h Chip Select Output Pin Setting Register 0
040055h Chip Select Output Pin Setting Register 1
040056h
040057h
040058h
040059h
04005Ah Low Speed Mode Clock Control Register
04005Bh
04005Ch
04005Dh
04005Eh
04005Fh
040060h Voltage Regulator Control Register
040061h
040062h Low Voltage Detector Control Register
040063h
040064h Detection Voltage Configuration Register
040065h
040066h
040067h
040068h to
040093h
X: Undefined
Blanks are reserved. No access is allowed.
Symbol
Reset Value
PM0
1000 0000b
(CNVSS pin = Low)
0000 0011b
(CNVSS pin = High)
CM0
CM1
PM3
0000 1000b
0010 0000b
00h
PRCR
XXXX X000b
PRCR3
CM2
0000 0000b
00h
PM2
CSOP0
CSOP1
00h
1000 XXXXb
01X0 XXXXb
CM3
XXXX XX00b
VRCR
0000 0000b
LVDC
0000 XX00b
DVCR
0000 XXXXb
Note:
1. The value in the PM0 register remains unchanged even after a software reset or watchdog timer reset.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 54 of 99
R32C/111 Group
Table 4.20
4. Special Function Registers (SFRs)
SFR List (20)
Address
Register
040094h
040095h
040096h
040097h Three-phase Output Buffer Control Register
040098h Input Function Select Register 0
040099h
04009Ah Input Function Select Register 2
04009Bh Input Function Select Register 3
04009Ch
04009Dh
04009Eh
04009Fh Input Function Select Register 7 (3)
0400A0h Port P0_0 Function Select Register
0400A1h Port P1_0 Function Select Register
0400A2h Port P0_1 Function Select Register
0400A3h Port P1_1 Function Select Register
0400A4h Port P0_2 Function Select Register
0400A5h Port P1_2 Function Select Register
0400A6h Port P0_3 Function Select Register
0400A7h Port P1_3 Function Select Register
0400A8h Port P0_4 Function Select Register
0400A9h Port P1_4 Function Select Register
0400AAh Port P0_5 Function Select Register
0400ABh Port P1_5 Function Select Register
0400ACh Port P0_6 Function Select Register
0400ADh Port P1_6 Function Select Register
0400AEh Port P0_7 Function Select Register
0400AFh Port P1_7 Function Select Register
0400B0h Port P2_0 Function Select Register
0400B1h Port P3_0 Function Select Register
0400B2h Port P2_1 Function Select Register
0400B3h Port P3_1 Function Select Register
0400B4h Port P2_2 Function Select Register
0400B5h Port P3_2 Function Select Register
0400B6h Port P2_3 Function Select Register
0400B7h Port P3_3 Function Select Register
0400B8h Port P2_4 Function Select Register
0400B9h Port P3_4 Function Select Register
0400BAh Port P2_5 Function Select Register
0400BBh Port P3_5 Function Select Register
0400BCh Port P2_6 Function Select Register
0400BDh Port P3_6 Function Select Register
0400BEh Port P2_7 Function Select Register
0400BFh Port P3_7 Function Select Register
X: Undefined
Blanks are reserved. No access is allowed.
Symbol
Reset Value
IOBC
IFS0
0XXX XXXXb
X000 0000b (1)
IFS2
IFS3
0000 00X0b (2)
XXXX XX00b
IFS7
P0_0S
P1_0S
P0_1S
P1_1S
P0_2S
P1_2S
P0_3S
P1_3S
P0_4S
P1_4S
P0_5S
P1_5S
P0_6S
P1_6S
P0_7S
P1_7S
P2_0S
P3_0S
P2_1S
P3_1S
P2_2S
P3_2S
P2_3S
P3_3S
P2_4S
P3_4S
P2_5S
P3_5S
P2_6S
P3_6S
P2_7S
P3_7S
XXXX XX0Xb
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
Notes:
1. The reset value is 0000 0000b in the 80-/64-pin package.
2. The reset value is 0000 000Xb in the 80-/64-pin package.
3. This register is provided for the 80-64/pin package. No access is allowed in the 100-pin package.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 55 of 99
R32C/111 Group
Table 4.21
4. Special Function Registers (SFRs)
SFR List (21)
Address
Register
0400C0h Port P4_0 Function Select Register
0400C1h Port P5_0 Function Select Register
0400C2h Port P4_1 Function Select Register
0400C3h Port P5_1 Function Select Register
0400C4h Port P4_2 Function Select Register
0400C5h Port P5_2 Function Select Register
0400C6h Port P4_3 Function Select Register
0400C7h Port P5_3 Function Select Register
0400C8h Port P4_4 Function Select Register
0400C9h Port P5_4 Function Select Register
0400CAh Port P4_5 Function Select Register
0400CBh Port P5_5 Function Select Register
0400CCh Port P4_6 Function Select Register
0400CDh Port P5_6 Function Select Register
0400CEh Port P4_7 Function Select Register
0400CFh Port P5_7 Function Select Register
0400D0h Port P6_0 Function Select Register
0400D1h Port P7_0 Function Select Register
0400D2h Port P6_1 Function Select Register
0400D3h Port P7_1 Function Select Register
0400D4h Port P6_2 Function Select Register
0400D5h Port P7_2 Function Select Register
0400D6h Port P6_3 Function Select Register
0400D7h Port P7_3 Function Select Register
0400D8h Port P6_4 Function Select Register
0400D9h Port P7_4 Function Select Register
0400DAh Port P6_5 Function Select Register
0400DBh Port P7_5 Function Select Register
0400DCh Port P6_6 Function Select Register
0400DDh Port P7_6 Function Select Register
0400DEh Port P6_7 Function Select Register
0400DFh Port P7_7 Function Select Register
0400E0h Port P8_0 Function Select Register
0400E1h
0400E2h Port P8_1 Function Select Register
0400E3h
0400E4h Port P8_2 Function Select Register
0400E5h
0400E6h Port P8_3 Function Select Register
0400E7h Port P9_3 Function Select Register
0400E8h Port P8_4 Function Select Register
0400E9h Port P9_4 Function Select Register
0400EAh
0400EBh Port P9_5 Function Select Register
0400ECh Port P8_6 Function Select Register
0400EDh Port P9_6 Function Select Register
0400EEh Port P8_7 Function Select Register
0400EFh Port P9_7 Function Select Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 56 of 99
Symbol
P4_0S
P5_0S
P4_1S
P5_1S
P4_2S
P5_2S
P4_3S
P5_3S
P4_4S
P5_4S
P4_5S
P5_5S
P4_6S
P5_6S
P4_7S
P5_7S
P6_0S
P7_0S
P6_1S
P7_1S
P6_2S
P7_2S
P6_3S
P7_3S
P6_4S
P7_4S
P6_5S
P7_5S
P6_6S
P7_6S
P6_7S
P7_7S
P8_0S
Reset Value
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
P8_1S
XXXX X000b
P8_2S
XXXX X000b
P8_3S
P9_3S
P8_4S
P9_4S
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
P9_5S
P8_6S
P9_6S
P8_7S
P9_7S
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
XXXX X000b
R32C/111 Group
Table 4.22
4. Special Function Registers (SFRs)
SFR List (22)
Address
Register
0400F0h Port P10_0 Function Select Register
0400F1h
0400F2h Port P10_1 Function Select Register
0400F3h
0400F4h Port P10_2 Function Select Register
0400F5h
0400F6h Port P10_3 Function Select Register
0400F7h
0400F8h Port P10_4 Function Select Register
0400F9h
0400FAh Port P10_5 Function Select Register
0400FBh
0400FCh Port P10_6 Function Select Register
0400FDh
0400FEh Port P10_7 Function Select Register
0400FFh
040100h
040101h
040102h
040103h
040104h
040105h
040106h
040107h
040108h
040109h
04010Ah
04010Bh
04010Ch
04010Dh
04010Eh
04010Fh
040110h
040111h
040112h
040113h
040114h
040115h
040116h
040117h
040118h
040119h
04011Ah
04011Bh
04011Ch
04011Dh
04011Eh
04011Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 57 of 99
Symbol
P10_0S
Reset Value
0XXX X000b
P10_1S
0XXX X000b
P10_2S
0XXX X000b
P10_3S
0XXX X000b
P10_4S
0XXX X000b
P10_5S
0XXX X000b
P10_6S
0XXX X000b
P10_7S
0XXX X000b
R32C/111 Group
Table 4.23
4. Special Function Registers (SFRs)
SFR List (23)
Address
Register
040120h to
04403Fh
044040h
044041h
044042h
044043h
044044h
044045h
044046h
044047h
044048h
044049h
04404Ah
04404Bh
04404Ch
04404Dh
04404Eh Watchdog Timer Start Register
04404Fh Watchdog Timer Control Register
044050h
044051h
044052h
044053h
044054h
044055h
044056h
044057h
044058h
044059h
04405Ah
04405Bh
04405Ch
04405Dh
04405Eh
04405Fh Protect Register 2
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 58 of 99
Symbol
Reset Value
WDTS
WDC
XXXX XXXXb
000X XXXXb
PRCR2
0XXX XXXXb
R32C/111 Group
Table 4.24
4. Special Function Registers (SFRs)
SFR List (24)
Address
Register
044060h
044061h
044062h
044063h
044064h
044065h
044066h
044067h
044068h
044069h
04406Ah
04406Bh
04406Ch
04406Dh External Interrupt Source Select Register 1
04406Eh
04406Fh External Interrupt Source Select Register 0
044070h DMA0 Request Source Select Register 2
044071h DMA1 Request Source Select Register 2
044072h DMA2 Request Source Select Register 2
044073h DMA3 Request Source Select Register 2
044074h
044075h
044076h
044077h
044078h DMA0 Request Source Select Register
044079h DMA1 Request Source Select Register
04407Ah DMA2 Request Source Select Register
04407Bh DMA3 Request Source Select Register
04407Ch
04407Dh Wake-up IPL Setting Register 2
04407Eh
04407Fh Wake-up IPL Setting Register 1
044080h
044081h
044082h
044083h
044084h
044085h
044086h
044087h
044088h
044089h
04408Ah
04408Bh
04408Ch
04408Dh
04408Eh
04408Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 59 of 99
Symbol
Reset Value
IFSR1
X0XX XXXXb
IFSR0
DM0SL2
DM1SL2
DM2SL2
DM3SL2
0000 0000b
XX00 0000b
XX00 0000b
XX00 0000b
XX00 0000b
DM0SL
DM1SL
DM2SL
DM3SL
XXX0 0000b
XXX0 0000b
XXX0 0000b
XXX0 0000b
RIPL2
XX0X 0000b
RIPL1
XX0X 0000b
R32C/111 Group
5.
5. Electrical Characteristics
Electrical Characteristics
Table 5.1
Absolute Maximum Ratings (1)
Symbol
Characteristic
Condition
Value (2)
Unit
VCC1 = AVCC
-0.3 to 6.0
V
—
-0.3 to VCC1
V
VCC1 = AVCC
-0.3 to 6.0
V
XIN, RESET, CNVSS, NSD, VREF,
P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_7, P9_1, P9_3 to P9_7,
P10_0 to P10_7 (3)
-0.3 to VCC1 +0.3
V
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7,P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7 (3)
-0.3 to VCC2 +0.3
V
-0.3 to 6.0
V
XOUT, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7,
P9_3 to P9_7, P10_0 to P10_7 (3)
-0.3 to VCC1 +0.3
V
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7,P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7 (3)
-0.3 to VCC2 +0.3
V
-0.3 to 6.0
V
500
mW
Operating temperature range
-40 to 85
°C
Storage temperature range
-65 to 150
°C
VCC1, VCC2 Supply voltage
VCC2
Supply voltage
AVCC
Analog supply voltage
VI
Input voltage
P7_0, P7_1
Output
voltage
VO
P7_0, P7_1
Power consumption
Pd
—
Tstg
Ta = 25°C
Notes:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. The VCC2 pin is available in the 100-pin package only. It should be considered as VCC1 in the 80-/64pin package.
3. Ports P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, and P9_5 to P9_7 are available in the 100- and
80-pin packages. Ports P4, P5, P9_1, and P9_4 are available in the 100-pin package only.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 60 of 99
R32C/111 Group
Table 5.2
5. Electrical Characteristics
Operating Conditions (1) (1)
Symbol
Characteristic
Value (2)
Min.
Typ.
Max.
3.0
5.0
5.5
Unit
VCC1,
VCC2
Digital supply voltage (VCC1 ≥ VCC2)
AVCC
Analog supply voltage
VREF
Reference voltage
VSS
Digital ground voltage
0
V
AVSS
Analog ground voltage
0
V
dVCC1/dt VCC1 ramp up rate (VCC1 < 2.0 V)
VIH
VIL
Topr
High level
input
voltage
Low level
input
voltage
VCC1
V
VCC1
3.0
V
0.05
V
V/ms
P2_0 to P2_7,P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7 (4)
0.8 × VCC2
VCC2
V
XIN, RESET, CNVSS, NSD, P6_0 to P6_7,
P7_2 to P7_7, P8_0 to P8_7 (3), P9_1,
P9_3 to P9_7, P10_0 to P10_7 (4)
0.8 × VCC1
VCC1
V
P7_0, P7_1
0.8 × VCC1
6.0
V
P0_0 to P0_7, P1_0 to P1_7
(in single-chip mode) (4)
0.8 × VCC2
VCC2
V
P0_0 to P0_7, P1_0 to P1_7 (in memory
0.5 × VCC2
expansion mode or microprocessor mode) (4, 5)
VCC2
V
P2_0 to P2_7,P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7 (4)
0
0.2 × VCC2
V
XIN, RESET, CNVSS, NSD, P6_0 to P6_7,
P7_0 to P7_7, P8_0 to P8_7 (3), P9_1,
P9_3 to P9_7, P10_0 to P10_7 (4)
0
0.2 × VCC1
V
P0_0 to P0_7, P1_0 to P1_7
(in single-chip mode) (4)
0
0.2 × VCC2
V
P0_0 to P0_7, P1_0 to P1_7 (in memory
expansion mode or microprocessor mode) (4, 5)
0
0.16 ×
VCC2
V
-20
85
°C
-40
85
°C
Operating Version N
temperature Version D
range
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. The VCC2 pin is available in the 100-pin package only. It should be considered as VCC1 in the 80-/64pin package.
3. VIH and VIL for P8_7 are specified for P8_7 as a programmable port. These values are not applicable
to P8_7 as XCIN.
4. Ports P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, and P9_5 to P9_7 are available in the 100- and
80-pin packages. Ports P4, P5, P9_1, and P9_4 are available in the 100-pin package only.
5. Memory expansion mode and microprocessor mode are available in the 100-pin package only.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 61 of 99
R32C/111 Group
Table 5.3
Symbol
CVDC
5. Electrical Characteristics
Operating Conditions (2)
(VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Value (2)
Characteristic
Decoupling capacitance for voltage
regulator
Min. Typ. Max.
Inter-pin voltage: 1.5 V
2.4
10.0
Unit
µF
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. This value should be satisfied with due consideration of every condition as follows: operating
temperature, DC bias, aging, etc.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 62 of 99
R32C/111 Group
Table 5.4
5. Electrical Characteristics
Operating Conditions (3)
(VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol
Characteristic
IOH(peak) High level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
peak output P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
current (2) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_3 to P9_7, P10_0 to P10_7 (3)
Value
Min.
Typ.
Max.
Unit
-10.0
mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_3 to P9_7, P10_0 to P10_7 (3)
-5.0
mA
IOL(peak) Low level
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
peak output P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
current (2) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_3 to P9_7, P10_0 to P10_7 (3)
10.0
mA
5.0
mA
IOH(avg)
IOL(avg)
High level
average
output
current (4)
Low level
average
output
current (4)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_3 to P9_7, P10_0 to P10_7 (3)
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. The following conditions should be satisfied:
• The sum of IOL(peak) of ports P0, P1, P2, P8_6, P8_7, P9, and P10 is 80 mA or less.
• The sum of IOL(peak) of ports P3, P4, P5, P6, P7, and P8_0 to P8_4 is 80 mA or less.
• The sum of IOH(peak) of ports P0, P1, and P2 is -40 mA or less.
• The sum of IOH(peak) of ports P8_6, P8_7, P9, and P10 is -40 mA or less.
• The sum of IOH(peak) of ports P3, P4, and P5 is -40 mA or less.
• The sum of IOH(peak) of ports P6, P7, and P8_0 to P8_4 is -40 mA or less.
3. Ports P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, and P9_5 to P9_7 are available in the 100- and
80-pin packages. Ports P4, P5, and P9_4 are available in the 100-pin package only.
4. Average value within 100 ms.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 63 of 99
R32C/111 Group
Table 5.5
5. Electrical Characteristics
Operating Conditions (4)
(VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol
Value
Characteristic
Min.
Typ.
Max.
Unit
f(XIN)
Main clock oscillator frequency
4
16
MHz
f(XRef)
Reference clock frequency
2
4
MHz
f(PLL)
PLL clock oscillator frequency
96
128
MHz
f(Base)
Base clock frequency
50
MHz
tc(Base)
Base clock cycle time
f(CPU)
CPU operating frequency
tc(CPU)
CPU clock cycle time
f(BCLK)
Peripheral bus clock operating frequency
tc(BCLK)
Peripheral bus clock cycle time
f(PER)
Peripheral clock source frequency
f(XCIN)
Sub clock oscillator frequency
20
50
20
40
Base clock
(Internal signal)
t c(CPU)
CPU clock
(Internal signal)
t c(BCLK)
Figure 5.1
Clock Cycle Time
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 64 of 99
MHz
ns
32.768
t c(Base)
MHz
ns
25
Note:
1. The device is operationally guaranteed under these operating conditions.
Peripheral bus clock
(Internal signal)
ns
32
MHz
62.5
kHz
R32C/111 Group
Table 5.6
5. Electrical Characteristics
Operating Conditions (5)
(VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol
Vr(VCC1)
Vr(VCC2)
Value
Characteristic
Allowable ripple voltage
Allowable ripple voltage
dVr(VCC1)/dt Ripple voltage gradient
dVr(VCC2)/dt Ripple voltage gradient
Min.
Typ.
Max.
Unit
VCC1 = 5.0 V
0.5
Vp-p
VCC1 = 3.0 V
0.3
Vp-p
VCC2 = 5.0 V
0.5
Vp-p
VCC2 = 3.0 V
0.3
Vp-p
VCC1 = 5.0 V
±0.3
V/ms
VCC1 = 3.0 V
±0.3
V/ms
VCC2 = 5.0 V
±0.3
V/ms
VCC2 = 3.0 V
±0.3
V/ms
fr(VCC1)
Allowable ripple frequency
10
kHz
fr(VCC2)
Allowable ripple frequency
10
kHz
Note:
1. The device is operationally guaranteed under these operating conditions.
1 / f r(VCC1)
VCC1
or
VCC2
Figure 5.2
Ripple Waveform
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 65 of 99
or
1 / f r(VCC2)
Vr(VCC1)
or
Vr(VCC2)
R32C/111 Group
Table 5.7
Symbol
VRDR
5. Electrical Characteristics
RAM Electrical Characteristics
(VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Characteristic
RAM data retention voltage (1)
Measurement
condition
in stop mode
Value
Min.
Typ.
Max.
2.0
Unit
V
Note:
1. The value listed in the table is the minimum VCC1 to retain RAM data.
Table 5.8
Flash Memory Electrical Characteristics
(VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
—
—
—
Min.
Programming and erasure endurance of flash Program area
memory (1)
Data area
4-word program time
Lock bit-program time
Block erasure time
—
—
Value
Characteristic
Data retention (2)
Typ.
Max.
Unit
1000
times
10000
times
Program area
150
900
µs
Data area
300
1700
µs
Program area
70
500
µs
Data area
140
1000
µs
4 Kbyte block
0.12
3.0
s
32 Kbyte block
0.17
3.0
s
64 Kbyte block
0.20
3.0
s
Ta = 55°C (3)
10
years
Notes:
1. Program/erase definition
This value represents the number of erasures per block.
If the flash memory is programmed/erased n times, each block can be erased n times.
i.e. If 4-word write is performed in 512 different addresses in the block A of 4 Kbyte and then the
block is erased, it is considered the programming/erasure is performed just once.
However a write in the same address more than once for one erasure is disabled. (overwrite
disabled).
2. The data retention time includes the periods when the supply voltage is not applied and no clock is
provided.
3. Please contact a Renesas sales office regarding data retention time other than the above.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 66 of 99
R32C/111 Group
Table 5.9
5. Electrical Characteristics
Power Supply Circuit Timing Characteristics
(VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
td(P-R)
Measurement
condition
Characteristic
Value
Min. Typ. Max.
Internal power supply start-up stabilization
time after the main power supply is turned on
t d(P-R)
Internal power supply start-up
stabilization time after the main
power supply is turned on
VCC1
2
Unit
ms
Recommended
operating voltage
t d(P-R)
Supply voltage for
internal logic
PLL oscillatoroutput waveform
Figure 5.3
Power Supply Circuit Timing
Table 5.10
Electrical Characteristics of Voltage Regulator for Internal Logic
(VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
VVDC1
Measurement
condition
Characteristics
Min.
Output voltage
Table 5.11
Symbol
∆Vdet
Typ.
Unit
V
Electrical Characteristics of Low Voltage Detector
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Characteristics
Measurement
condition
Value
Min.
Typ.
Detected voltage error
—
Max.
1.5
Self-consuming current
0
VCC1 = 5.0 V, low
voltage detector enabled
Operation start time of low voltage detector
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 67 of 99
Max.
±0.3
Vdet(R)-Vdet(F) Hysteresis width
td(E-A)
Value
Unit
V
V
4
µA
150
µs
R32C/111 Group
Table 5.12
5. Electrical Characteristics
Electrical Characteristics of Oscillator
(VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
Measurement
condition
Characteristics
fSO(PLL)
PLL clock self-oscillation frequency
tLOCK(PLL)
PLL lock time (1)
tjitter(p-p)
PLL jitter period (p-p)
f(OCO)
On-chip oscillator frequency
Value
Unit
Min.
Typ.
Max.
35
55
80
MHz
1
ms
2.0
ns
250
kHz
62.5
125
Note:
1. This value is applicable only when the main clock oscillation is stable.
Table 5.13
Symbol
Electrical Characteristics of Clock Circuitry
(VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Characteristics
Measurement
condition
Value
Min.
Typ.
Max.
Unit
trec(STOP)
Recovery time from stop mode (1)
225
µs
trec(WAIT)
Recovery time from wait mode to low power mode
225
µs
Note:
1. This recovery time does not include the period until the main clock oscillator is stabilized. The CPU
starts operating before the oscillator is stabilized.
Interrupt for exiting
stop mode
t rec(STOP)
Recovery time from stop mode
Main clock oscillator
output
On-chip oscillator
output
CPU clock
t rec(STOP)
Interrupt for exiting
wait mode
t rec(WAIT)
Recovery time from wait mode
to low power mode
Sub clock oscillator
output
On-chip oscillator
output
CPU clock
t rec(WAIT)
Figure 5.4
Clock Circuit Timing
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 68 of 99
R32C/111 Group
5. Electrical Characteristics
Timing Requirements (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.14
Flash Memory CPU Rewrite Mode Timing
Symbol
Value
Characteristics
Min.
Max.
Unit
tcR
Read cycle time
200
ns
tsu(S-R)
Chip-select setup time for read
200
ns
th(R-S)
Chip-select hold time after read
0
ns
tsu(A-R)
Address setup time for read
200
ns
th(R-A)
Address hold time after read
0
ns
tw(R)
Read pulse width
100
ns
tcW
Write cycle time
200
ns
tsu(S-W)
Chip-select setup time for write
0
ns
th(W-S)
Chip-select hold time after write
30
ns
tsu(A-W)
Address setup time for write
0
ns
th(W-A)
Address hold time after write
30
ns
tw(W)
Write pulse width
50
ns
Read cycle
t cR
t su(S-R)
t h(R-S)
t su(A-R)
t h(R-A)
CS0
A23 to A0, BC0 to BC3
t w(R)
RD
Write cycle
t cW
t su(S-W)
t h(W-S)
t su(A-W)
t h(W-A)
CS0 to CS3
A23 to A0, BC0 to BC3
t w(W)
WR
Figure 5.5
Flash Memory CPU Rewrite Mode Timing
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 69 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.15
Electrical Characteristics (1)
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and f(CPU) = 50 MHz, unless otherwise
noted)
VOH
Min.
IOH = -5 mA
VCC2 -2.0
VCC2
V
IOH = -5 mA
VCC1 -2.0
VCC1
V
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7,P3_0 to P3_7, P4_0 to P4_7, IOH = -200 µA VCC2 -0.3
P5_0 to P5_7 (1)
VCC2
V
VCC1
V
IOL = 5 mA
2.0
V
IOL = 200 µA
0.45
V
Characteristic
High
level
output
voltage
Value (2)
Measurement
condition
Symbol
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7,P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7 (1)
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7
Typ. Max.
Unit
(1)
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7 IOH = -200 µA VCC1 -0.3
(1)
VOL
Low
level
output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7
(1)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7
(1)
Notes:
1. Ports P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, and P9_5 to P9_7 are available in the 100- and
80-pin packages. Ports P4, P5, and P9_4 are available in the 100-pin package only.
2. The VCC2 pin is available in the 100-pin package only. It should be considered as VCC1 in the 80-/64pin package.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 70 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.16
Electrical Characteristics (2) (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and
f(CPU) = 50 MHz, unless otherwise noted)
Symbol
Characteristic
Value
Measurement
Unit
condition
Min. Typ. Max.
VT+ - VT- Hysteresis HOLD, RDY, NMI, INT0 to INT5, KI0 to KI3,
TA0IN to TA4IN, TA0OUT to TA4OUT,
TB0IN to TB5IN, CTS0 to CTS8,
CLK0 to CLK8, RXD0 to RXD8,
SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6,
SRXD0 to SRXD6, ADTRG,
IIO0_0 to IIO0_7, IIO1_0 to IIO1_7, UD0A,
UD0B, UD1A, UD1B, ISCLK2, ISRXD2,
IEIN(1)
RESET
IIH
IIL
0.2
1.0
V
0.2
1.8
V
High level XIN, RESET, CNVSS, NSD,
input
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
current
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_1, P9_3 to P9_7, P10_0 to P10_7 (2)
VI = 5 V
5.0
µA
XIN, RESET, CNVSS, NSD,
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_1, P9_3 to P9_7, P10_0 to P10_7 (2)
VI = 0 V
-5.0
µA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_1, P9_3 to P9_7,
P10_0 to P10_7 (2)
VI = 0 V
170
kΩ
Low level
input
current
RPULLUP Pull-up
resistor
30
50
RfXIN
Feedback XIN
resistor
1.5
MΩ
RfXCIN
Feedback XCIN
resistor
15
MΩ
Notes:
1. Pins CLK4, RXD4, TXD4, SDA4, SCL4, STXD4, and SRXD4 are available in the 100- and 80-pin
package only. Pins TB4IN, CTS4, RTS4, SS4, UART6, and UART7 are available in the 100-pin
package only.
2. Ports P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, and P9_5 to P9_7 are available in the 100- and
80-pin packages. Ports P4, P5, P9_1, and P9_4 are available in the 100-pin package only.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 71 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.17
Symbol
ICC
Electrical Characteristics (3)
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Characte
ristic
Power
supply
current
Measurement condition
Value
Min. Typ. Max.
Unit
In single-chip mode,
output pins are left open
and others are
connected to VSS
f(CPU) = 50 MHz, f(BCLK) = 25 MHz,
f(XIN) = 8 MHz,
Active: XIN, PLL,
Stopped: XCIN, OCO
32
XIN-XOUT
Drive power: low
f(CPU) = fSO(PLL)/24 MHz,
Active: PLL (self-oscillation),
Stopped: XIN, XCIN, OCO
10
mA
XCIN-XCOUT
Drive power: low
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO
1.2
mA
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown
220
µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown
230
µA
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO,
Ta = 25°C, Wait mode
960
1600
µA
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown,
Ta = 25°C, Wait mode
8
140
µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown,
Ta = 25°C, Wait mode
10
150
µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 25°C
5
70
µA
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 72 of 99
45
mA
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.18
Symbol
A/D Conversion Characteristics (VCC1 = VCC2 = AVCC = VREF = 4.2 to 5.5 V,
VSS = AVSS = 0 V, Ta = Topr, and f(BCLK) = 25 MHz, unless otherwise noted)
Characteristic
Measurement condition
Value
Min.
Typ.
Max.
Unit
Resolution
VREF = VCC1
10
Bits
Absolute error
VREF = VCC1 = VCC2 AN_0 to AN_7,
AN0_0 to AN0_7,
=5V
AN2_0 to AN2_7,
ANEX0, ANEX1 (1)
±3
LSB
±7
LSB
±3
LSB
±7
LSB
Differential non-linearity
error
±1
LSB
—
Offset error
±3
LSB
—
Gain error
±3
LSB
20
kΩ
—
—
External op-amp
connection mode
INL
Integral non-linearity
error
VREF = VCC1 = VCC2 AN_0 to AN_7,
AN0_0 to AN0_7,
=5V
AN2_0 to AN2_7,
ANEX0, ANEX1 (1)
External op-amp
connection mode
DNL
RLADDER
Resistor ladder
VREF = VCC1
tCONV
Conversion time
(10 bits)
φAD = 16 MHz, with sample and hold
function
2.06
µs
φAD = 16 MHz, without sample and hold
function
3.69
µs
φAD = 16 MHz, with sample and hold
function
1.75
µs
φAD = 16 MHz, without sample and hold
function
3.06
µs
φAD = 16 MHz
0.188
µs
tCONV
Conversion time
(8 bits)
tSAMP
Sample time
VIA
Analog input voltage
φAD
Operating clock
frequency
without sample and hold function
with sample and hold function
4
0
VREF
V
0.25
16
MHz
1
16
MHz
Note:
1. Pins AN0_4 to AN0_7, ANEX0, and ANEX1 are available in the 100- and 80-pin package only.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 73 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.19
Symbol
D/A Conversion Characteristics (VCC1 = VCC2 = AVCC = VREF = 4.2 to 5.5 V,
VSS = AVSS = 0 V, and Ta = Topr, unless otherwise noted)
Characteristic
—
Resolution
—
Absolute precision
tS
Settling time
RO
Output resistance
IVREF
Reference input current
Measurement condition
Value
Min.
4
(1)
Typ.
10
Max.
Unit
8
Bits
1.0
%
3
µs
20
kΩ
1.5
mA
Note:
1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The
resistor ladder for A/D converter is not considered.
Even when the VCUT bit in the AD0CON1 register is set to 0 (VREF disconnected), IVREF is supplied.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 74 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.20
External Clock Input
Symbol
Value
Characteristic
Min.
Max.
62.5
250
Unit
tc(X)
External clock input period
tw(XH)
External clock input high level pulse width
25
ns
tw(XL)
External clock input low level pulse width
25
ns
tr(X)
External clock input rise time
5
ns
tf(X)
External clock input fall time
5
ns
tw / tc
External clock input duty
60
%
Table 5.21
Symbol
40
ns
External Bus Timing
Characteristic
Value
Min.
Max.
Unit
tsu(D-R)
th(R-D)
Data setup time for read
40
ns
Data hold time after read
0
ns
tdis(R-D)
Data disable time after read
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 75 of 99
0.5 × tc(Base) + 10
ns
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.22
Timer A Input (Counting input in event counter mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
200
ns
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.23
Timer A Input (Gating input in timer mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
400
ns
tw(TAH)
TAiIN input high level pulse width
180
ns
tw(TAL)
TAiIN input low level pulse width
180
ns
Table 5.24
Timer A Input (External trigger input in one-shot timer mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
200
ns
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.25
Timer A Input (External trigger input in pulse-width modulation mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.26
Timer A Input (Increment/decrement count switching input in event counter mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(UP)
TAiOUT input clock period
2000
ns
tw(UPH)
TAiOUT input high level pulse width
1000
ns
tw(UPL)
TAiOUT input low level pulse width
1000
ns
tsu(UP-TIN)
TAiOUT input setup time
400
ns
th(TIN-UP)
TAiOUT input hold time
400
ns
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 76 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.27
Symbol
Timer B Input (Counting input in event counter mode)
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period (one edge counting)
200
ns
tw(TBH)
TBiIN input high level pulse width (one edge counting)
80
ns
tw(TBL)
TBiIN input low level pulse width (one edge counting)
80
ns
tc(TB)
TBiIN input clock period (both edges counting)
200
ns
tw(TBH)
TBiIN input high level pulse width (both edges counting)
80
ns
tw(TBL)
TBiIN input low level pulse width (both edges counting)
80
ns
Table 5.28
Symbol
Timer B Input (Pulse period measure mode)
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period
400
ns
tw(TBH)
TBiIN input high level pulse width
180
ns
tw(TBL)
TBiIN input low level pulse width
180
ns
Table 5.29
Symbol
Timer B Input (Pulse-width measure mode)
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period
400
ns
tw(TBH)
TBiIN input high level pulse width
180
ns
tw(TBL)
TBiIN input low level pulse width
180
ns
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 77 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Timing requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.30
Serial Interface
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(CK)
CLKi input clock period
200
ns
tw(CKH)
CLKi input high level pulse width
80
ns
tw(CKL)
CLKi input low level pulse width
80
ns
tsu(D-C)
RXDi input setup time
80
ns
th(C-D)
RXDi input hold time
90
ns
Table 5.31
A/D Trigger Input
Symbol
Characteristic
Value
Min.
Max.
Unit
tw(ADH)
ADTRG input high level pulse width
Hardware trigger input high level pulse width
3--------φ AD
ns
tw(ADL)
ADTRG input low level pulse width
Hardware trigger input high level pulse width
125
ns
Table 5.32
External Interrupt INTi Input
Symbol
INTi input high level pulse width
tw(INH)
INTi input low level pulse width
tw(INL)
Table 5.33
Value
Characteristic
Min.
Max.
Unit
Edge sensitive
250
ns
Level sensitive
tc(CPU) + 200
ns
Edge sensitive
250
ns
Level sensitive
tc(CPU) + 200
ns
Intelligent I/O
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(ISCLK2)
ISCLK2 input clock period
600
ns
tw(ISCLK2H)
ISCLK2 input high level pulse width
270
ns
tw(ISCLK2L)
ISCLK2 input low level pulse width
270
ns
tsu(RXD-ISCLK2)
ISRXD2 input setup time
150
ns
th(ISCLK2-RXD)
ISRXD2 input hold time
100
ns
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 78 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.34
Symbol
External Bus Timing (Separate bus)
Characteristic
Measurement
condition
Value
Min.
Max.
Unit
tsu(S-R)
Chip-select setup time for read
(1)
ns
th(R-S)
Chip-select hold time after read
tc(Base) - 10
ns
tsu(A-R)
Address setup time for read
(1)
ns
th(R-A)
Address hold time after read
tc(Base) - 10
ns
tw(R)
Read pulse width
(1)
ns
tsu(S-W)
Chip-select setup time for write
(1)
ns
th(W-S)
Chip-select hold time after write
1.5 × tc(Base) - 10
ns
tsu(A-W)
Address setup time for write
(1)
ns
th(W-A)
Address hold time after write
1.5 × tc(Base) - 10
ns
tw(W)
Write pulse width
(1)
ns
tsu(D-W)
Data setup time for write
(1)
ns
th(W-D)
Data hold time after write
0
ns
Refer to
Figure 5.6
Note:
1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For the details of how to set values,
refer to the Hardware manual.
tsu(S-R) = tsu(A-R) = Tsu(A-R) × tc(Base) - 15 [ns]
tw(R) = Tw(R) × tc(Base) - 10 [ns]
tsu(S-W) = tsu(A-W) = Tsu(A-W) × tc(Base) - 15 [ns]
tw(W) = tsu(D-W) = Tw(W) × tc(Base) - 10 [ns]
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 79 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and unless otherwise noted)
Table 5.35
Symbol
External Bus Timing (Multiplexed bus)
Characteristic
Measurement
condition
Value
Min.
Max.
Unit
tsu(S-ALE)
Chip-select setup time for ALE
(1)
ns
th(R-S)
Chip-select hold time after read
1.5 × tc(Base) - 10
ns
tsu(A-ALE)
Address setup time for ALE
(1)
ns
th(ALE-A)
Address hold time after ALE
0.5 × tc(Base) - 5
ns
th(R-A)
Address hold time after read
1.5 × tc(Base) - 10
ns
td(ALE-R)
ALE-read delay time
tw(ALE)
ALE pulse width
tdis(R-A)
Address disable time after read
tw(R)
Read pulse width
th(W-S)
0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns
(1)
Refer to
Figure 5.6
ns
8
ns
(1)
ns
Chip-select hold time after write
1.5 × tc(Base) - 10
ns
th(W-A)
Address hold time after write
1.5 × tc(Base) - 10
ns
td(ALE-W)
ALE-write delay time
tw(W)
Write pulse width
(1)
ns
tsu(D-W)
Data setup time for write
(1)
ns
th(W-D)
Data hold time after write
0.5 × tc(Base)
ns
0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns
Note:
1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For the details of how to set values,
refer to the Hardware manual.
tsu(S-ALE) = tsu(A-ALE) = tw(ALE) = (Tsu(A-R) - 0.5) × tc(Base) -15 [ns]
tw(R) = Tw(R) × tc(Base) -10 [ns]
tw(W) = tsu(D-W) = Tw(W) × tc(Base) -10 [ns]
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 80 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.36
Serial Interface
Symbol
Characteristic
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi output hold time
Table 5.37
Symbol
Measurement
condition
Refer to
Figure 5.6
Value
Min.
Max.
80
0
Unit
ns
ns
Intelligent I/O
Characteristic
td(ISCLK2-TXD)
ISTXD2 output delay time
th(ISCLK2-RXD)
ISTXD2 output hold time
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 81 of 99
Value
Min.
Max.
180
0
Unit
ns
ns
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.38
Electrical Characteristics (1) (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Ta = Topr, and
f(CPU) = 50 MHz, unless otherwise noted)
Symbol
VOH
Characteristic
High
level
output
voltage
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7,P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7 (1)
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7
Measurement
condition
Low
level
output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7
Min.
Typ. Max.
Unit
IOH = -1 mA
VCC2 0.6
VCC2
V
IOH = -1 mA
VCC1 0.6
VCC1
V
0.5
V
(1)
VOL
Value (2)
IOL = 1 mA
(1)
Notes:
1. Ports P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, and P9_5 to P9_7 are available in the 100- and
80-pin packages. Ports P4, P5, and P9_4 are available in the 100-pin package only.
2. The VCC2 pin is available in the 100-pin package only. It should be considered as VCC1 in the 80-/64pin package.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 82 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.39
Symbol
Electrical Characteristics (2) (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Ta = Topr, and
f(CPU) = 50 MHz, unless otherwise noted)
Characteristic
VT+ - VT- Hysteresis HOLD, RDY, NMI, INT0 to INT5, KI0 to KI3,
TA0IN to TA4IN, TA0OUT to TA4OUT,
TB0IN to TB5IN, CTS0 to CTS8,
CLK0 to CLK8, RXD0 to RXD8,
SCL0 to SCL6, SDA0 to SDA6,
SS0 to SS6, SRXD0 to SRXD6, ADTRG,
IIO0_0 to IIO0_7, IIO1_0 to IIO1_7, UD0A,
UD0B, UD1A, UD1B, ISCLK2, ISRXD2,
IEIN(1)
RESET
High level XIN, RESET, CNVSS, NSD,
IIH
input
P0_0 to P0_7, P1_0 to P1_7,
current
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_1, P9_3 to P9_7,
P10_0 to P10_7 (2)
Low level XIN, RESET, CNVSS, NSD,
IIL
input
P0_0 to P0_7, P1_0 to P1_7,
current
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_1, P9_3 to P9_7,
P10_0 to P10_7 (2)
P0_0 to P0_7, P1_0 to P1_7,
RPULLUP Pull-up
resistor
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_1,
P9_3 to P9_7, P10_0 to P10_7 (2)
RfXIN
Feedback XIN
resistor
RfXCIN
Feedback XCIN
resistor
Value
Measurement
Unit
condition
Min. Typ. Max.
0.2
1.0
V
0.2
1.8
V
VI = 3.3 V
4.0
µA
VI = 0 V
-4.0
µA
500
kΩ
VI = 0 V
50
100
3
MΩ
25
MΩ
Notes:
1. Pins CLK4, RXD4, TXD4, SDA4, SCL4, STXD4, and SRXD4 are available in the 100- and 80-pin
package only. Pins TB4IN, CTS4, RTS4, SS4, UART6, and UART7 are available in the 100-pin
package only.
2. Ports P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, and P9_5 to P9_7 are available in the 100- and
80-pin packages. Ports P4, P5, P9_1, and P9_4 are available in the 100-pin package only.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 83 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.40
Symbol
ICC
Electrical Characteristics (3)
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Characte
ristic
Power
supply
current
Measurement condition
Value
Min. Typ. Max.
Unit
In single-chip mode,
output pins are left open
and others are
connected to VSS
f(CPU) = 50 MHz, f(BCLK) = 25 MHz,
f(XIN) = 8 MHz,
Active: XIN, PLL,
Stopped: XCIN, OCO
28
XIN-XOUT
Drive power: low
f(CPU) = fSO(PLL)/24 MHz,
Active: PLL (self-oscillation),
Stopped: XIN, XCIN, OCO
7
mA
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO
670
µA
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown
180
µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown
190
µA
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO,
Ta = 25°C, Wait mode
500
900
µA
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown,
Ta = 25°C, Wait mode
8
140
µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown,
Ta = 25°C, Wait mode
10
150
µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 25°C
5
70
µA
XCIN-XCOUT
Drive power: low
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 84 of 99
40
mA
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.41
Symbol
—
A/D Conversion Characteristics (VCC1 = VCC2 = AVCC = VREF = 3.0 to 3.6 V,
VSS = AVSS = 0 V, Ta = Topr, and f(BCLK) = 25 MHz, unless otherwise noted)
Characteristic
Measurement condition
Resolution
VREF = VCC1
Absolute error
VREF = VCC1 =
VCC2 = 3.3 V
—
INL
Integral non-linearity
error
DNL
Differential nonlinearity error
VREF = VCC1 =
VCC2 = 3.3 V
Value
Min.
Typ.
Max.
Unit
10
Bits
AN_0 to AN_7,
AN0_0 to AN0_7,
AN2_0 to AN2_7,
ANEX0, ANEX1 (1)
±5
LSB
External op-amp
connection mode
±7
LSB
AN_0 to AN_7,
AN0_0 to AN0_7,
AN2_0 to AN2_7,
ANEX0, ANEX1 (1)
±5
LSB
External op-amp
connection mode
±7
LSB
±1
LSB
VREF = VCC1 = VCC2 = 3.3 V
—
Offset error
±3
LSB
—
Gain error
±3
LSB
20
kΩ
RLADDER
Resistor ladder
VREF = VCC1
tCONV
Conversion time
(10 bits)
φAD = 10 MHz,
with sample and hold function
3.3
µs
tCONV
Conversion time
(8 bits)
φAD = 10 MHz,
with sample and hold function
2.8
µs
tSAMP
Sampling time
φAD = 10 MHz
0.3
µs
VIA
Analog input voltage
φAD
Operating clock
frequency
without sample and hold function
with sample and hold function
4
0
VREF
V
0.25
10
MHz
1
10
MHz
Note:
1. Pins AN0_4 to AN0_7, ANEX0, and ANEX1 are available in the 100- and 80-pin package only.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 85 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.42
Symbol
D/A Conversion Characteristics (VCC1 = VCC2 = AVCC = VREF = 3.0 to 3.6 V,
VSS = AVSS = 0 V, and Ta = Topr, unless otherwise noted)
Characteristic
—
Resolution
—
Absolute precision
tS
Settling time
RO
Output resistance
IVREF
Reference input current
Measurement condition
Value
Min.
4
(1)
Typ.
10
Max.
Unit
8
Bits
1.0
%
3
µs
20
kΩ
1.0
mA
Note:
1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The
resistor ladder for A/D converter is not considered.
Even when the VCUT bit in the AD0CON1 register is set to 0 (VREF disconnected), IVREF is supplied.
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 86 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.43
External Clock Input
Symbol
Value
Characteristic
Min.
Max.
62.5
250
Unit
tc(X)
External clock input period
tw(XH)
External clock input high level pulse width
25
ns
tw(XL)
External clock input low level pulse width
25
ns
tr(X)
External clock input rise time
5
ns
tf(X)
External clock input fall time
5
ns
tw / tc
External clock input duty
60
%
Table 5.44
Symbol
40
ns
External Bus Timing
Characteristic
Value
Min.
Max.
Unit
tsu(D-R)
Data setup time for read
40
ns
th(R-D)
Data hold time after read
0
ns
tdis(R-D)
Data disable time after read
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 87 of 99
0.5 × tc(Base) + 10
ns
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.45
Timer A Input (Counting input in event counter mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
200
ns
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.46
Timer A Input (Gating input in timer mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
400
ns
tw(TAH)
TAiIN input high level pulse width
180
ns
tw(TAL)
TAiIN input low level pulse width
180
ns
Table 5.47
Timer A Input (External trigger input in one-shot timer mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
200
ns
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.48
Timer A Input (External trigger input in pulse-width modulation mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.49
Timer A Input (Increment/decrement count switching input in event counter mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(UP)
TAiOUT input clock period
2000
ns
tw(UPH)
TAiOUT input high level pulse width
1000
ns
tw(UPL)
TAiOUT input low level pulse width
1000
ns
tsu(UP-TIN)
TAiOUT input setup time
400
ns
th(TIN-UP)
TAiOUT input hold time
400
ns
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 88 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.50
Symbol
Timer B Input (Counting input in event counter mode)
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period (one edge counting)
200
ns
tw(TBH)
TBiIN input high level pulse width (one edge counting)
80
ns
tw(TBL)
TBiIN input low level pulse width (one edge counting)
80
ns
tc(TB)
TBiIN input clock period (both edges counting)
200
ns
tw(TBH)
TBiIN input high level pulse width (both edges counting)
80
ns
tw(TBL)
TBiIN input low level pulse width (both edges counting)
80
ns
Table 5.51
Symbol
Timer B Input (Pulse period measure mode)
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period
400
ns
tw(TBH)
TBiIN input high level pulse width
180
ns
tw(TBL)
TBiIN input low level pulse width
180
ns
Table 5.52
Symbol
Timer B Input (Pulse-width measure mode)
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period
400
ns
tw(TBH)
TBiIN input high level pulse width
180
ns
tw(TBL)
TBiIN input low level pulse width
180
ns
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 89 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.53
Serial Interface
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(CK)
CLKi input clock period
200
ns
tw(CKH)
CLKi input high level pulse width
80
ns
tw(CKL)
CLKi input low level pulse width
80
ns
tsu(D-C)
RXDi input setup time
80
ns
th(C-D)
RXDi input hold time
90
ns
Table 5.54
A/D Trigger Input
Symbol
Characteristic
Value
Min.
Max.
Unit
tw(ADH)
ADTRG input high level pulse width
Hardware trigger input high level pulse width
3--------φ AD
ns
tw(ADL)
ADTRG input low level pulse width
Hardware trigger input high level pulse width
125
ns
Table 5.55
External Interrupt INTi Input
Symbol
tw(INH)
tw(INL)
Table 5.56
Value
Characteristic
INTi input high level pulse width
INTi input low level pulse width
Min.
Max.
Unit
Edge sensitive
250
ns
Level sensitive
tc(CPU) + 200
ns
Edge sensitive
250
ns
Level sensitive
tc(CPU) + 200
ns
Intelligent I/O
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(ISCLK2)
ISCLK2 input clock period
600
ns
tw(ISCLK2H)
ISCLK2 input high level pulse width
270
ns
tw(ISCLK2L)
ISCLK2 input low level pulse width
270
ns
150
ns
100
ns
tsu(RXD-ISCLK2) ISRXD2 input setup time
th(ISCLK2-RXD)
ISRXD2 input hold time
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 90 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.57
Symbol
External Bus Timing (Separate bus)
Characteristic
Measurement
condition
Value
Min.
Max.
Unit
tsu(S-R)
Chip-select setup time for read
(1)
ns
th(R-S)
Chip-select hold time after read
tc(Base) - 10
ns
tsu(A-R)
Address setup time for read
(1)
ns
th(R-A)
Address hold time after read
tc(Base) - 10
ns
tw(R)
Read pulse width
(1)
ns
tsu(S-W)
Chip-select setup time for write
(1)
ns
th(W-S)
Chip-select hold time after write
1.5 × tc(Base) - 10
ns
tsu(A-W)
Address setup time for write
(1)
ns
th(W-A)
Address hold time after write
1.5 × tc(Base) - 10
ns
tw(W)
Write pulse width
(1)
ns
tsu(D-W)
Data setup time for write
(1)
ns
th(W-D)
Data hold time after write
0
ns
Refer to
Figure 5.6
Note:
1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For the details of how to set values,
refer to the Hardware manual.
tsu(S-R) = tsu(A-R) = Tsu(A-R) × tc(Base) - 15 [ns]
tw(R) = Tw(R) × tc(Base) - 10 [ns]
tsu(S-W) = tsu(A-W) = Tsu(A-W) × tc(Base) - 15 [ns]
tw(W) = tsu(D-W) = Tw(W) × tc(Base) - 10 [ns]
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 91 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.58
Symbol
External Bus Timing (Multiplexed bus)
Characteristic
Measurement
condition
Value
Min.
Max.
Unit
tsu(S-ALE)
Chip-select setup time for ALE
(1)
ns
th(R-S)
Chip-select hold time after read
1.5 × tc(Base) - 10
ns
tsu(A-ALE)
Address setup time for ALE
(1)
ns
th(ALE-A)
Address hold time after ALE
0.5 × tc(Base) - 5
ns
th(R-A)
Address hold time after read
1.5 × tc(Base) - 10
ns
td(ALE-R)
ALE-read delay time
0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns
tw(ALE)
ALE pulse width
tdis(R-A)
Address disable time after read
tw(R)
Read pulse width
th(W-S)
(1)
Refer to
Figure 5.6
ns
8
ns
(1)
ns
Chip-select hold time after write
1.5 × tc(Base) - 10
ns
th(W-A)
Address hold time after write
1.5 × tc(Base) - 10
ns
td(ALE-W)
ALE-write delay time
0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns
tw(W)
Write pulse width
(1)
ns
tsu(D-W)
Data setup time for write
(1)
ns
th(W-D)
Data hold time after write
0.5 × tc(Base)
ns
Note:
1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For the details of how to set values,
refer to the Hardware manual.
tsu(S-ALE) = tsu(A-ALE) = tw(ALE) = (Tsu(A-R) - 0.5) × tc(Base) -15 [ns]
tw(R) = Tw(R) × tc(Base) -10 [ns]
tw(W) = tsu(D-W) = Tw(W) × tc(Base) -10 [ns]
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 92 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.59
Serial Interface
Symbol
Characteristic
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi output hold time
Table 5.60
Intelligent I/O
Symbol
Measurement
condition
Refer to
Figure 5.6
Characteristic
td(ISCLK2-TXD)
ISTXD2 output delay time
th(ISCLK2-RXD)
ISTXD2 output hold time
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 93 of 99
Value
Min.
Max.
80
0
ns
ns
Value
Min.
Max.
180
0
Unit
Unit
ns
ns
R32C/111 Group
5. Electrical Characteristics
MCU
Pin to be
measured
Figure 5.6
30 pF
Switching Characteristic Measurement Circuit
t c(X)
XIN
t w(XH)
t r(X)
Figure 5.7
External Clock Input Timing
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 94 of 99
t w(XL)
t f(X)
R32C/111 Group
5. Electrical Characteristics
External bus timing (Separate bus)
Read cycle
t cR
t su(S-R)
t h(R-S)
t su(A-R)
t h(R-A)
CS0 to CS3
A23 to A0, BC0 and BC1
t w(R)
RD
t su(D-R)
t h(R-D)
D15 to D0
Write cycle
t cW
t su(S-W)
t h(W-S)
t su(A-W)
t h(W-A)
CS0 to CS3
A23 to A0, BC0 and BC1
t w(W)
WR, WR0 and WR1
t su(D-W)
t h(W-D)
D15 to D0
Measurement conditions
Item
Figure 5.8
VCC1 = VCC2 = 4.2 to 5.5 V
VCC1 = VCC2 = 3.0 to 3.6 V
Criterion for
input voltage
VIH
2.5 V
1.5 V
VIL
0.8 V
0.5 V
Criterion for
output voltage
VOH
2.0 V
2.4 V
VOL
0.8 V
0.5 V
External Bus Timing (Separate Bus)
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 95 of 99
R32C/111 Group
5. Electrical Characteristics
External bus timing (Multiplexed bus)
Read cycle
t cR
t su(S-ALE)
t h(R-S)
t su(A-ALE)
t h(R-A)
CS0 to CS3
A23 to A8, BC0 and
BC1
t w(ALE)
t h(ALE-A)
ALE
t su(A-ALE)
A15/D15 to A0/D0,
BC0/D0
t dis(R-A)
t su(D-R)
Address
t h(R-D)
Data
t d(ALE-R)
t w(R)
t dis(R-D)
RD
t su(D-R)
t h(R-D)
D15 to D8
Write cycle
t cW
t su(S-ALE)
t h(W-S)
t su(A-ALE)
t h(W-A)
CS0 to CS3
A23 to A8, BC0 and
BC1
t w(ALE)
ALE
t su(A-ALE)
A15/D15 to A0/D0,
BC0/D0
t h(ALE-A)
t su(D-W)
Address
t d(ALE-W)
t h(W-D)
Data
t w(W)
WR, WR0 and WR1
t su(D-W)
t h(W-D)
D15 to D8
Measurement conditions
Item
Figure 5.9
VCC1 = VCC2 = 4.2 to 5.5 V
VCC1 = VCC2 = 3.0 to 3.6 V
Criterion for
input voltage
VIH
2.5 V
1.5 V
VIL
0.8 V
0.5 V
Criterion for
output voltage
VOH
2.0 V
2.4 V
VOL
0.8 V
0.5 V
External Bus Timing (Multiplexed Bus)
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 96 of 99
R32C/111 Group
5. Electrical Characteristics
t c(TA)
t w(TAH)
t w(TAL)
TAiIN input
t c(UP)
t w(UPH)
t w(UPL)
TAiOUT input
In event counter mode
TAiOUT input (input for increment/
decrement count switching)
t su(UP-TIN)
t h(TIN-UP)
TAiIN input (in falling edge counting)
TAiIN input (in rising edge counting)
t c(TB)
t w(TBH)
t w(TBL)
TBiIN input
t c(CK)
t w(CKH)
t w(CKL)
CLKi
t d(C-Q)
t h(C-Q)
TXDi
t su(D-C)
t h(C-D)
RXDi
t w(ADL)
t w(ADH)
t w(INL)
t w(INH)
ADTRG input
INTi input
2 CPU clock cycles +
300 ns or more
NMI input
Figure 5.10
Timing of Peripheral Functions
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 97 of 99
2 CPU clock cycles +
300 ns or more
R32C/111 Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP100-14x14-0.50
RENESAS Code
PLQP0100KB-A
Previous Code
100P6Q-A / FP-100U / FP-100UV
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
c1
Reference
Symbol
c
E
*2
HE
b1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
100
26
1
ZE
Terminal cross section
25
Index mark
ZD
y
*3
e
bp
A1
c
A
A2
F
e
x
y
ZD
ZE
L
L1
L
x
L1
Detail F
JEITA Package Code
P-TFLGA100-5.5x5.5-0.5
RENESAS Code
PTLG0100KA-A
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
MASS[Typ.]
0.1g
b1
S
w S A
w S B
D
Previous Code
100F0M
Dimension in Millimeters
AB
b
ZD
A
S
AB
e
A
e
K
J
H
G
B
E
F
E
D
C
B
ZE
A
y S
x4
v
1
2
3
Index mark
(Laser mark)
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 98 of 99
S
Index mark
4
5
6
7
8
9
10
Reference
Symbol
D
E
v
w
A
e
b
b1
x
y
ZD
ZE
Dimension in Millimeters
Min
Nom Max
5.5
5.5
0.15
0.20
1.05
0.5
0.21 0.25 0.29
0.29 0.34 0.39
0.08
0.10
0.5
0.5
R32C/111 Group
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP80-12x12-0.50
RENESAS Code
PLQP0080KB-A
Previous Code
80P6Q-A
MASS[Typ.]
0.5g
HD
*1
D
60
41
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
40
61
bp
E
c
*2
HE
c1
b1
Reference Dimension in Millimeters
Symbol
ZE
Terminal cross section
80
21
1
20
ZD
Index mark
A1
*3
c
A
y
bp
e
A2
F
L
x
L1
Detail F
JEITA Package Code
P-LQFP64-10x10-0.50
RENESAS Code
PLQP0064KB-A
Previous Code
64P6Q-A / FP-64K / FP-64KV
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Min Nom Max
11.9 12.0 12.1
11.9 12.0 12.1
1.4
13.8 14.0 14.2
13.8 14.0 14.2
1.7
0.1 0.2
0
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
10°
0.5
0.08
0.08
1.25
1.25
0.3 0.5 0.7
1.0
MASS[Typ.]
0.3g
HD
*1
D
48
33
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
64
1
c1
Terminal cross section
ZE
17
Reference
Symbol
c
E
*2
HE
b1
16
Index mark
ZD
c
A
*3
A1
y
e
A2
F
bp
L
x
L1
Detail F
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 99 of 99
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
9.9 10.0 10.1
9.9 10.0 10.1
1.4
11.8 12.0 12.2
11.8 12.0 12.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.25
1.25
0.35 0.5 0.65
1.0
REVISION HISTORY
Rev.
0.03
0.30
Date
Oct 17, 2007
Aug 19, 2008
Page
—
—
—
1
2
3
4
6
7
8
11
12
13, 14
—
15
R32C/111 Group Datasheet
Description
Summary
Initial release
Second edition released
The manual in general
• Maximum operating frequency changed from 48 MHz to 50 MHz
• Specification of on-chip oscillator disclosed
• Microprocessor mode becomes optional
• “memory-expanded mode” changed to “memory expansion mode”
Chapter 1
• “(MCUs)” added to line 1 of 1.1
• Applications in 1.1.1 revised and modified
• “Attention Users” below 1.1.1 modified to “Notes to users”; “The
specification” in this box changed to “Specifications”
• “instructions” in “CPU” of Table 1.1 deleted
• Minimum instruction execution time in “CPU” of Table 1.1 changed
• Microprocessor mode in CPU” of Table 1.1 changed to optional
• “TBD” for “Voltage Detection” in Table 1.1 deleted
• “3 circuits” for “Clock” in Table 1.1 changed to “4 circuits”
• “Total interrupt vectors” in Table 1.1 changed to “Interrupt vectors”
• Trigger sources” for DMA in Table 1.1 modified to “Request sources”;
Request sources for “DMA” defined as 51
• Scribal error: “peripheral interrupt sources” for “DMACII” in Table 1.1
corrected to “peripheral interrupt source”
• Unit names in Table 1.2 sorted in chapter order
• Description for “A/D Converter” in Table 1.2 changed
• “Operating frequency” in Table 1.2 changed from “48 MHz” to “50
MHz”
• “version N” and “version D” added to “Operating Temperature” in Table
1.2; “optional” deleted
• Values for “Current Consumption” in Table 1.2 added
• “version N” and “version D” added to Table 1.3
• All “version N”s in Table 1.3 become on planning phase
• Figure 1.2 modified
• Note 2 for Figure 1.3 modified
• Scribal error: “CLK5/” (pin No. 21) in Table 1.4 corrected to “CLK5”
• Description for “Connecting pins for decoupling capacitor”, “CNVSS”,
and “Debug port” in Table 1.7 modified
• Some descriptions for “WR0/WR1/WR/BC0/BC1/RD” of “Bus control
pins” in Table 1.8 modified
• Functional category items in Tables 1.9 and 1.10 sorted in chapter
order; Descriptions modified
Chapter 2
• Descriptions for this chapter modified; Expression “DMAC-related
registers”s modified to “DMAC-associated registers”s
• “Data register” and “Address register” in Figure 2.1 pluralized;
Explanation in Notes 1 and 2 for this figure revised
A- 1
REVISION HISTORY
Rev.
Date
Page
15, 16
18
19
20
21, 22
22
25
32
38
43
—
1.10
Sep 17, 2009
81
—
—
1
2
3
4-7
R32C/111 Group Datasheet
Description
Summary
• “Interrupt table register” in Figure 2.1 and 2.1.6 changed to “Interrupt
vector table base register”
• Scribal error: “24 bit” in 2.2.2 corrected to “32 bit”
Chapter 3
• Descriptions for this chapter and Figure 3.1 modified
Chapter 4
• “(SFR)” of chapter title changed to “(SFRs)”
• Description for initial paragraph of Chapter 4 modified
• Reset value for CCR and PBC in Table 4.1 changed
• “UARTi Bus Collision Detection Interrupt Control Register” (i = 0 to 6)
in Tables 4.2 and 4.3 changed to “UARTi Bus Collision, Start/Stop
Condition Detection Interrupt Control Register”
• “DMAi interrupt” in Tables 4.2 and 4.3 changed to “DMAi transfer
complete interrupt”
• Reset value for IIO3IR and IIO8IR to IIO11R in Table 4.3 modified
• Scribal error: address “00010Fh” added to Table 4.6
• “Upward/Downward Counting Select Register” in Table 4.13 changed
to “Increment/Decrement Counting Select Register”
• CSOP2 for address 040056h in Table 4.19 deleted
• Reset value for CM3 in Table 4.19 changed
• “DMAi Source Select Register i” in Table 4.24 changed to “DMAi
Request Source Select Register i”
Chapter 5
• This chapter newly added
Appendix 1
• “Package Dimension” as title changed to “Package Dimensions”
Third edition released
The manual in general
• Added 100-pin plastic molded LGA and 80- and 64-pin plastic molded
LQFP packages
• When new tables/figures are added for 80-/64-pin packages, add the
following description: “(for the 100-pin package)” to the title of
corresponding current tables/figures
Chapter 1. Overview
• Added description for 100-pin LGA and 80-/64-pin packages to lines
12 and 13 of 1.1; Added description “a maximum of” to “nine channels
of serial interface”; Deleted the whole description of “Notes to users”
• Changed minimum RAM size “40” in Table 1.1, to “32”
• Modified description for “External Bus Expansion”, to Table 1.1; Moved
this unit below “Clock”
• Added “(optional)” for IEBus mode for “Intelligent I/O” in Table 1.2
• Modified description for “Flash memory” in Tables 1.2
• Added “100-pin plastic molded TFLGA (PTLG0100KA-A)” to Table 1.2
• Added Tables 1.3 to 1.6 to provide specifications for 80-/64-pin
packages
A- 2
REVISION HISTORY
Rev.
Date
Page
8
9
11, 12,
14, 18,
21
13
15-17
19, 20,
22, 23
24
25
26
28-30
—
33
35
36
R32C/111 Group Datasheet
Description
Summary
• Completed “under development” phase of part numbers
R5F64110DFB, R5F64111DFB, R5F64112DFB, R5F64114DFB,
R5F64115DFB, and R5F64116DFB in Table 1.7
• Added product information for 100-pin LGA and 80-/64-pin packages
to Table 1.7
• Added product information for 100-pin LGA and 80-/64-pin packages,
and 32-Kbyte RAM to Figure 1.1
• Deleted hyphenation for part number in Figure 1.1
• Added Figures 1.3, 1.4, and 1.6 to 1.8 to provide block diagrams and
pin assignment for 100-pin LGA and 80-/64-pin packages
• Changed the order of Notes in Figures 1.5
• Added pin No. for 100-pin LGA package to Tables 1.8 to 1.10
• Added Tables 1.11 to 1.14 to provide pin characteristics for 80-/64-pin
packages.
• Changed the following expression: “A ceramic resonator or a crystal
oscillator” for “Main clock input/output” in Table 1.15, to “A crystal, or a
ceramic resonator”
• Modified descriptions for HLDA and RDY of “Bus control pins” in Table
1.16
• Changed the following expression: “selected” for “Input port” in Table
1.17, to “selectable”
• Modified description “TXD2” for TXD0 to TXD8 of “Serial interface” in
Table 1.17, to “TXD2 output”
• Added Tables 1.19 to 1.21 to provide pin definitions and functions for
80-/64-pin packages
Chapter 2. CPU
• Made major text modifications to this chapter
• Changed the following expression: “a requested interrupt’s priority
level” in line 2 of 2.1.8.11, to “the interrupt request level”
Chapter 3. Memory
• Made major text modifications to this chapter
• Changed RAM size “40” in line 7 of this chapter, to “63”, and address
“0000A3FFh” in line 8, to “0000FFFFh”
• Added descriptions for 32-Kbyte RAM and 128-Kbyte ROM to Figure
3.1
• Changed two “can be”s in Notes 3 and 4 of Figure 3.1, to “becomes”s
Chapter 4. SFRs
• Changed hexadecimal format of reset values for registers CCR and
FMCR in Table 4.1, to binary
• Added FEBC3 register to addresses 000010h-000011h in Table 4.1
• Changed FEBC register for addresses 00001Ch-00001Dh, to FEBC0
in Table 4.1
• Modified the following register name in Table 4.1: “Chip-select
Boundary (between n and n + 1) Setting Register”, to “Chip-select n
and n + 1 Boundary Setting Register”
A- 3
REVISION HISTORY
Rev.
Date
Page
37, 38
45
46
51
54
55
55-57
59
60
61
62
63
65
66
R32C/111 Group Datasheet
Description
Summary
• Changed register names associated with “Start/Stop Condition” for
BCNiIC in Tables 4.2 and 4.3, to “Start Condition/Stop Condition”
• Modified reset values “XXXX XXXXb” and “XXXX 000Xb” for registers
U7RB and U8RB in Table 4.10, to “XXXXh”
• Changed expression of register name “Xi Register Yi Register” (i = 0 to
15) and register symbol “XiR, YiR” in Table 4.11, to “Xi Register/Yi
Register” and “XiR/YiR”, respectively
• Changed hexadecimal format of reset values for PDi in Table 4.16, to
binary
• Modified Note 1 in Table 4.19
• Merged addresses 40090h to 40093h in Table 4.20, into previous
page
• Modified reset values for IFS0 and IFS2 in Table 4.20; Added Notes 1
to 3 for 80-/64-pin packages and IFS7 register
• Modified the following register name in Tables 4.20 to 4.22: “Port Pi_j
Port Function Select Register”, to “Port Pi_j Function Select Register”
• Modified register name “DMAi Request Source Select Register 1” in
Table 4.24, to “DMAi Request Source Select Register”
• Changed register names “Wake-up Interrupt Priority Level Control
Register 2” and “Wake-up Interrupt Priority Level Control Register 1” in
Table 4.24, to “Wake-up IPL Setting Register 2” and “Wake-up IPL
Setting Register 1”, respectively
Chapter 5. Electrical Characteristics
• Added Notes 2 and 3 for 80-/64-pin packages to Table 5.1
• Added specification of “dVCC1/dt” to Table 5.2; Added Notes 2, 4, and
5 for 80-/64-pin packages
• Added Note 2 for Table 5.3
• Added Note 3 for 80-/64-pin packages to Table 5.4
• Modified description “VCC”s in Table 5.6, to “VCC1”s and “VCC2”s
• Added Table 5.7 to provide RAM electrical characteristics
• Deleted specification of “tPS” from Table 5.8
67
• Deleted measurement condition for power supply circuit timing
characteristics in Table 5.9
• Added “Supply voltage for internal logic” to Figure 5.3 and deleted
“CPU clock” from the figure
• Changed voltage condition for Table 5.11, from “VCC1 = VCC2 = 3.3 to
5.5 V” to “VCC1 = VCC2 = 4.2 to 5.5 V”; Clarified maximum value for
“∆Vdet” in Table 5.11; Modified self-consuming current “VCC”, to
“VCC1”
68
• Changed typical value and maximum value for fSO(PLL) in Table 5.12,
to “55” and “80” respectively
• Changed the following expressions: “PLL frequency synthesizer
stabilization time” in Table 5.12, to “PLL lock time” and “tOSC(PLL)”, to
“tLOCK(PLL)”
• Modified description for Note1 of Table 5.13
A- 4
REVISION HISTORY
Rev.
Date
Page
70, 82
71, 83
72, 84
73, 85
75, 87
78
78, 90
R32C/111 Group Datasheet
Description
Summary
• Added Notes 1 and 2 for 80-/64-pin packages to Tables 5.15 and 5.38
• Deleted ports P7_0, P7_1, and P8_5 for RPULLUP from Tables 5.16
and 5.39; Added Notes 1 and 2 for 80-/64-pin packages
• Added “XIN” as “Active” to first, third, and sixth rows of Tables 5.17
and 5.40
• Deleted specification of ICC under condition “Ta = 85°C” from Tables
5.17 and 5.40
• Modified minimum value “0.125” for φAD in Tables 5.18 and 5.41, to
“0.25”; Added Note 1 for 80-/64-pin packages
• Clarified three “TBD”s for external bus timing in Tables 5.21 and 5.44
• Corrected a typo “th(C-Q)” in Table 5.30, to “th(C-D)”
• Modified maximum value for th(C-D) “30” in Tables 5.30 and 5.53, to
“80”
3
• Modified minimum value for tw(ADH) in Tables 5.31 and 5.54, to “ ---------- ”
φ AD
79, 91
80, 92
81, 93
83
85
87
95
96
98, 99
• Added Tables 5.33 and 5.56 to provide intelligent I/O timing
requirements
• Changed the third formula of Note 1 in Tables 5.34 and 5.57
• Modified minimum value of th(W-D) “0” in Tables 5.35 and 5.58, to “0.5
x tc(Base)”; Changed the first formula of Note 1
• Modified “Characteristic” for th(C-Q) in Tables 5.36 and 5.59, from
“TXDi hold time” to “TXDi output hold time”
• Added Tables 5.37 and 5.60 to provide intelligent switching
characteristics
• Changed measurement condition for “High level input current” in Table
5.39, from “VI = 3 V” to “VI = 3.3 V”
• Added a skipped word “error” after “Differential non-linearity” in Table
5.41
• Corrected typos “tw(H),” “tw(L)”, “tr”, and “tf” in Table 5.43, to “tw(XH)”,
“tw(XL)”, “tr(X)”, and “tf(X)”, respectively
• Changed D15 to D0 output period of write cycle in Figures 5.8
• Changed D15 to D8 output period of write cycle in Figures 5.9
Appendix 1
• Added figures for 100-pin plastic molded LGA, and 80-/64-pin plastic
molded LQFP packages
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