Ordering number : ENA1419 LC79401KNE CMOS LSI Dot-Matrix LCD Drivers http://onsemi.com Overview The LC79401KNE is a 80-outputs segment driver LSI for graphic dot-matrix liquid crystal display systems. The LC79401KNE latches 80 bits of display data sent from a controller using a 4-bit parallel transfer technique and generates LCD drive signals. When combined as a kit with common driver, either the LC79430KNE (QIP100E), the LC79401KNE can drive large screen LCD panels. Features • Incorporates LCD drive circuits for 80 bits of display. • Supports display duties from 1/64 to 1/256 • The provision of a chip disable pin supports power reduction in large-scale panels. • Allows external provision of the bias power supply • Operating supply voltage/operating temperature VDD (logic block) : 2.7 to 5.5V/-20 to +85°C VDD-VEE (LCD block) : 12 to 32V/-20 to +85°C • Data transfer clock : 6.0MHz (max), bidirectional shifting supported • Data input : 4-bit parallel input • CMOS process • 100-pin flat plastic package (QIP100E) Semiconductor Components Industries, LLC, 2013 July, 2013 91912HKPC 20120905-S00001 No. A1419-1/8 LC79401KNE Specifications Absolute Maximum Ratings at Ta = 25±2°C, VSS = 0V Parameter Symbol Maximum supply voltage (Logic) VDD max Maximum supply voltage (LCD) VDD-VEE max Maximum input voltage VI max Storage temperature Tstg Conditions Ratings *1 unit -0.3 to +7.0 V 0 to 35 V -0.3 to VDD+0.3 V -40 to +125 °C Note *1 VDD≥V1>V3>V4>VEE, VDD-V3≤7V, V4-VEE≤7V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Allowable Operating Ranges at Ta = -20 to +85°C, VSS = 0V Parameter Symbol Conditions Supply voltage (Logic) VDD Supply voltage (LCD) VDD-VEE *2, 3 Input high level voltage VIH DI1 to DI4, CP, LOAD, CDI, R/L, M, DISPOFF Input low level voltage VIL DI1 to DI4, CP, LOAD, CDI, R/L, M, DISPOFF CP Shift clock fCP CP CP pulse width tWC CP min typ max unit 2.7 5.5 V 12 32 V 0.8VDD V 0.2VDD 6.0 50 V MHz ns LOAD pulse width tWL LOAD 50 ns Setup time tSETUP DI1 to DI4 → CP 30 ns Hold time tHOLD DI1 to DI4 → CP VDD=2.7 to 4.5V 40 ns VDD=4.5 to 5.5V 30 ns CP → LOAD tCL CP → LOAD 80 ns LOAD → CP tLC1 LOAD → CP 110 ns tLC2 LOAD → CP VDD=2.7 to 4.5V 30 ns VDD=4.5 to 5.5V 15 CP and LOAD rise time tR CP, LOAD *4 ns CP and LOAD fall time tF CP, LOAD *4 ns ns Note *2 VDD≥V1>V3>V4>VEE, VDD-V3≤7V, V4-VEE≤7V *3 When the power is turned on, either the logic system power must be turned on before the LCD drive system power or else they must both be turned on at the same time. When the power is turned off, either the LCD drive system power must be turned off before the logic system power, or else both must be turned off at the same time. *4 The CP and LOAD rise time (tR) and the CP and LOAD fall time (tF) must satisfy equations (1) and (2) below at the same time. 1 (1) tR, tF < 2f - tWC CP (2) tR, tF < 50ns No. A1419-2/8 LC79401KNE Electrical Characteristics at Ta = 25±2°C, VDD = 2.7 to 5.5V Parameter Symbol Conditions Input high level current IIH VIN=VDD, LOAD, CP, CDI, R/L, DI1 to DI4, M, DISPOFF Input low level current IIL VIN=VSS, LOAD, CP, CDI, R/L, DI1 to DI4, M, DISPOFF Output high level voltage VOH IOH=-400μA, CDO Output low level voltage VOL IOL=400μA, CDO Driver on resistance RON(1) VDD-VEE=30V, ⎜VDE-VO⎜=0.5V: O1 to O80 *5 RON(2) VDD-VEE=20V, ⎜VDE-VO⎜=0.5V: O1 to O80 *5 Standby current drain IST Operating current drain Input capacitance min typ max unit 1 μA μA -1 VDD-0.4 V 0.4 V 0.6 1.5 kΩ 0.7 2.0 kΩ CDI=VDD, VDD-VEE=30V, CP=6.0MHz, Output unloaded: VSS 200 μA ISS *6 VDD-VEE=30V, CP=6MHz, LOAD=14kHz, M=35Hz: VSS 4.0 mA IEE *7 VDD-VEE=30V, CP=6MHz, LOAD=14kHz, M=35Hz: VEE 0.5 mA CI f=6.0MHz ; CP 8 pF Note *5 VDE = one of V1, V3, V4 or VEE, V1 = VDD, V3 = 15/17 (VDD-VEE), V4 = 2/17 (VDD-VEE) *6 ISS is the current flowing from VDD to VSS *7 IEE is the current flowing from VDD to VEE Switching Characteristics at Ta = 25±2°C, VSS = 0V, VDD = 2.7 to 5.5V Parameter Output delay time 1 Output delay time 2 Symbol tD1 tD2 Conditions Load=15pF: CDO Load=15pF: CDO min typ max unit VDD=2.7 to 4.5V 100 ns VDD=4.5 to 5.5V 80 ns VDD=2.7 to 4.5V 100 ns VDD=4.5 to 5.5V 80 ns No. A1419-3/8 LC79401KNE Package Dimensions unit:mm (typ) 3151A 23.2 0.8 20.0 51 50 100 31 14.0 81 1 17.2 80 30 0.65 0.15 0.3 0.1 3.0max (2.7) (0.58) SANYO : QIP100E(14X20) O51 O55 O54 O53 O52 O59 O58 O57 O56 O67 O66 O65 O64 O63 O62 O61 O60 O72 O71 O70 O69 O68 O76 O75 O74 O73 O80 O79 O78 O77 Pin Assignment 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 LC79401KNE O50 O49 O48 O47 O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O30 O26 O27 O28 O29 O22 O23 O24 O25 O14 O15 O16 O17 O18 O19 O20 O21 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 O9 O10 O11 O12 O13 1 2 3 4 5 6 O5 O6 O7 O8 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 O1 O2 O3 O4 CDI V1 V3 V4 VEE M LOAD VSS DISPOFF VDD R/L NC NC NC DI4 DI3 DI2 DI1 CP CDO Top view No. A1419-4/8 LC79401KNE O80 O79 O3 O2 O1 Equivalent Circuit Block Diagram V1 V3 VDD 4 Level LCD Drive Circuit (80 bits) V4 VSS VEE 80 Level Shifter (80 bits) M DISPOFF 80 2nd Latch (80 bits) 80 1st Latch (80 bits) 4 DI4 DI3 DI2 4 bits Data Bus Interface Address Decoder Address Counter (5bits) DI1 R/L 20 Shift Control Chip Disable & Latch Control CDO CDI CP LOAD No. A1419-5/8 LC79401KNE Pin Function Pin No Symbol 90 VDD I/O 88 VSS 85 VEE 82 V1 83 V3 84 V4 99 CP I 87 LOAD I 95 DI4 96 DI3 97 DI2 98 DI1 Supply Function VDD-VSS : Logic power supply VDD-VEE : LCD drive circuit power supply LCD drive level power supply Supply V1,VEE : Selected level V3,V4 : Unselected level Display data acquisition clock (falling edge trigger) Display data latch clock (falling edge trigger) The display data LCD drive signal is output on the falling edge. Display data LCD drive output LCD display H Selected level On L Unselected level Off I Control pin that inverts the data output destination R/L L 91 R/L M 1 2 3 ••• DI1 O77 O73 O69 ••• O9 O5 O1 DI2 O78 O74 O70 ••• O10 O6 O2 DI3 O79 O75 O71 ••• O11 O7 O3 DI4 O80 O76 O72 ••• O12 O8 O4 DI1 O4 O8 O12 ••• O72 O76 O80 DI2 O3 O7 O11 ••• O71 O75 O79 DI3 O2 O6 O10 ••• O70 O74 O78 DI4 O1 O5 O9 ••• O69 O73 O77 18 19 20 I H 86 Number of clock Data input I LCD drive output alternation signal Chip disable pin 81 CDI I 100 CDO O High level : Data is not acquired. Low level : Data is acquired 89 DISPOFF I Connect to the CDI pin on the next chip when cascade connection is used. Input that controls the O1 to O80 output pins. During periods when this pin Is low, the O1 to O80 output pins output the V1 level. See the truth table. LCD drive outputs The output level are determined by the combination of the output the data, The M signal, and The DISPOFF pin as shown in the table. 1 to 80 O1 to O80 O M Q DISPOFF Output L L H V3 V1 L H H H L H V4 H H H VEE * * L V1 Note : don’t care (fixed at high or low) 92 NC 93 NC 94 NC - Must be left open. No. A1419-6/8 R R VEE + + V5 V4 Power supply circuit Case of 1/n bias (n-4)R V3 V2 O1 to O80 CDI CDO LC79401KNE VDD #4 VSS O1 to O80 CDI CDO LC79401KNE VDD #2 VSS CDI CDO LC79401KNE VDD #1 VSS LCD PANEL 240×320 1/240 duty O1 to O80 Seg3 Seg2 Seg1 R + + Com238 Com239 Com240 Com1 Com2 Com3 Seg320 Seg319 Seg318 R RS/LS DISPOFF MODE DMIN M LC79430KNE CP #3 V1 V2 V5 VEE V1 RS/LS DISPOFF MODE DMIN M LC79430KNE CP #1 V1 V2 V5 VSS DIO1 VDD O1 to O80 DIO80 VDD GND O1 to O80 DIO1 FLM M LOAD CP DI1 to DI4 DISPOFF Controller R/L DISPOFF DI1 to DI4 M LOAD CP V1 V3 V4 VEE R/L DISPOFF DI1 to DI4 M LOAD CP V1 V3 V4 VEE R/L DISPOFF DI1 to DI4 M LOAD CP V1 V3 V4 VEE LC79401KNE Application Example (LC79401KNE/LC79430KNE) DIO80 VDD VSS VEE No. A1419-7/8 LC79401KNE Switching Characteristics Diagram tR CP tWC tF tWC 0.8VDD 0.2VDD tSETUP DI1-DI4 tHOLD 0.8VDD 0.2VDD tR tWL tF 0.8VDD LOAD 0.2VDD tCL tLC1 0.8VDD tLC2 CP 0.2VDD tD1 tD2 0.8VDD CDO 0.2VDD ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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