RENESAS M34509G4

4509 Group
REJ03B0147-0102
Rev.1.02
2006.12.22
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 4509 Group is a 4-bit single-chip microcomputer designed with
CMOS technology. Its CPU is that of the 4500 series using a simple,
high-speed instruction set. The computer is equipped with two 8-bit
timers (each timer has two reload registers), interrupts, 10-bit A/D
converter, Serial interface and oscillation circuit switch function.
FEATURES
●Minimum instruction execution time .................................. 0.5 µs
(at 6 MHz oscillation frequency, in through-mode)
●Supply voltage .......................................................... 1.8 V to 5.5 V
(It depends on operation source clock, oscillation frequency and
operating mode.)
●Timers
Timer 1 ................................. 8-bit timer with two reload registers
Timer 2 ................................. 8-bit timer with two reload registers
●Interrupt ........................................................................ 5 sources
●Key-on wakeup function pins ................................................... 12
●Input/Output port ...................................................................... 18
ROM (PROM) size
(✕ 10 bits)
4096 words
4096 words
4096 words
4096 words
Part number
M34509G4FP (Note)
M34509G4-XXXFP
M34509G4HFP (Note)
M34509G4H-XXXFP
●A/D converter
10-bit successive comparison method ........................ 6 channel
●Serial intereface ............................................................. 8-bit ✕ 1
●Voltage drop detection circuit (only for H version)
Reset occurrence .................................... Typ. 2.6 V (Ta = 25 °C)
Reset release .......................................... Typ. 2.7 V (Ta = 25 °C)
●Power-on reset circuit (only for H version)
●Watchdog timer
●Clock generating circuit (on-chip oscillator/ceramic resonator/RC
oscillation)
●LED drive directly enabled (port D)
APPLICATION
Electrical household appliance, consumer electronic products, office
automation equipment, etc.
RAM size
(✕ 4 bits)
256 words
256 words
256 words
256 words
Package
ROM type
PRSP0024GA-A
PRSP0024GA-A
PRSP0024GA-A
PRSP0024GA-A
QzROM
QzROM
QzROM
QzROM
Note: Shipped in blank.
PIN CONFIGURATION
1
24
P30/AIN2
VSS
2
23
P31/AIN3
XIN
3
22
P00/SIN
XOUT
4
21
P01/SOUT
CNVSS
5
20
P02/SCK
RESET
6
19
P03
P21/AIN1
7
18
P10
P20/AIN0
8
17
P11/CNTR1
D5
9
16
P12/CNTR0
D4
10
15
P13/INT
D3/AIN5
11
14
D0
D2/AIN4
12
13
D1
M34509G4-XXXFP
M34509G4FP
M34509G4H-XXXFP
M34509G4HFP
VDD
Outline PRSP0024GA-A (24P2Q-A)
Pin configuration (top view) (4509 Group)
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REJ03B0147-0102
page 1 of 140
Block diagram (4509 Group)
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REJ03B0147-0102
page 2 of 140
Port P1
4
Serial I/O
(8 bits ✕ 1)
A/D converter
(10 bits ✕ 6 ch)
Watchdog timer
(16 bits)
Timer 2 (8 bits)
Timer 1 (8 bits)
Timer
Port P2
2
Register A (4 bits)
Register B (4 bits)
Register E (8 bits)
Register D (3 bits)
Stack register SK (8 levels)
Interrupt stack register SDP (1level)
ALU (4 bits)
4500 Series
CPU core
Internal peripheral functions
Port P0
Note: These circuits are equipped with only H version.
I/O port
4
Port D
6
256 words ✕ 4 bits
RAM
4096 words ✕ 10 bits
ROM
Memory
Power-on reset circuit (Note)
Voltage drop detection circuit (Note)
XIN -XOUT
(Ceramic/RC)
On-chip oscillator
System clock generating circuit
Port P3
2
4509 Group
4509 Group
PERFORMANCE OVERVIEW
Parameter
Number of
M34509G4
basic instructions
M34509G4H
Minimum instruction execution time
Memory sizes ROM
Input/Output
ports
RAM
D0–D5
I/O
P00–P03 I/O
P10–P13 I/O
P20, P21 I/O
P30, P31 I/O
Timers
CNTR0, Timer I/O
CNTR1
INT
Interrupt input
SIN, SOUT, Serial interface
SCK
input/output
AIN0–AIN5 Analog input
Timer 1
Timer 2
Watchdog timer function
A/D
converter
Analog input
Serial interface
Voltage drop Reset occurrence
detection
Reset release
circuit (Note)
Power-on reset circuit (Note)
Interrupt
Sources
Nesting
Subroutine nesting
Device structure
Package
Operating temperature range
Supply voltage
Power
Active mode
dissipation
RAM back-up mode
(typical value)
Function
134
135
0.5 µs (at 6 MHz oscillation frequency, in through mode)
4096 words ✕ 10 bits
256 words ✕ 4 bits
Six independent I/O ports.
Input is examined by skip decision.
Ports D 2 and D 3 are equipped with a pull-up function and a key-on wakeup function.
Both functions can be switched by software.
Ports D2 and D3 are also used as AIN4, and AIN5, respectively.
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function.
Both functions and output structure can be switched by software.
Ports P00, P01 and P02 are also used as SIN, SOUT and SCK, respectively.
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function.
Both functions and output structure can be switched by software.
Ports P11, P12 and P13 are also used as CNTR1, CNTR0 and INT, respectively.
2-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function.
Both functions and output structure can be switched by software.
Ports P20 and P21 are also used as AIN0 and AIN1, respectively.
2-bit I/O port; The output structure can be switched by software.
Ports P30 and P31 are also used as AIN2 and AIN3, respectively.
Two independent I/O; CNTR1 and CNTR0 pins are also used as ports P1 1 and P12, respectively.
1-bit input; INT pin is also used as port P13.
Three independent I/O;
SIN, SOUT, and SCK are also used as ports P00, P01, and P02, respectively.
Six independent input; AIN0–AIN5 are also used as P20, P21, P30, P31, D2 and D3, respectively.
8-bit programmable timer/event counter with two reload registers and PWM output function.
8-bit programmable timer/event counter with two reload registers and PWM output function.
16-bit timer (fixed dividing frequency) (for watchdog)
10-bit wide, This is equipped with an 8-bit comparator function.
6 channel (AIN0–AIN5 pins)
8-bit ✕ 1
Typ. 2.6 V (Ta = 25 °C)
Typ. 2.7 V (Ta = 25 °C)
Built-in type
5 (one for external, two for timer, one for A/D, one for Serial interface)
1 level
8 levels
CMOS silicon gate
24-pin plastic molded SSOP (PRSP0024GA-A)
–20 °C to 85 °C
1.8 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.)
2.2 mA (Ta = 25°C, VDD = 5.0 V, f(XIN) = 6.0 MHz, f(STCK) = f(XIN)/1)
0.1 µA (Ta = 25°C, VDD = 5.0 V, output transistors in the cut-off state)
Note: These circuits are equipped with only the H version.
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4509 Group
PIN DESCRIPTION
Pin
VDD
VSS
CNVSS
RESET
Name
Power supply
Ground
CNVSS
Reset input/output
Input/Output
—
—
—
I/O
XIN
System clock input
Input
XOUT
System clock output
Output
D0–D5
I/O port D
Input is examined by
skip decision.
I/O
P00–P03
I/O port P0
I/O
P10–P13
I/O port P1
I/O
P20, P21
I/O port P2
I/O
P30, P31
I/O port P3
I/O
CNTR0
Timer input/output
I/O
CNTR1
Timer input/output
I/O
INT
Interrupt input
Input
AIN0–AIN5 Analog input
SCK
SOUT
SIN
Input
Serial interface clock I/O
Serial interface data output
Serial interface data input
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I/O
Output
Input
page 4 of 140
Function
Connected to a plus power supply.
Connected to a 0 V power supply.
Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
An N-channel open-drain I/O pin for a system reset. When the SRST instruction,
watchdog timer, the voltage drop detection circuit (only for H version) or the built-in
power-on reset (only for H version) causes the system to be reset, the RESET pin outputs “L” level.
I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it
between pins XIN and XOUT. A feedback resistor is built-in between them. When using
the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open.
Each pin of port D has an independent 1-bit wide I/O function.
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Ports D2 and D3 are equipped with a pull-up function and a key-on wakeup function.
Both functions can be switched by software.
Ports D2 and D3 are also used as AIN4 and AIN5, respectively.
Port P0 serves as a 4-bit I/O port.
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Port P0 has a key-on wakeup function and a pull-up function. Both functions can be
switched by software.
Ports P00, P01 and P02 are also used as SIN, SOUT and SCK, respectively.
Port P1 serves as a 4-bit I/O port.
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Port P1 has a key-on wakeup function and a pull-up function. Both functions can be
switched by software.
Ports P11, P12 and P13 are also used as CNTR1, CNTR0 and INT, respectively.
Port P2 serves as a 2-bit I/O port.
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Port P2 has a key-on wakeup function and a pull-up function. Both functions can be
switched by software.
Ports P20 and P21 are also used as AIN0 and AIN1, respectively.
Port P3 serves as a 2-bit I/O port.
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Ports P30 and P31 are also used as AIN2 and AIN3, respectively.
CNTR0 pin has the function to input the clock for the timer 2 event counter, and to
output the PWM signal generated by timer 1.
This pin is also used as port P12.
CNTR1 pin has the function to input the clock for the timer 1 event counter, and to
output the PWM signal generated by timer 2.
This pin is also used as port P11.
INT pin accepts external interrupts. It has the key-on wakeup function which can be
switched by software.
This pin is also used as port P13.
A/D converter analog input pins.
AIN0–AIN5 are also used as ports P20, P21, P30, P31, D2 and D3, respectively.
Serial interface data transfer synchronous clock I/O pin. S CK pin is also used as port P02.
Serial interface data output pin. SOUT pin is also used as port P01.
Serial interface data input pin. SIN pin is also used as port P00.
4509 Group
MULTIFUNCTION
Pin
P00
P01
P02
P11
P12
P13
Pin
SIN
SOUT
SCK
CNTR1
CNTR0
INT
Multifunction
SIN
SOUT
SCK
CNTR1
CNTR0
INT
Multifunction
P00
P01
P02
P11
P12
P13
Pin
P20
P21
P30
P31
D2
D3
Multifunction
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
Pin
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
Multifunction
P20
P21
P30
P31
D2
D3
Notes 1: Pins except above have just single function.
2: The input/output of P00 can be used even when SIN is used. Be careful when using inputs of both SIN and P00 since the input threshold value of SIN pin
is different from that of port P00.
3: The input of P01 can be used even when SOUT is used.
4: The input of P02 can be used even when SCK is used. Be careful when using inputs of both SCK and P02 since the input threshold value of SCK pin is
different from that of port P02.
5: The input of P11 can be used even when CNTR1 (output) is selected.
The input/output of P11 can be used even when CNTR1 (input) is selected. Be careful when using inputs of both CNTR1 and P11 since the input threshold value of CNTR1 pin is different from that of port P11.
6: The input of P12 can be used even when CNTR0 (output) is selected.
The input/output of P12 can be used even when CNTR0 (input) is selected. Be careful when using inputs of both CNTR0 and P12 since the input threshold value of CNTR0 pin is different from that of port P12.
7: The input/output of P13 can be used even when INT is used. Be careful when using inputs of both INT and P13 since the input threshold value of INT
pin is different from that of port P13.
8: The input/output of P20, P21, P30, P31, D2, D3 can be used even when AIN0–AIN5 are used.
PORT FUNCTION
Input
Output
I/O
(6)
N-channel open-drain/
CMOS
Port P0 P00/SIN, P01/SOUT,
P02/SCK, P03
I/O
(4)
N-channel open-drain/
CMOS
Port P1 P10, P11/CNTR1,
P12/CNT0,
P13/INT
I/O
(4)
N-channel open-drain/
CMOS
Port P2 P20/AIN0
P21/AIN1
I/O
(2)
N-channel open-drain/
CMOS
Port P3 P30/AIN2
P31/AIN3
I/O
(2)
N-channel open-drain/
CMOS
Port
Port D
Pin
D0, D1, D4, D5
Output structure
D2/AIN4
D3/AIN5
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I/O
Control
Control
Remark
unit instructions registers
1
SD, RD
Programmable output structure selection
FR3, C1
SZD, CLD
function
FR3, PU2 Programmable pull-up function
Programmable key-on wakeup function
K2
Programmable output structure selection
Q1
function
4
OP0A
FR0, PU0 Programmable pull-up function
IAP0
K0
Programmable key-on wakeup function
J1
Programmable output structure selection
function
4
OP1A
FR1, PU1 Programmable pull-up function
IAP1
K1, L1, I1 Programmable key-on wakeup function
W1, W2
Programmable output structure selection
W5, W6
function
2
OP2A
FR2, PU2 Programmable pull-up function
IAP2
Q1
Programmable key-on wakeup function
K2
Programmable output structure selection
function
2
OP3A
C1
Programmable output structure selection
IAP3
Q1
functions
4509 Group
DEFINITION OF CLOCK AND CYCLE
● Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external RC oscillation
• Clock (f(XIN)) by the external input
• Clock (f(RING)) of the on-chip oscillator which is the internal oscillator.
● System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the register MR and register RG.
● Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one machine cycle.
● Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
Table Selection of system clock
MR3
1
1
0
0
1
1
0
0
Register MR, RG
MR1
MR0
MR2
1
–
1
0
–
1
1
–
1
0
–
1
1
0
0
0
0
0
1
0
0
0
0
0
System clock
RG0
0
0
0
0
–
–
–
–
f(STCK) = f(RING)/8
f(STCK) = f(RING)/4
f(STCK) = f(RING)/2
f(STCK) = f(RING)
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
Operation mode
Internal frequency divided by 8 mode
Internal frequency divided by 4 mode
Internal frequency divided by 2 mode
Internal frequency through mode
High-speed frequency divided by 8 mode
High-speed frequency divided by 4 mode
High-speed frequency divided by 2 mode
High-speed through mode
Note: The internal frequency divided by 8 is selected after system is released from reset.
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4509 Group
CONNECTIONS OF UNUSED PINS
Pin
XIN
XOUT
D 0, D1 , D4, D 5
D2/AIN4, D3/AIN5
P00/SIN
Connection
Connect to VSS.
Open.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
P01/SOUT
Open.
Connect to VSS.
P02/SCK
Open.
Connect to VSS.
P03
Open.
Connect to VSS.
P10
Open.
Connect to VSS.
P11/CNTR1
Open.
Connect to VSS.
P12/CNTR0
Open.
Connect to VSS.
P13/INT
Open.
Connect to VSS.
P20/AIN0, P21/AIN1
Open.
Connect to VSS.
P30/AIN2, P31/AIN3
Open.
Connect to VSS.
Usage condition
RC oscillation circuit is not selected. (CRCK instruction is not executed.)
N-channel open-drain is selected for the output structure (FR30, FR31, C12, C13 = “0”).
The key-on wakeup function is invalid (K22, K23 = “0”).
N-channel open-drain is selected for the output structure (FR32, FR33 = “0”).
Pull-up transistor is OFF (PU22, PU23 = “0”).
The key-on wakeup function is invalid (K22, K23 = “0”).
SIN pin is not selected (J11 = “0”).
The key-on wakeup function is invalid (K00 = “0”).
N-channel open-drain is selected for the output structure (FR00 = “0”).
Pull-up transistor is OFF (PU00 = “0”).
The key-on wakeup function is invalid (K00 = “0”).
The key-on wakeup function is invalid (K01 = “0”).
N-channel open-drain is selected for the output structure (FR01 = “0”).
Pull-up transistor is OFF (PU01 = “0”).
The key-on wakeup function is invalid (K01 = “0”).
SCK pin is not selected (J11J10 = “00”).
The key-on wakeup function is invalid (K02 = “0”).
N-channel open-drain is selected for the output structure (FR02 = “0”).
Pull-up transistor is OFF (PU02 = “0”).
The key-on wakeup function is invalid (K02 = “0”).
The key-on wakeup function is invalid (K03 = “0”).
N-channel open-drain is selected for the output structure (FR03 = “0”).
Pull-up transistor is OFF (PU03 = “0”).
The key-on wakeup function is invalid (K03 = “0”).
The key-on wakeup function is invalid (K10 = “0”).
N-channel open-drain is selected for the output structure (FR10 = “0”).
Pull-up transistor is OFF (PU10 = “0”).
The key-on wakeup function is invalid (K10 = “0”).
CNTR1 input is not selected for the timer 1 count source (W11, W10 ≠ “10”).
The key-on wakeup function is invalid (K11 = “0”).
N-channel open-drain is selected for the output structure (FR11 = “0”).
Pull-up transistor is OFF (PU11 = “0”).
The key-on wakeup function is invalid (K11 = “0”).
CNTR0 input is not selected for the timer 2 count source (W21, W20 ≠ “10”).
The key-on wakeup function is invalid (K12 = “0”).
N-channel open-drain is selected for the output structure (FR12 = “0”).
Pull-up transistor is OFF (PU12 = “0”).
The key-on wakeup function is invalid (K12 = “0”).
INT pin input is disabled (I13 = “0”).
The key-on wakeup function is invalid (K13 = “0”).
N-channel open-drain is selected for the output structure (FR13 = “0”).
Pull-up transistor is OFF (PU13 = “0”).
The key-on wakeup function is invalid (K13 = “0”).
The key-on wakeup function is invalid (K20, K21 = “0”).
N-channel open-drain is selected for the output structure (FR20, FR21 = “0”).
Pull-up transistor is OFF (PU20, PU21 = “0”).
The key-on wakeup function is invalid (K20, K21 = “0”).
N-channel open-drain is selected for the output structure (C11, C10 = “0”).
(Note when connecting to VSS or VDD)
● Connect the unused pins to VSS using the thickest wire at the shortest distance against noise.
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4509 Group
PORT BLOCK DIAGRAMS
Skip decision
Decoder
Register Y
SZD instruction
(Note 3) FR3j
CLD
instruction
(Note 1)
S
D0, D1 (Note 2)
SD instruction
(Note 1)
R Q
RD instruction
(Note 4)
K2k
“L” level
detection circuit
Key-on wakeup input
Pull-up transistor
PU2k (Note 4)
Skip decision
Decoder
Register Y
SZD instruction
CLD
instruction
(Note 4) FR3K
(Note 1)
(Note 2)
S
D2/AIN4, D3/AIN5
SD instruction
(Note 1)
R Q
RD instruction
Q1
Decoder
Analog input
Skip decision
Register Y
Decoder
CLD
instruction
SZD instruction
(Note 4) C1k
(Note 1)
S
SD instruction
R Q
RD instruction
D4, D5 (Notes 2)
(Note 1)
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: j represents bits 0 or 1.
4: k represents bits 2 or 3.
Port block diagram (1)
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4509 Group
K00
Level
detection circuit
Key-on wakeup input
PU00
IAP0 instruction
Register A
A0
F R 00
A0
D
OP0A instruction
T
(Note 1)
P00/SIN (Note 2)
(Note 1)
Q
Serial interface data input
J11
K01
Level
detection circuit
Key-on wakeup input
Register A
A1
PU01
IAP0 instruction
FR01
A1
D
OP0A instruction
T
(Note 1)
P01/SOUT (Note 2)
J10
Q
0
(Note 1)
1
Serial interface data output
K02
Level
detection circuit
Key-on wakeup input
Register A
A2
PU02
IAP0 instruction
F R 02
A2
OP0A instruction
(Note 1)
D
T
P02/SCK (Note 2)
(Note 1)
Q
Synchronous clock (output) for
serial interface data transfer
Synchronous clock (input) for
serial interface data transfer
J10
J11
This symbol represents a parasitic diode on the port.
Notes 1:
2: Applied potential to these ports must be VDD or less.
Port block diagram (2)
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4509 Group
K03
Level
detection circuit
Key-on wakeup input
Register A
A3
PU03
IAP0 instruction
FR03
A3
D
OP0A instruction
T
P03
0
1
K10
L12
0
Level detection circuit
Edge detection circuit
Register A
A0
PU10
1
IAP1 instruction
FR10
A0
D
OP1A instruction
T
0
1
(Note 1)
P10 (Note 2)
(Note 1)
Q
K11
L13
Key-on
wakeup
input
(Note 2)
(Note 1)
Q
L13
Key-on
wakeup
input
(Note 1)
L12
0
Level detection circuit
Edge detection circuit
Register A
A1
PU11
1
IAP1 instruction
FR11
A1
D
OP1A instruction
T
(Note 1)
P11/CNTR1 (Note 2)
W63
0
Q
PWMOD2
(Note 1)
1
W60
Clock (input) for
timer 1 event count
0
W10
1
W11
This symbol represents a parasitic diode on the port.
Notes 1:
2: Applied potential to these ports must be VDD or less.
Port block diagram (3)
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4509 Group
K12
L13
Key-on
wakeup
input
L12
0
0
Level detection circuit
Edge detection circuit
1
Register A
A2
PU12
1
IAP1 instruction
FR12
A2
D
OP1A instruction
T
(Note 1)
P12/CNTR0 (Note 2)
W53
0
Q
PWM1
(Note 1)
1
W50
0
Clock (input) for
timer 2 event count
1
W20
W21
K13
L13
Key-on
wakeup
input
0
1
L12
Level detection circuit
Edge detection circuit
Register A
A3
0
PU13
1
IAP1 instruction
FR13
(Note 1)
A3
D
OP1A instruction
T
P13/INT (Note 2)
(Note 1)
Q
(Notes 3, 4)
External 0 interrupt
External 0 interrupt circuit
Key-on wakeup input
Timer 1 count start synchronous circuit input
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: As for details, refer to the external interrupt structure.
4: The threshold value of port input is different from that of external interrupt input.
Port block diagram (4)
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4509 Group
(Note 3)
K2j
Key-on wakeup input
Level
detection circuit
(Note 3)
PU2j
(Note 3)
Register A
IAP2 instruction
Aj
FR2j
(Note 1)
P20/AIN0, (Note 2)
P21/AIN1
(Note 1)
D
Aj
OP2A instruction
T
Q
Q1
Decoder
Analog input
(Note 3)
Register A
IAP3 instruction
Aj
C1j
(Note 1)
P30/AIN2,(Notes 2)
P31/AIN3
(Note 1)
D
Aj
OP3A instruction
T
Q
Q1
Decoder
Analog input
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: j represents 0 or 1.
Port block diagram (5)
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4509 Group
I12
Falling
(Note 1)
0
One-sided edge
detection circuit
I11
0
P13/INT
EXF0
1
1
Both edges
detection circuit
Rising
SNZI0 instruction
I13
Skip
L10
(Note 2)
Level detection circuit
Edge detection circuit
(Note 3)
External 0
interrupt
Timer 1 count start
synchronization
circuit input
L11
0
Key-on wakeup input
1
This symbol represents a parasitic diode on the port.
Note 1: •
2: When I12 is 0, “L” level is detected.
When I12 is 1, “H” level is detected.
3: When I12 is 0, falling edge is detected.
When I12 is 1, rising edge is detected.
External interrupt circuit structure
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4509 Group
FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(CY)
(1) Arithmetic logic unit (ALU)
(M(DP))
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit
data addition, comparison, AND operation, OR operation, and bit
manipulation.
Addition
ALU
(A)
<Result>
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, exchange,
and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a carry
with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction. The
value of A0 is stored in carry flag CY with the RAR instruction (Figure
2).
Carry flag CY can be set to “1” with the SC instruction and cleared to
“0” with the RC instruction.
Fig. 1 AMC instruction execution example
<Set>
SC instruction
<Clear>
RC instruction
CY
A3 A2 A1 A0
<Rotation>
RAR instruction
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit data,
and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data transfer
with register B used as the high-order 4 bits and register A as the
low-order 4 bits (Figure 3).
Register E is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
TAB instruction
Register B
B3 B2 B1 B0
(4) Register D
Register E E7 E6 E5 E4 E3 E2 E1 E0
TABE instruction
B3 B2 B1 B0
Register B
p6 p5
A3 A2 A1 A0
TBA instruction
Register A
Fig. 3 Registers A, B and register E
ROM
Specifying address
PCH
p4 p3 p2 p1 p0
A3 A2 A1 A0
TEAB instruction
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register A and
is used as a pointer within the specified page when the TABP p, BLA
p, or BMLA p instruction is executed (Figure 4).
Also, when the TABP p instruction is executed at UPTF flag = “1”,
the high-order 2 bits of ROM reference data is stored to the low-order 2 bits of register D, the high-order 1 bit of register D is “0”. When
the TABP p instruction is executed at UPTF flag = “0”, the contents
of register D remains unchanged. The UPTF flag is set to “1” with the
SUPT instruction and cleared to “0” with the RUPT instruction. The
initial value of UPTF flag is “0”.
Register D is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
TABP p instruction
Register A
PCL
DR2DR1DR0 A3 A2 A1 A0
8
4
0
Low-order 4bits
Register A (4)
Middle-order 4 bits
Register B (4)
High-order 2 bits
Immediate field
value p
The contents of The contents of
register D
register A
Fig. 4 TABP p instruction execution example
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Register D (3)
* Flag UPTF = 1;
High-order 2 bits of reference data is
transferred to the low-order 2 bits of register D.
“0” is stored to the high-order 1 bit of register D.
Flag UPTF = 0;
Data is not transferred to register D.
4509 Group
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents of
program counter (PC) just before branching until returning to the
original routine when;
• branching to an interrupt service routine (referred to as an interrupt
service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is
used respectively when using an interrupt service routine and when
executing a table reference instruction. Accordingly, be careful not to
over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded.
The register SK nesting level is pointed automatically by 3-bit stack
pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction.
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an interrupt
occurs, this register (SDP) is used to temporarily store the contents
of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine.
Unlike the stack registers (SKs), this register (SDP) is not used when
executing the subroutine call instruction and the table reference instruction.
Program counter (PC)
Executing BM
instruction
Executing RT
instruction
SK0
(SP) = 0
SK1
(SP) = 1
SK2
(SP) = 2
SK3
(SP) = 3
SK4
(SP) = 4
SK5
(SP) = 5
SK6
(SP) = 6
SK7
(SP) = 7
Stack pointer (SP) points “7” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after eight
stack registers are used ((SP) = 7), (SP) = 0
and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(SP) ← 0
(SK0) ← 000116
(PC) ← SUB1
Main program
(7) Skip flag
Address
Skip flag controls skip decision for the conditional skip instructions
and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt
stack register (SDP) and the skip condition is retained.
000016 NOP
Subroutine
SUB1 :
NOP
·
·
·
RT
000116 BM SUB1
000216 NOP
(PC) ← (SK0)
(SP) ← 7
Note : Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction becomes the NOP instruction.
Fig. 6 Example of operation at subroutine call
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4509 Group
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page and
address). It determines a sequence in which instructions stored in
ROM are read. It is a binary counter that increments the number of
instruction bytes each time an instruction is executed. However,
the value changes to a specified address when branch instructions,
subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed.
Program counter consists of PC H (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address
(address 127) of a page, it specifies address 0 of the next page
(Figure 7).
Make sure that the PCH does not specify after the last page of the
built-in ROM.
Program counter
p6 p5 p4 p3 p2 p1 p0
a6 a5 a4 a3 a2 a1 a0
PCH
Specifying page
PCL
Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP)
Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists
of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure
8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y certainly
and execute the SD, RD, or SZD instruction (Figure 9).
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.
Specifying
RAM digit
Register Y (4)
Register X (4)
Register Z (2)
Specifying RAM file
Specifying RAM file group
Fig. 8 Data pointer (DP) structure
Specifying bit position
Set
D3
0
0
0
D2
1
Register Y (4)
page 16 of 140
D0
1
Port D output latch
Fig. 9 SD instruction execution example
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D1
4509 Group
PROGRAM MEMOY (ROM)
1 word of program memory is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127).
Table 1 shows the ROM size and pages. Figure 10 shows the ROM
map of M34509G4.
Table 1 ROM size and pages
Part number
M34509G4
M34509G4H
ROM (PROM) size
(✕ 10 bits)
4096 words
4096 words
Pages
32 (0 to 31)
32 (0 to 31)
A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address
(interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is
executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address.
Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any
page with the 1-word instruction (BM). Subroutines extending from
page 2 to another page can also be called with the BM instruction
when it starts on page 2.
ROM pattern (bits 7 to 0) of all addresses can be used as data areas
with the TABP p instruction.
ROM Code Protect Address
When selecting the protect bit write by using a serial programmer or
selecting protect enabled for writing shipment by Renesas Technology corp., reading or writing from/to QzROM is disabled by a serial
programmer.
As for the QzROM product in blank, the ROM code is protected by
selecting the protect bit write at ROM writing with a serial programmer.
As for the QzROM product shipped after writing, whether the ROM
code protect is used or not can be selected as ROM option setup
(“MASK option” written in the mask file converter) when ordering.
9 8 7 6
000016
007F16
008016
00FF16
010016
017F16
018016
5 4 3
2 1 0
Page 0
Interrupt address page
Page 1
Subroutine special page
Page 2
Page 3
0FFF16
Page 31
Fig. 10 ROM map of M34509G4
008016
9 8 7 6 5 4 3 2 1 0
External 0 interrupt address
008216
008416
Timer 1 interrupt address
008616
Timer 2 interrupt address
008816
008A16
008C16
A/D interrupt address
008E16 Serial interface interrupt address
00FF16
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure
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4509 Group
DATA MEMORY (RAM)
Table 2 RAM size
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with
the SB j, RB j, and SZB j instructions) is enabled for the entire
memory area. A RAM address is specified by a data pointer. The
data pointer consists of registers Z, X, and Y. Set a value to the
data pointer certainly when executing an instruction to access
RAM.
Table 2 shows the RAM size. Figure 12 shows the RAM map.
Part number
M34509G4
M34509G4H
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.
RAM 256 words ✕ 4 bits (1024 bits)
Register Z
Register X
0
1
2
3
4
5
Register Y
6
7
8
9
10
11
12
13
14
15
Fig. 12 RAM map
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0 1
0
2 3 ... 6 7
........ 15
RAM size
256 words ✕ 4 bits (1024 bits)
256 words ✕ 4 bits (1024 bits)
4509 Group
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source. An
interrupt occurs when the following 3 conditions are satisfied.
• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request flag
for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt
enable/disable. Interrupts are enabled when INTE flag is set to “1”
with the EI instruction and disabled when INTE flag is cleared to “0”
with the DI instruction. When any interrupt occurs, the INTE flag is
automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed.
Table 3 Interrupt sources
Priority
Interrupt name
level
1
External 0 interrupt
Activated condition
2
Timer 1 interrupt
Level change of INT
pin
Timer 1 underflow
3
Timer 2 interrupt
Timer 2 underflow
4
A/D interrupt
5
Serial interface
interrupt
Completion of
A/D conversion
Completion of serial
interface transmit/
recieve
Interrupt
address
Address 0
in page 1
Address 4
in page 1
Address 6
in page 1
Address C
in page 1
Address E
in page 1
Table 4 Interrupt request flag, interrupt enable bit and skip instruction
(2) Interrupt enable bit
External 0 interrupt
SNZ0
Interrupt
enable bit
V10
Use an interrupt enable bit of interrupt control registers V1 and V2 to
select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and skip
instruction.
Table 5 shows the interrupt enable bit function.
Timer 1 interrupt
T1F
SNZT1
V12
Timer 2 interrupt
T2F
SNZT2
V13
A/D interrupt
ADF
SIOF
SNZAD
V22
V23
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “1.” Each interrupt request
flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt
enable bit. Once set, the interrupt request flag retains set until a
clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown
in Table 3.
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Interrupt name
Serial interface
interrupt
Interrupt
request flag
EXF0
Skip instruction
SNZSI
Table 5 Interrupt enable bit function
Interrupt enable bit
1
0
Occurrence of interrupt
Enabled
Disabled
Skip instruction
Invalid
Valid
4509 Group
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as follows (Figure 14).
• Program counter (PC)
An interrupt address is set in program counter. The address to be
executed when returning to the main routine is automatically
stored in the stack register (SK).
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source is cleared to
“0.”
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored automatically
in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write
the branch instruction to an interrupt service routine at an interrupt
address.
Use the RTI instruction to return from an interrupt service routine.
Interrupt enabled by executing the EI instruction is performed after
executing 1 instruction (just after the next instruction is executed).
Accordingly, when the EI instruction is executed just before the RTI
instruction, interrupts are enabled after returning the main routine.
(Refer to Figure 13)
Main
routine
•
•
•
•
EI
R TI
Interrupt is
enabled
: Interrupt enabled state
: Interrupt disabled state
Fig. 13 Program example of interrupt processing
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REJ03B0147-0102
• Stack register (SK)
The address of main routine to be
....................................................................................................
executed when returning
• Interrupt enable flag (INTE)
.................................................................. 0 (Interrupt disabled)
• Interrupt request flag (only the flag for the current interrupt
source) ................................................................................... 0
• Data pointer, carry flag, registers A and B, skip flag
........ Stored in the interrupt stack register (SDP) automatically
Fig. 14 Internal state when interrupt occurs
INT pin
(L→H or
Timer 1
underflow
Timer 2
underflow
page 20 of 140
Serial interface
transmit/receive
completed
Activated
condition
Address 0
in page 1
EXF0
V10
T1F
V12
Address 4
in page 1
T2F
V13
Address 6
in page 1
H→L input)
Completion of
A/D conversion
Interrupt
service routine
Interrupt
occurs
• Program counter (PC)
............................................................... Each interrupt address
Address C
in page 1
ADF
V22
SIOF
V23
INTE
Request flag
(state retained)
Enable
bit
Enable
flag
Fig. 15 Interrupt system diagram
Address E
in page 1
4509 Group
(6) Interrupt control registers
• Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can be
used to transfer the contents of register V1 to register A.
• Interrupt control register V2
The A/D interrupt enable bit and serial interface interrupt enable bit
are assigned to register V2. Set the contents of this register
through register A with the TV2A instruction. The TAV2 instruction
can be used to transfer the contents of register V2 to register A.
Table 6 Interrupt control registers
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V2
V23
Serial interface interrupt enable bit
V22
A/D interrupt enable bit
V21
Not used
V20
Not used
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
at reset : 00002
0
1
0
1
0
1
0
1
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt enable
bits (V10, V12, V13, V22, V23), and interrupt request flag are “1.” The
interrupt actually occurs 2 to 3 machine cycles after the cycle in
which all three conditions are satisfied. The interrupt occurs after 3
machine cycles only when the three interrupt conditions are satisfied
on execution of other than one-cycle instructions (Refer to Figure
16).
page 21 of 140
R/W
TAV1/TV1A
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Note: “R” represents read enabled, and “W” represents write enabled.
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at RAM back-up : 00002
at RAM back-up : 00002
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
R/W
TAV2/TV2A
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Fig. 16 Interrupt sequence
page 22 of 140
T1F, T2F
ADF, SIOF
EXF0
T2
T3
EI instruction execution cycle
T1
T1
T2
T3
T1
T3
T1
T2
T1
T2
The program starts
from the interrupt
address.
Retaining level of system
clock for 4 periods or more
is necessary.
Interrupt disabled state
Flag cleared
T3
2 to 3 machine cycles
(Notes 1, 2)
Interrupt activated
condition is satisfied.
Interrupt enabled state
T2
Notes 1: The address is stacked to the last cycle.
2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
Timer 1,
Timer 2,
A/D
and serial
interface
interrupts
External
interrupt
INT
Interrupt enable
flag (INTE)
System clock
1 machine cycle
● When an interrupt request flag is set after its interrupt is enabled
4509 Group
4509 Group
EXTERNAL INTERRUPTS
The 4509 Group has the external 0 interrupt. An external interrupt
request occurs when a valid waveform is input to an interrupt input
pin (edge detection).
The external interrupt can be controlled with the interrupt control
register I1.
Table 7 External interrupt activated conditions
Name
Input pin
External 0 interrupt
Valid waveform
selection bit
Activated condition
P13/INT
I11
I12
When the next waveform is input to P13/INT pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
I12
Falling
(Note 1)
0
One-sided edge
detection circuit
I11
0
P13/INT
EXF0
1
1
Both edges
detection circuit
Rising
SNZI0 instruction
I13
Skip
(Note 2)
Level detection circuit
Edge detection circuit
L10
(Note 3)
External 0
interrupt
Timer 1 count start
synchronization
circuit input
L11
0
Key-on wakeup input
1
This symbol represents a parasitic diode on the port.
Note 1: •
2: When I12 is 0, “L” level is detected.
When I12 is 1, “H” level is detected.
3: When I12 is 0, falling edge is detected.
When I12 is 1, rising edge is detected.
Fig. 17 External interrupt circuit structure
(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to “1” when a valid
waveform is input to P13/INT pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure
16).
The state of EXF0 flag can be examined with the skip instruction
(SNZ0). Use the interrupt control register V1 to select the interrupt or
the skip instruction. The EXF0 flag is cleared to “0” when an interrupt
occurs or when the next instruction is skipped with the skip instruction.
• External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a valid
waveform is input to P13/INT pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of how
to use the external 0 interrupt is as follows.
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➀ Set the bit 3 of register I1 to “1” for the INT pin to be in the input
enabled state.
➁ Select the valid waveform with the bits 1 and 2 of register I1.
➂ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➃ Set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction.
➄ Set both the external 0 interrupt enable bit (V1 0) and the INTE
flag to “1.”
The external 0 interrupt is now enabled. Now when a valid waveform is input to the P13/INT pin, the EXF0 flag is set to “1” and the
external 0 interrupt occurs.
4509 Group
(2) External interrupt control registers
• Interrupt control register I1
Register I1 controls the valid waveform for the external 0 interrupt.
Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents
of register I1 to register A.
Table 8 External interrupt control register
Interrupt control register I1
I13
INT pin input control bit (Note 2)
I12
Interrupt valid waveform for INT pin/
return level selection bit (Note 2)
I11
I10
INT pin edge detection circuit control bit
INT pin
timer 1 control enable bit
at reset : 00002
0
1
0
1
0
1
0
1
at RAM back-up : state retained
INT pin input disabled
INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
Enabled
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.
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R/W
TAI1/TI1A
4509 Group
(3) Notes on interrupts
➂ Note [3] on bit 2 of register I1
When the interrupt valid waveform of the P13/INT pin is changed
with the bit 2 of register I1 in software, be careful about the following notes.
• Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1
is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀) and
then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0”
after executing at least one instruction (refer to Figure 18➁).
Also, set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction (refer to Figure 18➂).
• Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1
is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀) and
then, change the bit 2 of register I1 is changed.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0”
after executing at least one instruction (refer to Figure 20➁).
Also, set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction (refer to Figure 20➂).
•••
•••
➀ Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of register
I1 in software, be careful about the following notes.
LA
4
TV1A
LA
8
TI1A
NOP
SNZ0
LA
4
TV1A
LA
12
TI1A
NOP
SNZ0
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (1✕✕✕2)
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT pin input is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
✕ : these bits are not used here.
Fig. 18 External 0 interrupt program example-1
➁ Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
•••
• When the INT pin input is disabled (register I13 = “0”), set the keyon wakeup of INT pin to be invalid (register L1 0 = “0”) before
system enters to the RAM back-up mode. (refer to Figure 19➀).
; (✕✕✕02)
; INT key-on wakeup disabled ........... ➀
; RAM back-up
•••
LA
0
TI1A
DI
EPOF
POF
✕ : these bits are not used here.
Fig. 19 External 0 interrupt program example-2
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Fig. 20 External 0 interrupt program example-3
4509 Group
TIMERS
• Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency dividing
ratio (n). An interrupt request flag is set to “1” after every n count of
a count pulse.
The 4509 Group has the following timers.
• Programmable timer
The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a setting
value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload register,
and count continues (auto-reload function).
F F1 6
n : Counter initial value
Count starts
Reload
Reload
The contents of counter
n
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
Timer interrupt “1”
“0”
request flag
An interrupt occurs or
a skip instruction is executed.
Fig. 21 Auto-reload function
The 4509 Group timer consists of the following circuits.
• Prescaler : 8-bit programmable timer
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
(Timers 1 and 2 have the interrupt function, respectively)
• 16-bit timer
Prescaler and timers 1 and 2 can be controlled with the timer control
registers PA, W1, W2 , W5 and W6. The 16-bit timer is a free counter
which is not controlled with the control register.
Each function is described below.
Table 9 Function related timers
Circuit
Prescaler
• Instruction clock (INSTCK)
Frequency
dividing ratio
1 to 256
8-bit programmable
• PWM2 signal (PWMOD2)
1 to 256
binary down counter
• Prescaler output (ORCLK)
Count source
Structure
8-bit programmable
Use of output signal
• Timer 1 and 2 count sources
Control
register
PA
binary down counter
Timer 1
• CNTR1 input
(link to INT input)
(with PWM output function) • On-chip oscillator clock (f(RING))
Timer 2
binary down counter
• Timer 1 underflow (T1UDF)
• Prescaler output (ORCLK)
(INT input period count
• CNTR0 input
function)
• System clock (STCK)
8-bit programmable
(with PWM output function)
Watchdog 16-bit fixed dividing
• Instruction clock (INSTCK)
timer
frequency
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1 to 256
• Timer 2 count source
• CNTR0 output
W1
• Timer 1 interrupt
W6
• Timer 1 count source
W2
• CNTR1 output
W5
W6
• Timer 2 interrupt
65536
• System reset (counting twice)
• Decision of flag WDF1
W5
-
4509 Group
Division circuit
Divided by 8
MR3, MR2
11
System clock (STCK)
10
MR0
On-chip oscillator
Divided by 2
1
Ceramic resonance
Multiplexer
RC oscillation
(CRCK)
(Note 1)
XIN
Divided by 4
Internal clock
generating circuit
(divided by 3)
01
00
Instruction clock
(INSTCK)
0
Prescaler (8)
PA0
ORCLK
Reload register RPS (8)
(TPSAB)
(TPSAB)
(TPSAB)
Register B
Register A
(TABPS)
(TABPS)
Watchdog timer (16)
INSTCK
1 - - - - - - - - - - - - - - 16
(Note 2)
S
Q
WDF1
WRST instruction
R
RESET signal
(Note 4)
S
Q
WEF
DWDT instruction R
+
WRST instruction (Note 3)
D
Q
T
R
Watchdog reset signal
RESET signal
Data is set automatically from each reload
register when timer underflows
(auto-reload function).
Notes 1: When CRCK instruction is executed, RC oscillation is selected.
When CRCK instruction is not executed, ceramic resonance is selected.
2: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST
instruction is executed while flag WDF1 = “1”.
The next instruction is not skipped even when the WRST instruction is executed
while flag WDF1 = “0”.
3: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the
DWDT instruction and WRST instruction are executed continuously.
4: The WEF flag is set to “1” at system reset or RAM back-up mode.
Fig. 22 Timers structure (1)
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4509 Group
I12
P13/INT
0
One-sided edge
detection circuit
I11
0
Both edges
detection circuit
1
INTSNC
I13
1
W60
P11/CNTR1
0
1
Register B Register A
W11, W10
00
PWM2
(T1HAB)
01
ORCLK
W51
0
10
T
Timer 1 (8)
11
f(RING)
Reload register R1H (8) (Note 3)
Reload control circuit
Q
PWM1
1
(T1R1L)
W12
(T1AB)
(Note 1)
INTSNC
R
Reload register R1L (8)
S
(TAB1)
Q
I10
(T1AB)
(T1AB)
Register B Register A
(TAB1)
T1F
Timer 1
interrupt
Timer 1 underflow signal
(T1UDF)
R
W52
W13
T1UDF
P12/CNTR0
W50
0
1
T1UDF
ORCLK
STCK
Register B Register A
W21, W20
00
(T2HAB)
01
W61
0
10
Reload register R2H (8) (Note 4)
Reload control circuit
T
Timer 2 (8)
11
Q
PWM2
1
(T2R2L)
W22
(T2AB)
(Note 2)
INTSNC
D
Q
T
R
(TAB2)
W61
W53
0
R
Reload register R2L (8)
(T2AB)
(T2AB)
Register B Register A
(TAB2)
T2F
W23
Timer 2
interrupt
I13
Port P12 output
P12/CNTR0
PWM1
1
W63
0
Port P11 output
P11/CNTR1
PWM2
1
Notes 1: Timer 1 count start synchronous circuit is synchronized
with the valid edge of INT pin selected by bits 1 (I11) and
2 (I12) of register I1.
W62
2: Timer 2 INT input period count circuit is used to count
R T
W12
the valid edge period of INT pin selected by bits 1 (I11)
and 2 (I12) of register I1.
3: When the PWM1 function is valid (W13=“1”), the value is
auto-reloaded alternately from reload register R1L and
T1R1L: This instruction is used to transfer the contents of
R1H every timer 1 underflow.
reload register R1L to timer 1.
When the PWM1 function is invalid (W13=“0”), the value
This
instruction
is
used
to
transfer
the
contents
of
T2R2L:
is auto-reloaded from reload register R1L only.
reload register R2L to timer 2.
4: When the PWM2 function is valid (W23=“1”), the value is
STCK: System clock
auto-reloaded alternately from reload register R2L and
ORCLK: Prescaler output
R2H every timer 2 underflow.
Data is set automatically from each reload
When the PWM2 function is invalid (W23=“0”), the value
register when timer underflows
is auto-reloaded from reload register R2L only.
(auto-reload function).
PWMOD2
Q
D
Fig. 23 Timers structure (2)
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T1UDF
4509 Group
Table 10 Timer control registers
Timer control register PA
PA0
Prescaler control bit
at reset : 02
W13
PWM1 function control bit
W12
Timer 1 control bit
W11
Timer 1 count source selection bits
W10
at reset : 00002
W23
PWM2 function control bit
W22
Timer 2 control bit
W21
Timer 2 count source selection bits
W20
W11 W10
0
0
0
1
1
0
1
1
W53
P12/CNTR0 pin function selection bit
0
W52
Timer 1 count auto-stop circuit
selection bit (Note 2)
Timer 1 count start synchronous circuit
selection bit (Note 3)
W51
W50
CNTR0 pin input count edge selection bit
W21 W20
0
0
0
1
1
0
1
1
W63
P11/CNTR1 pin function selection bit
W62
CNTR 1 pin output auto-control circuit
selection bit
Timer 2
INT pin input period count circuit selection bit
W61
W60
CNTR1 pin input count edge selection bit
at RAM back-up : state retained
R/W
TAW5/TW5A
P12 (I/O) / CNTR0 (input)
P12 (input) /CNTR0 (I/O)
Count auto-stop circuit not selected
Count auto-stop circuit selected
Count start synchronous circuit not selected
Count start synchronous circuit selected
Falling edge
Rising edge
at reset : 00002
0
1
0
1
0
1
0
1
R/W
TAW2/TW2A
Count source
Timer 1 underflow signal (T1UDF)
Prescaler output (ORCLK)
CNTR0 input
System clock (STCK)
at reset : 00002
Timer control register W6
at RAM back-up : 00002
PWM2 function invalid
PWM2 function valid
Stop (state retained)
Operating
1
0
1
0
1
0
1
0
1
0
1
R/W
TAW1/TW1A
Count source
PWM2 signal
Prescaler output (ORCLK)
CNTR1 input
On-chip oscillator clock (f(RING))
at reset : 00002
Timer control register W5
at RAM back-up : 00002
PWM1 function invalid
PWM1 function valid
Stop (state retained)
Operating
0
1
0
1
Timer control register W2
W
TPAA
Stop (state initialized)
Operating
0
1
Timer control register W1
at RAM back-up : 02
at RAM back-up : state retained
R/W
TAW6/TW6A
P11 (I/O) / CNTR1 (input)
P11 (input) /CNTR1 (I/O)
Output auto-control circuit not selected
Output auto-control circuit selected
INT pin input period count circuit not selected
INT pin input period count circuit selected
Falling edge
Rising edge
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”) and the timer 1 count start synchronous circuit is selected (W51=“1”).
3: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”).
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4509 Group
(1) Timer control registers
(3) Timer 1 (interrupt function)
• Timer control register PA
Register PA controls the count operation of prescaler. Set the contents of this register through register A with the TPAA instruction.
• Timer control register W1
Register W1 controls the count operation and count source of
timer 1, and PWM1 function. Set the contents of this register
through register A with the TW1A instruction. The TAW1 instruction
can be used to transfer the contents of register W1 to register A.
• Timer control register W2
Register W2 controls the count operation and count source of
timer 2, and PWM2 function. Set the contents of this register
through register A with the TW2A instruction. The TAW2 instruction
can be used to transfer the contents of register W2 to register A.
• Timer control register W5
Register W5 controls the input count edge of CNTR0 pin, timer 1
count start synchronous circuit, timer 1 auto-stop circuit and P12/
CNTR0 pin function. Set the contents of this register through register A with the TW5A instruction. The TAW5 instruction can be
used to transfer the contents of register W5 to register A.
• Timer control register W6
Register W6 controls the input count edge of CNTR1 pin, the INT
pin input count start synchronous circuit and CNTR1 pin output
auto-control circuit and the P11/CNTR1 pin function. Set the contents of this register through register A with the TW6A instruction.
The TAW6 instruction can be used to transfer the contents of register W6 to register A.
Timer 1 is an 8-bit binary down counter with two timer 1 reload registers (R1L, R1H). Data can be set simultaneously in timer 1 and the
reload register R1L with the T1AB instruction. Data can be set in the
reload register R1H with the T1HAB instruction. The contents of reload register R1L set with the T1AB instruction can be set to timer 1
again with the T1R1L instruction. Data can be read from timer 1 with
the TAB1 instruction.
Stop counting and then execute the T1AB or TAB1 instruction to
read or set timer 1 data.
When executing the T1HAB instruction to set data to reload register
R1H while timer 1 is operating, avoid a timing when timer 1
underflows.
Timer 1 starts counting after the following process;
➀ set data in timer 1
➁ set count source by bits 0 and 1 of register W1, and
➂ set the bit 2 of register W1 to “1.”
(2) Prescaler
Prescaler is an 8-bit binary down counter with the prescaler reload
register RPS. Data can be set simultaneously in prescaler and the
reload register RPS with the TPSAB instruction. Data can be read
from reload register RPS with the TABPS instruction.
Stop counting and then execute the TPSAB or TABPS instruction to
read or set prescaler data.
Prescaler starts counting after the following process;
➀ set data in prescaler, and
➁ set the bit 0 of register PA to “1.”
When a value set in reload register RPS is n, prescaler divides the
count source signal by n + 1 (n = 0 to 255).
Count source for prescaler is the instruction clock (INSTCK).
Once count is started, when prescaler underflows (the next count
pulse is input after the contents of prescaler becomes “0”), new data
is loaded from reload register RPS, and count continues (auto-reload
function).
The output signal (ORCLK) of prescaler can be used for timer 1 and
2 count sources.
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When a value set in reload register R1L is n and a value set in reload register R1H is m, timer 1 divides the count source signal by n
+ 1 or m + 1 (n = 0 to 255, m = 0 to 255).
<Bit 3 of register W1 = “0” (PWM1 function invalid)>
Once count is started, when timer 1 underflows (the next count pulse
is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload
register R1L, and count continues (auto-reload function).
<Bit 3 of register W1 = “1” (PWM1 function valid)>
Timer 1 generates the PWM1 signal of the “L” interval set as reload
register R1L, and the “H” interval set as reload register R1H. The
PWM1 signal generated by timer 1 is output from CNTR0 pin by setting “1” to bit 3 of register W5.
After timer 1 control by INT pin is enabled by setting the bit 0 of register I1 to “1”, INT pin input can be used as the start trigger for timer
1 count operation by setting the bit 1 of register W5 to “1”.
Also, in this time, the auto-stop function by timer 1 underflow can be
performed by setting the bit 2 of register W5 to “1.”
4509 Group
(4) Timer 2 (interrupt function)
(5) Count start synchronization circuit (timer 1)
Timer 2 is an 8-bit binary down counter with two timer 2 reload registers (R2L, R2H). Data can be set simultaneously in timer 2 and the
reload register R2L with the T2AB instruction. Data can be set in the
reload register R2H with the T2HAB instruction. The contents of reload register R2L set with the T2AB instruction can be set to timer 2
again with the T2R2L instruction. Data can be read from timer 2 with
the TAB2 instruction.
Stop counting and then execute the T2AB or TAB2 instruction to read
or set timer 2 data.
When executing the T2HAB instruction to set data to reload register
R2H while timer 2 is operating, avoid a timing when timer 2
underflows.
Timer 2 starts counting after the following process;
➀ set data in timer 2
➁ set count source by bits 0 and 1 of register W2, and
➂ set the bit 2 of register W2 to “1.”
Timer 1 has the count start synchronous circuit which synchronizes
the input of INT pin, and can start the timer count operation.
Timer 1 count start synchronous circuit function can be selected after timer 1 control by INT pin is enabled by setting the bit 0 of
register I1 to “1” and its function is selected by setting the bit 1 of
register W5 to “1”.
When timer 1 count start synchronous circuit is used, the count start
synchronous circuit is set, the count source is input to timer by inputting valid waveform to INT pin.
The valid waveform of INT pin to set the count start synchronous circuit is the same as the external interrupt activated condition.
Once set, the count start synchronous circuit is cleared by clearing
the bit I10 to “0” or system reset.
However, when the count auto-stop circuit is selected (W22 = “1”),
the count start synchronous circuit is cleared (auto-stop) at the timer
1 underflow.
When a value set in reload register R2L is n and a value set in reload register R2H is m, timer 2 divides the count source signal by n +
1 or m + 1 (n = 0 to 255, m = 0 to 255).
(6) Count auto-stop circuit (timer 1)
Once count is started, when timer 2 underflows (the next count pulse
is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload
register R2L, and count continues (auto-reload function).
<Bit 3 of register W2 = “0” (PWM2 function invalid)>
Once count is started, when timer 2 underflows (the next count pulse
is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload
register R2L, and count continues (auto-reload function).
<Bit 3 of register W2 = “1” (PWM2 function valid)>
Timer 2 generates the PWM2 signal of the “L” interval set as reload
register R2L, and the “H” interval set as reload register R2H. The
PWM2 signal generated by timer 2 is output from CNTR1 pin by setting “1” to bit 3 of register W6.
PWM2 output to CNTR1 pin combined with timer 1 can be controlled
by setting the bit 2 of register W6 to “1.”
Input period of INT pin by timer 2 can be counted by setting the bit 1
of register W6 to “1.”
Timer 1 has the count auto-stop circuit which is used to stop timer 1
automatically by the timer 1 underflow when the count start synchronous circuit is used.
The count auto-stop circuit is valid by setting the bit 2 of register W5
to “1”. It is cleared by the timer 1 underflow and the count source to
timer 1 is stopped.
This function is valid only when the timer 1 count start synchronous
circuit is selected.
(7) INT pin input period count circuit (timer 2)
Timer 2 has the INT pin input period count circuit to count the valid
waveform input interval of the INT pin.
When bit 1 of register W6 is set to “1”, the INT pin input period count
circuit of timer 2 becomes valid, and the count source is input. The
count source input is stopped by the next input of valid waveform to
the INT pin.
Then, every a valid waveform is input to the INT pin, start/stop of the
count source input is alternately repeated.
A valid waveform of the INT pin input is the same as the activated
condition of an external interrupt.
The INT pin input period count circuit set once is cleared by setting
the INT pin input to be disabled state. The INT pin input can be disabled by clearing bit 3 of register I1 to “0”.
(8) Timer input/output pin (P12/CNTR0 pin, P11/
CNTR1 pin)
CNTR0 pin is used to input the timer 2 count source and output the
PWM1 signal generated by timer 1.
CNTR1 pin is used to input the timer 1 count source and output the
PWM2 signal generated by timer 2.
The P12/CNTR0 pin function can be selected by bit 3 of register W5.
The P11/CNTR1 pin function can be selected by bit 3 of register W6.
When the CNTR0 input is selected for timer 2 count source, timer 2
counts the falling or rising waveform of CNTR0 input. The count
edge is selected by bit 0 of register W5.
When the CNTR1 input is selected for timer 1 count source, timer 1
counts the falling or rising waveform of CNTR1 input. The count
edge is selected by bit 0 of register W6.
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4509 Group
(9) PWM1 output function (P12/CNTR0, timer 1)
When bit 3 of register W1 is set to “1”, the data is reloaded alternately from reload register R1L and R1H every timer 1 underflow.
Timer 1 generates the PWM1 signal of the “L” interval set as reload
register R1L, and the “H” interval set as reload register R1H.
In this time, the PWM1 signal generated by timer 1 is output from
CNTR0 pin by setting “1” to bit 3 of register W5.
When the TW1A instruction is executed while the PWM1 signal is
“H”, the contents of register W1 is changed after the “H” interval of
the PWM1 signal is ended.
(10) PWM2 output function (P11/CNTR1, timer
1, timer 2)
When bit 3 of register W2 is set to “1”, the data is reloaded alternately from reload register R2L and R2H every timer 2 underflow.
Timer 2 generates the PWM2 signal of the “L” interval set as reload
register R2L, and the “H” interval set as reload register R2H.
In this time, the PWM2 signal generated by timer 2 is output from
CNTR1 pin by setting “1” to bit 3 of register W6.
When bit 2 of register W6 is set to “1”, the PWM2 signal output to
CNTR1 pin is switched to valid/invalid alternately each timer 1 underflow. However, when timer 1 is stopped (bit 2 of register W1 is
cleared to “0”), this function is canceled.
When the TW2A instruction is executed while the PWM2 signal is
“H”, the contents of register W2 is changed after the “H” interval of
the PWM2 signal is ended.
(11) Timer interrupt request flags (T1F, T2F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the skip
instructions (SNZT1, SNZT2).
Use the interrupt control register V1, V2 to select an interrupt or a
skip instruction.
An interrupt request flag is cleared to “0” when an interrupt occurs or
when the next instruction is skipped with a skip instruction.
(12) Precautions
- Prescaler
Stop prescaler counting and then execute the TABPS instruction to
read its data.
Stop prescaler counting and then execute the TPSAB instruction to
write data to prescaler.
- Timer count source
Stop timer 1 or 2 counting to change its count source.
- Reading the count value
Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 instruction to read its data.
- Writing to the timer
Stop timer 1 or 2 counting and then execute the T1AB, T1R1L,
T2AB or T2R2L instruction to write data to timer.
- Writing to reload register
In order to write a data to the reload register R1H while the timer 1
is operating, execute the T1HAB instruction except a timing of the
timer 1 underflow.
In order to write a data to the reload register R2H while the timer 2
is operating, execute the T2HAB instruction except a timing of the
timer 2 underflow.
- PWM signal (PWM1, PWM2)
If the timer 1 count stop timing and the timer 1 underflow timing
overlap during output of the PWM1 signal, a hazard may occur in
the PWM1 output waveform.
If the timer 2 count stop timing and the timer 2 underflow timing
overlap during output of the PWM2 signal, a hazard may occur in
the PWM2 output waveform.
- Prescaler, timer 1 and timer 2 count start timing and count time
when operation starts
Count starts from the first rising edge of the count source (2) after
prescaler and timer operations start (1).
Time to first underflow (3) is shorter (for up to 1 period of the count
source) than time among next underflow (4) by the timing to start
the timer and count source operations after count starts.
When selecting CNTR input as the count source of timer, timer
operates synchronizing with the count edge (falling edge or rising
edge) of CNTR input selected by software.
A
A
➁
Count source
Count source
(When falling edge of
CNTR input is selected)
Timer value
3 2
1
0
3
2
1
0
3
2
→
Timer underflow signal
➂
➃
➀ Timer start
Fig. 24 Timer count start timing and count time when operation starts
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4509 Group
● PWM1 function invalid (W13 = “0”)
Timer 1 count source
→
(R1L)
(Reload register)
→
0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016
→
0316
→
Timer 1 count value
(R1L)
(R1L)
(R1L)
(R1L)
Timer 1 underflow signal
→
PWM1 signal
PWM1 signal “L” fixed
Timer 1 start
● PWM1 function valid (W13 = “1”)
Timer 1 count source
(R1H)
(R1L)
(R1H)
→
(Reload register)
→
(R1L)
→
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116
→
0316
→
Timer 1 count value
(R1L)
(R1H)
Timer 1 underflow signal
4 clock
→
PWM1 signal
Timer 1 start
3 clock
4 clock
PWM period 7 clock
3 clock
4 clock
PWM period 7 clock
* : “0316” is set to reload register R1L and “0216” is set to reload register R1H.
Fig. 25 Timer 1 operation example
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4509 Group
● CNTR1 output auto-control circuit operation example 1 (W23 = “1”, W63 = “1”, W62 = “1”)
PWM2 signal
→
Timer 1 underflow signal
Timer 1 start
→
CNTR1 output
CNTR1 output start
* When the CNTR1 output auto-control circuit is selected, valid/invalid of CNTR1 output is repeated every timer 1 underflows.
● CNTR1 output auto-control circuit operation example 2 (W23 = “1”, W63 = “1”)
PWM2 signal
→
→
Timer 1 underflow signal
Timer 1 start
Register W62
➀
➁
Timer 1 stop
➂
CNTR1 output start
→
→
CNTR1 output
CNTR1 output stop
➀ When the CNTR1 output auto-control function is not selected while the CNTR output is invalid, CNTR1 output invalid state is retained.
➁ When the CNTR1 output auto-control function is not selected while the CNTR output is valid, CNTR1 output valid state is retained.
➂ When the timer 1 is stopped, the CNTR1 output auto-control function becomes invalid.
Fig. 26 CNTR1 output auto-control function by timer 1
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4509 Group
● Timer 2 count start timing (R2L = “0216”, R2H = ”0216”, W23 = “1”)
Mi
Machine cycle
Timer 2 count source
(System clock (STCK))
Mi + 1
Mi + 2
TW2A instruction execution (W22←“1”)
Mi + 3
Register W22
0116
0016
0216
(R2H)
0116
0016
→
0216
(R2L)
0216
(R2L)
→
Timer 2 count value
(Reload register)
Timer 2 undeflow signal
PWM2 signal
Timer 2 count start timing
● Timer 2 count stop timing (R2L = “0216”, R2H = ”0216”, W23 = “1”)
Machine cycle
Mi
Mi + 1
Mi + 2
Mi + 3
TW2A instruction execution (W22←“0”)
Timer 2 count source
(System clock (STCK))
Register W22
0016
0216
(R2L)
0116
0016
0216
→
0116
→
0216
(R2H)
→
Timer 2 count value
(Reload register)
(R2H)
Timer 2 undeflow signal
PWM2 signal
(Note 1)
Timer 2 count stop timing
Notes 1: If the timer count stop timing and the timer underflow timing overlap while the PWM function is valid (W13=“1” or W23=“1”),
a hazard may occur in the PWM signal waveform.
2: When timer count is stopped during “H” duration of the PWM signal, timer is stopped after the end of the “H” output duration.
Fig. 27 Timer count start/stop timing
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4509 Group
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer
WDT(16-bit binary counter), watchdog timer enable flag (WEF),
and watchdog timer flags (WDF1, WDF2).
The timer WDT downcounts the instruction clocks as the count
source from “FFFF16” after system is released from reset.
After the count is started, when the timer WDT underflow occurs
(after the count value of timer WDT reaches “FFFF16,” the next
count pulse is input), the WDF1 flag is set to “1.”
If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to
“1,” and the RESET pin outputs “L” level to reset the microcomputer.
Execute the WRST instruction at each period of 65534 machine
cycle or less by software when using watchdog timer to keep the
microcomputer operating normally.
When the WEF flag is set to “1” after system is released from reset,
the watchdog timer function is valid.
When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to “0” and the
watchdog timer function is invalid.
The WEF flag is set to "1" at system reset or RAM back-up mode.
The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is “1”, the WDF1 flag is
cleared to “0” and the next instruction is skipped.
When the WRST instruction is executed while the WDF1 flag is “0”,
the next instruction is not skipped.
The skip function of the WRST instruction can be used even when
the watchdog timer function is invalid.
FFFF16
Value of 16-bit timer (WDT)
000016
➁
WDF1 flag
➁
65534 count
(Note)
➃
WDF2 flag
RESET pin output
➀ Reset
released
➂ WRST instruction
executed
(skip executed)
➄ System reset
➀ After system is released from reset (= after program is started), timer WDT starts count down.
➁ When timer WDT underflow occurs, WDF1 flag is set to “1.”
➂ When the WRST instruction is executed while the WDF1 flag is “1”, WDF1 flag is cleared to “0,”
the next instruction is skipped.
➃ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the
watchdog reset signal is output.
➄ The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is
executed.
Note: The number of count is equal to the number of machine cycle because the count source of watchdog timer
is the instruction clock.
Fig. 28 Watchdog timer function
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; WDF1 flag cleared
•••
WRST
; Watchdog timer function enabled/disabled
; WEF and WDF1 flags cleared
•••
DI
DWDT
WRST
Fig. 29 Program example to start/stop watchdog timer
•••
When the watchdog timer is used, clear the WDF1 flag at the period
of 65534 machine cycles or less with the WRST instruction.
When the watchdog timer is not used, execute the DWDT instruction
and the WRST instruction continuously (refer to Figure 29).
The watchdog timer is not stopped with only the DWDT instruction.
The contents of WDF1 flag and timer WDT are initialized at the RAM
back-up mode.
When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the
microcomputer enters the RAM back-up state (refer to Figure 30)
Also, set the NOP instruction after the WRST instruction, for the
case when a skip is performed with the WRST instruction.
•••
4509 Group
•••
WRST
; WDF1 flag cleared
NOP
DI
; Interrupt disabled
EPOF
; POF instruction enabled
POF
; RAM back-up mode
↓
Oscillation stop
Fig. 30 Program example to enter the RAM back-up mode
when using the watchdog timer
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4509 Group
A/D CONVERTER
Table 11 A/D converter characteristics
Parameter
Characteristics
Conversion format Successive comparison method
Resolution
10 bits
Relative accuracy
Linearity error: ±2LSB (VDD=2.7 to 5.5 V)
The 4509 Group has a built-in A/D conversion circuit that performs
conversion by 10-bit successive comparison method. Table 11
shows the characteristics of this A/D converter. This A/D converter
can also be used as an 8-bit comparator to compare analog voltages
input from the analog input pin with preset values.
Differential non-linearity error: ±0.9LSB
(VDD=2.7 to 5.5 V)
31 µs (f(XIN)=6 MHz, f(STCK)=f(XIN))
Conversion speed
Analog input pin
6
Register B (4)
Register A (4)
4
4
4
TAQ1
TQ1A
Q13 Q12 Q11 Q10
4
2
8
8
TALA
TABAD
TADAB
Instruction clock
1/6
2
Q13
P20/AIN0
P21/AIN1
P30/AIN2
P31/AIN3
D2/AIN4
D3/AIN5
6-channel multi-plexed analog switch
0
A/D control circuit
1
ADF
(1)
A/D
interrupt
1
Comparator
0
Q13
Successive comparison
register (AD) (10)
10
DAC
operation
signal
0
Q13
8
10
0
1
Q13
8
8
DA converter
(Note 1)
VDD
VSS
Comparator register (8)
(Note 2)
Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage.
2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1).
The value of the comparator register is retained even when the mode is switched to the A/D conversion
mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution
in the comparator mode is 8 bits because the comparator register consists of 8 bits.
Fig. 31 A/D conversion circuit structure
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1
1
8
4509 Group
Table 12 A/D control registers
at reset : 00002
A/D control register Q1
Q13
A/D operation mode selection bit
Q12
Q11
Analog input pin selection bits
Q10
at RAM back-up : state retained
A/D conversion mode
Comparator mode
Q12 Q11 Q10
0
0
0
AIN0
0
0
1
AIN1
0
1
0
AIN2
0
1
1
AIN3
1
0
0
AIN4
1
0
1
AIN5
1
1
0
Not available
1
1
1
Not available
R/W
TAQ1/TQ1A
0
1
Selected pins
Note: “R” represents read enabled, and “W” represents write enabled.
(1) A/D control register Q1
(6) Operation description
Register Q1 is used to select the operation mode and one of analog
input pins. Set the contents of this register through register A with the
TQ1A instruction. The TAQ1 instruction can be used to transfer the
contents of register Q1 to register A.
A/D conversion is started with the A/D conversion start instruction
(ADST). The internal operation during A/D conversion is as follows:
(2) Operating at A/D conversion mode
The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.”
(3) Successive comparison register AD
Register AD stores the A/D conversion result of an analog input in
10-bit digital data format. The contents of the high-order 8 bits of this
register can be stored in register B and register A with the TABAD instruction. The contents of the low-order 2 bits of this register can be
stored into the high-order 2 bits of register A with the TALA instruction. However, do not execute these instructions during A/D
conversion.
When the contents of register AD is n, the logic value of the comparison voltage V ref generated from the built-in DA converter can be
obtained with the reference voltage VDD by the following formula:
Logic value of comparison voltage Vref
Vref =
V DD
1024
✕n
n: The value of register AD (n = 0 to 1023)
(4) A/D conversion completion flag (ADF)
A/D conversion completion flag (ADF) is set to “1” when A/D conversion completes. The state of ADF flag can be examined with the skip
instruction (SNZAD). Use the interrupt control register V2 to select
the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when the
next instruction is skipped with the skip instruction.
(5) A/D conversion start instruction (ADST)
A/D conversion starts when the ADST instruction is executed. The
conversion result is automatically stored in the register AD.
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➀ When the A/D conversion starts, the register AD is cleared to
“00016.”
➁ Next, the topmost bit of the register AD is set to “1,” and the comparison voltage Vref is compared with the analog input voltage VIN.
➂ When the comparison result is Vref < VIN, the topmost bit of the
register AD remains set to “1.” When the comparison result is Vref
> VIN, it is cleared to “0.”
The 4509 Group repeats this operation to the lowermost bit of the
register AD to convert an analog value to a digital value. A/D conversion stops after 62 machine cycles (31 µs when f(XIN) = 6.0 MHz in
high-speed mode) from the start, and the conversion result is stored
in the register AD. An A/D interrupt activated condition is satisfied
and the ADF flag is set to “1” as soon as A/D conversion completes
(Figure 32).
4509 Group
Table 13 Change of successive comparison register AD during A/D conversion
At starting conversion
Comparison voltage (Vref) value
Change of successive comparison register AD
VDD
-------------
1
1st comparison
✼1
2nd comparison
✼1
3rd comparison
0
1
✼2
0
0
-----
0
0
0
-------------
2
-------------
VDD
-----
-------------
0
0
0
-------------
1
-----
-------------
0
0
0
✼2
✼3
-----
-------------
VDD
±
2
VDD
-------------
✼1
✼8
✼9
4
VDD
A/D conversion result
After 10th comparison
completes
VDD
±
2
✼A
±
VDD
±
4
○
○
2
○
○
±
8
VDD
1024
✼2: 2nd comparison result
✼8: 8th comparison result
✼A: 10th comparison result
✼1: 1st comparison result
✼3: 3rd comparison result
✼9: 9th comparison result
(7) A/D conversion timing chart
Figure 32 shows the A/D conversion timing chart.
ADST instruction
62 machine cycles
A/D conversion
completion flag (ADF)
DAC operation signal
Fig. 32 A/D conversion timing chart
(8) How to use A/D conversion
How to use A/D conversion is explained using as example in which
the analog input from P20/AIN0 pin is A/D converted, and the high-order 4 bits of the converted data are stored in address M(Z, X, Y) =
(0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and
the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A/
D interrupt is not used in this example.
➀ Select the A IN0 pin function and A/D conversion mode with the
register Q1 (refer to Figure 33).
➁ Execute the ADST instruction and start A/D conversion.
➂ Examine the state of ADF flag with the SNZAD instruction to determine the end of A/D conversion.
➃ Transfer the low-order 2 bits of converted data to the high-order 2
bits of register A (TALA instruction).
➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2).
➅ Transfer the high-order 8 bits of converted data to registers A and
B (TABAD instruction).
➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1).
➇ Transfer the contents of register B to register A, and then, store
into M(Z, X, Y) = (0, 0, 0).
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(Bit 3)
0
(Bit 0)
0
0
0
A/D control register Q1
A IN0 pin selected
A/D conversion mode
Fig. 33 Setting registers
4509 Group
(9) Operation at comparator mode
The A/D converter is set to comparator mode by setting bit 3 of the
register Q1 to “1.”
Below, the operation at comparator mode is described.
(10) Comparator register
In comparator mode, the built-in DA comparator is connected to the
8-bit comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of
the comparator register and the contents of register A is stored in the
low-order 4 bits of the comparator register with the TADAB instruction.
When changing from A/D conversion mode to comparator mode, the
result of A/D conversion (register AD) is undefined.
However, because the comparator register is separated from register
AD, the value is retained even when changing from comparator
mode to A/D conversion mode. Note that the comparator register
can be written and read at only comparator mode.
If the value in the comparator register is n, the logic value of comparison voltage Vref generated by the built-in DA converter can be
determined from the following formula:
Logic value of comparison voltage Vref
Vref =
VDD
256
✕n
(12) Comparator operation start instruction
(ADST instruction)
In comparator mode, executing ADST starts the comparator operating.
The comparator stops 8 machine cycles after it has started (6 µs at
f(XIN) = 4.0 MHz in high-speed through mode). When the analog input voltage is lower than the comparison voltage, the ADF flag is set
to “1.”
(13) Notes for the use of A/D conversion 1
• TALA instruction
When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A,
simultaneously, the low-order 2 bits of register A is “0.”
• Operating mode of A/D converter
Do not change the operating mode (both A/D conversion mode
and comparator mode) of A/D converter with the bit 3 of register
Q1 while the A/D converter is operating.
Clear the bit 2 of register V2 to “0” to change the operating mode
from the comparator mode to A/D conversion mode.
The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to
the bit 3 of register Q1, and execute the SNZAD instruction to clear
the ADF flag.
n: The value of register AD (n = 0 to 255)
(11) Comparison result store flag (ADF)
In comparator mode, the ADF flag, which shows completion of A/D
conversion, stores the results of comparing the analog input voltage
with the comparison voltage. When the analog input voltage is lower
than the comparison voltage, the ADF flag is set to “1.” The state of
ADF flag can be examined with the skip instruction (SNZAD). Use
the interrupt control register V2 to select the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when the
next instruction is skipped with the skip instruction.
ADST instruction
8 machine cycles
Comparison result
store flag(ADF)
DAC operation signal
→
Comparator operation completed.
(The value of ADF is determined)
Fig. 34 Comparator operation timing chart
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4509 Group
(14) Definition of A/D converter accuracy
The A/D conversion accuracy is defined below (refer to Figure 35).
• Relative accuracy
➀ Zero transition voltage (V0T)
This means an analog input voltage when the actual A/D conversion output data changes from “0” to “1.”
➁ Full-scale transition voltage (VFST)
This means an analog input voltage when the actual A/D conversion output data changes from “1023” to ”1022.”
➂ Linearity error
This means a deviation from the line between V0T and VFST of
a converted value between V0T and VFST.
➃ Differential non-linearity error
This means a deviation from the input potential difference required to change a converter value between V0T and VFST by 1
LSB at the relative accuracy.
Vn: Analog input voltage when the output data changes from “n” to
“n+1” (n = 0 to 1022)
• 1LSB at relative accuracy →
VFST–V0T
(V)
1022
• 1LSB at absolute accuracy →
VDD
1024
(V)
• Absolute accuracy
This means a deviation from the ideal characteristics between 0
to VDD of actual A/D conversion characteristics.
Output data
Full-scale transition voltage (VFST)
1023
1022
Differential non-linearity error = b–a [LSB]
a
Linearity error = c [LSB]
a
b
a
n+1
n
Actual A/D conversion
characteristics
c
a: 1LSB by relative accuracy
b: Vn+1–Vn
c: Difference between ideal Vn
a n d a ct u a l V n
Ideal line of A/D conversion
between V0–V1022
1
0
V0
V1
Zero transition voltage (V0T)
Fig. 35 Definition of A/D conversion accuracy
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Vn
Vn+1
V1022
VDD
Analog voltage
4509 Group
SERIAL INTERFACE
Table 14 Serial interface pins
The 4509 Group has a built-in clock synchronous serial interface
which can serially transmit or receive 8-bit data.
Serial interface consists of;
• Serial interface register SI
• Serial interface control register J1
• Serial interface transmit/receive completion flag (SIOF)
• Serial interface counter
Registers A and B are used to perform data transfer with internal
CPU.
The pin functions of the serial interface pins can be set with the register J1.
1/8
1/4
1/2
INSTCK
Pin
P02/SCK
P01/SOUT
P03/SIN
Pin function when selecting serial interface
Clock I/O (SCK)
Serial data output (SOUT)
Serial data input (SIN)
Note: Even when the SIN pin function is used, the I/O of port P00 is valid.
Even when the SOUT pin function is used, the input of port P01 is valid.
The input of P02 can be used even when SCK is used. Be careful when
using inputs of both SCK and P02 since the input threshold value of SCK
pin is different from that of port P02.
J13J12
00
01
10
Synchronous
circuit
Serial interface counter (3)
SIOF
11
P02/SCK
P01/SOUT
P00/SIN
SCK
Q
Serial
interface
interrupt
S
SST
instruction
R
Internal reset signal
SOUT
SIN
MSB Serial interface register (8) LSB
TABSI
TSIAB
Register B (4)
TABSI
Register A (4)
J11 J10
Fig. 36 Serial interface structure
Table 15 Serial interface control register
Serial interface control register J1
J13
J12
Serial interface synchronous clock
selection bits
J11
J10
Serial interface port function selection bits
at reset : 00002
Synchronous clock
J13 J12
0 Instruction clock (INSTCK) divided by 8
0
1 Instruction clock (INSTCK) divided by 4
0
0 Instruction clock (INSTCK) divided by 2
1
1 External clock (SCK input)
1
Port function
J11 J10
0 P00, P01,P02 selected/SIN, SOUT, SCK not selected
0
1 P00, SOUT, SCK selected/SIN, P01, P02 not selected
0
0 SIN, P01, SCK selected/P00, SOUT, P02 not selected
1
1 SIN, SOUT, SCK selected/P00, P01,P02 not selected
1
Note: “R” represents read enabled, and “W” represents write enabled.
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at RAM back-up : state retained
R/W
TAJ1/TJ1A
4509 Group
At transmit (D7–D0: transfer data)
At receive
SIN pin
Serial interface register (SI)
SOUT pin
SOUT pin
SIN pin
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
*D
7 D6 D5 D4 D3 D2 D1
* *D
* ** * * ** *
Transfer data set
Transfer start
7 D6 D5 D4 D3 D2
* ** * * ** *
Serial interface register (SI)
* ** * * ** *
D0
** * * ** *
D1 D0
Transfer complete
* * * ** *
D7 D6 D5 D4 D3 D2 D1 D0
Fig. 37 Serial interface register state when transferring
(1) Serial interface register SI
(3) Serial interface start instruction (SST)
Serial interface register SI is the 8-bit data transfer serial/parallel
conversion register. Data can be set to register SI through registers
A and B with the TSIAB instruction. The contents of register A is
transmitted to the low-order 4 bits of register SI, and the contents
of register B is transmitted to the high-order 4 bits of register SI.
During transmission, each bit data is transmitted LSB first from the
lowermost bit (bit 0) of register SI, and during reception, each bit
data is received LSB first to register SI starting from the topmost bit
(bit 7).
When register SI is used as a work register without using serial interface, do not select the SCK pin.
When the SST instruction is executed, the SIOF flag is cleared to
“0” and then serial interface transmission/reception is started.
(2) Serial interface transmit/receive
completion flag (SIOF)
Serial interface transmit/receive completion flag (SIOF) is set to “1”
when serial data transmission or reception completes. The state of
SIOF flag can be examined with the skip instruction (SNZSI). Use
the interrupt control register V2 to select the interrupt or the skip
instruction.
The SIOF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
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(4) Serial interface control register J1
Register J1 controls the synchronous clock, P0 2/S CK, P01/S OUT
and P00/SIN pin function. Set the contents of this register through
register A with the TJ1A instruction. The TAJ1 instruction can be
used to transfer the contents of register J1 to register A.
4509 Group
(5) How to use serial interface
Figure 38 shows the serial interface connection example. Serial interface interrupt is not used in this example. In the actual wiring, pull
Master (clock control)
Slave (external clock)
D3
(Bit 3)
0
0
(Bit 0)
1
1
up the wiring between each pin with a resistor. Figure 38 shows the
data transfer timing and Table 16 shows the data transfer sequence.
SRDY signal
D3
SCK
SCK
SOUT
SIN
SIN
SOUT
(Bit 0)
(Bit 3)
Serial interface
control register J1
Serial interface port
SCK,SOUT,SIN
1
1
1
1
Instruction clock/8 selected
as synchronous clock
(Bit 3)
0
✕
✕
✕
External clock selected
as synchronous clock
(Bit 3)
(Bit 0)
Interrupt control
register V2
Serial interface
interrupt enable bit
(SNZSI instruction
valid)
Serial interface
control register J1
Serial interface port
SCK,SOUT,SIN
0
(Bit 0)
✕
✕
✕
Interrupt control
register V2
Serial interface
interrupt enable bit
(SNZSI instruction
valid)
✕: Set an arbitrary value.
Fig. 38 Serial interface connection example
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4509 Group
Master
SOUT
M7’
SIN
M1
M0
S7’
S0
M3
M2
S1
S2
M4
S3
M5
S4
M6
S5
M7
S6
S7
SST instruction
SCK
Slave
SST instruction
SRDY signal
SOUT
SIN
S1
S0
S7’
M7’
M0
S2
M1
S3
M2
S4
M3
S5
M4
S6
M5
S7
M6
M7
M0–M7: Contents of master serial interface register
S0–S7: Contents of slave serial interface register
Rising of SCK: Serial input
Falling of SCK: Serial output
Fig. 39 Timing of serial interface data transfer
Table 16 Processing sequence of data transfer from master to slave
Slave (reception)
Master (transmission)
[Initial setting]
[Initial setting]
• Setting the serial interface control register J1 and inter- • Setting serial interface control register J1, and interrupt control register V2
shown in Figure 38.
rupt control register V2 shown in Figure 38.
TJ1A and TV2A instructions
TJ1A and TV2A instructions
• Setting the port received the reception enable signal • Setting the port transmitted the reception enable signal (SRDY) and outputting “H” level.
(SRDY) to the input mode.
(Port D3 is used in this example)
SD instruction
* [Transmission enable state]
• Storing transmission data to serial interface register SI.
TSIAB instruction
(Port D3 is used in this example)
SD instruction
*[Reception enable state]
• The SIOF flag is cleared to “0.”
SST instruction
• “L” level (reception possible) is output from port D3.
RD instruction
[Reception]
[Transmission]
•Check port D3 is “L” level.
SZD instruction
•Serial transfer starts.
SST instruction
•Check transmission completes.
• Check reception completes.
SNZSI instruction
•Wait (timing when continuously transferring)
SNZSI instruction
• “H” level is output from port D3.
SD instruction
[Data processing]
1-byte data is serially transferred on this process. Subsequently, data
can be transferred continuously by repeating the process from *.
When an external clock is selected as a synchronous clock, control
the clock externally because serial transfer is performed as long as
clock is externally input. (Unlike an internal clock, an external clock
is not stopped when serial transfer is completed.) However, the
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SIOF flag is set to “1” when the clock is counted 8 times after executing the SST instruction. Be sure to set the initial level of the
external clock to “H.”
4509 Group
RESET FUNCTION
(1) RESET pin input
System reset is performed by the followings:
• “L” level is applied to the RESET pin externally,
• System reset instruction (SRST) is executed,
• Reset occurs by watchdog timer,
• Reset occurs by built-in power-on reset (only for H version)
• Reset occurs by voltage drop detection circuit (only for H version)
Then when “H” level is applied to RESET pin, software starts from
address 0 in page 0.
System reset is performed certainly by applying “L” level to RESET
pin for 1 machine cycle or more when the following condition is satisfied;
the value of supply voltage is the minimum value or more of the recommended operating conditions.
Pull-up transistor
Internal reset signal
SRST instruction
Power-on reset circuit(Note 3)
RESET
pin
Voltage drop detection circuit (Note 3)
Watchdog reset signal
(Note 2)
(Note 1)
WEF
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
3: These are equipped with only H version.
Fig. 40 Structure of reset pin and its peripherals
=
Reset input
1 machine cycle or more
0.85VDD
RESET
Program starts
(address 0 in page 0)
0.3VDD
(Note 1)
f(RING)
On-chip oscillator (internal oscillator) is
counted 120 to 144 times (Note 2).
Notes 1: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
2: It depends on the internal state at reset.
Fig. 41 RESET pin input waveform and reset release timing
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4509 Group
(2) Power-on reset (only for H version)
100 µs or less
→ ←
Reset can be automatically performed at power on (power-on reset)
by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 V
to the minimum voltage of recommended operating conditions to
100 µs or less.
If the rising time exceeds 100 µs, connect a capacitor between the
RESET pin and Vss at the shortest distance, and input “L” level to
RESET pin until the value of supply voltage reaches the minimum
operating voltage.
VDD
Power-on reset
circuit output
Reset
state
Internal reset signal
(3) System reset instruction (SRST)
By executing the SRST instruction, “L” level is output to RESET pin
and system reset is performed.
Power-on
Reset released
Reset state
Note: Keep the value of supply voltage to
the minimum value or more of the
recommended operating conditions.
Fig. 42 Power-on reset operation
Table 17 Port state at reset
Name
State
D0, D1
Function
D 0 , D1
High-impedance (Notes 1, 2)
D2/AIN4, D3/AIN5
D 2 , D3
High-impedance (Notes 1, 2, 3)
D4, D5
D 4 , D5
High-impedance (Notes 1, 2)
P00/SIN, P01/SOUT, P02/SCK P00, P01, P02
P03
P03
P10
P10
P11/CNTR1
P11
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
P12/CNTR0
P12
High-impedance (Notes 1, 2, 3)
P13/INT
P13
High-impedance (Notes 1, 2, 3)
P20/AIN0, P21/AIN1
P30/AIN2, P31/AIN3
P20, P21
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2)
P30, P31
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
Notes 1: Output latch is set to “1.”
2: The output structure is N-channel open-drain.
3: Pull-up transistor is turned OFF.
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4509 Group
(4) Internal state at reset
Figure 43 shows internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags
and RAM except shown in Figure 43 are undefined, so set the initial
value to them.
• Program counter (PC) ..........................................................................................................
0 0 0 0 0 0
Address 0 in page 0 is set to program counter.
0
0
0
0
0
• Interrupt enable flag (INTE) .................................................................................................. 0
• Power down flag (P) ............................................................................................................. 0
(Interrupt disabled)
0
0
0
• External 0 interrupt request flag (EXF0) .............................................................................. 0
• Interrupt control register V1 ..................................................................................................
0 0 0 0
(Interrupt disabled)
• Interrupt control register V2 ..................................................................................................
0 0 0 0
• Interrupt control register I1 ...................................................................................................
0 0 0 0
• Timer 1 interrupt request flag (T1F) ..................................................................................... 0
(Interrupt disabled)
• Timer 2 interrupt request flag (T2F) ..................................................................................... 0
• Watchdog timer flags (WDF1, WDF2) .................................................................................. 0
• Watchdog timer enable flag (WEF) ...................................................................................... 1
• Timer control register PA ...................................................................................................... 0
• Timer control register W1 .....................................................................................................
0 0 0 0
• Timer control register W2 .....................................................................................................
0 0 0 0
(Prescaler stopped)
(Timer 1 stopped)
(Timer 2 stopped)
• Timer control register W5 .....................................................................................................
0 0 0 0
• Timer control register W6 .....................................................................................................
0 0 0 0
• Clock control register MR .....................................................................................................
1 1 0 1
• Clock control register RG ..................................................................................................... 0
• Serial interface transmit/receive completion flag (SIOF) ..................................................... 0
• Serial interface control register J1 .......................................................................................
0 0 0 0
(On-chip oscillator operating)
(Serial interface port not selected)
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Serial interface register SI ....................................................................................................
• A/D conversion completion flag (ADF) ................................................................................. 0
• A/D control register Q1 .........................................................................................................
0 0 0 0
• Successive comparison register AD ....................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Comparator register ..............................................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Key-on wakeup control register K0 ......................................................................................
0 0 0 0
• Key-on wakeup control register K1 ......................................................................................
0 0 0 0
• Key-on wakeup control register K2 ......................................................................................
0 0 0 0
• Key-on wakeup control register L1 ......................................................................................
0 0 0 0
• Pull-up control register PU0 .................................................................................................
0 0 0 0
• Pull-up control register PU1 .................................................................................................
0 0 0 0
• Pull-up control register PU2 .................................................................................................
0 0 0 0
• Port output structure control register FR0 ...........................................................................
0 0 0 0
• Port output structure control register FR1 ...........................................................................
0 0 0 0
• Port output structure control register FR2 ...........................................................................
0 0 0 0
• Port output structure control register FR3 ...........................................................................
0 0 0 0
• Port output structure control register C1 ..............................................................................
0 0 0 0
• Carry flag (CY) ...................................................................................................................... 0
• Register A .............................................................................................................................
0 0 0 0
• Register B .............................................................................................................................
0 0 0 0
• Register D .............................................................................................................................
✕ ✕ ✕
• Register E .............................................................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Register X .............................................................................................................................
0 0 0 0
• Register Y .............................................................................................................................
0 0 0 0
• Register Z .............................................................................................................................
✕ ✕
• Stack pointer (SP) ................................................................................................................
1 1 1
• Operation source clock .......................................................... On-chip oscillator (operating)
• Ceramic resonator circuit ..................................................................................... Operating
• RC oscillation circuit ...................................................................................................... Stop
Fig. 43 Internal state at reset
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“✕” represents undefined.
4509 Group
VOLTAGE DROP DETECTION CIRCUIT
(only for H version)
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer by outputting “L”
level to RESET pin if the supply voltage drops below a set value.
S
EPOF instruction +POF instruction
Q
R
Internal reset signal
Key-on wakeup signa
Q
S
SVDE instruction
R
Internal reset signal
Voltage drop detection circuit
Reset signal
–
+
VRST
(1) SVDE instruction
If the SVDE instruction is not executed (initial state), the voltage
drop detection circuit becomes invalid at RAM back-up mode.
When the SVDE instruction is executed, the voltage drop deteciton
circuit is valid even after system enters into the RAM back-up mode.
The SVDE instruction can be executed only once.
In order to release the execution of the SVDE instruction, the system
reset is required.
Voltage drop detection circuit
Fig. 44 Voltage drop detection reset circuit
VDD
+
VRST (reset release voltage)
VRST -(reset occurrence voltage)
Voltage drop detection circuit
Reset signal
Microcomputer starts operation after
on-chip oscillator (internal oscillator)
clock is counted 120 to 144 times.
RESET pin
Note: Detection voltage hysteresis of voltage drop detection circuit is 0.2 V (Typ).
Fig. 45 Voltage drop detection circuit operation waveform
Table 18 Voltage drop detection circuit operation state
SVDE instruction not executed
SVDE instruction executed
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At CPU operating At RAM back-up mode
Valid
Invalid
Valid
Valid
page 50 of 140
4509 Group
RAM BACK-UP MODE
The 4509 Group has the RAM back-up mode.
When the POF instruction is executed continuously after the EPOF
instruction, system enters the RAM back-up state.
The POF instruction is equal to the NOP instruction when the EPOF
instruction is not executed before the POF instruction.
As oscillation stops retaining RAM, the function of reset circuit and
states at RAM back-up mode, current dissipation can be reduced
without losing the contents of RAM.
Table 19 shows the function and states retained at RAM back-up.
Figure 46 shows the state transition.
Table 19 Functions and states retained at RAM back-up
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
RAM back-up
✕
Contents of RAM
O
Interrupt control registers V1, V2
✕
Interrupt control register I1
O
O
Selected oscillation circuit (execution of CRCK)
Clock control register MR
✕
Clock control register RG
✕
Timer 1, Timer 2 function
(Note 3)
(1) Identification of the start condition
Watchdog timer function
✕ (Note 4)
Warm start (return from the RAM back-up state) or cold start (return
from the normal reset state) can be identified by examining the state
of the power down flag (P) with the SNZP instruction.
Timer control register PA
✕
✕
Timer control registers W1, W2
Timer control registers W5, W6
O
Serial interface function
✕
(2) Warm start condition
Serial interface control register J1
O
When the external wakeup signal is input after the system enters the
RAM back-up state by executing the EPOF instruction and POF instruction continuously, the CPU starts executing the program from
address 0 in page 0. In this case, the P flag is “1.”
A/D conversion function
✕
A/D control register Q1
O
(Note 5)
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
• “L” level is applied to RESET pin,
• system reset (SRST) is performed,
• reset by watchdog timer is performed,
• reset by the built-in power-on reset circuit is performed (only for H
version), or
• reset by the voltage drop detection circuit is performed (only for H
version).
In this case, the P flag is “0.”
Voltage drop detection circuit
Port level
O
Key-on wakeup control registers K0 to K2, L1
O
Pull-up control registers PU0 to PU2
O
Port output structure control registers FR0 to FR3, C1
O
External interrupt request flag (EXF0)
Timer interrupt request flags (T1F, T2F)
A/D conversion completion flag (ADF)
Serial interface transmit/receive completion flag
(SIOF)
Interrupt enable flag (INTE)
✕
(Note 3)
✕
✕
✕
Watchdog timer flags (WDF1, WDF2)
✕ (Note 4)
Watchdog timer enable flag (WEF)
✕ (Note 4)
Notes 1:“O” represents that the function can be retained, and “✕” represents
that the function is initialized.
Registers and flags other than the above are undefined at RAM
back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer flag WDF1 with the WRST instruction,
and then set the system to be in the RAM back-up mode.
5: The voltage drop detection circuit is equipped with only H version.
In the RAM back-up mode, when the SVDE instruction is not executed, the voltage drop detection circuit is invalid, and when the
SVDE instruction is executed, the voltage drop detection circuit is
valid.
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4509 Group
(4) Return signal
An external wakeup signal is used to return from the RAM back-up
mode because the oscillation is stopped. Table 20 shows the return
condition for each return source.
(5) Control registers
• Key-on wakeup control register K0
Register K0 controls the port P0 key-on wakeup function. Set the
contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the
contents of register K0 to register A.
• Key-on wakeup control register K1
Register K1 controls the port P1 key-on wakeup function. Set the
contents of this register through register A with the TK1A instruction. In addition, the TAK1 instruction can be used to transfer the
contents of register K1 to register A.
• Key-on wakeup control register K2
Register K2 controls the ports P2, D2 and D3 key-on wakeup function. Set the contents of this register through register A with the
TK2A instruction. In addition, the TAK2 instruction can be used to
transfer the contents of register K2 to register A.
• Key-on wakeup control register L1
Register L1 controls the selection of the return condition and valid
waveform/level of port P1, and the selection of the INT pin return
condition and INT pin key-on wakeup function. Set the contents of
this register through register A with the TL1A instruction. In addition, the TAL1 instruction can be used to transfer the contents of
register L1 to register A.
External wakeup signal
Table 20 Return source and return condition
Return source
Return condition
Port P00–P03
Port P20, P21
Port D2, D3
Return by an external “L” level input.
P o r t P 1 0 – P 1 3 Return by an external “H” level or
“L” level input, or falling edge
(“H”→“L”) or rising edge (“L”→“H”).
INT pin
Return by an external “H” level or
“L” level input, or falling edge
(“H”→“L”) or rising edge (“L”→“H”).
When the return level is input, the
EXF0 flag is not set.
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• Pull-up control register PU0
Register PU0 controls the ON/OFF of the port P0 pull-up transistor. Set the contents of this register through register A with the
TPU0A instruction. In addition, the TAK1 instruction can be used to
transfer the contents of register K0 to register A.
• Pull-up control register PU1
Register PU1 controls the ON/OFF of the port P1 pull-up transistor. Set the contents of this register through register A with the
TPU1A instruction. In addition, the TAPU1 instruction can be used
to transfer the contents of register PU1 to register A.
• Pull-up control register PU2
Register PU2 controls the ON/OFF of the ports P2, D2 and D3 pullup transistor. Set the contents of this register through register A
with the TPU2A instruction. In addition, the TAPU2 instruction can
be used to transfer the contents of register PU2 to register A.
• Interrupt control register I1
Register I1 controls the valid waveform/level of the external 0 interrupt and the input control of INT pin. Set the contents of this
register through register A with the TI1A instruction. In addition, the
TAI1 instruction can be used to transfer the contents of register I1
to register A.
Remarks
The key-on wakeup function can be selected by one port unit. Set the port
using the key-on wakeup function to “H” level before going into the RAM
back-up state.
The key-on wakeup function can be selected by one port unit. Select the
return level (“L” level or “H” level) and return condition (level or edge) with
the register L1 according to the external state before going into the RAM
back-up state.
Before going into the RAM backup state, set an opposite level of the
selected return level (edge) to the port using the key-on wakeup function.
The key-on wakeup function can be selected by one port unit. Select the
return level (“L” level or “H” level) with the register I1 and return condition
(level or edge) with the register L1 according to the external state before
going into the RAM back-up state.
4509 Group
Internal mode
D
A
Operating state
Operating state
Reset
(Note 1)
POF instruction execution
(Note 5)
RAM back-up
Operation source clock:
f(RING)
Key-on wakeup
(Note 6)
On-chip oscillator
(MR0)←1
(Note 3)
(MR0)←0
(Note 2)
CRCK instruction no execution
B
Operating state
POF instruction execution
(Note 5)
Operation source clock: f(XIN)
Ceramic resonator: operating
(Note 4)
CRCK instruction execution
C
Operating state
POF instruction execution
(Note 5)
Operation source clock: f(XIN)
RC oscillation
f(RING): stop
f(XIN): stop
High-speed mode
Notes 1: Microcomputer starts its operation after counting f(RING) 120 to 144 times from system is released from reset.
2: When changing the operation source clock from f(RING) to f(XIN), first make the setting to enable f(XIN) oscillation (set MR1 to “0”),
allow the oscillation stabilization time to elapse using software, and then set the operation source clock to f(XIN) (set MR0 to “0”).
After this, stop f(RING) (set RG0 to “1”). (Do not start f(XIN) oscillation and change the operation source clock at the same time.)
3: When changing the operation source clock from f(XIN) to f(RING), first make the setting to enable f(RING) oscillation (set RG0 to “0”),
allow the oscillation stabilization time to elapse using software, and then set the operation source clock to f(RING) (set MR0 to “1”).
After this, stop f(XIN) (set MR1 to “1”). (Do not change the operation source clock and stop f(XIN) at the same time.)
4: After system is released from reset, the ceramic oscillation circuit is selected for the main clock f(XIN).
When the RC oscillation circuit is used, execute the CRCK instruction.
5: Continuous execution of the EPOF instruction and the POF instruction is required to go into the RAM back-up state.
6: Microcomputer starts its operation after counting f(RING) 120 to 144 times.
System returns to state A certainly when returning from the RAM back-up mode. The operation mode (system clock frequency divided)
also returns to the initial state (internal frequency divided by 8 mode) (registers RG and MR initialized).
However, the selected contents (CRCK instruction execution state) of f(XIN) oscillation circuit is retained.
Fig. 46 State transition
Power down flag P
EPOF
POF
+
instruction instruction
S
R
Reset input
● Set source
•••••••
Program start
Q
SNTP
P = “1”
?
No
EPOF instruction + POF instruction
Cold start
● Clear
source • • • • • • Reset
Warm start
input
Fig. 47 Set source and clear source of the P flag
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Yes
page 53 of 140
Fig. 48 Start condition identified example using the SNZP instruction
4509 Group
Table 21 Key-on wakeup control register
at reset : 00002
Key-on wakeup control register K0
K03
K02
K01
K00
Port P03 key-on wakeup
control bit
0
Key-on wakeup not used
1
Key-on wakeup used
Port P02 key-on wakeup
Key-on wakeup not used
control bit
0
1
Port P01 key-on wakeup
0
control bit
1
Key-on wakeup not used
Key-on wakeup used
Port P00 key-on wakeup
0
Key-on wakeup not used
control bit
1
Key-on wakeup used
Key-on wakeup control register K1
K13
K12
K11
K10
Port P13 key-on wakeup
K22
K21
K20
0
1
Port P12 key-on wakeup
0
Key-on wakeup used
Key-on wakeup not used
control bit
Port P11 key-on wakeup
1
Key-on wakeup used
0
Key-on wakeup not used
control bit
1
Key-on wakeup used
Port P10 key-on wakeup
0
1
Key-on wakeup not used
L12
L11
L10
Key-on wakeup used
at RAM back-up : state retained
Port D3 key-on wakeup
control bit
0
Key-on wakeup not used
1
Key-on wakeup used
Port D2 key-on wakeup
Key-on wakeup not used
control bit
0
1
Port P21 key-on wakeup
0
control bit
1
Key-on wakeup not used
Key-on wakeup used
Port P20 key-on wakeup
control bit
0
Key-on wakeup not used
1
Key-on wakeup used
Ports P10–P13 return condition selection
at reset : 00002
at RAM back-up : state retained
0
1
Return by level
Ports P10–P13 valid waveform/
0
level selection bit
1
Falling waveform/“L” level
Rising waveform/“H” level
INT pin
return condition selection bit
0
Return by level
1
Return by edge
INT pin
0
1
Key-on wakeup not used
Notes 1: “R” represents read enabled, and “W” represents write enabled.
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page 54 of 140
R/W
TAK2/TK2A
Key-on wakeup used
bit
key-on wakeup control bit
R/W
TAK1/TK1A
Key-on wakeup not used
at reset : 00002
Key-on wakeup control register L1
L13
at RAM back-up : state retained
control bit
control bit
R/W
TAK0/TK0A
Key-on wakeup used
at reset : 00002
Key-on wakeup control register K2
K23
at RAM back-up : state retained
Return by edge
Key-on wakeup used
R/W
TAL1/TL1A
4509 Group
Table 22 Pull-up control register and interrupt control register
Pull-up control register PU0
PU03
PU02
PU01
PU00
at reset : 00002
Port P03 pull-up transistor
0
Pull-up transistor OFF
control bit
Port P02 pull-up transistor
1
Pull-up transistor ON
0
Pull-up transistor OFF
control bit
1
Port P01 pull-up transistor
0
Pull-up transistor ON
Pull-up transistor OFF
control bit
1
0
Pull-up transistor ON
Port P00 pull-up transistor
control bit
1
Pull-up transistor ON
PU12
PU11
PU10
0
Pull-up transistor OFF
control bit
1
Port P12 pull-up transistor
0
Pull-up transistor ON
Pull-up transistor OFF
control bit
1
0
Pull-up transistor ON
control bit
Port P10 pull-up transistor
1
Pull-up transistor ON
0
Pull-up transistor OFF
control bit
1
Pull-up transistor ON
Pull-up control register PU2
PU23
PU22
PU21
PU20
at RAM back-up : state retained
Port P13 pull-up transistor
Port P11 pull-up transistor
at reset : 00002
at RAM back-up : state retained
0
Pull-up transistor OFF
control bit
1
Pull-up transistor ON
Port D2 pull-up transistor
0
control bit
1
Pull-up transistor OFF
Pull-up transistor ON
Port P21 pull-up transistor
0
1
Pull-up transistor OFF
0
Pull-up transistor OFF
1
Pull-up transistor ON
Port P20 pull-up transistor
control bit
Notes 1: “R” represents read enabled, and “W” represents write enabled.
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page 55 of 140
R/W
TAPU1/TPU1A
Pull-up transistor OFF
Port D3 pull-up transistor
control bit
R/W
TAPU0/TPU0A
Pull-up transistor OFF
at reset : 00002
Pull-up control register PU1
PU13
at RAM back-up : state retained
Pull-up transistor ON
R/W
TAPU2/TPU2A
4509 Group
CLOCK CONTROL
The system clock and the instruction clock are generated as the
source clock for operation by these circuits.
Figure 49 shows the structure of the clock control circuit.
The 4509 Group operates by the on-chip oscillator clock (f(RING))
which is the internal oscillator after system is released from reset.
Also, the ceramic resonator or the RC oscillation can be used for the
source oscillation (f(XIN)) of the 4509 Group.
The clock control circuit consists of the following circuits.
• On-chip oscillator (internal oscillator)
• Ceramic oscillation circuit
• RC oscillation circuit
• Multi-plexer (clock selection circuit)
• Frequency divider
• Internal clock generating circuit
Division circuit
divided by 8
f(RING)
MR0
divided by 4
1
divided by 2
11
System clock
Internal clock
generation circuit
(divided by 3)
10
01
On-chip oscillator
f(XIN)
MR3, MR2
00
0
RG0
XIN
XOUT
Ceramic resonator
circuit
Multiplexer
RC oscillation circuit
Q S
CRCK instruction
Q R
Internal reset signal
MR1
Q S
R
Fig. 49 Clock control circuit structure
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Key-on wakeup signal
EPOF instruction + POF instruction
Instruction clock
(INSTCK)
4509 Group
(1) On-chip oscillator operation
Main clock f(XIN)
After system is released from reset, the MCU starts operation by the
clock output from the on-chip oscillator which is the internal oscillator.
The clock frequency of the on-chip oscillator depends on the supply
voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
• Ceramic oscillation valid
• RC oscillation invalid
Reset
CRCK instruction
(2) Main clock generating circuit (f(XIN))
The ceramic resonator or RC oscillation can be used for the main
clock of this product.
After system is released from reset, the ceramic oscillation is active
for main clock.
The ceramic oscillation is invalid and the RC oscillation circuit is
valid with the CRCK instruction.
Execute the CRCK instruction in the initial setting routine of program
(executing it in address 0 in page 0 is recommended).
The execution of the CRCK instruction can be valid only once.
Register MR controls the enable/disable of the oscillation and the
selection of the operation source clock.
Also, when the MCU operates only by the on-chip oscillator without
using main clock f(XIN), connect XIN pin to Vss and leave XOUT pin
open, and do not execute the CRCK instruction (Figure 51).
• Ceramic oscillation invalid
• RC oscillation valid
Fig. 50 Switch to ceramic oscillation/RC oscillation
4509
XIN
not execute the CRCK
* Do
instruction in program.
XOUT
Fig. 51 Handling of XIN and XOUT when main clock is not used
(3) Ceramic resonator
When the ceramic resonator is used as the main clock (f(XIN)), connect the ceramic resonator and the external circuit to pins XIN and
XOUT at the shortest distance. A feedback resistor is built in between
pins XIN and XOUT (Figure 52).
Do not execute the CRCK instruction.
Set “0” to bit 0 of register MR after the oscillation stabilizing wait
time is generated by software to select the clock generated by the
ceramic oscillation circuit for the source oscillation clock.
4509
XIN
XOUT
Note: Externally connect a damping
resistor Rd depending on the
oscillation frequency.
Rd
(A feedback resistor is built-in.)
Use the resonator manufacturer’s recommended value
COUT
because constants such as capacitance depend on the
resonator.
CIN
(4) RC oscillation
When the RC oscillation is used as the main clock (f(XIN)), connect
the XIN pin to the external circuit of resistor R and the capacitor C at
the shortest distance and leave XOUT pin open. Then, execute the
CRCK instruction (Figure 53).
The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the recommended operating
condition of the frequency limits.
not execute the CRCK
* Do
instruction in program.
Fig. 52 Ceramic resonator external circuit
4509
R
XIN
C
Fig. 53 External RC circuit
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XOUT
the CRCK
* Execute
instruction in program.
4509 Group
(5) External clock
When the external signal clock is used for the main clock (f(X IN)),
connect the X IN pin to the clock source and leave X OUT pin open
(Figure 54). Do not execute the CRCK instruction in program.
Be careful that the maximum value of the oscillation frequency when
using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition).
Also, note that the RAM back-up mode (POF instruction) cannot be
used when using the external clock.
XIN
XOUT
VDD
VSS
(6) Clock control register MR
Register MR controls the selection of operation mode and the operation source clock, and enable/stop of main clock. Set the contents of
this register through register A with the TMRA instruction. In addition,
the TAMR instruction can be used to transfer the contents of register
MR to register A.
not execute the CRCK
* Do
instruction in program.
4509
External oscillation circuit
Fig. 54 External clock input circuit
(7) Clock control register RG
Register RG controls the on-chip oscillator. Set the contents of this
register through register A with the TRGA instruction.
Table 23 Clock control register MR
Clock control register MR
MR3
Operation mode selection bits
MR2
MR1
Main clock f(XIN) control bit (Notes 2, 5)
MR0
Operation source clock selection bit (Notes 3, 5)
at reset : 11012
MR3 MR2
0
0
0
1
1
0
1
1
On-chip oscillator (f(RING)) control bit
(Note 4)
Frequency divided by 4 mode
Frequency divided by 8 mode
Main clock (f(XIN)) oscillation enabled
1
Main clock (f(XIN)) oscillation stop
0
1
Main clock (f(XIN))
On-chip oscillator clock (f(RING))
at reset : 02
0
1
R/W
TAMR/TMRA
Operation mode
Through mode (frequency not divided)
Frequency divided by 2 mode
0
Clock control register RG
RG0
at RAM back-up : 11012
at RAM back-up : 02
W
TRGA
On-chip oscillator (f(RING)) oscillation enabled
On-chip oscillator (f(RING)) oscillation stop
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Main clock cannot be stopped when the main clock is selected for the operation source clock.
3: The stopped clock cannot be selected for the operation source clock. In order to switch the operation source clock, generate the oscillation stabilizing wait time by software first and set the oscillation of the destination clock to be enabled.
4: On-chip oscillator cannot be stopped when the on-chip oscillator is selected for the operation source clock.
5: When changing the setting of MR1 and MR0 from “00” to “11”, make settings in the sequence “00” → “01” → “11”.
When changing the setting of MR1 and MR0 from “11” to “0”, make settings in the sequence “11” → “01” → “00”.
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4509 Group
QzROM Writing Mode
In the QzROM writing mode, the user ROM area can be rewritten
while the microcomputer is mounted on-board by using a serial programmer which is applicable for this microcomputer.
Table 24 lists the pin description (QzROM writing mode) and Figure
55 shows the pin connections.
Refer to Figure 56 for examples of a connection with a serial programmer.
Contact the manufacturer of your serial programmer for serial programmer. Refer to the user’s manual of your serial programmer for
details on how to use it.
Table 24 Pin description (QzROM writing mode)
Pin
Name
VDD
VSS
CNVSS
Power source
GND
VPP input
P20/AIN0
P21/AIN1
SDA input/output
SCLK input
________
PGM input
Reset input
D3/AIN5
____________
RESET
XIN
Clock input
XOUT
Clock output
D0, D1, D2/AIN4, D4, D5, I/O port
P00/SIN, P01/SOUT,
P02/SCK, P03, P10,
P11/CNTR1,
P12/CNTR0, P13/INT,
P30/AIN2, P31/AIN3
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I/O



I/O
Input
Input
Input


I/O
Function
• Power supply voltage pin.
• GND pin.
• QzROM programmable power source pin.
• VPP input is possible with VSS connected via a resistor of about 5 kΩ.
• QzROM serial data I/O pin.
• QzROM serial clock input pin.
• QzROM read/program pulse input pin.
• Reset input pin.
• Input “L” level signal.
• Either connect an oscillation circuit or connect XIN pin to VSS and leave the
XOUT pin open.
• Input “H” or “L” level signal or leave the pin open.
4509 Group
1
24
P30/AIN2
VSS
VSS
2
23
P31/AIN3
XIN
3
22
P00/SIN
XOUT
4
21
P01/SOUT
20
P02/SCK
19
P03
18
P10
17
P11/CNTR1
16
P12/CNTR0
(Note 1)
VPP
M34509G4-XXXFP
M34509G4FP
M34509G4H-XXXFP
VDD
M34509G4HFP
VDD
CNVSS (Note 2)
5
RESET
6
SCLK
P21/AIN1
7
SDA
P20/AIN0
8
D5
9
D4
10
15
P13/INT
D3/AIN5
11
14
D0
D2/AIN4
12
13
D1
1kΩ
PGM
Package type: PRSP0024GA-A (24P2Q-A)
Note 1: Either connect an oscillation circuit or connect XIN pin to VSS and leave the XOUT
pin open.
2: VPP input is possible with VSS connected via a resistor of about 5 kΩ.
: QzROM pin
Fig. 55 Pin connection diagram
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4509 Group
4509 Group
T_VDD
VDD
T_VPP
CNVSS
T_T XD
1 kΩ
T_RXD
P20/AIN0 (SDA)
T_SCLK
P21/AIN1 (SCLK)
T_BUSY
T_PGM/OE/MD
N.C.
D3/AIN5 (PGM)
RESET circuit
T_RESET
GND
RESET
Vss
XIN
XOUT
Either connect an oscillation circuit
or connect XIN pin to VSS and
leave the XOUT pin open.
Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.
Fig. 56 When using programmer of Suisei Electronics System Co., LTD, connection example
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4509 Group
DATA REQUIRED FOR QzROM WRITING
ORDERS
The following are necessary when ordering a QzROM product
shipped after writing:
1. QzROM Writing Confirmation Form*
2. Mark Specification Form*
3. ROM data...........Mask file
* For the QzROM writing confirmation form and the mark specification form, refer to the “Renesas Technology Corp.” Homepage (http:/
/www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.
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4509 Group
LIST OF PRECAUTIONS
➀Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1 µF) between pins VDD
and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire.
CNVSS pin is also used as VPP pin. Accordingly, when using this
pin, connect this pin to VSS through a resistor about 5 kΩ (connect
this resistor to CNVSS/VPP pin as close as possible).
➁Note on Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when the
power source voltage drops or the power supply is turned off, reset
a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause
errors to the system by this unstable operation.
➂Register initial values 1
The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set
initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits)
➃Register initial values 2
The initial value of the following registers are undefined at RAM
back-up. After system is returned from RAM back-up, set initial values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits)
➄Program counter
Make sure that the PCH does not specify after the last page of the
built-in ROM.
➅Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers
is used respectively when using an interrupt service routine and
when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations
together.
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➆ Multifunction
- The input/output of P0 0 can be used even when SIN is used. Be
careful when using inputs of both S IN and P0 0 since the input
threshold value of SIN pin is different from that of port P00.
- The input of P01 can be used even when SOUT is used.
- The input of P02 can be used even when SCK is used. Be careful
when using inputs of both S CK and P02 since the input threshold
value of SCK pin is different from that of port P02.
- The input of P11 can be used even when CNTR1 (output) is selected.
The input/output of P11 can be used even when CNTR1 (input) is
selected. Be careful when using inputs of both CNTR1 and P1 1
since the input threshold value of CNTR1 pin is different from that
of port P11.
- The input of P12 can be used even when CNTR0 (output) is selected.
The input/output of P12 can be used even when CNTR0 (input) is
selected. Be careful when using inputs of both CNTR0 and P1 2
since the input threshold value of CNTR0 pin is different from that
of port P12.
- The input/output of P13 can be used even when INT is used. Be
careful when using inputs of both INT and P1 3 since the input
threshold value of INT pin is different from that of port P13.
- The input/output of P20, P21, P30, P31, D2, D 3 can be used even
when AIN0–AIN5 are used.
➇Power-on reset (only for H version)
When the built-in power-on reset circuit is used, set the time for
the supply voltage to rise from 0 V to the minimum voltage of recommended operating conditions to 100 µs or less.
If the rising time exceeds 100 µs, connect a capacitor between the
RESET pin and Vss at the shortest distance, and input “L” level to
RESET pin until the value of supply voltage reaches the minimum
operating voltage.
➈POF instruction
When the POF instruction is executed continuously after the EPOF
instruction, system enters the RAM back-up state.
Note that system cannot enter the RAM back-up state when executing only the POF instruction.
Be sure to disable interrupts by executing the DI instruction before
executing the EPOF instruction and the POF instruction continuously.
4509 Group
P13/INT pin
Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes.
Note [3] on bit 2 of register I1
When the interrupt valid waveform of the P13/INT pin is changed
with the bit 2 of register I1 in software, be careful about the following notes.
• Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 57➀)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 57➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 57➂).
• Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 59➀)
and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 59➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 59➂).
LA
4
TV1A
LA
8
TI1A
NOP
SNZ0
LA
4
TV1A
LA
12
TI1A
NOP
SNZ0
NOP
✕ : these bits are not used here.
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (1✕✕✕2)
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
•••
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT pin input is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
•••
•••
10
Fig. 57 External 0 interrupt program example-1
✕ : these bits are not used here.
➁ Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
•••
• When the INT pin input is disabled (register I13 = “0”), set the keyon wakeup of INT pin to be invalid (register L1 0 = “0”) before
system enters to the RAM back-up mode. (refer to Figure 58➀).
; (✕✕✕02)
; INT key-on wakeup disabled ........... ➀
; RAM back-up
•••
LA
0
TI1A
DI
EPOF
POF2
✕ : these bits are not used here.
Fig. 58 External 0 interrupt program example-2
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Fig. 59 A/D conversion interrupt program example
4509 Group
11
Prescaler
Stop prescaler counting and then execute the TABPS instruction
to read its data.
Stop prescaler counting and then execute the TPSAB instruction
to write data to prescaler.
12
Timer count source
Stop timer 1 or 2 counting to change its count source.
13
Reading the count value
Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 instruction to read its data.
14
Writing to the timer
Stop timer 1 or 2 counting and then execute the T1AB, T1R1L,
T2AB or T2R2L instruction to write data to timer.
15
Writing to reload register
In order to write a data to the reload register R1H while the timer
1 is operating, execute the T1HAB instruction except a timing of
the timer 1 underflow.
In order to write a data to the reload register R2H while the timer
2 is operating, execute the T2HAB instruction except a timing of
the timer 2 underflow.
16
Prescaler, timer 1 and timer 2 count start timing and count time
when operation starts
Count starts from the first rising edge of the count source (2) after
prescaler and timer operations start (1).
Time to first underflow (3) is shorter (for up to 1 period of the count
source) than time among next underflow (4) by the timing to start
the timer and count source operations after count starts.
When selecting CNTR input as the count source of timer, timer
operates synchronizing with the count edge (falling edge or rising
edge) of CNTR input selected by software.
A
A
Watchdog timer
• The watchdog timer function is valid after system is released from
reset. When not using the watchdog timer function, execute the
DWDT instruction and the WRST instruction continuously, and
clear the WEF flag to “0” to stop the watchdog timer function.
• The contents of WDF1 flag and timer WDT are initialized at the
RAM back-up mode.
• When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the
microcomputer enters the RAM back-up state.
Also, set the NOP instruction after the WRST instruction, for the
case when a skip is performed with the WRST instruction.
18
19
Clock control
When the RC oscillation is used as the main clock f(XIN), execute
the CRCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended).
The oscillation circuit by the CRCK instruction can be selected
only once. When the CRCK instruction is not executed, the ceramic oscillation is selected for the main clock f(XIN).
Also, when the MCU operates only by the on-chip oscillator without using main clock f(XIN), connect XIN pin to Vss and leave XOUT
pin open, and do not execute the CRCK instruction.
In order to switch the operation source clock (f(RING)) or f(X IN)),
generate the oscillation stabilizing wait time by software first and
set the oscillation of the destination clock to be enabled.
Registers RG and MR are initialized when system returns from
RAM back-up mode.
However, the selected contents (CRCK instruction execution state)
of main clock (f(XIN)) oscillation circuit is retained.
20
On-chip oscillator
The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range.
Be careful that variable frequencies when designing application products.
Also, when considering the oscillation stabilize wait time for switching clock, be careful that the variable frequency of the on-chip
oscillator clock.
21
External clock
When the external clock is used for the main clock (f(X IN)), connect the XIN pin to the clock source and leave XOUT pin open. Do
not execute the CRCK instruction in program.
Be careful that the maximum value of the oscillation frequency
when using the external clock differs from the value when using
the ceramic resonator (refer to the recommended operating condition).
Also, note that the RAM back-up mode (POF instruction) cannot
be used when using the external clock.
➁
Count source
Count source
(When falling edge of
CNTR input is selected)
Timer value
3 2
1
0
3
2
1
0
3
2
Timer underflow signal
→
➂
➃
➀ Timer start
Fig. 60 Timer count start timing and count time when operation starts
17
PWM signal (PWM1, PWM2)
If the timer 1 count stop timing and the timer 1 underflow timing
overlap during output of the PWM1 signal, a hazard may occur in
the PWM1 output waveform.
If the timer 2 count stop timing and the timer 2 underflow timing
overlap during output of the PWM2 signal, a hazard may occur in
the PWM2 output waveform.
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4509 Group
22
•
•
•
•
Notes for the use of A/D conversion 1
TALA instruction
When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A,
simultaneously, the low-order 2 bits of register A is “0.”
Do not change the operating mode (both A/D conversion mode and
comparator mode) of A/D converter with the bit 3 of register Q1
while the A/D converter is operating.
Clear the bit 2 of register V2 to “0” to change the operating mode
from the comparator mode to A/D conversion mode.
The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to
the bit 3 of register Q1, and execute the SNZAD instruction to clear
the ADF flag.
23
Notes for the use of A/D conversion 2
Each analog input pin is equipped with a capacitor which is used to
compare the analog voltage. Accordingly, when the analog voltage
is input from the circuit with high-impedance and, charge/discharge noise is generated and the sufficient A/D accuracy may not
be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 µF to 1 µF) to analog input pins (Figure 60).
When the overvoltage applied to the A/D conversion circuit may
occur, connect an external circuit in order to keep the voltage
within the rated range as shown the Figure 61. In addition, test the
application products sufficiently.
AIN
•••
Sensor
LA
8
TV2A
LA
0
TQ1A
; (✕0✕✕2)
; The SNZAD instruction is valid ........ ➀
; (0✕✕✕2)
; Operation mode of A/D converter is
changed from comparator mode to A/D
conversion mode.
Apply the voltage withiin the specifications
to an analog input pin.
Fig. 62 Analog input external circuit example-1
•••
SNZAD
NOP
About 1kΩ
✕ : this bit is not related to change the operation
mode of A/D converter.
Sensor
AIN
Fig. 61 External 0 interrupt program example-3
Fig. 63 Analog input external circuit example-2
QzROM
(1) Be careful not to apply overvoltage to MCU. The contents of
QzROM may be overwritten because of overvoltage. Take care
especially at turning on the power.
(2) As for the product shipped in blank, Renesas does not perform
the writing test to user ROM area after the assembly process
though the QzROM writing test is performed enough before the
assembly process. Therefore, a writing error of approx.0.1 %
may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may
cause some writing errors.
24
25
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Notes On ROM Code Protect
(QzROM product shipped after writing)
As for the QzROM product shipped after writing, the ROM code
protect is specified according to the ROM option setup data in the
mask file which is submitted at ordering.
The ROM option setup data in the mask file is “0016” for protect
enabled or “FF16” for protect disabled.
Note that the mask file which has nothing at the ROM option data
or has the data other than “0016” and “FF16” can not be accepted.
4509 Group
NOTES ON NOISE
Countermeasures against noise are described below.
The following countermeasures are effective against noise in theory,
however, it is necessary not only to take measures as follows but to
evaluate before actual use.
1. Shortest wiring length
(1) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as
short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring.
<Reason>
In order to reset a microcomputer correctly, 1 machine cycle or more
of the width of a pulse input into the RESET pin is required.
If noise having a shorter pulse width than this is input to the RESET
input pin, the reset is released before the internal state of the microcomputer is completely initialized.
This may cause a program runaway.
(2) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as
short as possible.
• Make the length of wiring across the grounding lead of a capacitor
which is connected to an oscillator and the VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns.
<Reason>
If noise enters clock I/O pins, clock waveforms may be deformed.
This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a
microcomputer and the V SS level of an oscillator, the correct clock
will not be input in the microcomputer.
Noise
XIN
XOUT
VSS
Noise
XIN
XOUT
VSS
O.K.
N.G.
Reset
circuit
RESET
VSS
VSS
N.G.
Reset
circuit
VSS
RESET
VSS
O.K.
Fig. 64 Wiring for the RESET pin
Fig. 65 Wiring for clock I/O pins
(3) Wiring to CNVSS pin
Connect CNVSS pin to a GND pattern at the shortest distance.
The GND pattern is required to be as close as possible to the GND
supplied to VSS.
In order to improve the noise reduction, to connect a 5 kΩ resistor
serially to the CNVSS pin - GND line may be valid.
As well as the above-mentioned, in this case, connect to a GND pattern at the shortest distance. The GND pattern is required to be as
close as possible to the GND supplied to VSS.
<Reason>
The CNVSS pin of the QzROM is the power source input pin for the
built-in QzROM. When programming in the built-in QzROM, the impedance of the CNV SS pin is low to allow the electric current for
writing flow into the QzROM. Because of this, noise can enter easily.
If noise enters the CNVSS pin, abnormal instruction codes or data
are read from the built-in QzROM, which may cause a program runaway.
(Note)
The shortest
CNVSS
About 5kΩ
VSS
(Note)
The shortest
Note: This indicates pin.
Fig. 66 Wiring for the CNVSS pin of the QzPROM
Rev.1.02 2006.12.22
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page 67 of 140
4509 Group
2. Connection of bypass capacitor across VSS line and VDD line
Connect an approximately 0.1 µF bypass capacitor across the VSS
line and the VDD line as follows:
• Connect a bypass capacitor across the VSS pin and the VDD pin at
equal length.
• Connect a bypass capacitor across the VSS pin and the V DD pin
with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line
and VDD line.
• Connect the power source wiring via a bypass capacitor to the VSS
pin and the VDD pin.
AA
AA
AA
AA
AA
VDD
VSS
N.G.
AA
AA
AA
AA
AA
VDD
3. Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog input pin in series.
Besides, connect the resistor to the microcomputer as close as
possible.
• Connect an approximately 1000 pF capacitor across the Vss pin
and the analog input pin. Besides, connect the capacitor to the Vss
pin as close as possible. Also, connect the capacitor across the
analog input pin and the Vss pin at equal length.
<Reason>
Signals which is input in an analog input pin (such as an A/D converter/comparator input pin) are usually output signals from sensor.
The sensor which detects a change of event is installed far from the
printed circuit board with a microcomputer, the wiring to an analog
input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise
to an analog input pin.
VSS
Noise
O.K.
(Note)
Microcomputer
Fig. 67 Bypass capacitor across the VSS line and the VDD line
Analog
input pin
Thermistor
N.G.
O.K.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 68 Analog signal line and a resistor and a capacitor
Rev.1.02 2006.12.22
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page 68 of 140
4509 Group
4. Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of
current value flows.
<Reason>
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large
current flows through those signal lines, strong noise occurs because of mutual inductance.
(2) Installing oscillator away from signal lines where potential levels
change frequently
Install an oscillator and a connecting pattern of an oscillator away
from signal lines where potential levels change frequently. Also, do
not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
<Reason>
Signal lines where potential levels change frequently (such as the
CNTR pin signal line) may affect other lines at signal rising edge or
falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a program runaway.
Microcomputer
Mutual inductance
M
XIN
XOUT
VSS
GND
Fig. 69 Wiring for a large current signal line
N.G.
CNTR
XIN
XOUT
VSS
Fig. 70 Wiring to a signal line where potential levels change frequently
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An example of VSS patterns on the
underside of a printed circuit board
A A
AAA
AAA
A
A
AAA
A
A
AA
AA
Oscillator wiring
pattern example
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 71 Vss pattern on the underside of an oscillator
5. Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
Large
current
Do not cross
(3) Oscillator protection using Vss pattern
As for a two-sided printed circuit board, print a Vss pattern on the
underside (soldering side) of the position (on the component side)
where an oscillator is mounted.
Connect the Vss pattern to the microcomputer Vss pin with the
shortest possible wiring. Besides, separate this Vss pattern from
other Vss patterns.
page 69 of 140
<Software>
• As for an input port, read data several times by a program for
checking whether input levels are equal or not.
• As for an output port or an I/O port, since the output data may reverse because of noise, rewrite data to its port latch at fixed
periods.
• Rewrite data to pull-up control registers at fixed periods.
6. Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be
detected by a software watchdog timer and the microcomputer can
be reset to normal operation. This is equal to or more effective than
program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing
routine and the interrupt processing routine detects errors of the
main routine.
This example assumes that interrupt processing is repeated multiple
times in a single main routine processing.
4509 Group
<The main routine>
• Assigns a single word of RAM to a software watchdog timer
(SWDT) and writes the initial value N in the SWDT once at each
execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ (Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a
margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after
the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery
processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the
SWDT contents are reset to the initial value N at almost fixed
cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch
to the program initialization routine for recovery processing in the
following case:
If the SWDT contents are not initialized to the initial value N but
continued to decrement and if they reach 0 or less.
≠N
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
EI
Interrupt processing
Main processing
(SWDT)
≤0?
≤0
(SWDT)
= N?
N
R TI
Return
Interrupt processing
routine errors
Main routine
errors
Fig. 72 Watchdog timer by software
Rev.1.02 2006.12.22
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>0
page 70 of 140
4509 Group
CONTROL REGISTERS
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
0
1
0
1
0
1
0
1
Interrupt control register V2
V23
Serial interface interrupt enable bit
V22
A/D interrupt enable bit
V21
Not used
V20
Not used
I12
I11
I10
INT pin input control bit (Note 2)
Interrupt valid waveform for INT pin/
return level selection bit (Note 2)
INT pin edge detection circuit control bit
INT pin
timer 1 control enable bit
MR3
Operation mode selection bits
MR2
MR1
MR0
Main clock f(XIN) control bit (Note 3)
Operation source clock selection bit (Note 4)
On-chip oscillator (f(RING)) control bit
(Note 5)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
at RAM back-up : 00002
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
0
1
at RAM back-up : state retained
INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
1
instruction)/“H” level
0
1
0
1
One-sided edge detected
Both edges detected
Disabled
Enabled
at reset : 11012
MR3 MR2
0
0
0
1
1
0
1
1
at RAM back-up : 11012
R/W
TAMR/TMRA
Operation mode
Through mode (frequency not divided)
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
Main clock (f(XIN)) oscillation enabled
1
Main clock (f(XIN)) oscillation stop
0
Main clock (f(XIN))
1
On-chip oscillator clock (f(RING))
at reset : 02
0
1
R/W
TAI1/TI1A
INT pin input disabled
0
0
R/W
TAV2/TV2A
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
at reset : 00002
Clock control register RG
RG0
This bit has no function, but read/write is enabled.
0
1
0
1
0
1
0
1
Clock control register MR
R/W
TAV1/TV1A
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
at reset : 00002
Interrupt control register I1
I13
at RAM back-up : 00002
at reset : 00002
at RAM back-up : 02
W
TRGA
On-chip oscillator (f(RING)) oscillation enabled
On-chip oscillator (f(RING)) oscillation stop
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.
3: Main clock cannot be stopped when the main clock is selected for the operation source clock.
4: The stopped clock cannot be selected for the operation source clock. In order to switch the operation source clock, generate the oscillation stabilizing wait time by software first and set the oscillation of the destination clock to be enabled.
5: On-chip oscillator cannot be stopped when the on-chip oscillator is selected for the operation source clock.
Rev.1.02 2006.12.22
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page 71 of 140
4509 Group
Timer control register PA
PA0
Prescaler control bit
at reset : 02
W13
PWM1 function control bit
W12
Timer 1 control bit
W11
Timer 1 count source selection bits
W10
at reset : 00002
W11 W10
0
0
0
1
1
0
1
1
at RAM back-up : 00002
at reset : 00002
PWM2 function control bit
0
1
PWM2 function invalid
PWM2 function valid
W22
Timer 2 control bit
0
1
Stop (state retained)
Operating
Timer 2 count source selection bits
W20
W21 W20
0
0
0
1
1
0
1
1
Timer control register W5
W53
P12/CNTR0 pin function selection bit
W52
Timer 1 count auto-stop circuit
selection bit (Note 2)
Timer 1 count start synchronous circuit
selection bit (Note 3)
W51
W50
CNTR0 pin input count edge selection bit
Timer control register W6
W63
W62
W61
W60
P11/CNTR1 pin function selection bit
CNTR 1 pin output auto-control circuit
selection bit
Timer 2
INT pin input period count circuit selection bit
CNTR1 pin input count edge selection bit
at RAM back-up : state retained
R/W
TAW5/TW5A
P12 (I/O) / CNTR0 (input)
P12 (input) /CNTR0 (I/O)
Count auto-stop circuit not selected
Count auto-stop circuit selected
Count start synchronous circuit not selected
Count start synchronous circuit selected
Falling edge
Rising edge
at reset : 00002
0
1
0
1
0
1
0
1
R/W
TAW2/TW2A
Count source
Timer 1 underflow signal (T1UDF)
Prescaler output (ORCLK)
CNTR0 input
System clock (STCK)
at reset : 00002
0
1
0
1
0
1
0
1
R/W
TAW1/TW1A
Count source
PWM2 signal
Prescaler output (ORCLK)
CNTR1 input
On-chip oscillator clock (f(RING))
W23
W21
at RAM back-up : 00002
PWM1 function invalid
PWM1 function valid
Stop (state retained)
Operating
0
1
0
1
Timer control register W2
W
TPAA
Stop (state initialized)
Operating
0
1
Timer control register W1
at RAM back-up : 02
at RAM back-up : state retained
R/W
TAW6/TW6A
P11 (I/O) / CNTR1 (input)
P11 (input) /CNTR1 (I/O)
Output auto-control circuit not selected
Output auto-control circuit selected
INT pin input period count circuit not selected
INT pin input period count circuit selected
Falling edge
Rising edge
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”) and the timer 1 count start synchronous circuit is selected (W51=“1”).
3: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”).
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page 72 of 140
4509 Group
at reset : 00002
A/D control register Q1
Q13
A/D operation mode selection bit
Q12
Q11
Analog input pin selection bits
Q10
0
1
J13
J12
Serial interface synchronous clock
selection bits
J11
Serial interface port function selection bits
J10
at reset : 00002
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REJ03B0147-0102
page 73 of 140
Selected pins
at RAM back-up : state retained
Synchronous clock
J13 J12
0 Instruction clock (INSTCK) divided by 8
0
1 Instruction clock (INSTCK) divided by 4
0
0 Instruction clock (INSTCK) divided by 2
1
1 External clock (SCK input)
1
J1
0
Port function
J11
0
P00, P01, P02 selected/SIN, SOUT, SCK not selected
0
1 P00, SOUT, SCK selected/SIN, P01, P02 not selected
0
0 SIN, P01, SCK selected/P00, SOUT, P02 not selected
1
1 SIN, SOUT, SCK selected/P00, P01, P02 not selected
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
R/W
TAQ1/TQ1A
A/D conversion mode
Comparator mode
Q12 Q11 Q10
0
0
0
AIN0
0
0
1
AIN1
0
1
0
AIN2
0
1
1
AIN3
1
0
0
AIN4
1
0
1
AIN5
1
1
0
Not available
1
1
1
Not available
Serial interface control register J1
at RAM back-up : state retained
R/W
TAJ1/TJ1A
4509 Group
at reset : 00002
Key-on wakeup control register K0
K03
K02
K01
K00
Port P03 key-on wakeup
0
1
Key-on wakeup not used
control bit
Port P02 key-on wakeup
0
control bit
1
Key-on wakeup not used
Key-on wakeup used
Port P01 key-on wakeup
control bit
0
Key-on wakeup not used
1
Key-on wakeup used
Port P00 key-on wakeup
0
1
Key-on wakeup not used
control bit
Key-on wakeup control register K1
K13
K12
K11
K10
K22
K21
K20
L12
L11
L10
at RAM back-up : state retained
Port P13 key-on wakeup
0
Key-on wakeup not used
1
Key-on wakeup used
0
Key-on wakeup not used
control bit
1
Key-on wakeup used
Port P11 key-on wakeup
Key-on wakeup not used
control bit
0
1
Port P10 key-on wakeup
0
Key-on wakeup used
Key-on wakeup not used
control bit
1
Key-on wakeup used
at reset : 00002
at RAM back-up : state retained
Port D3 key-on wakeup
0
Key-on wakeup not used
control bit
Key-on wakeup used
Port D2 key-on wakeup
1
0
control bit
1
Key-on wakeup not used
Key-on wakeup used
Port P21 key-on wakeup
control bit
0
Key-on wakeup not used
1
Key-on wakeup used
Port P20 key-on wakeup
0
1
Key-on wakeup not used
Key-on wakeup control register L1
L13
Key-on wakeup used
control bit
Port P12 key-on wakeup
control bit
at reset : 00002
at RAM back-up : state retained
0
bit
1
Ports P10–P13 valid waveform/
level selection bit
0
Falling waveform/“L” level
1
Rising waveform/“H” level
INT pin
0
1
Return by level
return condition selection bit
INT pin
0
key-on wakeup control bit
1
Key-on wakeup not used
Key-on wakeup used
Notes 1: “R” represents read enabled, and “W” represents write enabled.
page 74 of 140
R/W
TAK1/TK1A
R/W
TAK2/TK2A
Key-on wakeup used
Ports P10–P13 return condition selection
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REJ03B0147-0102
R/W
TAK0/TK0A
Key-on wakeup used
at reset : 00002
Key-on wakeup control register K2
K23
at RAM back-up : state retained
Return by level
Return by edge
Return by edge
R/W
TAL1/TL1A
4509 Group
Pull-up control register PU0
PU03
PU02
PU01
PU00
Port P03 pull-up transistor
at reset : 00002
0
1
Pull-up transistor OFF
Port P02 pull-up transistor
control bit
0
Pull-up transistor OFF
1
Pull-up transistor ON
Port P01 pull-up transistor
0
control bit
1
Pull-up transistor OFF
Pull-up transistor ON
Port P00 pull-up transistor
0
1
control bit
control bit
PU12
PU11
PU10
PU22
PU21
PU20
Pull-up transistor ON
at RAM back-up : state retained
0
Pull-up transistor OFF
control bit
1
Port P12 pull-up transistor
0
Pull-up transistor ON
Pull-up transistor OFF
control bit
1
0
Pull-up transistor ON
control bit
Port P10 pull-up transistor
1
Pull-up transistor ON
0
Pull-up transistor OFF
control bit
1
Pull-up transistor ON
Pull-up control register PU2
PU23
Pull-up transistor OFF
Port P13 pull-up transistor
Port P11 pull-up transistor
at reset : 00002
at RAM back-up : state retained
0
Pull-up transistor OFF
control bit
Port D2 pull-up transistor
1
Pull-up transistor ON
0
Pull-up transistor OFF
control bit
1
Port P21 pull-up transistor
0
1
Pull-up transistor ON
Pull-up transistor OFF
Port P20 pull-up transistor
control bit
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REJ03B0147-0102
page 75 of 140
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
Notes 1: “R” represents read enabled, and “W” represents write enabled.
R/W
TAPU1/TPU1A
Pull-up transistor OFF
Port D3 pull-up transistor
control bit
R/W
TAPU0/TPU0A
Pull-up transistor ON
at reset : 00002
Pull-up control register PU1
PU13
at RAM back-up : state retained
R/W
TAPU2/TPU2A
4509 Group
at reset : 00002
Port output structure control register FR0
FR03
FR02
Port P03 output structure selection bit
Port P02 output structure selection bit
FR01
Port P01 output structure selection bit
FR00
Port P00 output structure selection bit
0
1
N-channel open-drain output
0
N-channel open-drain output
1
CMOS output
0
N-channel open-drain output
CMOS output
Port P13 output structure selection bit
FR12
Port P12 output structure selection bit
FR11
Port P11 output structure selection bit
FR10
Port P10 output structure selection bit
1
0
1
N-channel open-drain output
CMOS output
at reset : 00002
N-channel open-drain output
1
0
CMOS output
1
CMOS output
0
N-channel open-drain output
1
0
CMOS output
N-channel open-drain output
1
CMOS output
Not used
FR22
Not used
FR21
Port P21 output structure selection bit
FR20
at reset : 00002
1
0
Port P20 output structure selection bit
1
0
Port D3 output structure selection bit
FR32
Port D2 output structure selection bit
FR31
Port D1 output structure selection bit
FR30
Port D0 output structure selection bit
Port D5 output structure selection bit
C12
Port D4 output structure selection bit
C11
Port P31 output structure selection bit
C10
Port P30 output structure selection bit
page 76 of 140
N-channel open-drain output
N-channel open-drain output
1
CMOS output
at reset : 00002
at RAM back-up : state retained
0
N-channel open-drain output
1
CMOS output
0
N-channel open-drain output
CMOS output
0
1
N-channel open-drain output
0
N-channel open-drain output
1
CMOS output
at power down : state retained
0
N-channel open-drain output
1
CMOS output
N-channel open-drain output
0
W
TFR3A
CMOS output
at reset : 00002
1
0
CMOS output
1
CMOS output
0
N-channel open-drain output
1
CMOS output
Notes 1: “R” represents read enabled, and “W” represents write enabled.
Rev.1.02 2006.12.22
REJ03B0147-0102
This bit has no function, but read/write is enabled.
CMOS output
1
W
TFR2A
This bit has no function, but read/write is enabled.
0
Port output structure control register C1
C13
at RAM back-up : state retained
1
Port output structure control register FR3
FR33
W
TFR1A
N-channel open-drain output
0
FR23
at RAM back-up : state retained
0
Port output structure control register FR2
W
TFR0A
CMOS output
Port output structure control register FR1
FR13
at RAM back-up : state retained
N-channel open-drain output
W
TC1A
4509 Group
INSTRUCTIONS
SYMBOL
Each instruction is described as follows;
(1) Index list of instruction function
(2) Machine instructions (index by alphabet)
(3) Machine instructions (index by function)
(4) Instruction code table
The symbols shown below are used in the following list of instruction
function and the machine instructions.
Symbol
Contents
Symbol
RPS
Contents
Prescaler reload register (8 bits)
Register B (4 bits)
Register D (3 bits)
R1L
Timer 1 reload register (8 bits)
R1H
Timer 1 reload register (8 bits)
E
Q1
Register E (8 bits)
Timer 2 reload register (8 bits)
A/D control register Q1 (4 bits)
R2L
R2H
V1
Interrupt control register V1 (4 bits)
PS
Timer 2 reload register (8 bits)
Prescaler
V2
Interrupt control register V2 (4 bits)
T1
Timer 1
I1
Interrupt control register I1 (4 bits)
Timer control register W1 (4 bits)
T2
Timer 2
T1F
Timer 1 interrupt request flag
W2
W5
Timer control register W2 (4 bits)
Timer 2 interrupt request flag
Timer control register W5 (4 bits)
T2F
WDF1
W6
Timer control register W6 (4 bits)
WEF
Watchdog timer flag
Watchdog timer enable flag
FR0
Port output structure control register FR0 (4 bits)
INTE
Interrupt enable flag
FR1
Port output structure control register FR1 (4 bits)
Port output structure control register FR2 (4 bits)
EXF0
External 0 interrupt request flag
P
Power down flag
FR3
C1
Port output structure control register FR3 (4 bits)
ADF
SIOF
A/D conversion completion flag
J1
Serial interface control register J1 (4 bits)
MR
Clock control register MR (4 bits)
D
Port D (6 bits)
K0
Key-on wakeup control register K0 (4 bits)
Key-on wakeup control register K1 (4 bits)
P0
Port P0 (4 bits)
Port P1 (4 bits)
Key-on wakeup control register K2 (4 bits)
P1
P2
L1
Key-on wakeup control register L1 (4 bits)
P3
Port P2 (2 bits)
Port P3 (2 bits)
PU0
Pull-up control register PU0 (4 bits)
PU1
Pull-up control register PU1 (4 bits)
x
Hexadecimal variable
PU2
Pull-up control register PU2 (4 bits)
Register X (4 bits)
y
Hexadecimal variable
Hexadecimal variable
Register Y (4 bits)
z
p
Z
Register Z (2 bits)
n
Hexadecimal variable
Hexadecimal constant
DP
Data pointer (10 bits)
i
Hexadecimal constant
(It consists of registers X, Y, and Z)
j
Hexadecimal constant
Program counter (14 bits)
High-order 7 bits of program counter
A 3 A 2A 1A 0
Binary notation of hexadecimal variable A
A
Register A (4 bits)
B
DR
W1
FR2
K1
K2
X
Y
PC
PCH
PCL
Port output structure control register C1 (4 bits)
Serial interface transmit/receive completion flag
(same for others)
Low-order 7 bits of program counter
SK
Stack register (14 bits ✕ 8)
←
Direction of data movement
SP
Stack pointer (3 bits)
↔
Data exchange between a register and memory
CY
Carry flag
?
Decision of state shown before “?”
( )
Contents of registers and memories
—
M(DP)
Negate, Flag unchanged after executing instruction
a
RAM address pointed by the data pointer
Label indicating address a6 a5 a4 a3 a2 a1 a0
p, a
Label indicating address a6 a5 a4 a3 a2 a1 a0
in page p6 p5 p4 p3 p2 p1 p0
C
Hex. C + Hex. number x (also same for others)
+
x
Note : The 4509 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the
number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.
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4509 Group
INDEX LIST OF INSTRUCTION FUNCTION
Register to register transfer
Function
TAB
(A) ← (B)
TBA
(B) ← (A)
TAY
(A) ← (Y)
TYA
(Y) ← (A)
TEAB
(E7–E4) ← (B)
(E3–E0) ← (A)
Grouping Mnemonic
RAM to register transfer
GroupMnemonic
ing
XAMI j
Function
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
LA n
(A) ← n
n = 0 to 15
TABE
(B) ← (E7–E4)
(A) ← (E3–E0)
TDA
TABP p
(DR2–DR0) ← (A2–A0)
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
TAD
(A2–A0) ← (DR2–DR0)
(UPTF) = 1,
(A3) ← 0
TAZ
(DR1, DR0) ← (ROM(PC))9, 8
(A1, A0) ← (Z1, Z0)
(DR2) ← 0
(B) ← (ROM(PC))7–4
(A3, A2) ← 0
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(A) ← (X)
TASP
(A2–A0) ← (SP2–SP0)
(A3) ← 0
RAM addresses
LXY x, y
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
(SP) ← (SP) – 1
Arithmetic operation
TAX
AM
(A) ← (A) + (M(DP))
AMC
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
An
(A) ← (A) + n
LZ z
(Z) ← z z = 0 to 3
INY
(Y) ← (Y) + 1
AND
(A) ← (A) AND (M(DP))
DEY
(Y) ← (Y) – 1
OR
(A) ← (A) OR (M(DP))
TAM j
(A) ← (M(DP))
SC
(CY) ← 1
j = 0 to 15
RC
(CY) ← 0
(A) ← → (M(DP))
SZC
(CY) = 0 ?
j = 0 to 15
CMA
(A) ← (A)
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
RAR
→ CY → A3A2A1A0
n = 0 to 15
RAM to register transfer
(X) ← (X)EXOR(j)
XAM j
(X) ← (X)EXOR(j)
XAMD j
j = 0 to 15
(Y) ← (Y) – 1
Note: p is 0 to 31.
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4509 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
GroupMnemonic
ing
SB j
Function
GroupMnemonic
ing
Function
DI
(INTE) ← 0
EI
(INTE) ← 1
SNZ0
V10 = 0: (EXF0) = 1 ?
(EXF0) ← 0
V10 = 1: SNZ0 = NOP
SNZI0
I12 = 0 : (INT) = “L” ?
I12 = 1 : (INT) = “H” ?
TAV1
(A) ← (V1)
TV1A
(V1) ← (A)
TAV2
(A) ← (V2)
TV2A
(V2) ← (A)
TAI1
(A) ← (I1)
TI1A
(I1) ← (A)
TPAA
(PA) ← (A)
TAW1
(A) ← (W1)
TW1A
(W1) ← (A)
TAW2
(A) ← (W2)
(PCL) ← a6–a0
TW2A
(W2) ← (A)
(SP) ← (SP) + 1
TAW5
(A) ← (W5)
TW5A
(W5) ← (A)
TAW6
(A) ← (W6)
TW6A
(W6) ← (A)
TABPS
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
TPSAB
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
TAB1
(B) ← (T17–T14)
(A) ← (T13–T10)
(Mj(DP)) ← 1
Bit operation
j = 0 to 3
RB j
(Mj(DP)) ← 0
j = 0 to 3
SZB j
(Mj(DP)) = 0 ?
SEAM
(A) = (M(DP)) ?
SEA n
(A) = n ?
n = 0 to 15
Branch operation
Ba
BL p, a
BLA p
Interrupt operation
Comparison
operation
j = 0 to 3
(PCL) ← a6–a0
(PCH) ← p (Note)
(PCL) ← a6–a0
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
BM a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
BML p, a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
BMLA p
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
RTI
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RT
(PC) ← (SK(SP))
Timer operation
Subroutine operation
(PCL) ← a6–a0
Return operation
(SP) ← (SP) – 1
RTS
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Note: p is 0 to 31.
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4509 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Grouping Mnemonic
Function
CLD
(D) ← 1
RD
(D(Y)) ← 0
(Y) = 0 to 5
T1HAB
(R1H7–R1H4) ← (B)
(R1H3–R1H0) ← (A)
SD
(D(Y)) ← 1
(Y) = 0 to 5
TAB2
(B) ← (T27–T24)
(A) ← (T23–T20)
SZD
(D(Y)) = 0 ?
(Y) = 0 to 5
T2AB
(R2L7–R2L4) ← (B)
(T27–T24) ← (B)
(R2L3–R2L0) ← (A)
(T23–T20) ← (A)
TFR0A
(FR0) ← (A)
TFR1A
(FR1) ← (A)
TFR2A
(FR2) ← (A)
(R2H7–R2H4) ← (B)
(R2H3–R2H0) ← (A)
TFR3A
(FR3) ← (A)
T1R1L
(T17–T10) ← (R1L7–R1L0)
TC1A
(C1) ← (A)
T2R2L
(T27–T20) ← (R2L7–R2L0)
TK0A
(K0) ← (A)
SNZT1
V12 = 0: (T1F) = 1 ?
(T1F) ← 0
V12 = 1: SNZT1 = NOP
TAK0
(A) ← (K0)
TK1A
(K1) ← (A)
TAK1
(A) ← (K1)
TK2A
(K2) ← (A)
T2HAB
SNZT2
V13 = 0: (T2F) = 1 ?
(T2F) ← 0
V13 = 1: SNZT2 = NOP
Input/Output operation
Timer operation
GroupMnemonic
ing
(R1L7–R1L4) ← (B)
(T17–T14) ← (B)
(R1L3–R1L0) ← (A)
(T13–T10) ← (A)
T1AB
Input/Output operation
Function
IAP0
(A) ← (P0)
TAK2
(A) ← (K2)
OP0A
(P0) ← (A)
TPU0A
(PU0) ← (A)
IAP1
(A) ← (P1)
TAPU0
(A) ← (PU0)
OP1A
(P1) ← (A)
TPU1A
(PU1) ← (A)
IAP2
(A1, A0) ← (P21, P20)
(A3, A2) ← 0
TAPU1
(A) ← (PU1)
TPU2A
(PU2) ← (A)
OP2A
(P21, P20) ← (A1, A0)
TAPU2
(A) ← (PU2)
IAP3
(A1, A0) ← (P31, P30)
(A3, A2) ← 0
TL1A
(L1) ← (A)
(P31, P30) ← (A1, A0)
TAL1
(A) ← (L1)
OP3A
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4509 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Clock operation
Function
Function
TABSI
(B) ← (SI7–SI4) (A) ← (SI3–SI0)
NOP
(PC) ← (PC) + 1
TSIAB
(SI7–SI4) ← (B) (SI3–SI0) ← (A)
POF
RAM back-up
SST
(SIOF) ← 0
EPOF
POF instruction valid
SNZP
(P) = 1 ?
DWDT
Stop of watchdog timer function enabled
WRST
(WDF1) = 1 ?,
Serial interface transmit/receive starting
SNZSI
V23=0: (SIOF)=1?
(SIOF) ← 0
V23 = 1: SNZSI = NOP
TAJ1
(A) ← (J1)
TJ1A
(J1) ← (A)
CRCK
RC oscillator selected
SRST
System reset
TRGA
(RG0) ← (A0)
RUPT
(UPTF) ← 0
TAMR
(A) ← (MR)
SUPT
(UPTF) ← 1
TMRA
(MR) ← (A)
SVDE**
Voltage drop detection circuit valid at RAM backup
TABAD
Q13 = 0,
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
Q13 = 1,
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
TALA
(A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
A/D conversion operation
GroupMnemonic
ing
Other operation
Serial interface operation
GroupMnemonic
ing
TADAB
Q13 = 1 : (AD7–AD4) ← (B)
(AD3–AD0) ← (A)
Q13 = 0 : TABAD = NOP
TAQ1
(A) ← (Q1)
TQ1A
(Q1) ← (A)
ADST
(ADF) ← 0
Q13 = 0 : A/D conversion starting
Q13 = 1 : Comparator operation starting
SNZAD
V22 = 0: (ADF) = 1 ?
(ADF) ← 0
V22 = 1: SNZAD = NOP
Note: The SVDE instruction can be used only in the H version.
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(WDF1) ← 0
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET)
A n (Add n and accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
1
1
0
n
n
n
n
2
0
6
n
16
(A) ← (A) + n
n = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Overflow = 0
Grouping:
Arithmetic operation
Description: Adds the value n in the immediate field to
register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no
overflow as the result of operation.
Executes the next instruction when there is
overflow as the result of operation.
ADST (A/D conversion STart)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
1
1
1
2
2
9
F
16
(ADF) ← 0
Q13 = 0: A/D conversion starting
Q13 = 1: Comparator operation starting
(Q13 : bit 3 of A/D control register Q1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Clears (0) to A/D conversion completion
flag ADF, and the A/D conversion at the A/D
conversion mode (Q13 = 0) or the comparator operation at the comparator mode (Q13
= 1) is started.
AM (Add accumulator and Memory)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
0
1
0
2
0
0
A
16
(A) ← (A) + (M(DP))
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Adds the contents of M(DP) to register A.
Stores the result in register A. The contents
of carry flag CY remains unchanged.
AMC (Add accumulator, Memory and Carry)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
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REJ03B0147-0102
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0
1
1
2
0
0
B
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0/1
–
Grouping:
Arithmetic operation
Description: Adds the contents of M(DP) and carry flag
CY to register A. Stores the result in register A and carry flag CY.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
AND (logical AND between accumulator and memory)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
0
0
0
2
0
1
8
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Takes the AND operation between the contents of register A and the contents of
M(DP), and stores the result in register A.
(A) ← (A) AND (M(DP))
B a (Branch to address a)
Instruction
code
Operation:
D0
D9
0
1
1
a6 a5 a4 a3 a2 a1 a0
2
1
8
+a
a
16
(PCL) ← a6 to a0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Branch operation
Description: Branch within a page : Branches to address
a in the identical page.
Note:
Specify the branch address within the page
including this instruction.
BL p, a (Branch Long to address a in page p)
Instruction
code
Operation:
D9
D0
0
0
1
1
1
p4 p3 p2 p1 p0
1
0
0
a6 a5 a4 a3 a2 a1 a0 2
2
0
E
+p
2
a
(PCH) ← p
(PCL) ← a6 to a0
p
16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
a 16
Grouping:
Branch operation
Description: Branch out of a page : Branches to address
a in page p.
Note:
p is 0 to 31.
BLA p (Branch Long to address (D) + (A) in page p)
Instruction
code
Operation:
D9
D0
0
0
0
0
0
1
0
1
0
0
p4 0
0
p3 p2 p1 p0 2
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
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0
0
0
2
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
0
1
0
2
p
p 16
Grouping:
Branch operation
Description: Branch out of a page : Branches to address
(DR2 DR1 DR0 A3 A 2 A1 A 0)2 specified by
registers D and A in page p.
Note:
p is 0 to 31.
16
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
BM a (Branch and Mark to address a in page 2)
Instruction
code
Operation:
D9
0
D0
1
0
a6 a5 a4 a3 a2 a1 a0
2
1
a
a
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
Grouping:
Subroutine call operation
Description: Call the subroutine in page 2 : Calls the
subroutine at address a in page 2.
Note:
Subroutine extending from page 2 to another page can also be called with the BM
instruction when it starts on page 2.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
BML p, a (Branch and Mark Long to address a in page p)
Instruction
code
Operation:
D9
D0
0
0
1
1
0
p4 p3 p2 p1 p0
1
0
0
a6 a5 a4 a3 a2 a1 a0 2
2
0
C
+p
2
a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
p
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
16
a 16
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address a in page p.
Note:
p is 0 to 31.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
BMLA p (Branch and Mark Long to address (D) + (A) in page p)
Instruction
code
Operation:
D9
D0
0
0
0
0
1
1
0
0
0
0
1
0
0
p4 0
0
p3 p2 p1 p0 2
2
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
0
3
0
2
p
p 16
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
Note:
p is 0 to 31.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
16
CLD (CLear port D)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
(D) ← 1
Rev.1.02 2006.12.22
REJ03B0147-0102
0
0
1
2
0
1
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Sets (1) to port D.
page 84 of 140
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
CMA (CoMplement of Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
1
0
0 2
0
1
C 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Stores the one’s complement for register
A’s contents in register A.
(A) ← (A)
CRCK (Clock select: Rc oscillation ClocK)
Instruction
code
Operation:
D0
D9
1
0
1
0
0
1
1
0
1
1
2
2
9
B
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Selects the RC oscillation circuit for main
clock f(XIN).
RC oscillation circuit selected
DEY (DEcrement register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
1
1
1
2
0
1
7
16
(Y) ← (Y) – 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 15
Grouping:
RAM addresses
Description: Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.
DI (Disable Interrupt)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
(INTE) ← 0
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page 85 of 140
1
0
0
2
0
0
4
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt control operation
Description: Clears (0) to interrupt enable flag INTE, and
disables the interrupt.
Note:
Interrupt is disabled by executing the DI instruction after executing 1 machine cycle.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
DWDT (Disable WatchDog Timer)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
1
0
0
2
2
9
C
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Stops the watchdog timer function by the
WRST instruction after executing the
DWDT instruction.
Stop of watchdog timer function enabled
EI (Enable Interrupt)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
0
1
2
0
0
5
16
(INTE) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt control operation
Description: Sets (1) to interrupt enable flag INTE, and
enables the interrupt.
Note:
Interrupt is enabled by executing the EI instruction after executing 1 machine cycle.
EPOF (Enable POF instruction)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
1
0
1
1
2
0
5
B
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Makes the immediate after POF instruction
valid by executing the EPOF instruction.
POF instruction valid
IAP0 (Input Accumulator from port P0)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
0
0
(A) ← (P0)
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0
0
0
2
2
6
0
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P0 to register A.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
IAP1 (Input Accumulator from port P1)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
0
0
0
0
1
2
2
6
1
16
(A) ← (P1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P1 to register A.
IAP2 (Input Accumulator from port P2)
Instruction
code
Operation:
D0
D9
1
0
0
1
1
0
0
0
1
0
2
2
6
2
16
(A1, A0) ← (P21, P20)
(A3, A2) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P2 to the low-order 2 bits (A1, A0) of register A.
Note:
After this instruction is executed, “0” is
stored to the high-order 2 bits (A3 , A2 ) of
register A.
IAP3 (Input Accumulator from port P3)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
0
0
0
1
1
2
2
6
3
16
(A1, A0) ← (P31, P30)
(A3, A2) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P3 to the low-order 2 bits (A1, A0) of register A.
Note:
After this instruction is executed, “0” is
stored to the high-order 2 bits (A3 , A2 ) of
register A.
INY (INcrement register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
(Y) ← (Y) + 1
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0
1
1
2
0
1
3
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 0
Grouping:
RAM addresses
Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of
register Y is 0, the next instruction is
skipped. When the contents of register Y is
not 0, the next instruction is executed.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
LA n (Load n in Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
1
1
1
n
n
n
n
2
0
7
n
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Continuous
description
Grouping:
Arithmetic operation
Description: Loads the value n in the immediate field to
register A.
When the LA instructions are continuously
coded and executed, only the first LA instruction is executed and other LA
instructions coded continuously are
skipped.
(A) ← n
n = 0 to 15
LXY x, y (Load register X and Y with x and y)
Instruction
code
Operation:
D9
1
D0
1
x3 x2 x1 x0 y3 y2 y1 y0
2
3
x
y
16
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Continuous
description
Grouping:
RAM addresses
Description: Loads the value x in the immediate field to
register X, and the value y in the immediate
field to register Y. When the LXY instructions are continuously coded and executed,
only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
LZ z (Load register Z with z)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
1
0
z1 z0
2
0
4
8
+z 16
(Z) ← z z = 0 to 3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM addresses
Description: Loads the value z in the immediate field to
register Z.
NOP (No OPeration)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
(PC) ← (PC) + 1
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0
0
0
2
0
0
0
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: No operation; Adds 1 to program counter
value, and others remain unchanged.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OP0A (Output port P0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
0
0
0
0
2
2
2
0
16
(P0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P0.
OP1A (Output port P1 from Accumulator)
Instruction
code
Operation:
D0
D9
1
0
0
0
1
0
0
0
0
1
2
2
2
1
16
(P1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P1.
OP2A (Output port P2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
0
0
1
0
2
2
2
2
16
(P21, P20) ← (A1, A0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of the low-order 2 bits
(A1, A0) of register A to port P2.
OP3A (Output port P3 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
0
(P31, P30) ← (A1, A0)
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0
1
1
2
2
2
3
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of the low-order 2 bits
(A1, A0) of register A to port P3.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OR (logical OR between accumulator and memory)
Instruction
code
Operation:
D9
D0
0
0
0
0
0
1
1
0
0
1 2
0
1
9 16
(A) ← (A) OR (M(DP))
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Takes the OR operation between the contents of register A and the contents of
M(DP), and stores the result in register A.
POF (Power OFF)
Instruction
code
Operation:
D9
D0
0
0
0
0
0
0
0
0
1
0 2
0
0
2 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Puts the system in RAM back-up state by executing the POF instruction after executing
the EPOF instruction.
Note:
If the EPOF instruction is not executed just
before this instruction, this instruction is
equivalent to the NOP instruction.
RAM back-up
RAR (Rotate Accumulator Right)
Instruction
code
D9
D0
0
0
0
0
0
1
1
1
0
1
2
0
1
D
16
→ CY → A3A2A1A0
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0/1
–
Grouping:
Arithmetic operation
Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the
right.
RB j (Reset Bit)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
1
(Mj(DP)) ← 0
j = 0 to 3
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1
j
j
2
0
4
C
+j 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Bit operation
Description: Clears (0) the contents of bit j (bit specified
by the value j in the immediate field) of
M(DP).
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RC (Reset Carry flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
1
0
2
0
0
6
16
(CY) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0
–
Grouping:
Arithmetic operation
Description: Clears (0) to carry flag CY.
RD (Reset port D specified by register Y)
Instruction
code
Operation:
D0
D9
0
0
0
0
0
1
0
1
0
0
2
0
1
4
16
(D(Y)) ← 0
However,
(Y) = 0 to 5
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Clears (0) to a bit of port D specified by register Y.
Note:
(Y) = 0 to 5.
Do not execute this instruction if values except above are set to register Y.
RT (ReTurn from subroutine)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
0
1
0
0
2
0
4
4
16
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
–
–
Grouping:
Return operation
Description: Returns from subroutine to the routine
called the subroutine.
RTI (ReTurn from Interrupt)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
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1
1
0
2
0
4
6
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Return operation
Description: Returns from interrupt service routine to
main routine.
Returns each value of data pointer (X, Y, Z),
carry flag, skip status, NOP mode status by
the continuous description of the LA/LXY instruction, register A and register B to the
states just before interrupt.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RTS (ReTurn from subroutine and Skip)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
0
1
0
1
2
0
4
5
16
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
–
Skip at uncondition
Grouping:
Return operation
Description: Returns from subroutine to the routine
called the subroutine, and skips the next instruction at uncondition.
RUPT (Reset UPT flag)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
1
0
0
0
2
0
5
8
16
(UPTF) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Clears (0) to the high-order bit reference
enable flag UPTF.
SB j (Set Bit)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
1
1
j
j
2
0
5
C
+j 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Bit operation
Description: Sets (1) the contents of bit j (bit specified by
the value j in the immediate field) of M(DP).
(Mj(DP)) ← 0
j = 0 to 3
SC (Set Carry flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
1
2
0
0
7
16
Number of
cycles
Flag CY
Skip condition
1
1
1
–
Grouping:
Arithmetic operation
Description: Sets (1) to carry flag CY.
(CY) ← 1
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Number of
words
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4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SD (Set port D specified by register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
1
0
1
2
0
1
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Sets (1) to a bit of port D specified by register Y.
Note:
(Y) = 0 to 5.
Do not execute this instruction if values except above are set to register Y.
(D(Y)) ← 1
(Y) = 0 to 5
SEA n (Skip Equal, Accumulator with immediate data n)
Instruction
code
0
0
Operation:
D0
D9
0
0
0
0
0
1
1
1
0
0
1
n
1
n
0
n
1
2
n 2
0
0
2
7
(A) = n ?
n = 0 to 15
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
(A) = n
n 16
Grouping:
Comparison operation
Description: Skips the next instruction when the contents of register A is equal to the value n in
the immediate field.
Executes the next instruction when the contents of register A is not equal to the value n
in the immediate field.
SEAM (Skip Equal, Accumulator with Memory)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
0
1
1
0
2
0
2
6
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(A) = (M(DP))
Grouping:
Comparison operation
Description: Skips the next instruction when the contents of register A is equal to the contents of
M(DP).
Executes the next instruction when the contents of register A is not equal to the
contents of M(DP).
(A) = (M(DP)) ?
SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
0
0
0
2
V10 = 0: (EXF0) = 1 ?
(EXF0) ← 0
V10 = 1: SNZ0 = NOP
(V10 : bit 0 of the interrupt control register V1)
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0
3
8
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V10 = 0: (EXF0) = 1
Grouping:
Interrupt operation
Description: When V10 = 0 : Clears (0) to the EXF0 flag
and skips the next instruction when external
0 interrupt request flag EXF0 is “1.” When
the EXF0 flag is “0,” executes the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZAD (Skip if Non Zero condition of A/D conversion completion flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
1
1
1
2
2
8
7
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V22 = 0: (ADF) = 1
16
Grouping:
A/D conversion operation
Description: When V22 = 0 : Clears (0) to the ADF flag
and skips the next instruction when A/D
conversion completion flag ADF is “1.” After
skipping, . When the ADF flag is “0,” executes the next instruction.
When V22 = 1 : This instruction is equivalent to the NOP instruction.
V22 = 0: (ADF) = 1 ?
(ADF) ← 0
V22 = 1: SNZAD = NOP
(V22 : bit 2 of the interrupt control register V2)
SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
0
1
0 2
0
3
A 16
Number of
words
Number of
cycles
Flag CY
1
1
–
Skip condition
I12 = 0 : (INT) = “L”
I12 = 1 : (INT) = “H”
Grouping:
Interrupt operation
Description: When I12 = 0 : Skips the next instruction
when the level of INT pin is “L.” Executes
the next instruction when the level of INT
pin is “H.”
When I12 = 1 : Skips the next instruction
when the level of INT pin is “H.” Executes
the next instruction when the level of INT
pin is “L.”
I12 = 0 : (INT) = “L” ?
I12 = 1 : (INT) = “H” ?
(I12 : bit 2 of the interrupt control register I1)
SNZP (Skip if Non Zero condition of Power down flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
0
1
1
2
0
0
3
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(P) = 1
Grouping:
Other operation
Description: Skips the next instruction when the P flag is
“1”.
After skipping, the P flag remains unchanged.
Executes the next instruction when the P
flag is “0.”
(P) = 1 ?
SNZSI (Skip if Non Zero condition of Serial Interface interrupt request flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
1
V23=0: (SIOF)=1?
(SIOF) ← 0
V23 = 1: SNZSI = NOP
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0
0
0
2
2
8
8
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V23 = 0: (SIOF) =1
Grouping:
Serial interface operation
Description: Clears (0) to SIOF flag and skips the next
instruction when the contents of bit 3 (V23)
of interrupt control register V2 is “0” and
contents of SIOF flag is “1.”
When V23 = 1: This instruction is equivalent
to the NOP instruction.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
0
0
0
2
2
8
0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V12 = 0: (T1F) = 1
16
Grouping:
Timer operation
Description: When V1 2 = 0 : Clears (0) to the T1F flag
and skips the next instruction when timer 1
interrupt request flag T1F is “1.” When the
T1F flag is “0,” executes the next instruction.
When V12 = 1 : This instruction is equivalent to the NOP instruction.
V12 = 0: (T1F) = 1 ?
(T1F) ← 0
V12 = 1: SNZT1 = NOP
(V12 = bit 2 of interrupt control register V1)
SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)
Instruction
code
Operation:
D0
D9
1
0
1
0
0
0
0
0
0
1
2
2
8
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V13 = 0: (T2F) = 1
Grouping:
Timer operation
Description: When V1 3 = 0 : Clears (0) to the T2F flag
and skips the next instruction when timer 2
interrupt request flag T2F is “1.” When the
T2F flag is “0,” executes the next instruction.
When V13 = 1 : This instruction is equivalent to the NOP instruction.
V13 = 0: (T2F) = 1 ?
(T2F) ← 0
V13 = 1: SNZT2 = NOP
(V13 = bit 3 of interrupt control register V1)
SRST (System ReSet)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
0
0
1
2
0
0
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: System reset occurs.
System reset
SST (Serial interface transmission/reception STart)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
1
1
0
(SIOF) ← 0
Serial interface transmit/receive starting
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2
2
9
E
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Serial interface operation
Description: Clears (0) to SIOF flag and starts serial interface.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SUPT (Set UPT flag)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
1
0
0
1
2
0
5
9 16
(UPTF) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Sets (1) to the high-order bit reference enable flag UPTF. When the table reference
instruction (TABP p) is executed, the highorder 2 bits of ROM reference data is
transferred to the low-order 2 bits of register D.
SVDE (Set Voltage Detector Enable flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
0
0
1
1
2
2
9
3 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Validates the voltage drop detection circuit
at RAM back-up.
Note:
This instruction can be executed only for
the H version.
Voltage drop detection circuit valid at RAM back-up
SZB j (Skip if Zero, Bit)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
0
0
j
j
2
0
2
j
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Mj(DP)) = 0
j = 0 to 3
Grouping:
Bit operation
Description: Skips the next instruction when the contents of bit j (bit specified by the value j in
the immediate field) of M(DP) is “0.”
Executes the next instruction when the contents of bit j of M(DP) is “1.”
(Mj(DP)) = 0 ?
j = 0 to 3
SZC (Skip if Zero, Carry flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
1
1
1
2
0
2
F
16
Number of
cycles
Flag CY
Skip condition
1
1
–
(CY) = 0
Grouping:
Arithmetic operation
Description: Skips the next instruction when the contents of carry flag CY is “0.”
After skipping, the CY flag remains unchanged.
Executes the next instruction when the contents of the CY flag is “1.“
(CY) = 0 ?
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Number of
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4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZD (Skip if Zero, port D specified by register Y)
Instruction
code
Operation:
D9
D0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
1
0
1
1 2
2
0
2
4 16
0
2
B 16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
(D(Y)) = 0
(Y) = 0 to 5
Grouping:
Input/Output operation
Description: Skips the next instruction when a bit of port
D specified by register Y is “0.” Executes the
next instruction when the bit is “1.”
Note:
(Y) = 0 to 5.
Do not execute this instruction if values except above are set to register Y.
(D(Y)) = 0 ?
(Y) = 0 to 5
T1AB (Transfer data to timer 1 and register R1L from Accumulator and register B)
Instruction
code
Operation:
D0
D9
1
0
0
0
1
1
0
0
0
0
2
2
3
0 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 1 and timer 1 reload register R1L. Transfers the contents of
register A to the low-order 4 bits of timer 1
and timer 1 reload register R1L.
(R1L7–R1L4) ← (B)
(T17–T14) ← (B)
(R1L3–R1L0) ← (A)
(T13–T10) ← (A)
T1HAB (Transfer data to register R1H from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
0
0
1
0
2
2
9
2
16
(R1H7–R1H4) ← (B)
(R1H3–R1H0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 1 reload register
R1H. Transfers the contents of register A to
the low-order 4 bits of timer 1 reload register R1H.
T1R1L (Transfer data to timer 1 from register R1L)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
0
0
(T17–T10) ← (R1L7–R1L0)
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1
1
1
2
2
A
7
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer 1 reload
register R1L to timer 1.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
0
0
0
1
2
2
3
1 16
(R2L7–R2L4) ← (B)
(T27–T24) ← (B)
(R2L3–R2L0) ← (A)
(T23–T20) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 2 and timer 2 reload register R2L. Transfers the contents of
register A to the low-order 4 bits of timer 2
and timer 2 reload register R2L.
T2HAB (Transfer data to register R2H from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
0
1
0
0
2
2
9
4 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 2 reload register
R2H. Transfers the contents of register A to
the low-order 4 bits of timer 2 reload register R2H.
(R2H7–R2H4) ← (B)
(R2H3–R2H0) ← (A)
T2R2L (Transfer data to timer 2 from register R2L)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
0
1
0
1
2
2
9
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer 2 reload
register R2L to timer 2.
(T27–T20) ← (R2L7–R2L0)
TAB (Transfer data to Accumulator from register B)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
1
0
2
0
1
E
16
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register B to register A.
(A) ← (B)
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4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
0
0
0
0
2
2
7
0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(B) ← (T17–T14)
(A) ← (T13–T10)
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T17–T14) of
timer 1 to register B.
Transfers the low-order 4 bits (T13–T10) of
timer 1 to register A.
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruction
code
Operation:
D0
D9
1
0
0
1
1
1
0
0
0
1
2
2
7
1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(B) ← (T27–T24)
(A) ← (T23–T20)
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T27–T24) of
timer 2 to register B.
Transfers the low-order 4 bits (T23–T20) of
timer 2 to register A.
TABAD (Transfer data to Accumulator and register B from register AD)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
1
0
0
1
2
2
7
9
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
Grouping:
A/D conversion operation
Description: In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register
AD to register B, and the middle-order 4 bits
(AD5–AD2) of register AD to register A. In the
comparator mode (Q13 = 1), transfers the highorder 4 bits (AD7–AD4) of comparator register
to register B, and the low-order 4 bits (AD3–
AD0) of comparator register to register A.
In A/D conversion mode (Q13 = 0),
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
In comparator mode (Q13 = 1),
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
(Q13 : bit 3 of A/D control register Q1)
TABE (Transfer data to Accumulator and register B from register E)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
1
(B) ← (E7–E4)
(A) ← (E3–E0)
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0
1
0
2
0
2
A
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the high-order 4 bits (E 7–E4 ) of
register E to register B, and low-order 4 bits
of register E to register A.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction
code
Operation:
D9
0
D0
0
1
0
0
p4 p3 p2 p1 p0
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(UPTF) ← 1
(DR1, DR0) ← (ROM(PC))9, 8
(DR2) ← 0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
2
0
Grouping:
8
+p
p 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
3
–
–
Arithmetic operation
Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7
to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified
by registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the
low-order 2 bits (DR1, DR0) of register D, and “0” is stored to the least
significant bit (DR2) of register D.
When this instruction is executed, 1 stage of stack register (SK) is used.
Note:
p is 0 to 31.
When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used.
TABPS (Transfer data to Accumulator and register B from Pre-Scaler)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
0
1
0
1
2
2
7
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the high-order 4 bits of prescaler
to register B.
Transfers the low-order 4 bits of prescaler to
register A.
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
TABSI (Transfer data to Accumulator and register B from register SI)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
1
0
0
0
2
2
7
8
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Serial interface operation
Description: Transfers the high-order 4 bits of serial interface register SI to register B, and transfers
the low-order 4 bits of serial interface register SI to register A.
(B) ← (SI7–SI4) (A) ← (SI3–SI0)
TAD (Transfer data to Accumulator from register D)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
(A2–A0) ← (DR2–DR0)
(A3) ← 0
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0
0
1
2
0
5
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register D to the
low-order 3 bits (A2–A0) of register A.
Note:
When this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TADAB (Transfer data to register AD from Accumulator from register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
1
0
0
1
2
2
3
9
16
Q13 = 1: (AD7–AD4) ← (B)
(AD3–AD0) ← (A)
Q13 = 0: TADAB = NOP
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: In the comparator mode (Q13 = 1), transfers
the contents of register B to the high-order 4
bits (AD7–AD4) of comparator register, and
the contents of register A to the low-order 4
bits (AD3–AD0) of comparator register.
In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction.
(Q13 = bit 3 of A/D control register Q1)
TAI1 (Transfer data to Accumulator from register I1)
Instruction
code
Operation:
D0
D9
1
0
0
1
0
1
0
0
1
1
2
2
5
3
16
(A) ← (I1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register I1 to register A.
TAJ1 (Transfer data to Accumulator from register J1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
0
0
1
0
2
2
4
2
16
(A) ← (J1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Serial interface operation
Description: Transfers the contents of serial interface
control register J1 to register A.
TAK0 (Transfer data to Accumulator from register K0)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
(A) ← (K0)
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1
1
0
2
2
5
6
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K0 to register A.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAK1 (Transfer data to Accumulator from register K1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
1
0
0
1
2
2
5
9
16
(A) ← (K1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K1 to register A.
TAK2 (Transfer data to Accumulator from register K2)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
1
0
1
0
2
2
5
A
16
(A) ← (K2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K2 to register A.
TAL1 (Transfer data to Accumulator from register L1)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
1
0
1
0
2
2
4
A
16
(A) ← (L1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register L1 to register A.
TALA (Transfer data to Accumulator from register LA)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
(A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
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0
0
1
2
2
4
9
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the low-order 2 bits (AD1, AD0) of
register AD to the high-order 2 bits (A3, A2)
of register A. “0” is stored to the low-order 2
bits (A1, A0) of register A.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAM j (Transfer data to Accumulator from Memory)
Instruction
code
Operation:
D9
1
D0
0
1
1
0
0
j
j
j
j
2
2
C
j
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After transferring the contents of M(DP) to
register A, an exclusive OR operation is
performed between register X and the value
j in the immediate field, and stores the result in register X.
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
TAMR (Transfer data to Accumulator from register MR)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
0
1
0
2
2
5
2
16
(A) ← (MR)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Clock operation
Description: Transfers the contents of clock control register MR to register A.
TAPU0 (Transfer data to Accumulator from register PU0)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
1
1
1
2
2
5
7
16
(A) ← (PU0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of pull-up control
register PU0 to register A.
TAPU1 (Transfer data to Accumulator from register PU1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
1
(A) ← (PU1)
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1
1
0
2
2
5
E
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of pull-up control
register PU1 to register A.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAPU2 (Transfer data to Accumulator from register PU2)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
1
1
1
1
2
2
5
F
16
(A) ← (PU2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of pull-up control
register PU2 to register A.
TAQ1 (Transfer data to Accumulator from register Q1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
0
1
0
0
2
2
4
4
16
(A) ← (Q1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of A/D control register Q1 to register A.
TASP (Transfer data to Accumulator from Stack Pointer)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
0
0
0
2
0
5
0
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of stack pointer (SP)
to the low-order 3 bits (A2–A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
(A2–A0) ← (SP2–SP0)
(A3) ← 0
TAV1 (Transfer data to Accumulator from register V1)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
(A) ← (V1)
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1
0
0
2
0
5
4
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register V1 to register A.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAV2 (Transfer data to Accumulator from register V2)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
1
0
1
2
0
5
5
16
(A) ← (V2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register V2 to register A.
TAW1 (Transfer data to Accumulator from register W1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
0
1
1
2
2
4
B
16
(A) ← (W1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W1 to register A.
TAW2 (Transfer data to Accumulator from register W2)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
1
0
0
2
2
4
C
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W2 to register A.
(A) ← (W2)
TAW5 (Transfer data to Accumulator from register W5)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
(A) ← (W5)
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1
1
1
2
2
4
F
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W5 to register A.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAW6 (Transfer data to Accumulator from register W6)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
0
0
0
2
2
5
0
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W6 to register A.
(A) ← (W6)
TAX (Transfer data to Accumulator from register X)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
0
1
0
2
0
5
2
16
(A) ← (X)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register X to register A.
TAY (Transfer data to Accumulator from register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
1
1
1
2
0
1
F
16
(A) ← (Y)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register Y to register A.
TAZ (Transfer data to Accumulator from register Z)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
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0
1
1
2
0
5
3 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register Z to the
low-order 2 bits (A1, A0) of register A. “0” is
stored to the high-order 2 bits (A 3, A2 ) of
register A.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TBA (Transfer data to register B from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
1
1
0
2
0
0
E
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
Grouping:
Register to register transfer
Description: Transfers the contents of register A to register B.
(B) ← (A)
TC1A (Transfer data to register C1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
0
1
0
0
0
2
2
A
8
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
Grouping:
Input/Output operation
Description: Transfers the contents of register A to port
output structure control register C1.
(C1) ← (A)
TDA (Transfer data to register D from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
1
0
0
1
2
0
2
9
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(DR2–DR0) ← (A2–A0)
Grouping:
Register to register transfer
Description: Transfers the contents of the low-order 3
bits (A2–A0) of register A to register D.
TEAB (Transfer data to register E from Accumulator and register B)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
(E7–E4) ← (B)
(E3–E0) ← (A)
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0
1
0
2
0
1
A
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register B to the
high-order 4 bits (E3–E0) of register E, and
the contents of register A to the low-order 4
bits (E3–E0) of register E.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TFR0A (Transfer data to register FR0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
0
0
0
2
2
2
8
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to port
output structure control register FR0.
(FR0) ← (A)
TFR1A (Transfer data to register FR1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
0
0
1
2
2
2
9
16
(FR1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to port
output structure control register FR1.
TFR2A (Transfer data to register FR2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
0
1
0
2
2
2
A
16
(FR2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to port
output structure control register FR2.
TFR3A (Transfer data to register FR3 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
(FR3) ← (A)
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0
1
1
2
2
2
B
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to port
output structure control register FR3.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TI1A (Transfer data to register I1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
1
1
1
2
2
1
7
16
(I1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register I1.
TJ1A (Transfer data to register J1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
0
0
1
0
2
2
0
2
16
(J1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Serial interface operation
Description: Transfers the contents of register A to serial
interface control register J1.
TK0A (Transfer data to register K0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
1
0
1
1
2
2
1
B
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register K0.
(K0) ← (A)
TK1A (Transfer data to register K1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
(K1) ← (A)
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1
0
0
2
2
1
4
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register K1.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TK2A (Transfer data to register K2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
1
0
1
2
2
1
5
16
(K2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register K2.
TL1A (Transfer data to register L1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
1
0
1
0
2
2
0
A
16
(L1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register L1.
TMA j (Transfer data to Memory from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
1
j
j
j
j
2
2
B
j
16
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After transferring the contents of register A
to M(DP), an exclusive OR operation is performed between register X and the value j
in the immediate field, and stores the result
in register X.
TMRA (Transfer data to register MR from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
(MR) ← (A)
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1
1
0
2
2
1
6
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Clock operation
Description: Transfers the contents of register A to clock
control register MR.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TPAA (Transfer data to register PA from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
0
1
0
1
0
2
2
A
A
16
(PA0) ← (A0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the least significant bit of register
A to timer control register PA.
TPSAB (Transfer data to Pre-Scaler and register RPS from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
0
1
0
1
2
2
3
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of prescaler and prescaler
reload register RPS. Transfers the contents
of register A to the low-order 4 bits of
prescaler and prescaler reload register
RPS.
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
TPU0A (Transfer data to register PU0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
1
0
1
2
2
2
D
16
(PU0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pullup control register PU0.
TPU1A (Transfer data to register PU1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
(PU1) ← (A)
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1
1
0
2
2
2
E
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pullup control register PU1.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TPU2A (Transfer data to register PU2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
1
1
1
2
2
2
F
16
(PU2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pullup control register PU2.
TQ1A (Transfer data to register Q1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
0
1
0
0
2
2
0
4
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of register A to A/D
control register Q1.
(Q1) ← (A)
TRGA (Transfer data to register RG from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
1
0
0
1
2
2
0
9
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Clock operation
Description: Transfers the least significant bit (A0) of
register A to clock control regiser RG.
(RG0) ← (A0)
TSIAB (Transfer data to register SI from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
1
0
(SI7–SI4) ← (B) (SI3–SI0) ← (A)
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0
0
2
2
3
8
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Serial interface operation
Description: Transfers the contents of register B to the
high-order 4 bits of serial interface register
SI, and transfers the contents of register A
to the low-order 4 bits of serial interface
register SI.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TV1A (Transfer data to register V1 from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
1
1
1
2
0
3
F
16
(V1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register V1.
TV2A (Transfer data to register V2 from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
1
1
0 2
0
3
E 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register V2.
(V2) ← (A)
TW1A (Transfer data to register W1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
1
1
1
0
2
2
0
E
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W1.
(W1) ← (A)
TW2A (Transfer data to register W2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
1
(W2) ← (A)
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REJ03B0147-0102
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1
1
1
2
2
0
F
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W2.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TW5A (Transfer data to register W5 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
0
1
0
2
2
1
2
16
(W5) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W5.
TW6A (Transfer data to register W6 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
0
1
1 2
2
1
3 16
(W6) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W6.
TYA (Transfer data to register Y from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
1
0
0
2
0
0
C
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register A to register Y.
(Y) ← (A)
WRST (Watchdog timer ReSeT)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
0
0
(WDF1) = 1 ?
(WDF1) ← 0
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0
0
0
2
2
A
0
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(WDF1) = 1
Grouping:
Other operation
Description: Clears (0) to the WDF1 flag and skips the
next instruction when watchdog timer flag
WDF1 is “1.” When the WDF1 flag is “0,” executes the next instruction. Also, stops the
watchdog timer function when executing the
WRST instruction immediately after the
DWDT instruction.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
XAM j (eXchange Accumulator and Memory data)
Instruction
code
Operation:
D9
1
D0
0
1
1
0
1
j
j
j
j
2
2
D
j
16
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instruction
code
Operation:
D9
1
D0
0
1
1
1
1
j
j
j
j
2
2
F
j
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 15
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Instruction
code
Operation:
D9
1
D0
0
1
1
1
0
j
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
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j
j
j
2
2
E
j
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 0
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of
register Y is 0, the next instruction is
skipped. When the contents of register Y is
not 0, the next instruction is executed.
4509 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES)
Number of
words
Number of
cycles
Instruction code
TAB
0
0
0
0
0
1
1
1
1
0
0 1 E
1
1
(A) ← (B)
TBA
0
0
0
0
0
0
1
1
1
0
0 0 E
1
1
(B) ← (A)
TAY
0
0
0
0
0
1
1
1
1
1
0 1 F
1
1
(A) ← (Y)
TYA
0
0
0
0
0
0
1
1
0
0
0 0 C
1
1
(Y) ← (A)
TEAB
0
0
0
0
0
1
1
0
1
0
0 1 A
1
1
(E7–E4) ← (B)
(E3–E0) ← (A)
TABE
0
0
0
0
1
0
1
0
1
0
0 2 A
1
1
(B) ← (E7–E4)
(A) ← (E3–E0)
TDA
0
0
0
0
1
0
1
0
0
1
0 2 9
1
1
(DR2–DR0) ← (A2–A0)
TAD
0
0
0
1
0
1
0
0
0
1
0 5 1
1
1
(A2–A0) ← (DR2–DR0)
(A3) ← 0
TAZ
0
0
0
1
0
1
0
0
1
1
0 5 3
1
1
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
TAX
0
0
0
1
0
1
0
0
1
0
0 5 2
1
1
(A) ← (X)
TASP
0
0
0
1
0
1
0
0
0
0
0 5 0
1
1
(A2–A0) ← (SP2–SP0)
(A3) ← 0
LXY x, y
1
1
x3 x2 x1 x0 y3 y2 y1 y0
3 x y
1
1
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
LZ z
0
0
0
1
0
0
1
0
z1 z0
0 4 8
+z
1
1
(Z) ← z z = 0 to 3
INY
0
0
0
0
0
1
0
0
1
1
0 1 3
1
1
(Y) ← (Y) + 1
DEY
0
0
0
0
0
1
0
1
1
1
0 1 7
1
1
(Y) ← (Y) – 1
TAM j
1
0
1
1
0
0
j
j
j
j
2 C j
1
1
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAM j
1
0
1
1
0
1
j
j
j
j
2 D j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAMD j
1
0
1
1
1
1
j
j
j
j
2 F j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
XAMI j
1
0
1
1
1
0
j
j
j
j
2 E j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
1
0
1
0
1
1
j
j
j
j
2 B j
1
1
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Parameter
Mnemonic
RAM to register transfer
RAM addresses
Register to register transfer
Type of
instructions
D9 D8 D7 D6 D 5 D 4 D 3 D 2 D 1 D 0
Rev.1.02 2006.12.22
REJ03B0147-0102
page 116 of 140
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4509 Group
–
–
Transfers the contents of register B to register A.
–
–
Transfers the contents of register A to register B.
–
–
Transfers the contents of register Y to register A.
–
–
Transfers the contents of register A to register Y.
–
–
Transfers the contents of register B to the high-order 4 bits (E7–E4) of register E, and the contents of register A to the low-order 4 bits (E3–E0) of register E.
–
–
Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits of register E to register A.
–
–
Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D.
–
–
Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
–
–
Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A.
“0” is stored to the high-order 2 bits (A3, A2) of register A.
–
–
Transfers the contents of register X to register A.
–
–
Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
Continuous
description
–
Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y.
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
–
–
Loads the value z in the immediate field to register Z.
(Y) = 0
–
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.
(Y) = 15
–
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
–
–
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
–
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
(Y) = 0
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed.
–
–
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Rev.1.02 2006.12.22
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Datailed description
page 117 of 140
4509 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Arithmetic operation
Bit operation
operation
Comparison
D9 D8 D7 D6 D 5 D 4 D 3 D 2 D 1 D 0
n
0 7 n
1
1
(A) ← n
n = 0 to 15
0
0
1
1
1
TABP p
0
0
1
0
0
p4 p3 p2 p1 p0
0 8 p
+p
1
3
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(UPTF) = 1
(DR1, DR0) ← (ROM(PC))9, 8
(DR2) ← 0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
AM
0
0
0
0
0
0
1
0
1
0
0 0 A
1
1
(A) ← (A) + (M(DP))
AMC
0
0
0
0
0
0
1
0
1
1
0 0 B
1
1
(A) ← (A) + (M(DP)) +(CY)
(CY) ← Carry
An
0
0
0
1
1
0
n
n
n
n
0 6 n
1
1
(A) ← (A) + n
n = 0 to 15
AND
0
0
0
0
0
1
1
0
0
0
0 1 8
1
1
(A) ← (A) AND (M(DP))
OR
0
0
0
0
0
1
1
0
0
1
0 1 9
1
1
(A) ← (A) OR (M(DP))
SC
0
0
0
0
0
0
0
1
1
1
0 0 7
1
1
(CY) ← 1
RC
0
0
0
0
0
0
0
1
1
0
0 0 6
1
1
(CY) ← 0
SZC
0
0
0
0
1
0
1
1
1
1
0 2 F
1
1
(CY) = 0 ?
CMA
0
0
0
0
0
1
1
1
0
0
0 1 C
1
1
(A) ← (A)
RAR
0
0
0
0
0
1
1
1
0
1
0 1 D
1
1
→ CY → A3A2A1A0
SB j
0
0
0
1
0
1
1
1
j
j
0 5 C
+j
1
1
(Mj(DP)) ← 1
j = 0 to 3
RB j
0
0
0
1
0
0
1
1
j
j
0 4 C
+j
1
1
(Mj(DP)) ← 0
j = 0 to 3
SZB j
0
0
0
0
1
0
0
0
j
j
0 2 j
1
1
(Mj(DP)) = 0 ?
j = 0 to 3
SEAM
0
0
0
0
1
0
0
1
1
0
0 2 6
1
1
(A) = (M(DP)) ?
SEA n
0
0
0
0
1
0
0
1
0
1
0 2 5
2
2
(A) = n ?
n = 0 to 15
0
0
0
1
1
1
n
n
n
n
0 7 n
page 118 of 140
n
Function
0
Rev.1.02 2006.12.22
REJ03B0147-0102
n
Hexadecimal
LA n
Note : p is 0 to 31.
n
notation
Number of
cycles
Mnemonic
Type of
instructions
Number of
words
Instruction code
Parameter
Skip condition
Carry flag CY
4509 Group
Datailed description
Continuous
description
–
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed and
other LA instructions coded continuously are skipped.
–
–
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When UPTF is 1, Transfers bits
9, 8 to the low-order 2 bits (DR1, DR0) of register D, and “0” is stored to the least significant bit (DR2) of register D.
When this instruction is executed, 1 stage of stack register (SK) is used.
–
–
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
–
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
Overflow = 0
–
Adds the value n in the immediate field to register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
Executes the next instruction when there is overflow as the result of operation.
–
–
Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A.
–
–
Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result
in register A.
–
1
Sets (1) to carry flag CY.
–
0
Clears (0) to carry flag CY.
(CY) = 0
–
Skips the next instruction when the contents of carry flag CY is “0.”
–
–
Stores the one’s complement for register A’s contents in register A.
–
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
–
–
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
–
–
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
(Mj(DP)) = 0
j = 0 to 3
–
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of
M(DP) is “0.”
Executes the next instruction when the contents of bit j of M(DP) is “1.”
(A) = (M(DP))
–
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
Executes the next instruction when the contents of register A is not equal to the contents of M(DP).
(A) = n
n = 0 to 15
–
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
Executes the next instruction when the contents of register A is not equal to the value n in the immediate
field.
Rev.1.02 2006.12.22
REJ03B0147-0102
page 119 of 140
4509 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
Ba
0
1
1
a6 a5 a4 a3 a2 a1 a0
1 8 a
+a
1
1
(PCL) ← a6–a0
BL p, a
0
0
1
1
p4 p3 p2 p1 p0
0 E p
+p
2
2
(PCH) ← p (Note)
(PCL) ← a6–a0
1
0
0
a6 a5 a4 a3 a2 a1 a0
2 a a
0
0
0
0
0
1
0
0 1 0
2
2
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
1
0
0
p4 0
0
p3 p2 p1 p0
2 p p
BM a
0
1
0
a6 a5 a4 a3 a2 a1 a0
1 a a
1
1
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
BML p, a
0
0
1
1
p4 p3 p2 p1 p0
0 C p
+p
2
2
1
0
0
a6 a5 a4 a3 a2 a1 a0
2 a a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← a6–a0
0
0
0
0
1
1
0
0 3 0
2
2
1
0
0
p4 0
0
p3 p2 p1 p0
2 p p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0,A3–A0)
RTI
0
0
0
1
0
0
0
1
1
0
0 4 6
1
1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RT
0
0
0
1
0
0
0
1
0
0
0 4 4
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
0
0
0
1
0
0
0
1
0
1
0 4 5
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Parameter
Mnemonic
Return operation
Subroutine operation
Branch operation
Type of
instructions
D9 D8 D7 D6 D 5 D 4 D 3 D 2 D 1 D 0
BLA p
BMLA p
1
0
Note : p is 0 to 31.
Rev.1.02 2006.12.22
REJ03B0147-0102
page 120 of 140
0
0
0
0
0
0
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4509 Group
–
–
Branch within a page : Branches to address a in the identical page.
–
–
Branch out of a page : Branches to address a in page p.
–
–
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in
page p.
–
–
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
–
–
Call the subroutine : Calls the subroutine at address a in page p.
–
–
Call the subroutine : Calls the subroutine at address (DR 2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D
and A in page p.
–
–
Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt.
–
–
Returns from subroutine to the routine called the subroutine.
Skip at uncondition
–
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
Rev.1.02 2006.12.22
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Datailed description
page 121 of 140
4509 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
DI
0
0
0
0
0
0
0
1
0
0
0 0 4
1
1
(INTE) ← 0
EI
0
0
0
0
0
0
0
1
0
1
0 0 5
1
1
(INTE) ← 1
SNZ0
0
0
0
0
1
1
1
0
0
0
0 3 8
1
1
V10 = 0: (EXF0) = 1 ?
(EXF0) ← 0
V10 = 1: SNZ0 = NOP
SNZI0
0
0
0
0
1
1
1
0
1
0
0 3 A
1
1
I12 = 0 : (INT) = “L” ?
Parameter
Mnemonic
Timer operation
Interrupt operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal
notation
Function
I12 = 1 : (INT) = “H” ?
TAV1
0
0
0
1
0
1
0
1
0
0
0 5 4
1
1
(A) ← (V1)
TV1A
0
0
0
0
1
1
1
1
1
1
0 3 F
1
1
(V1) ← (A)
TAV2
0
0
0
1
0
1
0
1
0
1
0 5 5
1
1
(A) ← (V2)
TV2A
0
0
0
0
1
1
1
1
1
0
0 3 E
1
1
(V2) ← (A)
TAI1
1
0
0
1
0
1
0
0
1
1
2 5 3
1
1
(A) ← (I1)
TI1A
1
0
0
0
0
1
0
1
1
1
2 1 7
1
1
(I1) ← (A)
TPAA
1
0
1
0
1
0
1
0
1
0
2 A A
1
1
(PA0) ← (A0)
TAW1
1
0
0
1
0
0
1
0
1
1
2 4 B
1
1
(A) ← (W1)
TW1A
1
0
0
0
0
0
1
1
1
0
2 0 E
1
1
(W1) ← (A)
TAW2
1
0
0
1
0
0
1
1
0
0
2 4 C
1
1
(A) ← (W2)
TW2A
1
0
0
0
0
0
1
1
1
1
2 0 F
1
1
(W2) ← (A)
TAW5
1
0
0
1
0
0
1
1
1
1
2 4 F
1
1
(A) ← (W5)
TW5A
1
0
0
0
0
1
0
0
1
0
2 1 2
1
1
(W5) ← (A)
TAW6
1
0
0
1
0
1
0
0
0
0
2 5 0
1
1
(A) ← (W6)
TW6A
1
0
0
0
0
1
0
0
1
1
2 1 3
1
1
(W6) ← (A)
TABPS
1
0
0
1
1
1
0
1
0
1
2 7 5
1
1
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
TPSAB
1
0
0
0
1
1
0
1
0
1
2 3 5
1
1
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
TAB1
1
0
0
1
1
1
0
0
0
0
2 7 0
1
1
(B) ← (T17–T14)
(A) ← (T13–T10)
T1AB
1
0
0
0
1
1
0
0
0
0
2 3 0
1
1
(R1L7–R1L4) ← (B)
(T17–T14) ← (B)
(R1L3–R1L0) ← (A)
(T13–T10) ← (A)
T1HAB
1
0
1
0
0
1
0
0
1
0
2 9 2
1
1
(R1H7–R1H4) ← (B)
(R1H3–R1H0) ← (A)
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REJ03B0147-0102
page 122 of 140
Skip condition
Carry flag CY
4509 Group
–
–
Clears (0) to interrupt enable flag INTE, and disables the interrupt.
–
–
Sets (1) to interrupt enable flag INTE, and enables the interrupt.
V10 = 0: (EXF0) = 1
–
When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request
flag EXF0 is “1.” When the EXF0 flag is “0,” executes the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register
V1)
(INT) = “L”
However, I12 = 0
–
When I12 = 0 : Skips the next instruction when the level of INT pin is “L.” Executes the next instruction when
the level of INT pin is “H.”
(INT) = “H”
However, I12 = 1
Datailed description
When I12 = 1 : Skips the next instruction when the level of INT pin is “H.” Executes the next instruction when
the level of INT pin is “L.” (I12: bit 2 of interrupt control register I1)
–
–
Transfers the contents of interrupt control register V1 to register A.
–
–
Transfers the contents of register A to interrupt control register V1.
–
–
Transfers the contents of interrupt control register V2 to register A.
–
–
Transfers the contents of register A to interrupt control register V2.
–
–
Transfers the contents of interrupt control register I1 to register A.
–
–
Transfers the contents of register A to interrupt control register I1.
–
–
Transfers the contents of register A to timer control register PA.
–
–
Transfers the contents of timer control register W1 to register A.
–
–
Transfers the contents of register A to timer control register W1.
–
–
Transfers the contents of timer control register W2 to register A.
–
–
Transfers the contents of register A to timer control register W2.
–
–
Transfers the contents of timer control register W5 to register A.
–
–
Transfers the contents of register A to timer control register W5.
–
–
Transfers the contents of timer control register W6 to register A.
–
–
Transfers the contents of register A to timer control register W6.
–
–
Transfers the high-order 4 bits of prescaler to register B.
Transfers the low-order 4 bits of prescaler to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS.
Transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS.
–
–
Transfers the high-order 4 bits (T17–T14) of timer 1 to register B.
Transfers the low-order 4 bits (T13–T10) of timer 1 to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1L.
Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1L.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1H. Transfers the
contents of register A to the low-order 4 bits of timer 1 reload register R1H.
Rev.1.02 2006.12.22
REJ03B0147-0102
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4509 Group
Number of
words
Number of
cycles
Instruction code
TAB2
1
0
0
1
1
1
0
0
0
1
2 7 1
1
1
(B) ← (T27–T24)
(A) ← (T23–T20)
T2AB
1
0
0
0
1
1
0
0
0
1
2 3 1
1
1
(R2L7–R2L4) ← (B)
(T27–T24) ← (B)
(R2L3–R2L0) ← (A)
(T23–T20) ← (A)
T2HAB
1
0
1
0
0
1
0
1
0
0
2 9 4
1
1
(R2H7–R2H4) ← (B)
(R2H3–R2H0) ← (A)
T1R1L
1
0
1
0
1
0
0
1
1
1
2 A 7
1
1
(T1) ← (R1L)
T2R2L
1
0
1
0
0
1
0
1
0
1
2 9 5
1
1
(T2) ← (R2L)
SNZT1
1
0
1
0
0
0
0
0
0
0
2 8 0
1
1
V12 = 0: (T1F) = 1 ?
(T1F) ← 0
V12 = 1: SNZT1 = NOP
SNZT2
1
0
1
0
0
0
0
0
0
1
2 8 1
1
1
V13 = 0: (T2F) = 1 ?
(T2F) ← 0
V13 = 1: SNZT2 = NOP
IAP0
1
0
0
1
1
0
0
0
0
0
2 6 0
1
1
(A) ← (P0)
OP0A
1
0
0
0
1
0
0
0
0
0
2 2 0
1
1
(P0) ← (A)
IAP1
1
0
0
1
1
0
0
0
0
1
2 6 1
1
1
(A) ← (P1)
OP1A
1
0
0
0
1
0
0
0
0
1
2 2 1
1
1
(P1) ← (A)
IAP2
1
0
0
1
1
0
0
0
1
0
2 6 2
1
1
(A1, A0) ← (P21, P20)
(A3, A2) ← 0
OP2A
1
0
0
0
1
0
0
0
1
0
2 2 2
1
1
(P21, P20) ← (A1, A0)
IAP3
1
0
0
1
1
0
0
0
1
1
2 6 3
1
1
(A1, A0) ← (P31, P30)
(A3, A2) ← 0
OP3A
1
0
0
0
1
0
0
0
1
1
2 2 3
1
1
(P31, P30) ← (A1, A0)
CLD
0
0
0
0
0
1
0
0
0
1
0 1 1
1
1
(D) ← 1
RD
0
0
0
0
0
1
0
1
0
0
0 1 4
1
1
(D(Y)) ← 0
(Y) = 0 to 5
SD
0
0
0
0
0
1
0
1
0
1
0 1 5
1
1
(D(Y)) ← 1
(Y) = 0 to 5
SZD
0
0
0
0
1
0
0
1
0
0
0 2 4
2
2
(D(Y)) = 0 ?
(Y) = 0 to 5
0
0
0
0
1
0
1
0
1
1
0 2 B
Parameter
Mnemonic
Input/Output operation
Timer operation
Type of
instructions
D9 D8 D7 D6 D 5 D 4 D 3 D 2 D 1 D 0
Rev.1.02 2006.12.22
REJ03B0147-0102
page 124 of 140
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4509 Group
–
–
Transfers the high-order 4 bits (T27–T24) of timer 2 to register B.
Transfers the low-order 4 bits (T23–T20) of timer 2 to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2L. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2L.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 2 reload register R2H. Transfers the contents of register A to the low-order 4 bits of timer 2 reload register R2H.
–
–
Transfers the contents of timer 1 reload register R1L to timer 1.
–
–
Transfers the contents of timer 2 reload register R2L to timer 2.
V12 = 0: (T1F) = 1
–
When V12 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag
T1F is “1.” . When the T1F flag is “0,” executes the next instruction.
When V12 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1)
V13 = 0: (T2F) =1
–
When V13 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag
T2F is “1.” When the T2F flag is “0,” executes the next instruction.
When V13 = 1 : This instruction is equivalent to the NOP instruction. (V13: bit 3 of interrupt control register V1)
–
–
Transfers the input of port P0 to register A.
–
–
Outputs the contents of register A to port P0.
–
–
Transfers the input of port P1 to register A.
–
–
Outputs the contents of register A to port P1.
–
–
Transfers the input of port P2 to the low-order 2 bits (A1, A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
–
–
Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P2.
–
–
Transfers the input of port P3 to the low-order 2 bits (A1, A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
–
–
Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P3.
–
–
Sets (1) to port D.
–
–
Clears (0) to a bit of port D specified by register Y.
–
–
Sets (1) to a bit of port D specified by register Y.
(D(Y)) = 0 ?
–
Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction
when a bit of port D specified by register Y is “1.”
Rev.1.02 2006.12.22
REJ03B0147-0102
Datailed description
page 125 of 140
4509 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
TFR0A
1
0
0
0
1
0
1
0
0
0
2 2 8
1
1
(FR0) ← (A)
TFR1A
1
0
0
0
1
0
1
0
0
1
2 2 9
1
1
(FR1) ← (A)
TFR2A
1
0
0
0
1
0
1
0
1
0
2 2 A
1
1
(FR2) ← (A)
TFR3A
1
0
0
0
1
0
1
0
1
1
2 2 B
1
1
(FR3) ← (A)
TC1A
1
0
1
0
1
0
1
0
0
0
2 A 8
1
1
(C1) ← (A)
TK0A
1
0
0
0
0
1
1
0
1
1
2 1 B
1
1
(K0) ← (A)
TAK0
1
0
0
1
0
1
0
1
1
0
2 5 6
1
1
(A) ← (K0)
TK1A
1
0
0
0
0
1
0
1
0
0
2 1 4
1
1
(K1) ← (A)
TAK1
1
0
0
1
0
1
1
0
0
1
2 5 9
1
1
(A) ← (K1)
TK2A
1
0
0
0
0
1
0
1
0
1
2 1 5
1
1
(K2) ← (A)
TAK2
1
0
0
1
0
1
1
0
1
0
2 5 A
1
1
(A) ← (K2)
TPU0A
1
0
0
0
1
0
1
1
0
1
2 2 D
1
1
(PU0) ← (A)
TAPU0
1
0
0
1
0
1
0
1
1
1
2 5 7
1
1
(A) ← (PU0)
TPU1A
1
0
0
0
1
0
1
1
1
0
2 2 E
1
1
(PU1) ← (A)
TAPU1
1
0
0
1
0
1
1
1
1
0
2 5 E
1
1
(A) ← (PU1)
TPU2A
1
0
0
0
1
0
1
1
1
1
2 2 F
1
1
(PU2) ← (A)
TAPU2
1
0
0
1
0
1
1
1
1
1
2 5 F
1
1
(A) ← (PU2)
TL1A
1
0
0
0
0
0
1
0
1
0
2 0 A
1
1
(L1) ← (A)
TAL1
1
0
0
1
0
0
1
0
1
0
2 4 A
1
1
(A) ← (L1)
TABSI
1
0
0
1
1
1
1
0
0
0
2 7 8
1
1
(B) ← (SI7–SI4) (A) ← (SI3–SI0)
TSIAB
1
0
0
0
1
1
1
0
0
0
2 3 8
1
1
(SI7–SI4) ← (B) (SI3–SI0) ← (A)
SST
1
0
1
0
0
1
1
1
1
0
2 9 E
1
1
(SIOF) ← 0
Serial interface transmit/receive starting
SNZSI
1
0
1
0
0
0
1
0
0
0
2 8 8
1
1
V23=0: (SIOF)=1?
(SIOF) ← 0
V23 = 1: SNZSI = NOP
TAJ1
1
0
0
1
0
0
0
0
1
0
2 4 2
1
1
(A) ← (J1)
TJ1A
1
0
0
0
0
0
0
0
1
0
2 0 2
1
1
(J1) ← (A)
CRCK
1
0
1
0
0
1
1
0
1
1
2 9 B
1
1
RC oscillator selected
TRGA
1
0
0
0
0
0
1
0
0
1
2 0 9
1
1
(RG0) ← (A0)
TAMR
1
0
0
1
0
1
0
0
1
0
2 5 2
1
1
(A) ← (MR)
TMRA
1
0
0
0
0
1
0
1
1
0
2 1 6
1
1
(MR) ← (A)
Parameter
Mnemonic
Clock
operation
Serial interface operation
Input/Output operation
Type of
instructions
D9 D8 D7 D6 D 5 D 4 D 3 D 2 D 1 D 0
Rev.1.02 2006.12.22
REJ03B0147-0102
page 126 of 140
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4509 Group
–
–
Transfers the contents of register A to port output structure control register FR0.
–
–
Transfers the contents of register A to port output structure control register FR1.
–
–
Transfers the contents of register A to port output structure control register FR2.
–
–
Transfers the contents of register A to port output structure control register FR3.
–
–
Transfers the contents of register A to port output structure control register C1.
–
–
Transfers the contents of register A to key-on wakeup control register K0.
–
–
Transfers the contents of key-on wakeup control register K0 to register A.
–
–
Transfers the contents of register A to key-on wakeup control register K1.
–
–
Transfers the contents of key-on wakeup control register K1 to register A.
–
–
Transfers the contents of register A to key-on wakeup control register K2.
–
–
Transfers the contents of key-on wakeup control register K2 to register A.
–
–
Transfers the contents of register A to pull-up control register PU0.
–
–
Transfers the contents of pull-up control register PU0 to register A.
–
–
Transfers the contents of register A to pull-up control register PU1.
–
–
Transfers the contents of pull-up control register PU1 to register A.
–
–
Transfers the contents of register A to pull-up control register PU2.
–
–
Transfers the contents of pull-up control register PU2 to register A.
–
–
Transfers the contents of register A to key-on wakeup control register L1.
–
–
Transfers the contents of key-on wakeup control register L1 to register A.
–
–
Transfers the high-order 4 bits of serial interface register SI to register B, and transfers the low-order 4 bits
of serial interface register SI to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of serial interface register SI, and transfers the
contents of register A to the low-order 4 bits of serial interface register SI.
–
–
Clears (0) to SIOF flag and starts serial interface transmit/receive.
V23 = 0: (SIOF) =1
–
Clears (0) to SIOF flag and skips the next instruction when the contents of bit 3 (V23) of interrupt control register V2 is “0” and contents of SIOF flag is “1.” When V23 = 1: This instruction is equivalent to the NOP
instruction.
–
–
Transfers the contents of serial interface control register J1 to register A.
–
–
Transfers the contents of register A to serial interface control register J1.
–
–
Selects the RC oscillation circuit for main clock f(XIN).
–
–
Transfers the least significant bit (A0) of register A to clock control regiser RG.
–
–
Transfers the contents of clock control regiser MR to register A.
–
–
Transfers the contents of register A to clock control register MR.
Rev.1.02 2006.12.22
REJ03B0147-0102
Datailed description
page 127 of 140
4509 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
TABAD
1
0
0
1
1
1
1
0
0
1
2 7 9
1
1
Q13 = 0:
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
Q13 = 1:
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
TALA
1
0
0
1
0
0
1
0
0
1
2 4 9
1
1
(A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
TADAB
1
0
0
0
1
1
1
0
0
1
2 3 9
1
1
Q13 = 0:
(AD7–AD4) ← (B)
(AD3–AD0) ← (A)
Q13 = 1: TADAB = NOP
TAQ1
1
0
0
1
0
0
0
1
0
0
2 4 4
1
1
(A) ← (Q1)
TQ1A
1
0
0
0
0
0
0
1
0
0
2 0 4
1
1
(Q1) ← (A)
ADST
1
0
1
0
0
1
1
1
1
1
2 9 F
1
1
(ADF) ← 0
Q13 = 0: A/D conversion starting
Q13 = 1: Comparator operation starting
SNZAD
1
0
1
0
0
0
0
1
1
1
2 8 7
1
1
V22 = 0: (ADF) = 1 ?
(ADF) ← 0
V22 = 1: SNZAD = NOP
NOP
0
0
0
0
0
0
0
0
0
0
0 0 0
1
1
(PC) ← (PC) + 1
POF
0
0
0
0
0
0
0
0
1
0
0 0 2
1
1
RAM back-up
EPOF
0
0
0
1
0
1
1
0
1
1
0 5 B
1
1
POF instruction valid
SNZP
0
0
0
0
0
0
0
0
1
1
0 0 3
1
1
(P) = 1 ?
DWDT
1
0
1
0
0
1
1
1
0
0
2 9 C
1
1
Stop of watchdog timer function enabled
WRST
1
0
1
0
1
0
0
0
0
0
2 A 0
1
1
(WDF1) = 1 ?,
(WDF1) ← 0
SRST
0
0
0
0
0
0
0
0
0
1
0 0 1
1
1
System reset
RUPT
0
0
0
1
0
1
1
0
0
0
0 5 8
1
1
(UPTF) ← 0
SUPT
0
0
0
1
0
1
1
0
0
1
0 5 9
1
1
(UPTF) ← 1
SVDE**
1
0
1
0
0
1
0
0
1
1
2 9 3
1
1
Voltage drop detection circuit valid at RAM
back-up
Parameter
Mnemonic
Other operation
A/D conversion operation
Type of
instructions
D9 D8 D7 D6 D 5 D 4 D 3 D 2 D 1 D 0
Note: The SVDE instruction can be used only in the H version.
Rev.1.02 2006.12.22
REJ03B0147-0102
page 128 of 140
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4509 Group
–
–
In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register
B, and the middle-order 4 bits (AD5–AD2) of register AD to register A.
In the comparator mode (Q13 = 1), transfers the high-order 4 bits (AD7–AD4) of comparator register to register B, and the low-order 4 bits (AD3–AD0) of comparator register to register A.
(Q13: bit 3 of A/D control register Q1)
–
–
Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (A3, A2) of register A.
“0” is stored to the least significant bit (A0) of register A.
–
–
In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of
comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register.
In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction.
(Q13 = bit 3 of A/D control register Q1)
–
–
Transfers the contents of A/D control register Q1 to register A.
–
–
Transfers the contents of register A to A/D control register Q1.
–
–
Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13
= 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
(Q13 = bit 3 of A/D control register Q1)
V22 = 0: (ADF) = 1
–
When V22 = 0 : Clears (0) to the ADF flag and skips the next instruction when A/D conversion completion
flag ADF is “1.” When the ADF flag is “0,” executes the next instruction.
When V22 = 1 : This instruction is equivalent to the NOP instruction. (V22: bit 2 of interrupt control register V2)
–
–
No operation; Adds 1 to program counter value, and others remain unchanged.
–
–
Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction.
Operations of all functions are stopped.
–
–
Makes the immediate after POF instruction valid by executing the EPOF instruction.
(P) = 1
–
Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
Executes the next instruction when the P flag is “0.”
–
–
Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
(WDF1) = 1
–
Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1.” When the
WDF1 flag is “0,” executes the next instruction. Also, stops the watchdog timer function when executing the
WRST instruction immediately after the DWDT instruction.
–
–
System reset occurs.
–
–
Clears (0) to the high-order bit reference enable flag UPTF.
–
–
Sets (1) to the high-order bit reference enable flag UPTF.
–
–
Validates the voltage drop detection circuit at RAM back-up (only for the H version).
Rev.1.02 2006.12.22
REJ03B0147-0102
Datailed description
page 129 of 140
4509 Group
INSTRUCTION CODE TABLE
D9–D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011 001100 001101 001110 001111
010000 011000
010111 011111
Hex.
D3–D0 notation
00
01
BLA
02
03
04
05
06
07
SZB
BMLA
0
–
TASP
A
0
LA
0
SZB
1
–
–
TAD
A
1
SZB
2
–
–
TAX
SZB
3
–
–
RT
08
09
0A
0B
0C
0D
0E
0F
10–17 18–1F
TABP TABP
0
16
–
–
BML
BML
BL
BL
BM
B
LA
1
TABP TABP
1
17
–
–
BML
BML
BL
BL
BM
B
A
2
LA
2
TABP TABP
2
18
–
–
BML
BML
BL
BL
BM
B
TAZ
A
3
LA
3
TABP TABP
3
19
–
–
BML
BML
BL
BL
BM
B
TAV1
A
4
LA
4
TABP TABP
4
20
–
–
BML
BML
BL
BL
BM
B
0000
0
NOP
0001
1
SRST CLD
0010
2
0011
3
0100
4
DI
RD
SZD
–
0101
5
EI
SD
SEAn
–
RTS TAV2
A
5
LA
5
TABP TABP
5
21
–
–
BML
BML
BL
BL
BM
B
0110
6
RC
–
SEAM
–
RTI
–
A
6
LA
6
TABP TABP
6
22
–
–
BML
BML
BL
BL
BM
B
0111
7
SC
DEY
–
–
–
–
A
7
LA
7
TABP TABP
7
23
–
–
BML
BML
BL
BL
BM
B
1000
8
–
AND
–
SNZ0
LZ
0
RUPT
A
8
LA
8
TABP TABP
8
24
–
–
BML
BML
BL
BL
BM
B
1001
9
–
OR
TDA
–
LZ
1
SUPT
A
9
LA
9
TABP TABP
9
25
–
–
BML
BML
BL
BL
BM
B
1010
A
AM
TEAB TABE SNZI0
LZ
2
–
A
10
LA
10
TABP TABP
10
26
–
–
BML
BML
BL
BL
BM
B
1011
B
AMC
–
–
–
LZ
3
EPOF
A
11
LA
11
TABP TABP
11
27
–
–
BML
BML
BL
BL
BM
B
1100
C
TYA
CMA
–
–
RB
0
SB
0
A
12
LA
12
TABP TABP
12
28
–
–
BML
BML
BL
BL
BM
B
1101
D
–
RAR
–
–
RB
1
SB
1
A
13
LA
13
TABP TABP
13
29
–
–
BML
BML
BL
BL
BM
B
1110
E
TBA
TAB
–
TV2A
RB
2
SB
2
A
14
LA
14
TABP TABP
14
30
–
–
BML
BML
BL
BL
BM
B
1111
F
–
TAY
SZC TV1A
RB
3
SB
3
A
15
LA
15
TABP TABP
15
31
–
–
BML
BML
BL
BL
BM
B
POF
–
SNZP INY
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is
shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BLA
BMLA
SEA
SZD
The second word
10 0aaa aaaa
10 0aaa aaaa
10 0p00 pppp
10 0p00 pppp
00 0111 nnnn
00 0010 1011
Rev.1.02 2006.12.22
REJ03B0147-0102
page 130 of 140
4509 Group
INSTRUCTION CODE TABLE (continued)
D9–D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111
110000
111111
Hex.
D3–D0 notation
20
21
22
23
24
0000
0
–
–
OP0A T1AB
–
0001
1
–
–
OP1A T2AB
–
0010
2
0011
3
0100
4
0101
5
–
0110
6
0111
TJ1A TW5A OP2A
–
25
26
27
28
TAW6 IAP0 TAB1 SNZT1
–
IAP1 TAB2 SNZT2
TAJ1 TAMR IAP2
29
2A
2B
2C
2D
2E
2F
30–3F
–
WRST
TMA
0
TAM XAM XAMI XAMD LXY
0
0
0
0
–
–
TMA
1
TAM XAM XAMI XAMD LXY
1
1
1
1
–
–
T1HAB
–
TMA
2
TAM XAM XAMI XAMD LXY
2
2
2
2
–
–
TAI1
IAP3
–
–
SVDE*
–
TMA
3
TAM XAM XAMI XAMD LXY
3
3
3
3
–
–
TAQ1
–
–
–
–
T2HAB
–
TMA
4
TAM XAM XAMI XAMD LXY
4
4
4
4
TK2A
–
TPSAB
–
–
–
TABPS
–
T2R2L
–
TMA
5
TAM XAM XAMI XAMD LXY
5
5
5
5
–
TMRA
–
–
–
TAK0
–
–
–
–
–
TMA
6
TAM XAM XAMI XAMD LXY
6
6
6
6
7
–
TI1A
–
–
–
TAPU0
–
–
SNZAD
–
T1R1L
TMA
7
TAM XAM XAMI XAMD LXY
7
7
7
7
1000
8
–
–
TFR0A TSIAB
–
–
–
TABSI SNZSI
–
TC1A
TMA
8
TAM XAM XAMI XAMD LXY
8
8
8
8
1001
9
TRGA
–
TFR1ATADAB TALA TAK1
–
TABAD
–
–
–
TMA
9
TAM XAM XAMI XAMD LXY
9
9
9
9
1010
A
TL1A
–
TFR2A
–
TAL1 TAK2
–
–
–
–
TPAA
TMA
10
TAM XAM XAMI XAMD LXY
10
10
10
10
1011
B
–
TK0A TFR3A
–
TAW1
–
–
–
–
CRCK
–
TMA
11
TAM XAM XAMI XAMD LXY
11
11
11
11
1100
C
–
–
–
–
TAW2
–
–
–
–
DWDT
–
TMA
12
TAM XAM XAMI XAMD LXY
12
12
12
12
1101
D
–
–
TPU0A
–
–
–
–
–
–
–
–
TMA
13
TAM XAM XAMI XAMD LXY
13
13
13
13
1110
E
TW1A
–
TPU1A
–
–
TAPU1
–
–
–
SST
–
TMA
14
TAM XAM XAMI XAMD
LXY
14
14
14
14
1111
F
TW2A
–
TPU2A
–
TAW5 TAPU2
–
–
–
ADST
–
TMA
15
TAM XAM XAMI XAMD LXY
15
15
15
15
–
TW6A OP3A
TQ1A TK1A
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the loworder 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of
each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BLA
BMLA
SEA
SZD
The second word
10 0aaa aaaa
10 0aaa aaaa
10 0p00 pppp
10 0p00 pppp
00 0111 nnnn
00 0010 1011
Rev.1.02 2006.12.22
REJ03B0147-0102
• * can be used only in the H version.
page 131 of 140
4509 Group
Electrical characteristics
Absolute maximum ratings
Symbol
VDD
VI
Parameter
Conditions
–
Supply voltage
Input voltage P0, P1, P2, P3, D0–D5,
–
Ratings
–0.3 to 6.5
–0.3 to VDD+0.3
Unit
V
V
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
V
V
V
–0.3 to VDD+0.3
–0.3 to VDD+0.3
300
–20 to 85
–40 to 125
V
V
mW
°C
°C
RESET, XIN
VI
VI
Input voltage INT, CNTR0, CNTR1, SIN, SCK
Input voltage AIN0–AIN5
VO
Output voltage P0, P1, P2, P3, D 0–D5,
–
–
Output transistors in cut-off state
RESET
VO
Output voltage CNTR0, CNTR1, SOUT, SCK
VO
Output voltage XOUT
Pd
Topr
Power dissipation
Operating temperature range
Tstg
Storage temperature range
Rev.1.02 2006.12.22
REJ03B0147-0102
page 132 of 140
Output transistors in cut-off state
–
Ta = 25 °C
–
–
4509 Group
Recommended operating conditions 1
(Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Symbol
VDD
VDD
Parameter
Limits
Conditions
Min.
Typ.
Max.
Unit
Supply voltage
f(STCK) ≤ 6 MHz
4
5.5
(with a ceramic resonator)
f(STCK) ≤ 4.4 MHz
2.7
5.5
f(STCK) ≤ 2.2 MHz
f(STCK) ≤ 1.1 MHz
2.0
1.8
5.5
5.5
f(STCK) ≤ 4.4 MHz
2.7
5.5
V
1.8
5.5
V
5.5
V
Supply voltage
V
(with RC oscillation)
VDD
Supply voltage
(with an on-chip oscillator)
VRAM
VSS
RAM back-up voltage
Supply voltage
(at RAM back-up)
VIH
“H” level input voltage
P0, P1, P2, P3, D0–D5
1.6
0
VDD
RESET
0.85VDD
VDD
INT, CNTR0, CNTR1, SIN, SCK
0.85VDD
VDD
P0, P1, P2, P3, D0–D5
XIN
0
0
0.2VDD
0.3VDD
RESET
0
0
0.15VDD
XIN
VIL
“L” level input voltage
INT, CNTR0, CNTR1, SIN, SCK
IOH(peak)
IOH(avg)
IOL(peak)
“H” level peak output current
“H” level average output current
(Note)
“L” level peak output current
ΣIOH(avg)
ΣIOL(avg)
“H” level total average current
“L” level total average current
page 133 of 140
0.3VDD
VDD = 5.0 V
–20
VDD = 3.0 V
–10
P0, P1, P2, P3, D0–D5
CNTR0, CNTR1, SOUT, SCK
VDD = 5.0 V
–10
–5
mA
VDD = 3.0 V
P0, P1
VDD = 5.0 V
24
mA
CNTR0, CNTR1, SOUT, SCK
VDD = 3.0 V
VDD = 5.0 V
12
VDD = 3.0 V
VDD = 5.0 V
4.0
40
VDD = 3.0 V
30
VDD = 5.0 V
24
12
P0, P1
VDD = 3.0 V
VDD = 5.0 V
CNTR0, CNTR1, SOUT, SCK
VDD = 3.0 V
P2, P3, RESET
VDD = 5.0 V
6.0
5.0
VDD = 3.0 V
2.0
D 0, D1 , D4, D 5
VDD = 5.0 V
30
VDD = 3.0 V
VDD = 5.0 V
15
D 2, D 3
VDD = 3.0 V
7.0
–40
P0, P1, P3, CNTR0, CNTR1, SOUT, SCK
P2, D0–D5
mA
10
D 2, D 3
12
mA
15
mA
–40
P0, P1, P3, CNTR0, CNTR1, SOUT, SCK
60
P2, D0–D5, RESET
60
Notes 1: The average output current (IOH, IOL) is the average value during 100 ms.
Rev.1.02 2006.12.22
REJ03B0147-0102
V
CNTR0, CNTR1, SOUT, SCK
D 0, D1 , D4, D 5
“L” level average output current
V
P0, P1, P2, P3, D0–D5
P2, P3, RESET
IOL(avg)
V
VDD
0.8VDD
0.7VDD
mA
4509 Group
Recommended operating conditions 2
(Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Symbol
Parameter
Conditions
Oscillation frequency
f(XIN)
Through mode
(with a ceramic resonator)
Internal frequency divided
by 2
Min.
Limits
Typ.
VDD = 4.0 V to 5.5 V
Max.
6
VDD = 2.7 V to 5.5 V
4.4
VDD = 2.0 V to 5.5 V
2.2
VDD = 1.8 V to 5.5 V
1.1
f(XIN)
Oscillation frequency
(with RC oscillation) (Note 1)
VDD = 2.7 V to 5.5 V
f(XIN)
Oscillation frequency
Through mode
f(CNTR)
4.4
2.2
VDD = 2.0 V to 5.5 V
6
VDD = 1.8 V to 5.5 V
4.4
4.4
MHz
MHz
(with a ceramic oscillation selected,
VDD = 2.7 V to 5.5 V
4.8
3.2
external clock input)
VDD = 2.0 V to 5.5 V
1.6
VDD = 1.8 V to 5.5 V
0.8
Internal frequency divided
VDD = 2.7 V to 5.5 V
4.8
by 2
VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
3.2
Internal frequency divided
VDD = 2.0 V to 5.5 V
by 4, 8
CNTR0, CNTR1
VDD = 1.8 V to 5.5 V
Timer external input frequency
VDD = 4.0 V to 5.5 V
CNTR0, CNTR1
tw(CNTR) Timer external input period
(“H” and “L” pulse width)
f(SCK)
tw(SCK)
Serial interface external input period
SCK
Serial interface external input period
SCK
TPON
Power-on reset circuit
MHz
6
VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
Internal frequency divided
by 4, 8
Unit
1.6
4.8
3/f(STCK)
3.2
f(STCK)/6 Hz
s
3/f(STCK)
f(STCK)/6 Hz
s
(“H” and “L” pulse width)
VDD = 0 → 1.8 V
µs
100
valid supply voltage rising time (Note 2)
Notes 1: The frequency at RC oscillation is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
2: If the rising time exceeds the maximum rating value, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level
to RESET pin until the value of supply voltage reaches the minimum operating voltage.
When ceramic resonator is used
When RC oscillation is used
f(STCK)
[MHz]
When external clock is used
f(STCK)
[MHz]
f(STCK)
[MHz]
6
4.8
4.4
4.4
3.2
2.2
1.6
1.1
Recommended
operating condition
Recommended
operating condition
1.8
2
2.7
4
5.5
VDD
[V]
2.7
System clock (STCK) operating condition map
Rev.1.02 2006.12.22
REJ03B0147-0102
Recommended
operating condition
0.8
page 134 of 140
5.5
VDD
[V]
1.8
2
2.7
4
5.5
VDD
[V]
4509 Group
Electrical characteristics 1
Symbol
VOH
(Ta = –20 °C to 85 °C, V DD = 1.8 to 5.5 V, unless otherwise noted)
Parameter
“H” level output voltage
P0, P1, P2, P3, D0–D5
CNTR0, CNTR1, SOUT, SCK
VOL
“L” level output voltage
Test conditions
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
P0, P1
VOL
V
IOH = –5.0 mA
2.1
IOH = –1.0 mA
2.4
IOL = 12 mA
2.0
IOL = 4.0 mA
0.9
0.9
“L” level output voltage
VDD = 5.0 V
IOL = 5.0 mA
0.6
2.0
IOL = 1.0 mA
0.6
VDD = 3.0 V
IOL = 2.0 mA
0.9
VDD = 5.0 V
IOL = 30 mA
2.0
0.9
VDD = 3.0 V
IOL = 10 mA
IOL = 15 mA
“L” level output voltage
“L” level output voltage
VDD = 5.0 V
VDD = 3.0 V
“H” level input current
P0, P1, P2, P3, D0–D5
Unit
4.1
IOL = 6.0 mA
IOL = 2.0 mA
D 2 , D3
IIH
Max.
VDD = 3.0 V
D 0 , D1, D 4, D5
VOL
Typ.
CNTR0, CNTR1, SOUT, SCK
P2, P3, RESET
VOL
IOH = –10 mA
IOH = –3.0 mA
Limits
Min.
3.0
IOL = 5.0 mA
2.0
0.9
IOL = 15 mA
2.0
IOL = 5.0 mA
0.9
IOL = 9.0 mA
1.4
IOL = 3.0 mA
0.9
V
V
V
V
VI = VDD
2.0
µA
VI = 0 V P0, P1, P2, D2, D3 No pull-up
–2.0
µA
60
125
kΩ
120
250
RESET, INT
CNTR0, CNTR1, SIN, SCK
IIL
“L” level input current
P0, P1, P2, P3, D0–D5
RESET, INT
CNTR0, CNTR1, SIN, SCK
RPU
Pull-up resistor value
VI = 0 V
VT+ – VT– Hysteresis RESET
VT+ – VT– Hysteresis INT, CNTR0, CNTR1
SIN, SCK
f(RING)
On-chip oscillator clock frequency
∆ f(XIN)
VDD = 5.0 V
VDD = 3.0 V
P0, P1, P2, D2, D3, RESET
VDD = 5.0 V
1.0
VDD = 3.0 V
0.4
VDD = 5.0 V
0.2
0.2
VDD = 3.0 V
VDD = 5.0 V
V
200
100
500
700
250
400
VDD = 1.8 V
30
120
200
Notes 1: When the RC oscillation is used, use a 33 pF capacitor externally.
page 135 of 140
V
VDD = 3.0 V
VDD = 5.0 V ± 10 %, Ta = center 25 °C
Oscillation frequency error
(Note 1)
(at RC oscillation, error value of external VDD = 3.0 V ± 10 %, Ta = center 25 °C
R, C not included)
Rev.1.02 2006.12.22
REJ03B0147-0102
30
50
±17
±17
kHz
%
4509 Group
Electrical characteristics 2
Symbol
IDD
(Ta = –20 °C to 85 °C, V DD = 1.8 to 5.5 V, unless otherwise noted)
Parameter
Supply current
at active mode
Test conditions
VDD = 5.0 V
(with a ceramic resonator) f(XIN) = 6.0 MHz
f(RING) = stop
(Notes 1, 2)
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
Typ.
1.2
Max.
1.3
2.6
3.2
1.6
2.2
VDD = 5.0 V
f(STCK) = f(XIN)/8
0.9
1.8
f(XIN) = 4.0 MHz
f(STCK) = f(XIN)/4
1
2
f(RING) = stop
f(STCK) = f(XIN)/2
1.2
2.4
1.6
VDD = 3.0 V
f(STCK) = f(XIN)
f(STCK) = f(XIN)/8
3.2
0.4
VDD = 5.0 V
(with an on-chip oscillator) f(XIN) = stop
f(RING) = operating
(Notes 1, 2)
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
0.3
f(STCK) = f(XIN)
0.4
0.8
f(STCK) = f(RING)/8
50
100
f(STCK) = f(RING)/4
f(STCK) = f(RING)/2
60
120
160
VDD = 3.0 V
f(STCK) = f(RING)/8
10
20
f(XIN) = stop
f(STCK) = f(RING)/4
13
26
f(RING) = opertaing
f(STCK) = f(RING)/2
19
38
f(STCK) = f(RING)
31
62
3
at RAM back-up mode
(POF instruction execution)
(Note 3)
VDD = 5.0 V
VDD = 3.0 V
page 136 of 140
mA
mA
0.6
80
120
0.1
mA
0.5
f(STCK) = f(RING)
Ta = 25 °C
Unit
4.4
0.2
0.25
Notes 1: When the A/D converter is used, the A/D operation current (IADD) is included.
2: In the M34509G4H, the voltage drop detection circuit operation current (IRST) is added.
3: In the M34509G4H, when the SVDE instruction is executed, the voltage drop detection circuit operation current (IRST) is added.
Rev.1.02 2006.12.22
REJ03B0147-0102
2.4
f(STCK) = f(XIN)
f(XIN) = 2.0 MHz
f(RING) = stop
at active mode
f(STCK) = f(XIN)/8
Limits
Min.
µA
240
10
6
µA
µA
4509 Group
A/D converter recommended operating conditions
(Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
Parameter
VDD
Supply voltage
VIA
Analog input voltage
f(ADCK)
A/D clock frequency (Note)
Conditions
Min.
Limits
Typ.
Max.
5.5
Ta = 0 °C to 50 °C
2.0
Ta = –20 °C to 85 °C
2.7
5.5
0
VDD
0.8
334
VDD = 2.2 V to 5.5 V
0.8
0.8
123
61.2
VDD = 2.0 V to 5.5 V
0.8
15.3
VDD = 4.0 V to 5.5 V
VDD = 2.7 V to 5.5 V
Unit
V
V
kHz
Note: Definition of A/D conversion clock (ADCK)
Division circuit
Divided by 8
Divided by 4
On-chip oscillator
MR0
Divided by 2
1
Ceramic resonance
XIN
Multiplexer
RC oscillation
0
f(ADCK)
[kHz]
334
123
61.2
A/D clock
recommended
operating condition
15.3
0.8
2 2.2
2.7
4
5.5
VDD
[V]
A/D clock (ADCK) operating condition map
Rev.1.02 2006.12.22
REJ03B0147-0102
page 137 of 140
MR3, MR2
11
10
01
00
System clock (STCK)
Instruction clock (INSTCK)
Internal clock
generating circuit
(divided by 3)
A/D clock
generating circuit
(divided by 6)
A/D conversion
clock (ADCK)
4509 Group
A/D converter characteristcs
(Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
Parameter
–
–
Resolution
–
Differential non-linearity error
V0T
Zero transition voltage
Test conditions
Full-scale transition voltage
Absolute accuracy
Max.
10
±4.0
Ta = –20 °C to 85 °C, 2.7 V ≤ VDD ≤ 5.5 V
±2.0
VDD = 2.56 V
7.5
±0.9
±0.9
15
7.5
15
Ta = 0 °C to 50 °C, 2.2 V ≤ VDD < 2.7 V
Ta = –20 °C to 85 °C, 2.7 V ≤ VDD ≤ 5.5 V
VDD = 3.075 V
–
Limits
Typ.
Ta = 0 °C to 50 °C, 2.2 V ≤ VDD 0 °C 2.7 V
Linearity error
VFST
Min.
0
0
VDD = 5.12 V
0
10
20
VDD = 2.56 V
2552.5
2560
VDD = 3.075 V
VDD = 5.12 V
3064.5
3072
5110
2567.5
3079.5
Ta = 0 °C to 50 °C, 2.0 V ≤ VDD < 2.2 V
5100
Unit
bits
LSB
LSB
mV
mV
5120
±8.0
LSB
µA
(Quantization error excluded)
IADD
A/D operating current (Note 1)
TCONV
–
–
A/D conversion time
Comparator resolution
Comparator error (Note 2)
VDD = 5.0 V
300
900
VDD = 3.0 V
100
300
f(ADCK) = 334 kHz
f(ADCK) = 123 kHz
f(ADCK) = 61.2 kHz
85
169
f(ADCK) = 15.3 kHz
676
VDD = 2.56 V
± 15
± 15
± 20
8
VDD = 3.072 V
VDD = 5.12 V
–
Comparator comparison time
31
f(ADCK) = 334 kHz
4
f(ADCK) = 123 kHz
11
f(ADCK) = 61.2 kHz
22
f(ADCK) = 15.3 kHz
88
µs
bits
mV
µs
Notes 1: When the A/D converter is used, the IADD is included to IDD.
2: As for the error from the logic value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison
voltage Vref which is generated by the built-in DA converter can be obtained by the following formula.
Logic value of comparison voltage Vref
Vref =
VDD
256
✕n
n = Value of register AD (n = 0 to 255)
Rev.1.02 2006.12.22
REJ03B0147-0102
page 138 of 140
4509 Group
VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS
(Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
VRST–
Test conditions
Parameter
Detection voltage
Ta = 25 °C
(reset occurs) (Note 2)
-20 °C ≤ Ta < 0 °C
0 °C ≤ Ta < 50 °C
Min.
2.5
50 °C ≤ Ta ≤ 85 °C
VRST+
Detection voltage
Ta = 25 °C
(reset release) (Note 3)
-20 °C
Max.
V
2.2
3
2
2.7
50 °C ≤ Ta ≤ 85 °C
V
3.2
3.1
2.6
2.3
2.1
Detection voltage hysteresis
Unit
3.1
2.7
≤ Ta < 0 °C
0 °C ≤ Ta < 50 °C
VRST+ –
Limits
Typ.
2.6
2.8
0.1
V
VRST–
IRST
TRST
Operation current (Note 4)
Detection time (Note 5)
VDD = 5 V
50
100
µA
VDD = 3 V
30
0.2
60
1.2
ms
VDD → (VRST– – 0.1 V)
Notes 1: The voltage drop detection circuit is equipped with only the M34509G4H.
2: The detection voltage (VRST–) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.
3: The detection voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset occurs.
4: In the M34509G4H, IRST is added to IDD (supply current).
5: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST– – 0.1 V].
Basic timing diagram
Machine cycle
Parameter
Pin name
System clock
STCK
Port output
D0–D5
P00–P03
P10–P13
P20, P21
P30, P31
Port input
D0–D5
P00–P03
P10–P13
P20, P21
P30, P31
Interrupt input
INT
Rev.1.02 2006.12.22
REJ03B0147-0102
page 139 of 140
Mi
Mi+1
4509 Group
Package outline
JEITA Package Code
RENESAS Code
Previous Code
MASS[Typ.]
P-SSOP24-5.3x10.1-0.80
PRSP0024GA-A
24P2Q-A
0.2g
E
13
*1
HE
24
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
F
1
12
Index mark
*2
c
A2
A1
D
Reference
Symbol
Dimension in Millimeters
Min
Nom
Max
D
10.0
10.1
10.2
E
5.2
5.3
5.4
A2
1.8
L
A
A
e
*3
y
bp
2.1
A1
0
0.1
0.2
bp
0.3
0.35
0.45
c
0.18
0.2
0.25
8.1
0°
Detail F
8°
HE
7.5
7.8
e
0.65
0.8
y
L
Rev.1.02 2006.12.22
REJ03B0147-0102
page 140 of 140
0.95
0.10
0.4
0.6
0.8
4509 Group Data Sheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
1.00 Mar. 18, 2005
–
First edition issued
1.01 Aug. 12, 2005
17
52
57
58
ROM Code Protect Address added.
Table 20: Some description about Port P1 added.
Fig.52 revised.
Fig.54 revised.
“DATA REQUIRED FOR QzROM WRITING ORDERS” added.
Notes On ROM Code Protect added.
A/D converter characteristics:
Linearity error, Differential non-linearity error and Absolute accuracy
→ Parameters and Test conditions revised.
Voltage drop detection circuit characteristics: VRST-, VRST+ → Test conditions revised.
MULFUNCTION: Note 4 revised.
TIMER: Description revised and Structure of Timer 2 in Table 9 revised.
Fig.23: INSTCK (wrong) → INTSNC (correct)
(2) Prescaler: PRS → RPS
(3) Timer 3 → Timer 1
SERIAL I/O: Table 14: Note revised.
Fig. 46: Notes revised.
Table 23: Changes referring ahead and note 5 added.
QzROM Writing Mode added.
LIST OF PRECAUTIONS: Mulfunction revised.
NOTES ON NOISE added.
Description of Port output structure control register FR2 and FR3 revised.
Instruction code of TAL1 revised. Description of TALA revised.
Detailed description of TEAB revised.
f(SCK): Serial interface external input frequency →
Serial interface external input period
∆ f(XIN): Ta = around 25 °C → center 25 °C
Figure title revised, “When ceramic resonator is used” deleted.
Note 4: (power current) → (supply current)
Pages 79–81, 93–95, 114, 122–129:
Description of SNZ0, SNZT1, SNZT2, SNZAD, SNZSI and WRST instructions revised.
62
130
1.02 Dec. 22, 2006
131
5
26
28
30
43
53
58
59 to 61
63
67 to 70
76
102
117
134
135
137
139
→
(1/1)
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Colophon .7.0