LC717A10PJ

Ordering number : EN*A2214
LC717A10PJ
Advance Information
CMOS LSI
http://onsemi.com
Capacitance-Digital-Converter LSI
for Electrostatic Capacitive Touch
Sensors
Overview
The LC717A10PJ is a high-performance and low-cost capacitance-digital-converter LSI for electrostatic
capacitive touch sensor, especially focused on usability.
It has 16 channels capacitance-sensor input. This makes it ideal for use in the products that need many switches.
Since the calibration function and the judgment of ON/OFF are automatically performed in LSI internal, it can
make development time more short. A detection result (ON/OFF) for each input can be read out by the serial
interface (I2C compatible bus or SPI).
Also, measurement value of each input can be read out as 8-bit digital data. Moreover, gain and other parameters
can be adjusted using serial interface.
Function
 Detection system: Differential capacitance detection (Mutual capacitance type)
 Input capacitance resolution: Can detect capacitance changes in the femto Farad order
 Measurement interval (16 differential inputs): 30ms (Typ) (at initial configuration),
6ms (Typ) (at minimum interval configuration)
 External components for measurement: Not required
 Interface: I2C * compatible bus or SPI selectable.
 Current consumption: 570A (Typ) (VDD = 2.8V), 1.3mA (Typ) (VDD = 5.5V)
 Supply voltage: 2.6V to 5.5V
 Detection operations: Switch
 Packages: SSOP30
SSOP30(225mil)
* I2C Bus is a trademark of Philips Corporation.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
ORDERING INFORMATION
See detailed ordering and shipping information on page 14 of this data sheet.
Semiconductor Components Industries, LLC, 2014
May, 2014
53014HK No.A2214-1/14
LC717A10PJ
Specifications
Absolute Maximum Ratings at Ta = +25C
Parameter
Symbol
Ratings (VSS = 0V)
Unit
Remarks
Supply voltage
VDD
-0.3 to +6.5
V
Input voltage
VIN
-0.3 to VDD+0.3
V
*1
Output voltage
VOUT
-0.3 to VDD+0.3
V
*2
Power dissipation
Pd max
Peak output current
IOP
Total output current
IOA
160
mW
±8
mA
±40
mA
Ta = +105C,
Mounted on a substrate *3
Per a pin
Duty ratio 50% *2
LSI outputs total value
Duty ratio 25% *2
*1) Apply to Cin0 to 15, Cref, CrefAdd, nRST, SCL, SDA, SA0, SA1, SCK, SI, nCS
*2) Apply to Cdrv, SDA, SO, INTOUT
*3) Single-layer glass epoxy board (76.1114.31.6t mm)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Recommended Operating Conditions
Parameter
Symbol
Operating supply voltage
Conditions
VDD
Supply ripple + noise
Vpp
Operating temperature
Topr
min
typ
max
2.6
-40
25
Unit
5.5
V
±20
mV
105
C
Remarks
*1
*1) We recommend connecting large and small capacitance between VDD and VSS.
In this case, the small capacitance is equal to or more than 0.1F, and layout nearby LSI.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Electrical Characteristics at VSS = 0V, VDD = 2.6 to 5.5V, Ta  -40 to +105C
* Unless otherwise specified, the Cdrv drive frequency is fCDRV = 143kHz.
* Not tested at low temperature before shipment.
Parameter
Symbol
Capacitance detection resolution
N
Output noise RMS
NRMS
Input offset capacitance
CoffRANGE
Conditions
min
typ
minimum gain setting
±1.0
*1 *3
±8.0
pF
*1 *3
8
bit
CoffRESO
Cin offset drift
CinDRIFT
minimum gain setting
Cin detection sensitivity
CinSENSE
minimum gain setting
Cin
allowable
parasitic
input
ICin
Cin = Hi-Z
CinSUB
Cin against VSS
±8
0.052
±25
capacitance
Cdrv drive frequency
fCDRV
100
VDD = 5V ±3%, 54.8kHz
setting
nRST minimum pulse width
tNRST
Power-on reset time
tPOR
Power-on
reset
operation
tPOROP
reset
operation
VPOROP
operation
tVDD
143
59.45
reset
*1
LSB/fF
*2
±500
nA
30
pF
186
kHz
68.5
10
0.1
0V to VDD
kHz
*1 *3
*1
s
20
condition: Input voltage
Power-on
LSB
0.108
1
condition: Hold time
Power-on
50.4
Remarks
bit
LSB
adjustment resolution
Cin pin leak current
Unit
8
adjustment range
Input offset capacitance
max
1
ms
ms
*1
V
*1
V/ms
*1
condition: Power supply rise rate
Long interval time
TIVAL
40
101
162
ms
Continued to the next page.
No.A2214-2/14
LC717A10PJ
Continued from the previous page.
Parameter
Pin input voltage
Pin output voltage
Symbol
Conditions
VIH
High input
VIL
Low input
VOH
High output
(IOH = +3mA)
VOL
min
typ
0.2VDD
SDA pin output voltage
VOL
VDD = 5V ±3%, Low output
(IOL = -3mA)
VOL I2C
ILEAK
Current consumption
IDD
V
*4
V
*5
V
*1 *5
0.96VDD
0.02VDD
SDA Low output
0.4
V
±1
A
*6
570
980
A
*1
1.3
2.2
mA
*1
interval time is set to 5ms)
4.2
6.5
mA
VDD = 5.5V
During Sleep process
0.1
70
A
(IOL = -3mA)
Pin leak current
Remarks
0.2VDD
(IOL = -3mA)
VDD = 5V ±3%, High output
(IOH = +3mA)
Unit
0.8VDD
Low output
VOH
max
0.8VDD
When initial setting and
non-touch
VDD = 2.8V
When initial setting and
non-touch
VDD = 5.5V
Short interval mode ( short
ISTBY
*1) Design guarantee values (not tested before shipment)
*2) Measurements conducted using the test mode in the LSI
*3) Ta = +25C
*4) Apply to nRST, SCL, SDA, SA0, SA1, SCK, SI, nCS
*5) Apply to Cdrv, SO, INTOUT
*6) Apply to nRST, SCL, SDA, SA0, SA1, SCK, SI, nCS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
No.A2214-3/14
LC717A10PJ
2
I C Compatible Bus Timing Characteristics at VSS = 0, VDD = 2.6 to 5.5V, Ta = -40 to +105C
*Not tested at low temperature before shipment
Parameter
Symbol
SCL clock frequency
fSCL
START condition hold time
tHD;STA
Pin Name
Conditions
min
typ
SCL
SCL
SDA
max
400
Unit
0.6
s
SCL clock low period
tLOW
SCL
1.3
s
SCL clock high period
tHIGH
SCL
0.6
s
0.6
s
Repeated
START
condition
tSU;STA
setup time
Data hold time
SCL
SDA
tHD;DAT
SCL
SDA
Data setup time
SDA, SCL rise/fall time
tSU;DAT
tr / tf
0
tSU;STO
time
tBUF
s
SCL
500
ns
100
ns
*1
ns
*1
SCL
SCL
SDA
STOP-to-START bus release
*1
SDA
300
SDA
STOP condition setup time
0.9
Remarks
kHz
0.6
s
SCL
2.5
s
SDA
1.3
s
*1
*1) Design guarantee values (not tested before shipment)
No.A2214-4/14
LC717A10PJ
SPI Bus Timing Characteristics at VSS = 0, VDD = 2.6 to 5.5V, Ta = -40 to +105C
*Not tested at low temperature before shipment
Parameter
Symbol
Pin Name
SCK clock frequency
fSCK
SCK
SCK clock Low time
tLOW
SCK
SCK clock High time
Input signal rise/fall time
tHIGH
tr / tf
Conditions
SCK
min
typ
max
Unit
5
100
Remarks
MHz
ns
90
ns
100
ns
*1
90
ns
*1
ns
*1
nCS
SCK
300
SI
nCS setup time
tSU;NCS
SCK clock setup time
tSU;SCK
Data setup time
tSU;SI
nCS
tHD;SI
90
ns
100
ns
SCK
90
ns
SCK
100
ns
SCK
SI
nCS hold time
SCK clock hold time
nCS standby pulse width
Output high impedance time
tHD;NCS
tHD;SCK
tCPH
tCHZ
from nCS
Output data determination time
20
ns
100
ns
tHD;SO
Output low impedance time from
tCLZ
*1
30
ns
ns
SCK
90
ns
nCS
700
ns
SCK
90
ns
nCS
300
ns
90
ns
*1
80
ns
*1
100
ns
nCS
SCK
SCK
SO
SCK clock
*1
200
SO
Output data hold time
*1
nCS
SO
tv
ns
nCS
SI
Data hold time
200
SCK
SCK
SO
80
ns
100
ns
0
ns
100
ns
0
ns
*1
*1
*1
*1
*1
*1
*1) Design guarantee values (not tested before shipment)
No.A2214-5/14
LC717A10PJ
Dynamic offset calibration function to correct Cin offset drift
When measurement data at a certain channel are consecutively within the execution range of dynamic offset
calibration (4 to touch threshold, or -128 to -4) for the period of time corresponding to a value, dynamic offset
calibration is performed and the reference value at the channel is gradually corrected to 0.
The figure below shows the operation when the measured value began to drift in the positive
direction from the central value gradually.
The examples of setting to 8 times the dynamic offset calibration carried count.
Judgment points (They means measurement points where the LC717A10
judges whether to perform dynamic offset calibration
Judgment points within the execution range of dynamic offset calibration
All other measurement points other than the above
CinX Threshold
Dynamic Offset
Calibration
Execution Range of
Dynamic Offset Calibration
(Positive range)
4
0
t
Measurement Timing
Dynamic Offset Calibration
Execution Count Number 0
(Positive range)
0
1
2
Measurement Time + Long Interval Time [ms]
3
4
5
6
7
8
0
Dynamic OffCal
= 0x01
Count Plus Register
No.A2214-6/14
LC717A10PJ
Power-on Reset (POR)
When power is turned on, power-on reset is enabled inside the LSI and its state is released after a certain power-on reset
time, tPOR. Power-on Reset operation condition; Power supply rise rate tVDD must be at least 1V/ms.
Since INTOUT pin changes from “High” to “Low” at the same time as the released of power-on reset, it is possible to
verify the timing of release of power-on reset externally.
During power-on reset, Cin, Cref and CrefAdd are unknown.
VDD
tVDD
VPOROP
tPOR
tPOR
tPOROP
POR
(LSI internal signal)
RESET
UNKNOWN
RELEASE
INTOUT
VALID
Cin,
Cref,
CrefAdd
RESET
UNKNOWN
UNKNOWN
VALID
UNKNOWN
RELEASE
fig.1
I2C Compatible Bus Data Timing
90%
90%
SDA
10%
tHD;DTA
tLOW
tSU;DTA
90% 90%
90%
10% 10%
tHD;STA
10%
tHIGH
tr
10%
tHD;STA
tSU;STA
90%
SCL
90%
10%
10%
90%
tSU;STO
90%
tBUF
10%
90%
10%
tf
repeated START
condition
START
condition
STOP
condition
START
condition
fig.2
I2C Compatible Bus Communication Formats
 Write format (data can be written into sequentially incremented addresses)
START
Slave Address
Write=L ACK
Register Address (N)
Slave
ACK Data written to Register Address (N) ACK Data written to Register Address (N+1) ACK STOP
Slave
Slave
Slave
fig.3
 Read format (data can be read from sequentially incremented addresses)
START
Slave Address
Write=L ACK
Slave
RESTART
Slave Address
Register Address (N)
ACK
Slave
Read=H ACK Data read from Register Address (N) ACK Data read from Register Address (N+1) ACK Data read from Register Address (N+2) NACK STOP
Slave
Master
Master
Master
fig.4
No.A2214-7/14
LC717A10PJ
2
I C Compatible Bus Slave Address
Selection of two kinds of addresses is possible through the SA0 and SA1 terminals.
SA1 input
SA0 input
7bit slave address
Binary notation
8bit slave address
Low
Low
0x16
00101100b (Write)
0x2C
00101101b (Read)
0x2D
Low
High
0x17
00101110b (Write)
0x2E
00101111b (Read)
0x2F
00110000b (Write)
0x30
00110001b (Read)
0x31
High
Low
0x18
High
High
0x19
00110010b (Write)
0x32
00110011b (Read)
0x33
SPI Data Timing (SPI Mode 0 / Mode 3)
tCPH
nCS
tSU;SCK
tSU;NCS
tHIGH
tHD;NCS
tf
tr
tLOW
tHD;SCK
SCK
tHD;SI
tSU;SI
VALID
SI
tCLZ
SO
tHD;SO
tCHZ
VALID
Hi-Z
tV
fig.5
SPI Communication Formats (Example of Mode 0)
 Write format (data can be written into sequentially incremented addresses with preserving nCS = L)
nCS
SCK
SI
SO
Write=L
7 6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Data written to Register Address(N)
Register Address(N)
7
6
5
4
3
2
1
0
Data written to Register Address(N+1)
Hi-Z
fig.6
 Read format (data can be read from sequentially incremented addresses with preserving nCS = L)
nCS
SCK
SI
Read=H
7 6 5
4
3
2
Register Address(N)
SO
Hi-Z
1
0
7
6
5
4
3
2
1
0
Data read from Register Address(N)
7
6
5
4
3
2
1
0
7
Data read from Register Address(N+1)
fig.7
No.A2214-8/14
LC717A10PJ
Package Dimensions
[LC717A10PJ]
unit : mm
SSOP30 (225 mil)
CASE 565AZ
ISSUE A
(Unit: mm)
1.00
SOLDERING FOOTPRINT*
5.80
GENERIC
MARKING DIAGRAM*
0.50
0.32
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
XXXXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
No.A2214-9/14
LC717A10PJ
Pin Assignment
Pin No.
Pin Name
Pin No.
Pin Name
1
VDD
16
Cref
2
VSS
17
CrefAdd
3
Non Connect *1
18
Cdrv
4
Cin4
19
INTOUT
5
Cin5
20
SA1
6
Cin6
21
SCL/SCK
7
Cin7
22
SDA/SI
SA0/SO
8
Cin8
23
9
Cin9
24
nCS
10
Cin10
25
nRST
11
Cin11
26
Non Connect *1
12
Cin12
27
Cin0
13
Cin13
28
Cin1
14
Cin14
29
Cin2
15
Cin15
30
Cin3
*1) connect to GND when mounted
Block Diagram
Cin0
Cin1
Cin2
Cin3
VDD
Cin4
VSS
Cin5
Cin6
Cin7
Cin8
1st
AMP
2nd
AMP
A/D
CONVERTER
MUX
Cin9
Cin10
Cin11
Cdrv
CONTROL
LOGIC
Cin12
INTOUT
Cin13
nRST
Cin14
Cin15
nCS
POR
Cref
CrefAdd
OSCILLATOR
SCL/SCK
2
I C/SPI
MUX
SDA/SI
SA0/SO
SA1
LC717A10PJ is capacitance-digital-converter LSI capable of detecting changes in capacitance in the order of femto
Farads. It consists of an oscillation circuit that generates the system clock, a power-on reset circuit that resets the system
when the power is turned on, a multiplexer that selects the input channels, a two-stage amplifier that detects the changes in
the capacitance and outputs analog-amplitude values, a A/D converter that converts the analog-amplitude values into
digital data, an I2C compatible bus or a SPI that enables serial communication with external devices and a control logic
that controls the entire chip.
No.A2214-10/14
LC717A10PJ
Pin Functions
Pin Name
I/O
Pin Functions
Cin0
I/O
Capacitance sensor input
Cin1
I/O
Capacitance sensor input
Cin2
I/O
Capacitance sensor input
Cin3
I/O
Capacitance sensor input
Cin4
I/O
Capacitance sensor input
Cin5
I/O
Capacitance sensor input
Cin6
I/O
Capacitance sensor input
Cin7
I/O
Capacitance sensor input
Cin8
I/O
Capacitance sensor input
Cin9
I/O
Capacitance sensor input
Cin10
I/O
Capacitance sensor input
Cin11
I/O
Capacitance sensor input
Cin12
I/O
Capacitance sensor input
Cin13
I/O
Capacitance sensor input
Cin14
I/O
Capacitance sensor input
Cin15
I/O
Capacitance sensor input
Cref
I/O
Reference capacitance input
CrefAdd
I/O
Reference capacitance input for addition
Pin Type
VDD
AMP
R
VSS
Buffer
VDD
Cdrv
O
Output for capacitance sensors drive
INTOUT
O
Interrupt output
Buffer
VSS
Clock input (I2C)
SCL/SCK
I
nCS
I
nRST
I
External reset signal inverting input
SA1
I
Slave address selection (I2C)
/ Clock input (SPI)
VDD
Interface selection
R
/ Chip select inverting input (SPI)
VSS
VDD
R
SDA/SI
I/O
Data input and output (I2C)
/ Data input (SPI)
VSS
Continued to the next page.
No.A2214-11/14
LC717A10PJ
Continued from the previous page.
Pin Name
I/O
Pin Functions
Pin Type
VDD
SA0/SO
I/O
R
Slave address selection (I2C)
/ Data output (SPI)
VSS
VDD
Power supply (2.6V to 5.5V) *1
VSS
Ground (Earth) *1 *2
Buffer
*1) Inserting a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS is recommended.
In this case, the small-valued capacitor should be at least 0.1F, and is mounted near the LSI.
*2) When VSS terminal is not grounded in battery-powered mobile equipment, detection sensitivity may be degraded.
Details of Pin Functions
●Cin0 to Cin15
These are the capacitance-sensor-input pins. These pins are used by connecting them to the touch switch pattern.
Cin and the Cdrv wire patterns should be close to each other. By doing so, Cdrv and Cin patterns are capacitively
coupled. Therefore, LSI can detect capacitance change near each pattern as 8bit digital data.
However, if the shape of each pattern or the capacitively coupled value of Cdrv is not appropriate, it may not be able to
detect the capacitance change correctly.
In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude
values. Cin0 to Cin15 are connected to the inverting input of the 1st amplifier.
During measurement process, channels other than the one being measured are all in “Low” condition.
Leave the unused terminals open.
●Cref, CrefAdd
These are the reference-capacitance-input pins. These are used by connecting to the wire pattern like Cin pins or are
used by connecting any capacitance between this pin and Cdrv pin.
In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude
values. Cref is connected to the non-inverting input of the 1st amplifier.
Due to the parasitic capacitance generated in the wire connections of Cin pins and their patterns, as well as the one
generated between the wire patterns of Cin and Cdrv pins, Cref may not detect capacitance change of each Cin pin
accurately. In this case, connect an appropriate capacitance between Cref and Cdrv to detect capacitance change
accurately.
However, if the difference between the parasitic capacitance of each Cin pin is extremely large, it may not detect
capacitance change of each Cin pin correctly.
CrefAdd can be used as additional terminal for Cref. Leave the CrefAdd open if not in used.
●Cdrv
It is the output pin for capacitance sensors drive. It outputs the pulse voltage which is needed to detect capacitance at
Cin0 to Cin15.
Cdrv and Cin wire patterns should be close to each other so that they are capacitively coupled.
●INTOUT
It is the interrupt-output pin.
It is used by connecting to a main microcomputer if necessary, and use as interrupt signal. (High Active)
Leave the terminal open if not in used.
●SCL/SCK
Clock input (I2C) / Clock input (SPI)
It is the clock input pin of the I2C compatible bus or the SPI depending on the mode of operation.
No.A2214-12/14
LC717A10PJ
●nCS
Interface selection / Chip-select-inverting input (SPI)
Selection of I2C compatible bus mode or SPI mode is through this terminal. After initialization, the LSI is automatically
in I2C compatible bus mode. To continually use I2C compatible bus mode, fix nCS pin to “High”. To switch to SPI mode
after LSI initialization, change the nCS input “High”  “Low”. The nCS pin is used as the chip-select-inverting input
pin of SPI, and SPI mode is kept until LSI is again initialized.
●nRST
It is the external-reset-signal-inverting-input pin. When nRST pin is “Low”, LSI is in reset state.
Each pin (Cin0 to 15, Cref, CrefAdd) is “Hi-Z” during reset state.
●SDA/SI
Data input and output (I2C) / Data input (SPI)
It is the data input and output pin of the I2C compatible bus or the data input pin of the SPI depending on the mode of
operation.
●SA0/SO
Slave address selection (I2C) / Data output (SPI)
It is the slave address selection pin of the I2C compatible bus or the data output pin of the SPI depending on the mode of
operation.
●SA1
Slave address selection (I2C)
It is the slave address selection pin of the I2C compatible bus.
When SPI mode, connect to the SA1 pin to GND.
No.A2214-13/14
LC717A10PJ
ORDERING INFORMATION
Device
LC717A10PJ-AH
Package
Shipping (Qty / Packing)
SSOP30(225mil)
(Pb-Free / Harogen Free)
1000 / Tape & Reel
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PS No.A2214-14/14