Ordering number : ENA1059A LA72730 Monolithic Linear IC Audio/Video Switch for TV http://onsemi.com Overview The LA72730 is an Audio/Video Switch for TV. Functions • Audio : Possible to Change 4 Channel×2, ALC OUTPUT, 4dB Amplifier MONITOR OUTPUT • Video : Possible to Change 4 Channel, 6dB Amplifier • Control : I2C (Slave address : 92h) Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Allowable power dissipation Symbol VCC max Pd max Conditions Ratings Pin 8 Ta ≤ 70°C Unit 7.0 V 300 mW Operating temperature Topr -20 to +70 °C Storage temperature Tstg -55 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Recommended Operating Conditions at Ta = 25°C Parameter Recommended operating voltage Operating voltage range Symbol Conditions Ratings Unit VCC Pin 8 5.0 V VCC op Pin 8 4.5 to 5.5 V Semiconductor Components Industries, LLC, 2013 July, 2013 21010 SY / 52108 MS PC 20080514-S00004 No.A1059-1/8 LA72730 Electrical Characteristics at Ta = 25°C, VDD = 5.0V Parameter Symbol Ratings Conditions min Current dissipation ICC VCC = 5V, No signal 15.2 typ Unit max 18 20.8 mA Audio block Audio input DC voltage INa No signal pin 1, 2, 3, 4, 5, 6, 23, 24 DC voltage 2.2 2.4 2.6 V Audio output DC voltage Oa No signal pin 19, 20 DC voltage 2.2 2.4 2.6 V Fa Input : 1kHz/20kHz, -6dBV : Pin 19, 20 output Audio channel bandwidth Audio voltage gain (Audio-out) Aa1 f = 1kHz, VIN = -6dBV, Pin 19, 20 output Audio voltage gain (Monitor-out) Aa2 f = 1kHz, VIN = -6dBV, Pin 12, 16 output Audio input dynamic range Da1 f = 1kHz, THD = ≤1% (Audio-out) -2 0 +2 dB -0.3 0.0 +0.3 dB 4.5 3.5 4.0 -3.0 -1.0 dBV dB -5.0 -3.0 dBV 35 50 Pin 19, 20 output Audio input dynamic range f = 1kHz, THD = ≤1% Da2 (Monitor-out) Pin 13, 16 output Audio channel PSRR PSa VCC = 5V+1Vp-p, SINE WAVE (50Hz) dB Audio channel input impedance Ria 80 100 120 Audio channel output impedance Roa 150 200 250 Audio channel crosstalk CTa f = 1kHz 65 80 Audio channel S/N SNa Filter = DIN/AUDIO 70 Audio channel THD THDa ALC Detect level-1 ALC1 ALC Detect level-2 ALC Detect level-3 ALC Detect level-4 f = 1kHz, VIN = -6dBV kΩ Ω dB 85 dB 0.15 0.3 % -10.5 -9 -7.5 dBV ALC2 -15.5 -14 -12.5 dBV ALC3 -13.5 -12 -10.5 dBV ALC4 -19.5 -18 -16.5 dBV Video block Video input DC voltage INv 1.44 1.6 1.76 V Video output DC voltage Ov 1.26 1.4 1.54 V Video channel bandwidth Fv -3dB frequency Video signal voltage gain Av f = 500kHz, VIN = 1Vp-p 5.0 6.0 Video input dynamic range Dv f = 100kHz, THD ≤ 1% 2.0 2.5 Vp-p VCC = 5V+1Vp-p, SINE WAVE (50Hz) 35 50 dB Video channel PSRR PSv 10 MHz 7.0 dB Video channel input impedance Riv 8.0 10 12.0 Video channel output impedance Rov 30 40 50 kΩ Video channel crosstalk CTv f = 3.58MHz, VIN = 1Vp-p 45 60 dB Video channel noise SNv Bandwidth 10MHz 55 60 dB Ω Package Dimensions unit : mm (typ) 3067B 13 1 12 (3.25) 0.95 0.51min 3.3 3.9 max 0.9 0.25 6.4 24 7.62 21.0 (0.71) 1.78 0.48 SANYO : DIP24S(300mil) No.A1059-2/8 LA72730 Block Diagram LIN-1 LIN-TV 1 24 0.1μF 0.1μF LIN-2 RIN-TV 2 23 0.1μF 0.1μF LIN-3 REG 3 22 0.1μF 47μF VIN-TV RIN-1 4 21 0.1μF RIN-2 5 ALC 0.1μF 6 ALC 0.1μF 20 AUDIO L OUT + 10μF BUFF 19 AUDIO R OUT + 10μF 6dB 18 75Ω + VIDEO OUT 220μF 75Ω VIN-1 VCC 47μF + 100μH VCC 5V 7 DET 8 17 VIN-2 GND + 47μF ALC FILT 0.1μF + 10μF + 10μF BUFF RIN-3 + 10μF + 4dB 9 16 + 10μF L Monitor out 10 NC 15 + 10μF 11 14 + 10μF 12 VIN-3 SDA MODE SELECT 4dB 13 SCL R Monitor out No.A1059-3/8 LA72730 I2C Bit Pattarn D8 D7 D6 D5 D4 D3 * * * * * * D2 D1 Condition 0 0 AV IN-TV 0 1 AV IN-1 1 0 AV IN-2 1 1 AV IN-3 0 Norma 1 Mute 0 0 ALC Level-1 (-9dBV) 0 1 ALC Level-2 (-14dBV) 1 0 ALC Level-3 (-12dBV) 1 1 ALC Level-4 (-18dBV) 0 ALC-ON 1 ALC-OFF 0 Prohibit 1 Fix 0 Fix 1 Prohibit “*” : Shows initial condition. Slave address : 92h (1001 0010) LINE-OUT 10 10 5 5 F OF OUTPUT – dBV OUTPUT – dBV 0 C- –5 AL ALC-1 ALC-3 ALC-2 – 10 – 15 ALC-4 – 20 0 –5 R ITO N MO – 10 – 15 – 20 – 25 – 30 – 30 MONITOR 15 – 25 – 25 – 20 – 15 – 10 INPUT – dBV –5 0 – 30 – 30 – 25 – 20 – 15 – 10 –5 0 INPUT – dBV No.A1059-4/8 LA72730 Test Circuit LIN-1 1 620Ω LIN-TV 24 0.1μF 0.1μF LIN-2 2 620Ω 0.1μF LIN-3 REG 3 620Ω 22 0.1μF 620Ω + 1μF RIN-1 VIN-TV 4 620Ω RIN-TV 23 0.1μF 620Ω 21 0.1μF 0.1μF 75Ω RIN-2 5 620Ω BUFF ALC 0.1μF 20 AUDIO L OUT RIN-3 AUDIO R OUT 6 620Ω ALC 0.1μF BUFF 19 6dB 18 VIN-1 VIDEO OUT 7 75Ω 0.1μF VCC VCC5V 75Ω DET 8 + 47μF 4dB 16 10 15 11 14 VIN-3 75Ω + 1μF ALC FILT 0.1μF VIN-2 9 0.1μF GND 17 0.1μF L Monitor out NC SDA MODE SELECT 12 4dB 13 SCL R Monitor out No.A1059-5/8 LA72730 Pin Functions Pin No. Pin Name 1 PIA_L1 2 PIA_L2 3 PIA_L3 4 PIA_R1 5 PIA_R2 6 PIA_R3 23 PIA_RTV 24 PIA_LTV 7 PIV_1 9 PIV_2 11 PIV_3 21 PIV_TV Function Audio input DC : voltage Equivalent Circuit AC : level DC : 2.4V 50kΩ 50kΩ Video input DC : 1.6V 500Ω 8 VCC 10 GND 12 POMONITR 16 POMONITL Monitor output DC : 2.4V 200Ω 13 PISCL Serial clock input 1kΩ 14 PISDA Serial data input 1kΩ 17 POALCFIL ALC detect filter 2kΩ 150Ω Continued on next page No.A1059-6/8 LA72730 Continued from preceding page. Pin No. Pin Name DC : voltage Function Equivalent Circuit AC : level 18 POVIDEO Video output DC : 1.4V 19 POALCR Audio output DC : 2.4V 20 POALCL 200Ω 10kΩ 22 PCREG Reference voltage DC : 2.4V 10kΩ 9.6kΩ 500Ω 1kΩ I2C BUS serial interface specification (1) Data Transfer Manual This IC adopts control method (I2C-BUS) with serial data, and controlled by two terminals which called SCL (serial clock) and SDA (serial data).At first, set up *1 the condition of starting data transfer, and after that, input 8 bit data to SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of Bit), and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes “H”, this IC pull down the SDA terminal. After transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition, thus the transfer comes to close. *1 Defined by SDA fall down SCL during ‘H’ period. *2 Defined by SDA rise up SCL during ‘H’ period. (2) Transfer Data Format After transfer start condition, transfers slave address (92h : 1001 0010 ) to SDA terminal, control data, then, stop condition (See figure 1). Slave address is made up of 7bits, *3 8th bit shows the direction of transferring data, but this IC does not have READ mode, so that this bit fix to “L”. Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be canceled the transfer dates. *3 It is called R/W bit. Fig.1 DATA STRUCTURE START Condition Slave Address R/W L ACK Control data ACK STOP condition (3) Initialize This IC is initialized for circuit protection. Initial condition is shown on bitmap. No.A1059-7/8 LA72730 Reference Parameter Symbol min max unit LOW level input voltage VIL -0.5 1.5 HIGH level input voltage VIH 2.5 5.5 V LOW level output current IOL 3.0 mA 100 kHz SCL clock frequency fSCL 0 V Set-up time for a repeated START condition tSU : STA 4.7 μs Hold time START condition. After this period, the first clock pulse is generated tHD : STA 4.0 μs tLOW 4.7 μs LOW period of the SCL clock Rise time of both SDA and SDL signals tR HIGH period of the SCL clock 0 tHIGH Fall time of both SDA and SDL signals tF 1.0 0 μs μs 4.0 1.0 μs μs Data hold time tHD : DAT 0 Data set-up time tSU : DAT 250 ns Set-up time for STOP condition tSU : STO 4.0 μs tBUF 4.7 μs BUS free time between a STOP and START condition Definition of timing tR t HI G H tF S CL t HD : S TA t SU : S TA t LO W t HD : D AT A t SU : D AT t SU : S TO t BU F S DA ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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