LE25U20AQG CMOS IC 2M-bit (256K x 8) Serial Flash Memory www.onsemi.com Overview The LE25U20AQG is a serial interface-compatible flash memory device with a 256K 8-bit configuration. It uses a single 2.5V power supply. While making the most of the features inherent to a serial flash memory device, the LE25U20AQG is housed in an 8-pin ultra-miniature package. These features make this device ideally suited to storing program codes in applications such as portable information devices, which are required to have increasingly more compact dimensions. Moreover, by using the small sector erase function this product is also suitable for the parameter or the date storage usage with comparatively little rewriting times that becomes a capacity shortage in EEPROM. WDFN8 2x3 Features Read / write operations enabled by single 2.5V power supply: 2.30 to 3.60V supply voltage range Operating frequency : 30MHz Temperature range : 40 to 85C Serial interface : SPI mode 0, mode 3 supported Sector size : 4K bytes/small sector, 64K bytes/sector Small sector erase, sector erase, chip erase functions Page program function (256 bytes / page) Block protect function Status functions : Ready/busy information, protect information Highly reliable read/write Number of rewrite times : 100,000 times Small sector erase time : 40ms (typ.), 150ms (max.) Sector erase time : 80ms (typ.), 250ms (max.) Chip erase time : 250ms (typ.), 1.6s (max.) Page program time : 4.0ms/256 bytes (typ.), 5.0ms/256 bytes (max.) Data retention period : 20 years Package : WDFN8 23 * This product is licensed from Silicon Storage Technology, Inc. (USA). ORDERING INFORMATION See detailed ordering and shipping information on page 21 of this data sheet. © Semiconductor Components Industries, LLC, 2014 October 2014 - Rev. 1 1 Publication Order Number : LE25U20AQG/D LE25U20AQG Package Dimensions unit : mm WDFN8 2x3, 0.5P CASE 511BY ISSUE O A D B L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L1 DETAIL A ALTERNATE CONSTRUCTIONS E PIN ONE REFERENCE 0.10 C EXPOSED Cu DIM A A1 A3 b D D2 E E2 e L L1 MOLD CMPD 0.10 C TOP VIEW 0.08 C NOTE 4 DETAIL B A DETAIL B 0.10 C ALTERNATE CONSTRUCTIONS A3 A1 SIDE VIEW C 0.10 D2 DETAIL A 1 M SEATING PLANE GENERIC MARKING DIAGRAM* C A B 1 L 4 0.10 M C A B XXXXX A WL Y W E2 8 5 8X e BOTTOM VIEW b 0.10 0.05 M M = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package RECOMMENDED SOLDERING FOOTPRINT* 1.66 0.50 2.04 3.30 1 8X 0.32 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 8 7 6 5 SI WP 4 SCK SO 3 HOLD 2 V DD CS VSS Figure 1 Pin Assignments 1 XXXXX AWLYW *This information is generic. Please refer to device data sheet for actual part marking. C A B C NOTE 3 8X MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.40 1.60 3.00 BSC 1.80 2.00 0.50 BSC 0.25 0.35 −−− 0.15 Bottom View www.onsemi.jp 2 LE25U20AQG Figure 2 Block Diagram 2M Bit Flash EEPROM Cell Array XDECODER ADDRESS BUFFERS & LATCHES Y-DECODER I/O BUFFERS & DATA LATCHES CONTROL LOGIC SERIAL INTERFACE CS SCK SI SO WP HOLD Table 1 Pin Description Symbol SCK Pin Name Serial clock Description This pin controls the data input/output timing. The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is output synchronized to the falling edge of the serial clock. SI Serial data input The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the serial clock. SO Serial data output CS Chip select The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock. The device becomes active when the logic level of this pin is low; it is deselected and placed in standby status when the logic level of the pin is high. WP Write protect The status register write protect (SRWP) takes effect when the logic level of this pin is low. HOLD Hold Serial communication is suspended when the logic level of this pin is low. VDD Power supply This pin supplies the 2.30 to 3.60V supply voltage. VSS Ground This pin supplies the 0V supply voltage. www.onsemi.jp 3 LE25U20AQG Device Operation The LE25U20AQG features electrical on-chip erase functions using a single 2.5V power supply, that have been added to the EPROM functions of the industry standard that support serial interfaces. Interfacing and control are facilitated by incorporating the command registers inside the chip. The read, erase, program and other required functions of the device are executed through the command registers. The command addresses and data input in accordance with "Table 2 Command Settings" are latched inside the device in order to execute the required operations. "Figure 3 Serial Input Timing" shows the timing waveforms of the serial data input. First, at the falling CS edge the device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are introduced internally in sequence starting with bit 7 in synchronization with the rising SCK edge. At this time, output pin SO is in the high-impedance state. The output pin is placed in the low-impedance state when the data is output in sequence starting with bit 7 synchronized to the falling clock edge during read, status register read and silicon ID. Refer to "Figure 4 Serial Output Timing" for the serial output timing. The LE25U20AQG supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of SCK is high. Table 2 Command Settings Command Read 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 03h A23-A16 A15-A8 A7-A0 0Bh A23-A16 A15-A8 A7-A0 D7h/20h A23-A16 A15-A8 A7-A0 Sector erase D8h A23-A16 A15-A8 A7-A0 Chip erase C7h Page program 02h A23-A16 A15-A8 A7-A0 Write enable 06h X X Small sector erase Write disable 04h Power down B9h Status register read 05h Status register write 01h Read silicon ID 1 9Fh Read silicon ID 2 ABh Exit power down mode ABh 5th bus cycle 6th bus cycle Nth bus cycle PD * PD * X PD * DATA X Explanatory notes for Table 2 "X" signifies "don't care" (that is to say, any value may be input). The "h" following each code indicates that the number given is in hexadecimal notation. Addresses A23 to A18 for all commands are "Don't care". In order for commands other than the read command to be recognized, CS must rise after all the bus cycle input. *: "PD" stands for page program data. Figure 3 Serial Input Timing www.onsemi.jp 4 LE25U20AQG tCPH CS tCSH tCLHI tCSS tCLLO tCSH tCSS SCK tDS SI SO tDH DATA VALID High Impedance High Impedance Figure 4 Serial Output Timing CS SCK tCLZ SO tHO tCHZ DATA VALID tV SI www.onsemi.jp 5 LE25U20AQG Description of Commands and Their Operations "Table 2 Command Settings" provides a list and overview of the commands. A detailed description of the functions and operations corresponding to each command is presented below. 1. Read There are two read commands, the 4 bus cycle read command and 5 bus cycle read command. Consisting of the first through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses following (03h), and the data in the designated addresses is output synchronized to SCK. The data is output from SO on the falling clock edge of fourth bus cycle bit 0 as a reference. "Figure 5-a 4 Bus Read" shows the timing waveforms. Consisting of the first through fifth bus cycles, the 5 bus cycle read command inputs the 24-bit addresses and 8 dummy bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a reference. "Figure 5-b 5 Bus Read" shows the timing waveforms. The only difference between these two commands is whether the dummy bits in the fifth bus cycle are input. When SCK is input continuously after the read command has been input and the data in the designated addresses has been output, the address is automatically incremented inside the device while SCK is being input, and the corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the highest address (3FFFFh), the internal address returns to the lowest address (00000h), and data output is continued. By setting the logic level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin SO is in a high-impedance state. Figure 5-a 4 Bus Read CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 31 32 23 24 39 40 47 Mode0 8CLK SI 03h Add. Add. Add. N High Impedance SO DATA MSB N+1 N+2 DATA DATA MSB MSB Figure 5-b 5 Bus Read CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 Mode0 8CLK SI SO 0Bh Add. Add. High Impedance Add. X N N+1 N+2 DATA DATA DATA MSB www.onsemi.jp 6 MSB MSB LE25U20AQG 2. Status Registers The status registers hold the operating and setting statuses inside the device, and this information can be read (status register read) and the protect information can be rewritten (status register write). There are 8 bits in total, and "Table 3 Status registers" gives the significance of each bit. Table 3 Status Registers Bit Name Bit0 RDY Bit1 WEN Bit2 BP0 Bit3 BP1 Logic Function 0 Ready Power-on Time Information 1 Erase/Program 0 Write disabled 1 Write enabled 0 1 Block protect information 0 See status register descriptions on BP0 and BP1. 1 Bit4 0 Nonvolatile information Nonvolatile information 0 Bit5 Reserved bits Bit6 Bit7 0 0 0 SRWP 0 Status register write enabled 1 Status register write disabled Nonvolatile information 2-1. Status Register Read The contents of the status registers can be read using the status register read command. This command can be executed even during the following operations. Small sector erase, sector erase, chip erase Page program Status register write "Figure 6 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the first to be output, and each time one clock is input, all the other bits up to RDY (bit 0) are output in sequence, synchronized to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is output by returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock input is continued. The data can be read by the status register read command at any time (even during a program or erase cycle). Figure 6 Status Register Read CS Mode 3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 Mode 0 8CLK SI SO 05h High Impedance DATA MSB DATA MSB www.onsemi.jp 7 DATA MSB LE25U20AQG 2-2. Status Register Write The information in status registers BP0, BP1, and SRWP can be rewritten using the status register write command. RDY, WEN, bit 4, bit 5, and bit 6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, and SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at powerdown. "Figure 7 Status Register Write" shows the timing waveforms of status register write, and Figure 20 shows a status register write flowchart. Consisting of the first and second bus cycles, the status register write command initiates the internal write operation at the rising CS edge after the data has been input following (01h). Erase and program are performed automatically inside the device by status register write so that erasing or other processing is unnecessary before executing the command. By the operation of this command, the information in bits BP0, BP1, and SRWP can be rewritten. Since bits RDY (bit 0), WEN (bit 1), bit 4, bit 5, and bit 6 of the status register cannot be written, no problem will arise if an attempt is made to set them to any value when rewriting the status register. Status register write ends can be detected by RDY of status register read. Information in the status registers can be rewritten 1,000 times (min.). To initiate status register write, the logic level of the WP pin must be set high and status register WEN must be set to "1". Figure 7 Status Register Write Self-timed Write Cycle tSRW CS tWPH tWPS WP Mode3 SCK 0 1 2 3 4 5 6 7 8 15 Mode0 8CLK SI SO 01h DATA High Impedance 2-3. Contents of Each Status Register RDY (bit 0) The RDY register is for detecting the write (program, erase and status register write) end. When it is "1", the device is in a busy state, and when it is "0", it means that write is completed. www.onsemi.jp 8 LE25U20AQG WEN (bit 1) The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not perform the write operation even if the write command is input. If it is set to "1", the device can perform write operations in any area that is not block-protected. WEN can be controlled using the write enable and write disable commands. By inputting the write enable command (06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0". In the following states, WEN is automatically set to "0" in order to protect against unintentional writing. At power-on Upon completion of small sector erase, sector erase or chip erase Upon completion of page program Upon completion of status register write * If a write operation has not been performed inside the LE25U20AQG because, for instance, the command input for any of the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has failed or a write operation has been performed for a protected address, WEN will retain the status established prior to the issue of the command concerned. Furthermore, its state will not be changed by a read operation. BP0, BP1 (bits 2, 3) Block protect BP0 and BP1 are status register bits that can be rewritten, and the memory space to be protected can be set depending on these bits. For the setting conditions, refer to "Table 4 Protect level setting conditions". Table 4 Protect Level Setting Conditions Status Register Bits Protect Level Protected Area BP1 BP0 0 (Whole area unprotected) 0 0 None 1 (1/4 protected) 0 1 30000h to 3FFFFh 2 (1/2 protected) 1 0 20000h to 3FFFFh 3 (Whole area protected) 1 1 00000h to 3FFFFh * Chip erase is enabled only when the protect level is 0. SRWP (bit 7) Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten. When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status registers BP0, BP1, and SRWP are protected. When the logic level of the WP pin is high, the status registers are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 5 SRWP setting conditions". Table 5 SRWP Setting Conditions WP Pin 0 1 SRWP Status Register Protect State 0 Unprotected 1 Protected 0 Unprotected 1 Unprotected Bits 4, Bits 5, and Bits 6 are reserved bits, and have no significance. www.onsemi.jp 9 LE25U20AQG 3. Write Enable Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command. "Figure 8 Write Enable" shows the timing waveforms when the write enable operation is performed. The write enable command consists only of the first bus cycle, and it is initiated by inputting (06h). Small sector erase, sector erase, chip erase Page program Status register write 4. Write Disable The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 9 Write Disable" shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write enable command (06h). Figure 8 Write Enable Figure 9 Write Disable CS CS Mode3 SCK Mode3 0 1 2 3 4 5 6 7 SCK Mode0 8CLK SI 8CLK SI 06h High Impedance SO 0 1 2 3 4 5 6 7 Mode0 04h High Impedance SO 5. Power-down The power-down command sets all the commands, with the exception of the silicon ID read command and the command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 10 Power-down" shows the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by inputting (B9h). However, a power-down command issued during an internal write operation will be ignored. The power-down state is exited using the power-down exit command (power-down is exited also when one bus cycle or more of the silicon ID read command (ABh) has been input). "Figure 11 Exiting from Power-down" shows the timing waveforms of the power-down exit command. Figure 10 Power-down Figure 11 Exiting from Power-down Power down mode Power down mode CS CS tPRB tDP Mode3 SCK Mode3 0 1 2 3 4 5 6 7 SCK Mode0 8CLK SI SO 0 1 2 3 4 5 6 7 Mode0 8CLK SI B9h High Impedance SO www.onsemi.jp 10 ABh High Impedance LE25U20AQG 6. Small Sector Erase Small sector erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of 4Kbytes. "Figure 12 Small Sector Erase" shows the timing waveforms, and Figure 21 shows a small sector erase flowchart. The small sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (D7h/20h). Addresses A17 to A12 are valid, and Addresses A23 to A18 are "don't care". After the command has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY. Figure 12 Small Sector Erase Self-timed Erase Cycle tSSE CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 Mode0 8CLK SI D7h/20h Add. Add. Add. High Impedance SO 7. Sector Erase Sector erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64Kbytes. "Figure 13 Sector Erase" shows the timing waveforms, and Figure 21 shows a sector erase flowchart. The sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (D8h). Addresses A17 to A16 are valid, and Addresses A23 to A18 are "don't care". After the command has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY. Figure 13 Sector Erase Self-timed Erase Cycle tSE CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 Mode0 8CLK SI SO D8h Add. Add. Add. High Impedance www.onsemi.jp 11 31 LE25U20AQG 8. Chip Erase Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 14 Chip Erase" shows the timing waveforms, and Figure 21 shows a chip erase flowchart. The chip erase command consists only of the first bus cycle, and it is initiated by inputting (C7h). After the command has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY. Figure 14 Chip Erase Self-timed Erase Cycle tCHE CS Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI C7h High Impedance SO 9. Page Program Page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page (page addresses: A17 to A8). Before initiating page program, the data on the page concerned must be erased using small sector erase, sector erase, or chip erase. "Figure 15 Page Program" shows the page program timing waveforms, and Figure 22 shows a page program flowchart. After the falling CS, edge, the command (02H) is input followed by the 24-bit addresses. Addresses A17 to A0 are valid. The program data is then loaded at each rising clock edge until the rising CS edge, and data loading is continued until the rising CS edge. If the data loaded has exceeded 256 bytes, the 256 bytes loaded last are programmed. The program data must be loaded in 1-byte increments, and the program operation is not performed at the rising CS edge occurring at any other timing. The page program time is 2.0ms (typ.) when 256 bytes (1 page) are programmed at one time. Figure 15 Page Program Self-timed Program Cycle tPP CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 2079 Mode0 8CLK SI SO 02h Add. Add. Add. High Impedance www.onsemi.jp 12 PD PD PD LE25U20AQG 10. Silicon ID Read Silicon ID read is an operation that reads the manufacturer code and device code information. The silicon ID read command is not accepted during writing. Two methods are used for silicon ID reading. The first method involves inputting the 9Fh command: the setting is completed with only the first bus cycle input, and in subsequent bus cycles the manufacturer code 62h, 2 bytes of device ID code (Memory type, Memory capacity) and reserved code are repeatedly output in succession so long as the clock input is continued. Refer to "Figure 16-a Silicon ID Read 1" for the waveforms. "Table 6_1 Silicon ID Read 1" lists the silicon ID read1 codes. The second method involves inputting the ABh command. This command consists of the first through fourth bus cycles, and the 1 byte silicon ID can be read when 24 dummy bits are input after (ABh). Refer to "Figure 16-b Silicon ID Read 2" for the waveforms. "Table 6_2 Silicon ID Read 2" lists the silicon ID read2 code. If, after the device code has been read, the SCK input is continued, the device code is output repeatedly. The data is output starting with the falling clock edge of the fourth bus cycle bit 0, and silicon ID reading ends at the rising CS edge. Table 6_1 Silicon ID Read 1 Table 6_2 Silicon ID Read 2 Output Code Output Code Manufacturer code Memory Type 2Byte Device ID 1Byte 62h 06h Memory Capacity code 44h Device ID 12h(2MBit) Reserved code 00h Figure 16-a Silicon ID Read 1 CS Mode3 SCK 0 1 2 3 4 5 6 7 8 23 24 15 16 39 31 32 Mode0 8CLK SI 9Fh High Impedance SO 62h MSB 06h MSB 12h MSB 00h MSB 06h MSB Figure 16-b Silicon ID Read 2 CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 31 32 23 24 39 Mode0 8CLK SI SO ABh X X High Impedance X 44h MSB www.onsemi.jp 13 44h MSB LE25U20AQG 11. Hold Function Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure 17 HOLD" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is high, HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is exited and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the high-impedance state, and SI and SCK are "don't care". Figure 17 HOLD Active CS Active HOLD tHS tHS SCK tHH tHH HOLD tHLZ tHHZ High Impedance SO 12. Power-on In order to protect against unintentional writing, CS must be kept at VCC At power-on. After power-on, the supply voltage has stabilized at 2.30V or higher, wait for 100s (tPU_READ) before inputting the command to start a read operation. Similarly, wait for 10ms (tPU_WRITE) after the voltage has stabilized before inputting the command to start a write operation. Figure 18 Power-on Timing Program, Erase and Write Command not Allowed VDD VDD(Max) Chip selection not Allowed Read Access Allowed VDD(Min) tPU_READ tPU_WRITE 0V www.onsemi.jp 14 Full Access Allowed LE25U20AQG 13. Hardware Data Protection In order to protect against unintentional writing at power-on, the LE25U20AQG incorporates a power-on reset function. The following conditions must be met in order to ensure that the power reset circuit will operate stably. No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period. Figure 19 Power-down Timing Program, Erase and Write Command not Allowed VDD VDD(Max) No Device Access Allowed VDD(Min) tPU_READ tPU_WRITE tPD 0V vBOT 14. Software Data Protection The LE25U20AQG eliminates the possibility of unintentional operations by not recognizing commands under the following conditions. When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK) When the page program data is not in 1-byte increments When the status register write command is input for 2 bus cycles or more 15. Decoupling Capacitor A 0.1F ceramic capacitor must be provided to each device and connected between VDD and VSS in order to ensure that the device will operate stably. www.onsemi.jp 15 LE25U20AQG Specifications Absolute Maximum Ratings Parameter Symbol Maximum supply voltage Conditions Ratings unit VDDmax With respect to VSS -0.5 to +4.6 V DC voltage (all pins) VIN/VOUT With respect to VSS -0.5 to VDD+0.5 V Storage temperature Tstg -55 to +150 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Operating Conditions Parameter Symbol Conditions Ratings unit Operating supply voltage VDD 2.30 to 3.60 V Operating ambient temperature Topr -40 to 85 C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Allowable DC Operating Conditions Parameter Read mode operating current Symbol ICCR Conditions Ratings min typ CS=0.1VDD, HOLD=WP=0.9VDD SI=0.1VDD/0.9VDD, SO=open 6 mA 15 mA CS=HOLD=WP=VDD, SI=VSS/VDD, SO=open, 50 A VDD=VDD max CS=HOLD=WP=VDD, SI=VSS/VDD, SO=open, 10 A 2 A 2 A 0.3VDD VDD+0.3 V operating frequency=30MHz, Write mode operating current ICCW (erase+page program) unit max VDD=VDD max VDD=VDD max, tSSE=40ms, tSE=80ms, tCHE=160ms, tPP=5.0ms CMOS standby current ISB Power-down standby current IDSB Input leakage current ILI Output leakage current ILO Input low voltage Input high voltage VIL VIH Output low voltage VOL VDD=VDD max VIN=VSS to VDD, VDD=VDD max VIN=VSS to VDD, VDD=VDD max VDD=VDD max VDD=VDD min IOL=100A, VDD=VDD min -0.3 0.7VDD IOL=1.6mA, VDD=VDD min Output high voltage VOH IOH=-100A, VDD=VDD min V 0.2 V 0.4 VCC-0.2 V Power-on Timing Parameter Ratings Symbol Time from power-on to read operation Power-down time tPU_READ tPU_WRITE tPD Power-down voltage vBOT Time from power-on to write operation min unit max 100 s 10 ms 10 ms 0.2 V Pin Capacitance at Ta=25C, f=1MHz Parameter Output pin capacitance Input pin capacitance Symbol CDQ CIN Conditions VDQ=0V VIN=0V Ratings unit max 12 pF 6 pF Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values for some of the sampled devices. www.onsemi.jp 16 LE25U20AQG AC Characteristics Parameter Symbol Ratings min typ unit max Clock frequency fCLK SCK logic high level pulse width tCLHI 16 SCK logic low level pulse width tCLLO 16 Input signal rising/falling time tRF CS setup time tCSS 10 ns CS hold time tCSH 10 ns Data setup time tDS 5 ns Data hold time tDH 5 ns CS wait pulse width tCPH Output high impedance time from CS tCHZ Output data time from SCK tV 30 MHz ns ns 20 ns 25 ns 10 15 ns 15 ns Output data hold time tHO 1 HOLD setup time tHS 7 ns HOLD hold time tHH 3 ns Output low impedance time from HOLD tHLZ 9 Output high impedance time from HOLD tHHZ 9 WP setup time tWPS 20 ns WP hold time tWPH 20 ns Write status register time tSRW Page programming cycle time tPP Small sector erase cycle time ns ns ns 5 15 ms 4.0 5.0 ms tSSE 0.04 0.15 s Sector erase cycle time tSE 0.08 0.25 s Chip erase cycle time tCHE 0.25 1.6 s Power-down time tDP 3 s Power-down recovery time tPRB 3 s Output low impedance time from SCK tCLZ 0 ns AC Test Conditions Input pulse level ··········· 0V, 2.5V Input rising/falling time ·· 5ns Input timing level ········· 0.3VDD, 0.7VDD Output timing level ······· 1/2VDD Output load ················ 30pF Note: As the test conditions for "typ," the measurements are conducted using 2.5V for VDD at room temperature. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.jp 17 LE25U20AQG Figure 20 Status Register Write Flowchart Status register write Start 06h 01h Write enable Set status register write command Data Program start on rising edge of CS 05h NO Set status register read command Bit 0= “0” ? YES End of status register write * Automatically placed in write disabled state at the end of the status register write www.onsemi.jp 18 LE25U20AQG Figure 21 Erase Flowcharts Small sector erase Sector erase Start Start 06h Write enable 06h D8h D7h/20h Address 1 NO Address 1 Set small sector erase command Address 2 Address 2 Address 3 Address 3 Start erase on rising edge of CS Start erase on rising edge of CS Set status register read command 05h Write enable 05h NO Bit 0 = “0” ? Set sector erase command Set status register read command Bit 0 = “0” ? YES YES End of erase End of erase * Automatically placed in write disabled state at the end of the erase * Automatically placed in write disabled state at the end of the erase www.onsemi.jp 19 LE25U20AQG Figure 22 Page Program Flowchart Page program Chip erase Start Start 06h 06h Write enable C7h Set chip erase command Write enable 02h Address 1 Start erase on rising edge of CS 05h Set page program command Address 2 Address 3 Set status register read command Data 0 Bit 0 = “0” ? Data n YES NO Start program on rising edge of CS End of erase * Automatically placed in write disabled state at the end of the erase Set status register read command 05h NO Bit 0= “0” ? YES End of programming * Automatically placed in write disabled state at the end of the programming operation. www.onsemi.jp 20 LE25U20AQG ORDERING INFORMATION Device LE25U20AQGTXG Package WDFN8 2x3 (Pb-Free / Halogen Free) Shipping (Qty / Packing) 2000 / Tape & Reel ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. www.onsemi.jp 21