Ordering number : ENA0858 LC87F76C8A CMOS IC FROM 128K byte, RAM 4K byte on-chip http://onsemi.com 8-bit 1-chip Microcontroller Overview The LC87F76C8A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 128K-byte flash ROM (onboard programmable), 4K-byte RAM, an on-chip debugger, an LCD controller/driver, a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer (may be divided into 8-bit timers or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a day and time counter, a synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), a 8-bit 12-channel AD converter, two 12-bit PWM channels, a high-speed clock counter, a system clock frequency divider, a small signal detector, an infrared remote controller receiver function, and a 22source 10-vector interrupt feature. Features Flash ROM • Capable of on-board-programming with a wide range of souce voltages: 3.0 to 5.5V. • Block-erasable in 2-byte units • 131072 × 8 bits (LC87F76C8A) RAM • 4096 × 9 bits (LC87F76C8A) Minimum Bus Cycle Time • 83.3ns (12MHz) VDD=3.0 to 5.5V • 125ns (8MHz) VDD=2.5 to 5.5V • 250ns (4MHz) VDD=2.2 to 5.5V Note: The bus cycle time here refers to the ROM read speed. * This product is licensed from Silicon Storage Technology, Inc. (USA). Semiconductor Components Industries, LLC, 2013 May, 2013 Ver.0.09 30409HKIM 20070523-S00003 No.A0858-1/24 LC87F76C8A Minimum Instruction Cycle Time (tCYC) • 250ns (12MHz) VDD=3.0 to 5.5V • 375ns (8MHz) VDD=2.5 to 5.5V • 750ns (4MHz) VDD=2.2 to 5.5V Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1-bit units Ports whose I/O direction can be designated in 4-bit units • Normal withstand voltage input port • LCD ports Segment output Common output Bias terminals for LCD driver Other functions Input/output ports Input ports • Dedicated oscillator ports • Reset pins • Power pins 23 (P1n, P30 to P31, P70 to P73, P8n, XT2) 8 (P0n) 1 (XT1) 32 (S00 to S31) 4 (COM0 to COM3) 3 (V1 to V3) 32 (PAn, PBn, PCn, PDn,) 7 (PLn) 2 (CF1, CF2) 1 (RES) 6 (VSS1 to VSS3, VDD1 to VDD3) LCD Controller 1) Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias) 2) Segment output and common output can be switched to general-purpose input/output ports Small Signal Detection (MIC signals etc) 1) Counts pulses with the level which is greater than a preset value 2) 2-bit counter Timers • Timer 0: 16-bit timer/counter with two capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with 16-bit capture registers) Mode 3: 16-bit counter (with 16-bit capture registers) • Timer 1: 16-bit timer that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes • Day and time counter 1) Used with a base timer, the day and time counter can be used as a 65000 day + minute + second counter. No.A0858-2/24 LC87F76C8A High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2) Can generate output real-time. SIO • SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits specifiable in 1-bit units, suspension and resumption of data transmission possible in 1-byte units) • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8-data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8-data bits, stop detect) UART • Full duplex • 7/8/9 bit data bits selectable • 1 stop bit (2-bit in continuous data transmission) • Built-in baudrate generator * When using UART, set P0LDDR (PODDR: Bit0) to “0” AD Converter: 12 bits × 12 channels PWM: Multi frequency 12-bit PWM × 2 channels Infrared Remote Control Receiver Circuit 1) Noise reduction function (Time constant of noise reduction filter: approx. 120μs, when selecting a 32.768kHz crystal oscillator as a reference clock.) 2) X’tal HOLD mode cancellation function Watchdog Timer • External RC watchdog timer • Interrupt and reset signals selectable Clock Output Function 1) Can output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 as system clock. 2) Can output the source oscillation clock for the sub clock. No.A0858-3/24 LC87F76C8A Interrupts • 22 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/remote control receiver 4 0001BH H or L INT3/base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/UART1 receive 8 0003BH H or L SIO1/UART1 transmit 9 00043H H or L ADC/MIC/T6/T7/PWM4, PWM5 10 0004BH H or L Port 0/T4/T5 • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. • IFLG (List of interrupt source flag function) 1) Shows a list of interrupt source flags that caused a branching to a particular vector address Subroutine Stack Levels: 2048 levels maximum (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation Circuits • RC oscillation circuit (internal): For system clock • CF oscillation circuit: For system clock, with internal Rf and external Rd • Crystal oscillation circuit: For low-speed system clock, with internal Rf and external Rd • Multifrequency RC oscillation circuit (internal): For system clock 1) Adjustable in ±4% (typ) increments from the selected center frequency. 2) Measures the frequency of the source oscillation clock using the input signal from XT1 as the reference. System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs (at a main clock rate of 10MHz). System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs (at a main clock rate of 10MHz). System Clock Multiplier Function • Allows the 2 or 3 times the clock frequency to be selected when the crystal oscillation output is used as the system clock. No.A0858-4/24 LC87F76C8A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. (Some parts of the serial transfer function stops operation.) 1) Oscillation is not stopped automatically. 2) Canceled by a system reset or occurrence of an interrupt • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, X’tal, and multifrequency RC oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, and INT2, pins to the specified level (3) Having an interrupt source established at port 0 • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer and infrared remote controller circuit. 1) The CF, RC, and multifrequency RC oscillators automatically stop operation 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, and INT2 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit (5) Having an interrupt source established in the infrared remote control receiver circuit On-chip Debugger • Supports software debugging with the IC mounted on the target board. Package Form • QIP80(14×14): • TQFP80J(12×12): Lead-free type Lead-free type Development Tools • On-chip debugger: TCB87-TypeB + LC87F76C8A Flash ROM Programming Board Package Programming Boards QIP80(14×14) W87F71256QF TQFP80J(12×12) W87F71256SQ Flash ROM Programmer Maker Flash Support Group, Inc (Single) Model Supported Version (Note) Device AF9708/AF9709/AF9709B (including models manufactured by Ando LC87F76C8A Electric Co., Ltd.) AF9723 (main unit) (including models manufactured by Ando Flash Support Group, Inc Electric Co., Ltd.) (Gang) AF9833 (unit) LC87F76C8A (including models manufactured by Ando Electric Co., Ltd.) SANYO SKK(SANYO FWS) Application Version: After 1.04 Chip Data Version: After 2.09 LC87F76C8A Note: Check for the latest version. Same Package and Pin Assignment as Mask ROM Version. 1) LC877600 series options can be specified by using flash ROM data. Thus the board used for mass production can be used for debugging and evaluation without modifications. 2) If the program for the mask ROM version is used, the size of the available ROM/RAM spaces is the same as that of the mask ROM version. No.A0858-5/24 LC87F76C8A Package Dimensions Package Dimensions unit : mm (typ) 3255 unit : mm (typ) 3290 17.2 14.0 12.0 60 80 21 61 40 80 21 12.0 40 41 14.0 17.2 61 0.5 41 1 1 0.65 0.25 20 0.15 0.125 (1.25) 0.1 0.1 1.2max (2.7) (1.0) (0.83) 3.0max 20 0.2 0.5 14.0 60 0.8 14.0 SANYO : QFP80(14X14) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 V1/PL4/DBGP0 V2/PL5/DBGP1 V3/PL6/DBGP2 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 S23/PC7 S22/PC6 S21/PC5 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 Pin Assignment SANYO : TQFP80J(12X12) LC87F76C8A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/MICIN/AN7 P70/INT0/T0LCP/AN8 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30/ PWM4 VSS3 VDD3 P31/ PWM5 P00/UTX1* P01/URX1* P02 P03 P04 P05/CKO P06/T6O P07/T7O P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS2 VDD2 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1 S0/PA0 P73/INT3/T0IN/RMIN P72/INT2/T0IN/NKIN P71/INT1/T0HCP/AN9 Top view *When using UART, set P0LDDR (PODDR: Bit0) to “0” SANYO: QFP80(14×14) “Lead-free Type” SANYO: TQFP80J(12×12) “Lead-free Type” No.A0858-6/24 LC87F76C8A System Block Diagram Interrupt control IR Standby control PLA Flash ROM RC VMRC Clock generator CF PC X’tal SIO0 Bus interface ACC SIO1 Port 0 B register Timer 0 (High speed clock counter) Port 1 C register Timer 1 Port 3 ALU Timer 4 Port 7 Timer 5 Port 8 PSW Timer 6 INT0 to INT3 Noise rejection filter RAR Timer 7 Small signal detector RAM LCD controller ADC Stack pointer UART1 Infrared remote control receiver Watchdog timer Base timer Day and time counter On-chip debugger PWM/PWM5 No.A0858-7/24 LC87F76C8A Pin Description Pin Name VSS1 VSS2 VSS3 VDD1 I/O Description Option - - power supply pin No - + power supply pin No • 8-bit I/O port Yes VDD2 VDD3 PORT0 I/O • I/O specifiable in 4-bit units P00 to P07 • Pull-up resistors can be turned on and off in 4-bit units. • Input for HOLD release • Input for port 0 interrupt • Shared pins P00: UART1 transmit * P01: UART1 receive * P05: Clock output (system clock/subclock selectable) P06: Timer 6 toggle output P07: Timer 7 toggle output * When using UART, set P0LDDR (PODDR: Bit0) to “0” PORT1 I/O • 8-bit I/O port Yes • I/O specifiable in 1-bit units P10 to P17 • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output P17: Timer 1PWMH output/beeper output PORT3 I/O Yes • 2-bit I/O port • I/O specifiable in 1-bit units P30 to P31 • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins P30: PWM4 output P31: PWM5 output PORT7 P70 to P73 I/O • 4-bit I/O port No • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD release input/timer 0H capture input P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/ high speed clock counter input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/ infrared remote control receiver input AD converter input ports: AN8 (P70), AN9 (P71) • Interrupt acknowledge type Rising Falling INT0 enable enable INT1 enable enable INT2 enable INT3 enable Rising & H level L level disable enable enable disable enable enable enable enable disable disable enable enable disable disable Falling Continued on next page. No.A0858-8/24 LC87F76C8A Continued from preceding page. Pin Name PORT8 I/O I/O Description • 8-bit I/O port Option No • I/O specifiable in 1-bit units P80 to P87 • Shared pins AD converter input ports: AN0 to AN7 Small signal detector input port: MICIN (P87) S0/PA0 to I/O S7/PA7 S8/PB0 to I/O I/O I/O • Segment output for LCD No • Segment output for LCD No • Can be used as general-purpose I/O port (PD) I/O COM3/PL3 V1/PL4 to No • Can be used as general-purpose I/O port (PC) S31/PD7 COM0/PL0 to • Segment output for LCD • Can be used as general-purpose I/O port (PB) S23/PC7 S24/PD0 to No • Can be used as general-purpose I/O port (PA) S15/PB7 S16/PC0 to • Segment output for LCD • Common output for LCD No • Can be used as general-purpose input port (PL) I/O V3/PL6 • LCD drive bias power supply No • Can be used as general-purpose input port (PL) • Shared pins On-chip debugger pins: DBGP0 (V1) to DBGP2 (V3) RES Input Reset pin No XT1 Input • 32.768kHz crystal oscillator input pin No • Shared pins General-purpose input port Must be connected to VDD1 if not to be used. AD converter input port: AN10 XT2 I/O • 32.768kHz crystal oscillator output pin No • Shared pins General-purpose I/O port Must be set for oscillation and kept open if not to be used. AD converter input port: AN11 CF1 Input CF2 Output Ceramic resonator input pin No Ceramic resonator output pin No No.A0858-9/24 LC87F76C8A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 Option Selected in Units of Output Type Pull-up Resistor 1 CMOS 2 N-channel open drain No 1 CMOS Programmable 2 N-channel open drain Programmable each bit 1 CMOS Programmable 2 N-channel open drain Programmable P70 - No N-channel open drain Programmable P71 to P73 - No CMOS Programmable P80 to P87 - No N-channel open drain No S0/PA0 to S31/PD7 - No CMOS Programmable COM0/PL0 to COM3/PL3 - No Input only No V1/PL4 to V3/PL6 - No Input only No XT1 - No Input only No XT2 - No Output for 32.768kHz crystal oscillator (Nch-open P10 to P17 P30 to P31 each bit Option Type each bit Programmable (Note) drain when in general-purpose output mode) No Note: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07). *1 Connect the IC as shown below to minimize the noise input to the VDD1 pin. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. LSI VDD1 Power supply For backup *2 VDD2 VDD3 VSS1 VSS2 VSS3 *2 The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. Make sure that the port outputs are held at the low level in the HOLD backup mode. No.A0858-10/24 LC87F76C8A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Maximum supply voltage VDD max Supply voltage for VLCD LCD VDD1,VDD2, VDD3 VDD1=VDD2=VDD3 V1/PL4, V2/PL5, VDD1=VDD2=VDD3 V3/PL6 Input voltage VI(1) • Port L • XT1, CF1, RES Input/output VIO(1) voltage min typ max -0.3 +6.5 -0.3 VDD -0.3 VDD+0.3 -0.3 VDD+0.3 unit V • Ports 0, 1, 3, 7, 8 • Ports A, B, C, D • XT2 Peak output IOPH(1) Ports 0, 1 current • CMOS output selected • Per applicable pin IOPH(2) Port 3 • CMOS output selected • Per applicable pin Average Ports 71 to 73 Per applicable pin -5 IOPH(4) Ports A, B, C, D Per applicable pin -5 IOMH(1) Ports 0, 1 • CMOS output selected High level output current • Per applicable pin IOMH(2) Port 3 • CMOS output selected • Per applicable pin Total output -7.5 -15 IOMH(3) Ports 71 to 73 Per applicable pin -3 IOMH(4) Ports A, B, C, D Per applicable pin -3 ΣIOAH(1) Ports 0, 1, 31 Total of currents at all current applicable pins ΣIOAH(2) Port 30 Total of currents at all applicable pins ΣIOAH(3) Ports 0, 1, 3 Total of currents at all applicable pins ΣIOAH(4) Ports 71 to 73 ΣIOAH(5) Ports A, B Total of currents at all applicable pins Total of currents at all applicable pins ΣIOAH(6) Ports C, D Total of currents at all applicable pins ΣIOAH(7) Ports A, B, C, D Total of currents at all applicable pins Low level output current -20 IOPH(3) output current (Note 1-1) -10 -25 -15 -40 mA -5 -25 -25 -45 Peak output IOPL(1) Ports 0, 1 Per applicable pin 20 current IOPL(2) Port 3 Per applicable pin 30 IOPL(3) • Ports 7, 8 Per applicable pin 10 • XT2 IOPL(4) Ports A, B, C, D Per applicable pin 10 Average IOML(1) Ports 0, 1 Per applicable pin 15 output current IOML(2) Port 3 Per applicable pin 20 IOML(3) • Ports 7, 8 Per applicable pin (Note 1-1) 7.5 • XT2 IOML(4) Ports A, B, C, D Per applicable pin 7.5 Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms. Continued on next page. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. No.A0858-11/24 LC87F76C8A Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Total output ΣIOAL(1) Ports 0, 1, 31 current min typ max Total of currents at all 45 applicable pins ΣIOAL(2) Port 30 Total of currents at all 45 Low level output current applicable pins ΣIOAL(3) Ports 0, 1, 3 Total of currents at all 80 applicable pins ΣIOAL(4) ΣIOAL(5) • Ports 7, 8 Total of currents at all • XT2 applicable pins Ports A, B 20 Total of currents at all Ports C, D Total of currents at all 45 applicable pins ΣIOAL(7) Ports A, B, C, D Total of currents at all 80 applicable pins Maximum power Pd max Ta=-20 to+70°C 290 mW dissipation Operating ambient QFP80(14×14) TQFP80J(12×12) Topr temperature Storage ambient mA 45 applicable pins ΣIOAL(6) unit -20 +85 -55 +125 °C Tstg temperature Note 1-1: Average output current refers to the average of output currents measured for a period of 100 ms. Allowable Operating Range at Ta = -20°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Operating VDD(1) supply voltage VDD(2) (Note 2-1) Memory VDD1=VDD2=VDD3 VDD(3) VHD VDD1 sustaining min typ max 0-237μs≤tCYC≤200μs 3.0 5.5 0-356μs≤tCYC≤200μs 2.5 5.5 0-712μs≤tCYC≤200μs 2.2 5.5 2.0 5.5 unit RAM and register contents sustained in HOLD mode supply voltage High level input VIH(1) voltage • Ports 0, 3, 8 Output disabled • Ports A, B, C, D 2.2 to 5.5 • Port L VIH(2) • Port 1 • Output disabled • Ports 71 to 73 • When INT1VTSL=0 • Port 70 port input/ (P71only) 0.3VDD VDD +0.7 V 2.2 to 5.5 0.3VDD +0.7 VDD 2.2 to 5.5 0.85VDD VDD 2.2 to 5.5 0.75VDD VDD 2.2 to 5.5 0.9VDD VDD 2.2 to 5.5 0.75VDD VDD interrupt side VIH(3) Port 71 interrupt side • Output disabled • When INT1VTSL=1 VIH(4) Port 87 small signal Output disabled input side VIH(5) Port 70 watchdog timer side VIH(6) XT1, XT2, CF1, RES Output disabled Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Continued on next page. No.A0858-12/24 LC87F76C8A Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Low level input VIL(1) voltage • Ports 0, 3, 8 Output disabled VSS 4.0 to 5.5 VSS 2.2 to 4.0 VSS 0.2VDD 2.2 to 5.5 VSS 0.45VDD 2.2 to 5.5 VSS 0.25VDD 2.2 to 5.5 VSS 2.2 to 5.5 VSS 0.25VDD 3.0 to 5.5 0.237 200 2.5 to 5.5 0.356 200 2.2 to 5.5 0.712 200 • CF2 pin open 3.0 to 5.5 0.1 12 • System clock frequency 2.5 to 5.5 0.1 8 2.2 to 5.5 0.1 4 • Port 1 • Output disabled • When INT1VTSL=0 (P71 only) interrupt side Port 71 interrupt side VIL(4) Port 87 small signal • Output disabled • When INT1VTSL=1 Output disabled input side VIL(5) Port 70 watchdog Output disabled timer side VIL(6) Instruction cycle XT1, XT2, CF1, RES tCYC time (Note 2-2) External system FEXCF(1) CF1 clock frequency unit 2.2 to 4.0 • Ports 71 to 73 VIL(3) max 0.15VDD VSS • Port L • Port 70 port input/ typ 4.0 to 5.5 • Ports A, B, C, D VIL(2) min +0.4 0.2VDD 0.1VDD +0.4 V 0.8VDD -1.0 μs division ratio=1/1 • External system clock DUTY50±5% • CF2 pin open 3.0 to 5.5 0.2 24.4 • System clock frequency 2.5 to 5.5 0.2 16 2.2 to 5.5 0.2 8 division ratio=1/2 Oscillation FmCF(1) CF1, CF2 frequency range (Note 2-3) • 12MHz ceramic oscillation • See figure 1. FmCF(2) CF1, CF2 • 8MHz ceramic oscillation • See figure 1. FmCF(3) CF1, CF2 • 4MHz ceramic oscillation • See figure 1. FmRC Internal RC oscillation FmVMRC(1) • Multifrequency RC source 3.0 to 5.5 12 2.5 to 5.5 8 2.2 to 5.5 4 MHz 2.2 to 5.5 0.3 1.0 2.0 oscillation • VMRAJ2 to 0=4, 2.2 to 5.5 10 2.2 to 5.5 4 2.2 to 5.5 32.768 VMFAJ2 to 0=0, When VMSL4M=0 FmVMRC(2) • Multifrequency RC source oscillation • VMRAJ2 to 0=4, VMFAJ2 to 0=0, When VMSL4M=1 FsX’tal XT1, XT2 • 32.768kHz crystal oscillation • See figure 2. Multifrequency kHz OpVMRC(1) When VMSL4M=0 2.2 to 5.5 8 10 12 OpVMRC(2) When VMSL4M=1 2.2 to 5.5 3.5 4 4.5 Multifrequency VmADJ(1) VMRAJn 1STEP (Wide range) 2.2 to 5.5 8 24 64 RC oscillation VmADJ(2) VMFAJn 1STEP (Narrow 2.2 to 5.5 1 4 8 RC oscillation usable range adjustment range) MHz % range Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants. No.A0858-13/24 LC87F76C8A Electrical Characteristics at Ta = -20°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High level input IIH(1) • Ports 0, 1, 3, 7, 8 • Output disabled • Ports A, B, C, D • Pull-up resistor off • Port L • VIN=VDD (including output Tr's IIH(2) RES VIN=VDD IIH(3) XT1, XT2 • When configured as input ports current min typ max unit 2.2 to 5.5 1 2.2 to 5.5 1 2.2 to 5.5 1 15 off leakage current) • VIN=VDD Low level input IIH(4) CF1 VIN=VDD 2.2 to 5.5 IIH(5) Port 87 small signal VIN=VBIS+0.5V (VBIS denotes bias voltage) 4.5 to 5.5 4.2 8.5 15 input side 2.2 to 4.5 1.5 5.5 10 • Ports 0, 1, 3, 7, 8 • Output disabled • Ports A, B, C, D • Pull-up resistor off • Port L • VIN=VSS (including output Tr's 2.2 to 5.5 -1 IIL(2) RES VIN=VSS 2.2 to 5.5 -1 IIL(3) XT1, XT2 • When configured as input ports 2.2 to 5.5 -1 -15 IIL(1) current μA off leakage current) • VIN=VSS IIL(4) CF1 VIN=VSS 2.2 to 5.5 IIL(5) Port 87 small signal VIN=VBIS-0.5V (VBIS denotes bias voltage) 4.5 to 5.5 -15 -8.5 -4.2 2.2 to 4.5 -10 -5.5 -1.5 input side High level output VOH(1) CMOS output ports IOH=-1mA 4.5 to 5.5 VDD-1 voltage VOH(2) 0, 1 IOH=-0.4mA 3.0 to 5.5 VDD-0.4 IOH=-0.2mA 2.2 to 5.5 VDD-0.4 VOH(3) VOH(4) CMOS output ports IOH=-10mA 4.5 to 5.5 VDD-1.5 VOH(5) 30, 31 IOH=-1.6mA 3.0 to 5.5 VDD-0.4 IOH=-1mA 2.2 to 5-5 VDD-0.4 IOH=-0.4mA 3.0 to 5.5 VDD-0.4 IOH=-0.2mA 2.2 to 5.5 VDD-0.4 IOH=-1mA 4.5 to 5.5 VDD-1 VOH(10) IOH=-0.4mA 3.0 to 5.5 VDD-0.4 VOH(11) IOH=-0.2mA 2.2 to 5.5 VDD-0.4 IOL=10mA 4.5 to 5.5 1.5 IOL=1.6mA 3.0 to 5.5 0.4 VOH(6) VOH(7) Ports 71 to 73 VOH(8) VOH(9) Low level output voltage VOL(1) VOL(2) Ports A, B, C, D Ports 0, 1 • Port 3 (PWM4, 5 function output VOL(3) mode) IOL=1mA 2.2 to 5.5 0.4 VOL(4) Port 3 IOL=30mA 4.5 to 5.5 1.5 VOL(5) (Port function output IOL=5mA 3.0 to 5.5 0.4 IOL=2.5mA 2.2 to 5.5 0.4 VOL(6) mode) VOL(7) • Ports 7, 8 IOL=1.6mA 3.0 to 5.5 0.4 VOL(8) • XT2 IOL=1mA 2.2 to 5.5 0.4 VOL(9) Ports A, B, C, D IOH=1.6mA 3.0 to 5.5 0.4 IOL=1mA 2.2 to 5.5 0.4 VOL(10) LCD output VODLS S0 to S31 voltage deviation V • IO=0mA • VLCD, 2/3VLCD 1/3VLCD level output 2.2 to 5.5 0 ±0.2 2.2 to 5.5 0 ±0.2 • See Fig. 8. VODLC COM0 to COM3 • IO=0mA • VLCD, 2/3VLCD 1/2VLCD, 1/3VLCD level output • See Fig. 8. LCD bias resistor RLCD(1) Resistance per See Fig. 8. one bias resister RLCD(2) • Resistance per one bias resister • 1/2 resistance 2.2 to 5.5 60 2.2 to 5.5 30 See Fig. 8. kΩ mode Continued on next page. No.A0858-14/24 LC87F76C8A Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Pull-up MOS Tr. Rpu(1) • Ports 0, 1, 3, 7 resistance Rpu(2) • Ports A, B, C, D Hysteresis voltage VHYS(1) • Ports 1, 7 VOH=0-9VDD • RES VHYS(2) Port 87 small signal CP All pins typ max 15 35 80 2.2 to 4.5 18 50 150 unit kΩ 2.2 to 5.5 0.1VDD 2.2 to 5.5 0.1VDD 2.2 to 5.5 10 V input side Pin capacitance min 4.5 to 5.5 • VIN=VSS for pins other than that under test • f=1MHz pF • Ta=25°C Input sensitivity Vsen Port 87 small signal 2.2 to 5.5 input side 0.12VDD Vp-p Serial I/O Characteristics at Ta = -20°C to +85°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Specification Parameter Symbol Pin/Remarks Conditions Input clock VDD[V] Frequency tSCK(1) Low level tSCKL(1) SCK0(P12) See Fig. 6. typ tSCKH(1) 2.2 to 5.5 pulse width tSCKHA(1) 1 tCYC • Continuous data 4 Serial clock • See Fig. 6. • (Note 4-1-2) Frequency tSCK(2) SCK0(P12) • CMOS output selected 4/3 • See Fig. 6. Output clock Low level tSCKL(2) 1/2 pulse width High level tSCK tSCKH(2) 2.2 to 5.5 pulse width tSCKHA(2) 1/2 • Continuous data tSCKH(2) transmission/reception mode +2tCYC • CMOS output selected • See Fig. 6. Data setup time Serial input unit 1 transmission/reception mode tsDI(1) SB0(P11), SI0(P11) Data hold time respect to rising edge of • See Fig. 6. thDI(1) tSCKH(2) +(10/3) tCYC tCYC • Must be specified with SIOCLK 0.03 2.2 to 5.5 0.03 Input clock Output delay tdDO(1) time SO0(P10), SB0(P11) • Continuous data (1/3)tCYC transmission/reception mode +0.05 • (Note 4-1-3) tdDO(2) • Synchronous 8-bit mode tdDO(3) μs 1tCYC • (Note 4-1-3) 2.2 to 5.5 Output clock Serial output max 2 pulse width High level min +0.05 (Note 4-1-3) (1/3)tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous transmission/reception mode, a time from SI0RUN being set when serial clock is "H" to the first falling edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. No.A0858-15/24 LC87F76C8A 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Specification Parameter Symbol Pin/Remarks Conditions Input clock Frequency tSCK(3) Low level tSCKL(3) SCK1(P15) typ See Fig.6. 2.2 to 5.5 tSCK(4) tCYC 1 SCK1(P15) • CMOS output selected 2 • See Fig. 6. Low level tSCKL(4) 2.2 to 5.5 pulse width High level 1/2 tSCK tSCKH(4) 1/2 pulse width Serial input Data setup time SB1(P14), SI1(P14) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 6. Data hold time thDI(2) 0.03 2.2 to 5.5 0.03 Output delay Serial output tsDI(2) unit 1 tSCKH(3) Frequency max 2 pulse width High level min pulse width Output clock Serial clock VDD[V] tdDO(4) time SO1(P13), SB1(P14) μs • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state (1/3)tCYC 2.2 to 5.5 +0.05 change in open drain output mode. • See Fig. 6. Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Pulse Input Conditions at Ta = -20°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High/low level tPIH(1) INT0(P70), • Interrupt source flag can be set. pulse width tPIL(1) INT1(P71), • Event inputs for timer 0 are INT2(P72) INT3(P73) when • Interrupt source flag can be set. tPIL(2) noise filter time • Event inputs for timer 0 are INT3(P73) when • Interrupt source flag can be set. tPIL(3) noise filter time • Event inputs for timer 0 are INT3(P73) when • Interrupt source flag can be set. tPIL(4) noise filter time • Event inputs for timer 0 are tPIH(5) MICIN(P87) tPIL(5) tPIH(6) RMIN(P73) 2 2.2 to 5.5 64 2.2 to 5.5 256 2.2 to 5.5 1 2.2 to 5.5 3 The pulses can be counted by the 2.2 to 5.5 2000 The pulses can be recognized as signals by the infrared remote control receiver circuit. tPIL(7) RES tCYC enabled. small signal sensor/counter. tPIL(6) 2.2 to 5.5 unit enabled. tPIH(4) constant is 1/128 1 max enabled. tPIH(3) constant is 1/32 2.2 to 5.5 typ enabled. tPIH(2) constant is 1/1 min Resetting is enabled. RMCK (Note5-1) μs Note 5-1: RMCK denotes the frequency of the base clock (1tCYC to 128tCYC/subclock source oscillation frequency) for the infrared remote control receiver circuit No.A0858-16/24 LC87F76C8A AD Converter Characteristics at VSS1 = VSS2 = 0V <12bits AD Converter Mode at Ta =-30 to +70°C> Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Resolution N AN0(P80) Absolute ET to AN7(P87), Conversion tCAD time Analog input 3.0 to 5.5 (Note 6-1) typ max AN9(P71), See conversion time calculation AN10(XT1), formulas. AN11(XT2) (Note 6-2) ±16 32 100 3.0 to 5.5 40 100 VSS VDD VAIN IAINH VAIN=VDD input current IAINL VAIN=VSS bit 4.0 to 5.5 voltage range Analog port unit 12 3.0 to 5.5 AN8(P70), accuracy min 1 5 -1 LSB μs V μA <8bits AD Converter Mode at Ta =-30 to +70°C> Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Resolution N AN0(P80) Absolute ET to AN7(P87), Conversion 3.0 to 5.5 (Note 6-1) tCAD time AN9(P71), See "Conversion time calculation AN10(XT1) method." AN11(XT2) (Note 6-2) typ max unit 8 3.0 to 5.5 AN8(P70), accuracy min bit 1.5 4.0 to 5.5 20 90 3.0 to 5.5 40 90 LSB μs See "Conversion time calculation method." 3.0 to 5.5 (Note 6-2) VSS VDD Ta=-10 to 50°C Analog input VAIN 3.0 to 5.5 voltage range 1 Analog port IAINH VAIN=VDD 3.0 to 5.5 -1 input current IAINL VAIN=VSS 3.0 to 5.5 -1 V μA <Conversion time calculation method> 12bits AD Converter Mode: tCAD (conversion time) = ((52/(division ratio)) + 2) × (1/3)×tCYC 8bits AD Converter Mode: tCAD (conversion time) = ((32/(division ratio)) + 2) × (1/3)×tCYC <Recommended Operating Conditions> External Supply Voltage System Clock oscillator Range Division FmCF[MHz] VDD[V] (SYSDIV) Cycle Time tCYC [ns] AD Frequency Conversion Time (tCAD)[μs] Division Ratio (ADDIV) 12-bit AD 8-bit AD 4.0 to 5.5 1/1 250 1/8 34.8 21.5 3.0 to 5.5 1/1 250 1/16 69.5 42.8 12 Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value. The absolute accuracy refers to the accuracy that is measured while there is no change in the I/O state of the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the time the complete digital- conversion-value corresponding to the analog input value is loaded in the required register. No.A0858-17/24 LC87F76C8A Consumption Current Characteristics at Ta = -20°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Normal mode Symbol Conditions rks VDD[V] • FmCF=12MHz ceramic oscillation mode consumption VDD1 =VDD2 current =VDD3 • System clock set to 12MHz side (Note 7-1) IDDOP(1) Specification Pin/Rema IDDOP(2) • FmX’tal=32.768kHz crystal oscillation mode min typ max 4.5 to 5.5 8.2 18.0 3.0 to 3.6 4.8 10.6 4.5 to 5.5 6.4 13.9 3.0 to 3.6 3.8 8.8 2.5 to 3.0 3.0 6.7 4.5 to 5.5 3.9 8.5 3.0 to 3.6 2.5 5.2 2.2 to 3.0 2.1 4.3 4.5 to 5.5 0.7 1.6 3.0 to 3.6 0.4 0.9 2.2 to 3.0 0.3 0.7 4.5 to 5.5 7.6 16.7 3.0 to 3.6 4.3 9.5 4.5 to 5.5 4.1 8.9 3.0 to 3.6 2.3 5.0 2.2 to 3.0 2.0 4.1 4.5 to 5.5 41.8 171.4 3.0 to 3.6 17.7 84.3 2.2 to 3.0 13 67.2 unit • Internal RC oscillation stopped • Multifrequency RC oscillation stopped • 1/1 frequency division ratio IDDOP(3) • FmCF=8MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode IDDOP(4) • System clock set to 8MHz side • Internal RC oscillation stopped IDDOP(5) • Multifrequency RC oscillation stopped • 1/1 frequency division ratio IDDOP(6) • FmCF=4MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode IDDOP(7) • System clock set to 4MHz side • Internal RC oscillation stopped IDDOP(8) • Multifrequency RC oscillation stopped • 1/2 frequency division ratio IDDOP(9) • FmCF=0Hz (oscillation stopped) mA • FmX’tal=32.768kHz crystal oscillation mode IDDOP(10) IDDOP(11) IDDOP(12) • System clock set to internal RC oscillation • Multifrequency RC oscillation stopped • 1/2 frequency division ratio • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped IDDOP(13) • System clock set to 10MHz multifrequency RC oscillation • 1/1 frequency division ratio IDDOP(14) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDOP(15) • Internal RC oscillation stopped • System clock set to 4MHz multifrequency IDDOP(16) RC oscillation • 1/1 frequency division ratio IDDOP(17) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDOP(18) • System clock set to 32.768kHz side • Internal RC oscillation stopped IDDOP(19) μA • Multifrequency RC oscillation stopped • 1/2 frequency division ratio Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.A0858-18/24 LC87F76C8A Continued from preceding page. Parameter HALT mode Symbol IDDHALT(1) Specification Pin/ Conditions Remarks VDD[V] HALT mode consumption VDD1 =VDD2 current =VDD3 • FmX’tal=32.768kHz crystal oscillation mode (Note 7-1) • FmCF=12MHz ceramic oscillation min typ max 4.5 to 5.5 3.7 8.2 3.0 to 3.6 1.9 4.3 4.5 to 5.5 6.4 13.9 3.0 to 3.6 3.8 8.8 2.5 to 3.0 3.0 6.7 4.5 to 5.5 3.9 8.5 3.0 to 3.6 2.5 5.2 2.2 to 3.0 2.1 4.3 4.5 to 5.5 0.4 0.9 3.0 to 3.6 0.18 0.4 2.2 to 3.0 0.13 0.3 4.5 to 5.5 3.4 7.3 3.0 to 3.6 1.7 3.7 4.5 to 5.5 1.7 3.9 3.0 to 3.6 0.8 1.8 2.2 to 3.0 0.6 1.4 4.5 to 5.5 25.7 141.9 3.0 to 3.6 8.3 66.6 2.2 to 3.0 5.2 52.3 HOLD mode 4.5 to 5.5 0.14 28.0 • CF1=VDD or open 3.0 to 3.6 0.03 19.0 unit • System clock set to 12MHz side. IDDHALT(2) • Internal RC oscillation stopped • Multifrequency RC oscillation stopped • 1/1 frequency division ratio IDDHALT(3) HALT mode • FmCF=8MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(4) • System clock set to 8MHz side • Internal RC oscillation stopped IDDHALT(5) • Multifrequency RC oscillation stopped • 1/1 frequency division ratio IDDHALT(6) HALT mode • FmCF=4MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(7) • System clock set to 4MHz side • Internal RC oscillation stopped IDDHALT(8) • Multifrequency RC oscillation stopped • 1/2 frequency division ratio IDDHALT(9) HALT mode • FmCF=0Hz (oscillation stopped) IDDHALT(10) • FmX’tal=32.768kHz crystal oscillation mode mA • System clock set to internal RC oscillation IDDHALT(11) • Multifrequency RC oscillation stopped • 1/2 frequency division ratio IDDHALT(12) HALT mode • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped IDDHALT(13) • System clock set to 10MHz multifrequency RC oscillation • 1/1 frequency division ratio IDDHALT(14) HALT mode • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(15) • Internal RC oscillation stopped • System clock set to 4MHz multifrequency RC IDDHALT(16) oscillation • 1/1 frequency division ratio IDDHALT(17) HALT mode • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(18) • System clock set to 32.768kHz side • Internal RC oscillation stopped IDDHALT(19) • Multifrequency RC oscillation stopped • 1/2 frequency division ratio HOLD mode consumption current Clock HOLD mode IDDHOLD(1) IDDHOLD(2) (external clock mode) IDDHOLD(3) IDDHOLD(4) IDDHOLD(5) VDD1 Clock HOLD mode • CF1=VDD or open (external clock mode) consumption current VDD1 IDDHOLD(6) • FmX’tal=32.768kHz crystal oscillation mode 2.2 to 3.0 0.03 16.0 4.5 to 5.5 21.9 80 3.0 to 3.6 6.3 37 2.2 to 3.0 3.6 30 μA Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. No.A0858-19/24 LC87F76C8A F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Onboard IDDFW(1) VDD1 programming min typ max unit • 128-byte programming • Erasing current included 3.0 to 5.5 mA 3.0 to 5.5 ms current Programming tFW(1) • 128-byte programming time • Erasing current included • Time for setting up 128-byte data is excluded. UART (Full Duplex) Operating Conditions at Ta = -20 to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Transfer rate UBR UTX(P00), 2.2 to 5.5 URX(P01) min typ max 16/3 8192/3 unit tCYC Data length: 7/8/9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission mode) Parity bits: None Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H) Start bit Start of transmission Stop bit Transmit data (LSB first) End of transmission UBR Example of 8-bit Data Reception Mode Processing (Receive Data=55H) Stop bit Start bit Start of reception Receive data (LSB first) End of reception UBR *When using UART, set P0LDDR (PODDR: Bit0) to “0” No.A0858-20/24 LC87F76C8A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Vendor Frequency Name 12MHz MURATA 8MHz MURATA 4MHz Circuit Constant Oscillator Name Operating Oscillation Voltage Stabilization Time C1 C2 Rf1 Rd1 Range typ max [pF] [pF] [Ω] [Ω] [V] [ms] [ms] CSTCE12M0G52-R0 (10) (10) Open 2.2k 2.8 to 5.5 CSTCE8M00G52-R0 (10) (10) Open 1.0k CSTLS8M00G52-R0 (15) (15) Open 1.0k Built-in C1, C2 Built-in 2.5 to 5.5 CSTCR4M00F53-R0 (15) (15) Open 2.2k CSTLS4M0053-B0 (15) (15) Open 2.2k MURATA Remarks C1, C2 Built-in 2.1 to 5.5 C1, C2 The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4). Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator Nominal Vendor Name Frequency Circuit Constant Oscillator Name Operating C3 C4 Rf2 Rd2 [pF] [pF] [Ω] [Ω] Voltage Range [V] Oscillation Stabilization Time typ max [s] [s] Remarks 32.768kHz The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 4). Caution: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF1 XT1 CF2 Rf1 Rf2 Rd1 C1 C2 XT2 Rd2 C3 C4 CF X’tal Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A0858-21/24 LC87F76C8A VDD Operating VDD lower limit 0V Power supply Reset time RES Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal absent HOLD release signal VALID Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 State HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times No.A0858-22/24 LC87F76C8A VDD Note: Determine the value of CRES and RRES so that the reset signal is present for a period of 200μs after the supply voltage goes beyond the lower limit of the IC's operating voltage. RRES RES CRES Figure 5 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DI7 DI8 DO7 DO8 Data RAM transfer period (SIO0 only) tSCK tSCKH tSCKL SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 only) tSCKL tSCKHA SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 6 Serial I/O Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.A0858-23/24 LC87F76C8A VDD SW : ON/OFF (programmable) RLCD RLCD SW: ON when VLCD=VDD RLCD RLCD VLCD RLCD RLCD 2/3VLCD RLCD 1/2VLCD RLCD 1/3VLCD RLCD RLCD GND Figure 8 LCD Bias Resistors ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No.A0858-24/24