NCP1060 - High Voltage Switcher for Low Power Offline SMPS

NCP1060, NCP1063
High-Voltage Switcher for
Low Power Offline SMPS
The NCP106X products integrate a fixed frequency current mode
controller with a 700 V MOSFET. Available in a PDIP−7, SOIC−10 or
SOIC−16 package, the NCP106X offer a high level of integration,
including soft−start, frequency−jittering, short−circuit protection,
skip−cycle, adjustable peak current set point, ramp compensation, and a
Dynamic Self−Supply (eliminating the need for an auxiliary winding).
Unlike other monolithic solutions, the NCP106X is quiet by nature:
during nominal load operation, the part switches at one of the available
frequencies (60 kHz or 100 kHz). When the output power demand
diminishes, the IC automatically enters frequency foldback mode and
provides excellent efficiency at light loads. When the power demand
reduces further, it enters into a skip mode to reduce the standby
consumption down to a no load condition.
Protection features include: a timer to detect an overload or a
short−circuit event, Overvoltage Protection with auto−recovery and
AC input line voltage detection (A version).
The ON proprietary integrated Over Power Protection (OPP) lets
you harness the maximum delivered power without affecting your
standby performance simply via external resistors.
For improved standby performance, the connection of an auxiliary
winding stops the DSS operation and helps to reduce input power
consumption below 50 mW at high line.
NCP106x can be seamlessly used both in non−isolated and in
isolated topologies.
Features
• Built−in 700 V MOSFET with RDS(on) of 34 W (NCP1060) and
11.4 W (NCP1063)
• Large Creepage Distance Between High−voltage Pins
• Current−Mode Fixed Frequency Operation – 60 kHz or 100 kHz
•
•
•
•
•
•
•
•
•
•
•
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MARKING DIAGRAMS
7
PDIP−7
CASE 626A
AP SUFFIX
8
1
P106xfyyy
AWL
YYWWG
1
16
1
16
SOIC−16
CASE 751B−05
D SUFFIX
1
NCP1063fyyyG
AWLYWW
10
10
1
SOIC−10
CASE 751BQ
AD or BD SUFFIX
1060fyyy
ALYWX
G
1
x = Power Switch Circuit On−state Resistance
x = (0 = 34 W, 3 = 11.4 W)
f = Brown In (A = Yes, B = No)
yyy = Oscillator Frequency
yyy = (060 = 60 kHz, 100 = 100 kHz)
A
= Assembly Location
L, WL = Wafer Lot
Y, YY
= Year
W, WW = Work Week
G or G = Pb−Free Package
(130 kHz on demand)
Adjustable Peak Current: see below table
ORDERING INFORMATION
See detailed ordering and shipping information in the package
Fixed Ramp Compensation
dimensions section on page 26 of this data sheet.
Direct Feedback Connection for Non−isolated Converter
Internal and Adjustable Over Power Protection (OPP) Circuit
Skip−Cycle Operation at Low Peak Currents Only
Dynamic Self−Supply: No Need for an Auxiliary
• Frequency Foldback to Improve Efficiency at Light
Winding
Load
Internal 4 ms Soft−Start
• These are Pb−Free Devices
Auto−Recovery Output Short Circuit Protection with
Typical Applications
Timer−Based Detection
• Auxiliary / Standby Isolated and Non−isolated Power
Auto−Recovery Overvoltage Protection with Auxiliary
Supplies
Winding Operation
• Power Meter SMPS
Frequency Jittering for Better EMI Signature
• Wide Vin Low Power Industrial SMPS
No Load Input Consumption < 50 mW
© Semiconductor Components Industries, LLC, 2015
February, 2015 − Rev. 0
1
Publication Order Number:
NCP1060/D
NCP1060, NCP1063
PRODUCT INFORMATION & INDICATIVE MAXIMUM OUTPUT POWER
230 Vac + 15%
85 − 265 Vac
Product
RDS(on)
IIPK(0)
Adapter
Open Frame
Adapter
Open Frame
NCP1060 60 kHz
34 W
300 mA
3.3 W
8.3 W
1.9 W
4.7 W
NCP1063 100 kHz
11.4 W
780 mA
6.2 W
15.5 W
3.3 W
7.8 W
NOTE:
Informative values only, with Tamb = 25°C, Tcase = 100°C, PDIP−7 package, Self supply via Auxiliary winding and circuit mounted
on minimum copper area as recommended.
GND
DRAIN
DRAIN
GND
GND
DRAIN
VCC
DRAIN
GND
GND
VCC
LIM/OPP
LIM/OPP
FB
COMP
DRAIN
DRAIN
N.C.
N.C.
N.C.
N.C.
FB
COMP
PDIP−7
GND
VCC
LIM/OPP
FB
COMP
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
SOIC−10
SOIC−16
Figure 1. Pin Connections
Table 1. PIN FUNCTION DESCRIPTION
Pin No
PDIP 7
SOIC 10
SOIC 16
Pin Name
Function
1
1
1−4
GND
The IC Ground
2
2
5
VCC
Powers the internal
circuitry
This pin is connected to an external capacitor. The VDD
includes an auto−recovery over voltage protection.
3
3
6
LIM/OPP
Ipeak set / Over
power limitation
The current drown from the pin decreases Ipeak of the
primary winding. If resistive divider from the auxiliary
winding is connected to this pin it sets the OPP compensation level (it diminishes the peak current.)
4
4
7
FB
Feedback signal
input
This is the inverting input of the trans conductance error
amplifier. It is normally connected to the switching power
supply output through a resistor divider.
5
5
8
Comp
Compensation
The error amplifier output is available on this pin. The
network connected between this pin and ground adjusts
the regulation loop bandwidth. Also, by connecting an
opto−coupler to this pin, the peak current set point is
adjusted accordingly to the output power demand.
6
7,8
9−12
6−10
13−16
Pin Description
This un−connected pin ensures adequate creepage distance
Drain
Drain connection
The internal drain MOSFET connection
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2
NCP1060, NCP1063
Figure 2. Typical Non−isolated Application (Buck Converter)
Figure 3. Typical Isolated Application (Flyback Converter)
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3
NCP1060, NCP1063
DRAIN
VCC
80−ms Filter
SCP
VOVP
I pflag
UVLO
Reset
Vdd
VCC
Management
VCC OVP
S
OFF UVLO
Q
t SCP
R
trecovery
LineOK
Line
Detection
UVLO
OFF
LineOK
Jittering
TSD
VCOMP(REF )
OSC
VCC
Sawtooth
R COMP(up)
S
Foldback
Q
Sawtooth
R
ICOMPskip
SKIP
Ramp
compensation
SKIP = ”1” è Shut down some
blocks to reduce consumption
COMP
FB/COMP
Processing
GND
LEB
Ipflag
ICOMPfault
ICOMP to CS setpoint
Reset
I Freeze
I LMDEC
IFB
Soft−Start
Ipk(0)
Reset SS as recoving from
SCP, TSD, VCC OVP or UVLO
FB
ILMOP (min)
0
ILMDEC
ILMOP (max )
ILMOP
I LMOP
IPKL
VLMOP
LIM/OPP
Figure 4. Simplified Internal Circuit Architecture
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NCP1060, NCP1063
Table 2. MAXIMUM RATING TABLE (All voltages related to GND terminal)
Symbol
Value
Unit
VCC
−0.3 to 20
V
Voltage on all pins, except Drain and VCC pin
Vinmax
−0.3 to 10
V
Drain voltage
BVdss
−0.3 to 700
V
ICC
10
mA
Rating
Power supply voltage, VCC pin, continuous voltage
Maximum Current into VCC pin
Drain Current Peak during Transformer Saturation (TJ = 150°C):
NCP1060
NCP1063
Drain Current Peak during Transformer Saturation (TJ = 125°C):
NCP1060
NCP1063
Drain Current Peak during Transformer Saturation (TJ = 25°C):
NCP1060
NCP1063
IDS(PK)
mA
Thermal Resistance Junction−to−Air – PDIP7 with 200 [email protected] of 35−m copper area
RθJ−A
115
°C/W
Thermal Resistance Junction−to−Air – SOIC10 with 200 [email protected] of 35−m copper area
RθJ−A
132
°C/W
Thermal Resistance Junction−to−Air – SOIC16 with 200 [email protected] of 35−m copper area
RθJ−A
104
°C/W
Maximum Junction Temperature
TJMAX
150
°C
−60 to +150
°C
300
850
335
950
520
1500
Storage Temperature Range
Human Body Model ESD Capability (All pins except HV pin) per JEDEC JESD22−A114F
HBM
2
kV
Charged−Device Model ESD Capability per JEDEC JESD22−C101E
CDM
1
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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NCP1060, NCP1063
Table 3. ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 14 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
SUPPLY SECTION AND VCC MANAGEMENT
VCC(on)
VCC increasing level at which the switcher starts operation
2 (5)
8.4
9.0
9.5
V
VCC(min)
VCC decreasing level at which the HV current source restarts
2 (5)
7.0
7.5
7.8
V
VCC(off)
VCC decreasing level at which the switcher stops operation (UVLO)
2 (5)
6.7
7.0
7.2
V
Internal IC consumption, NCP1060 switching at 60 kHz, LIM/OPP = 0 A
Internal IC consumption, NCP1060 switching at 100 kHz, LIM/OPP = 0 A
Internal IC consumption, NCP1063 switching at 60 kHz, LIM/OPP = 0 A
Internal IC consumption, NCP1063 switching at 100 kHz, LIM/OPP = 0 A
2 (5)
−
−
−
−
0.92
0.97
0.99
1.07
1.05
1.10
1.12
1.22
mA
Internal IC consumption, COMP is 0 V (No switching on MOSFET)
2 (5)
−
340
−
mA
ICC1
ICCskip
POWER SWITCH CIRCUIT
Power Switch Circuit on−state resistance
NCP1060 (Id = 50 mA)
Tj = 25°C
Tj = 125°C
NCP1063 (Id = 50 mA)
Tj = 25°C
Tj = 125°C
7, 8
(6−10)
(13−16)
BVDSS
Power Switch Circuit & Startup breakdown voltage
(ID(off) = 120 mA, Tj = 25°C)
IDSS(off)
RDS(on)
tr
tf
ton(min)
W
−
−
34
65
41
72
−
−
11.4
22
14.0
24
7, 8
(6−10)
(13−16)
700
−
−
V
Power Switch & Startup breakdown voltage off−state leakage current
Tj = 125°C (Vds = 700 V)
7, 8
(6−10)
(13−16)
−
84
−
mA
Switching characteristics (RL = 50 W, VDS set for Idrain = 0.7 x Ilim)
Turn−on time (90% − 10%)
Turn−off time (10% − 90%)
7, 8
(6−10)
(13−16)
−
−
20
10
−
−
Minimum on time
NCP1060
NCP1063
7, 8
(6−10)
(13−16)
−
−
200
230
−
−
ns
ns
INTERNAL START−UP CURRENT SOURCE
Istart1
High−voltage current source, VCC = VCC(on) – 200 mV
7, 8
(6−10)
(13−16)
5
8
12
mA
Istart2
High−voltage current source, VCC = 0 V
7, 8
(6−10)
(13−16)
−
0.5
−
mA
2 (5)
−
1.4
−
V
21
V
VCCTH
Vstart(min)
VCC Transient level for Istart1 to Istart2 toggling point
Minimum startup voltage, VCC = 0 V
7, 8
(6−10)
(13−16)
CURRENT COMPARATOR
IIPK
IIPK(0)
Maximum internal current setpoint at 50% duty cycle
FB = 2 V, LIM/OPP = 0 mA, Tj = 25°C
NCP1060
NCP1063
mA
−
−
Maximum internal current setpoint at beginning of switching cycle
FB = 2 V, LIM/OPP pin open Tj = 25°C
NCP1060
NCP1063
−
−
250
650
−
−
mA
−
−
268
702
300
780
332
858
2. The final switch current is: IIPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage,
LP the primary inductor in a flyback, and tprop the propagation delay.
3. Oscillator frequency is measured with disabled jittering.
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NCP1060, NCP1063
Table 3. ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 14 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
CURRENT COMPARATOR
IIPKSW
IIPKSW
ILMDEC
Final switch current with a primary slope of 200 mA/ms,
FSW = 60 kHz (Note 2), LIM/OPP pin open
NCP1060
NCP1063
Final switch current with a primary slope of 200 mA/ms,
FSW = 100 kHz (Note 2), LIM/OPP pin open
NCP1060
NCP1063
mA
−
−
−
−
330
740
−
−
mA
−
−
−
−
320
710
−
−
Maximum internal current setpoint at beginning of switching cycle
FB = 2 V, LIM/OPP = −285 mA, Tj = 25°C
NCP1060
NCP1063
mA
−
−
−
−
128
312
−
−
tSS
Soft−start duration (guaranteed by design)
−
−
4
−
ms
tprop
Propagation delay from current detection to drain OFF state
−
−
70
−
ns
tLEB
Leading Edge Blanking Duration
NCP1060
NCP1063
−
−
−
−
130
160
−
−
ns
INTERNAL OSCILLATOR
fOSC
Oscillation frequency, 60 kHz version, Tj = 25°C (Note 3)
−
54
60
66
kHz
fOSC
Oscillation frequency, 100 kHz version, Tj = 25°C (Note 3)
−
90
100
110
kHz
fjitter
Frequency jittering in percentage of fOSC
−
−
±6
−
%
fswing
Jittering swing frequency
−
−
300
−
Hz
Dmax
Maximum duty−cycle
−
62
66
72
%
Voltage Feedback Input (VCOMP = 2.5 V)
4 (7)
3.2
3.3
3.4
V
IFB
Input Bias Current (VFB = 3.3 V)
4 (7)
−
1
−
mA
GM
ERROR AMPLIFIER SECTION
VREF
Transconductance
5 (8)
2
mS
IOTAlim
OTA maximum current capability (VFB > VOTAen)
5 (8)
±150
mA
VOTAen
FB voltage to disable OTA
4 (7)
0.7
1.3
1.7
V
COMPENSATION SECTION
ICOMPfault
COMP current for which Fault is detected
5 (8)
−
−40
−
mA
ICOMP100%
COMP current for which internal current set−point is 100% (IIPK(0))
5 (8)
−
−44
−
mA
ICOMPfreeze
COMP current for which internal current setpoint is:
IFreeze1 or 2 (NCP1060/3)
5 (8)
−
−80
−
mA
VCOMP(REF)
Equivalent pull−up voltage in linear regulation range
(Guaranteed by design)
5 (8)
−
2.7
−
V
Equivalent feedback resistor in linear regulation range
(Guaranteed by design)
5 (8)
−
17.7
−
kΩ
VLMOP
Voltage on LIM/OPP pin @ ILMOP = −35 mA
Voltage on LIM/OPP pin @ ILMOP = −250 mA, Tj = 25°C
3 (6)
1.40
1.28
1.50
1.35
1.60
1.42
V
ILMOP
−330
−420
mA
−26
−32
mA
RCOMP(up)
Maximum current from LIM/OPP pin
3 (6)
ILMOP(min)
Current at which LIM/OPP starts to decrease IPEAK
3 (6)
ILMOP(max)
Current at which LIM/OPP stops to decrease IPEAK
3 (6)
−285
mA
ILMOP(neg)
Negative Active Clamp Voltage (ILMOP = −2.5 mA)
3 (6)
−0.7
V
−20
2. The final switch current is: IIPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage,
LP the primary inductor in a flyback, and tprop the propagation delay.
3. Oscillator frequency is measured with disabled jittering.
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NCP1060, NCP1063
Table 3. ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 14 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
COMPENSATION SECTION
ILMOP(pos)
Positive Active Clamp (Guaranteed by design)
3 (6)
2.5
mA
FREQUENCY FOLDBACK & SKIP
ICOMPfold
Start of frequency foldback COMP pin current level
ICOMPfold(end) End of frequency foldback COMP pin current level, fsw = fmin
5 (8)
−
−68
−
mA
5 (8)
−
−100
−
mA
kHz
fmin
The frequency below which skip−cycle occurs
−
21
25
29
ICOMPskip
The COMP pin current level to enter skip mode
5 (8)
−
−120
−
mA
IFreeze1
Internal minimum current setpoint (ICOMP = ICOMPFreeze) in NCP1060
−
110
−
mA
IFreeze2
Internal minimum current setpoint (ICOMP = ICOMPFreeze) in NCP1063
−
270
−
mA
RAMP COMPENSATION
Sa(60)
Sa(100)
The internal ramp compensation @ 60 kHz:
NCP1060
NCP1063
−
−
−
−
8.4
15.6
−
−
The internal ramp compensation @ 100 kHz:
NCP1060
NCP1063
−
−
−
−
14
26
−
−
Fault validation further to error flag assertion
−
35
48
−
ms
OFF phase in fault mode
−
−
400
−
ms
1 (5)
17.0
18.0
18.8
V
−
−
80
−
ms
7,8
(6−10)
(13−16)
67
87
110
V
mA/ms
mA/ms
PROTECTIONS
tSCP
trecovery
VOVP
VCC voltage at which the switcher stops pulsing
tOVP
The filter of VCC OVP comparator
VHV(EN)
The drain pin voltage above which allows MOSFET operate, which is
detected after TSD, UVLO, SCP, or VCC OVP mode. (A version only)
TEMPERATURE MANAGEMENT
TSD
Temperature shutdown (Guaranteed by design)
−
150
163
−
°C
TSDhyst
Hysteresis in shutdown (Guaranteed by design)
−
−
20
−
°C
2. The final switch current is: IIPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage,
LP the primary inductor in a flyback, and tprop the propagation delay.
3. Oscillator frequency is measured with disabled jittering.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCP1060, NCP1063
TYPICAL CHARACTERISTICS
9.15
7.52
7.50
7.48
9.05
VOLTAGE (V)
VOLTAGE (V)
9.10
9.00
8.95
7.46
7.44
7.42
7.40
7.38
7.36
8.90
7.34
8.85
−40 −20
0
20
40
60
80
100
7.32
−40
120
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. VCC(on) vs. Temperature
Figure 6. VCC(min) vs. Temperature
120
800
7.00
700
6.98
CURRENT (mA)
VOLTAGE (V)
600
6.96
6.94
6.92
500
400
300
200
6.90
−20
0
20
40
60
80
100
0
−40
120
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 7. VCC(off) vs. Temperature
Figure 8. IDSS(off) vs. Temperature
0.95
0.99
0.94
0.98
0.93
0.97
0.92
0.91
0.90
120
0.96
0.95
0.94
0.93
0.89
0.88
−40
−20
TEMPERATURE (°C)
CURRENT (mA)
CURRENT (mA)
6.88
−40
100
−20
0
20
40
60
80
100
0.92
−40
120
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. ICC1 60 kHz vs. Temperature
Figure 10. ICC1 100 kHz vs. Temperature
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120
NCP1060, NCP1063
310
770
308
765
306
760
CURRENT (mA)
304
302
300
298
296
755
750
745
740
294
735
292
730
290
288
−40 −20
725
720
−40
0
20
40
60
80
100
120
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. IIPK(0)1060 vs. Temperature
Figure 12. IIPK(0)1063 vs. Temperature
12
0.6
10
0.5
CURRENT (mA)
CURRENT (mA)
CURRENT (mA)
TYPICAL CHARACTERISTICS
8
6
4
2
120
0.4
0.3
0.2
0.1
0
−40 −20
0
20
40
60
80
100
0
−40
120
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Istart1 vs. Temperature
Figure 14. Istart2 vs. Temperature
70
120
25
60
RESISTIVITY (W)
RESISTIVITY (W)
20
50
40
30
20
15
10
5
10
0
−40
−20
0
20
40
60
80
100
0
−40
120
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. RDS(on)1060 vs. Temperature
Figure 16. RDS(on)1063 vs. Temperature
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10
120
NCP1060, NCP1063
100
59.5
99
59.0
98
58.5
58.0
57.5
57.0
96
95
94
56.0
93
−20
0
20
40
60
80
100
92
−40
120
20
40
60
80
100
Figure 17. fOSC60 vs. Temperature
Figure 18. fOSC100 vs. Temperature
108
272
107
270
106
105
104
103
266
264
262
260
101
258
0
20
40
60
80
100
256
−40
120
120
268
102
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. Ifreeze1060 vs. Temperature
Figure 20. Ifreeze1063 vs. Temperature
120
25.8
66.2
25.6
FREQUENCY (kHz)
66.1
66.0
65.9
65.8
65.7
65.6
−40
0
TEMPERATURE (°C)
274
−20
−20
TEMPERATURE (°C)
109
100
−40
DUTY CYCLE (%)
97
56.5
55.5
−40
CURRENT (mA)
FREQUENCY (kHz)
60.0
CURRENT (mA)
FREQUENCY (kHz)
TYPICAL CHARACTERISTICS
25.4
25.2
25.0
24.8
24.6
−20
0
20
40
60
80
100
24.4
−40 −20
120
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. D(max) vs. Temperature
Figure 22. fmin vs. Temperature
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11
100
120
NCP1060, NCP1063
TYPICAL CHARACTERISTICS
53
430
425
52
420
51
TIME (ms)
TIME (ms)
415
410
405
400
50
49
48
395
47
390
−20
0
20
40
60
80
100
46
−40
120
40
60
80
100
Figure 24. tSCP vs. Temperature
18.1
91
18.0
90
17.9
17.8
17.7
88
87
86
17.5
85
−20
0
20
40
60
80
100
84
−40
120
120
89
17.6
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 25. VOVP vs. Temperature
Figure 26. VHV(EN) vs. Temperature
3.34
1.6
3.33
1.4
3.32
120
1.2
3.31
VOLTAGE (V)
VOLTAGE (V)
20
Figure 23. trecovery vs. Temperature
92
3.30
3.29
3.28
3.27
1.0
0.8
0.6
0.4
3.26
3.25
3.24
−40
0
TEMPERATURE (°C)
18.2
17.4
−40
−20
TEMPERATURE (°C)
VOLTAGE (V)
VOLTAGE (V)
385
−40
0.2
−20
0
20
40
60
80
100
0
−40
120
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 27. VREF vs. Temperature
Figure 28. VOTAen vs. Temperature
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12
120
NCP1060, NCP1063
Application Information
♦
Introduction
The NCP106X offers a complete current−mode control
solution. The component integrates everything needed to
build a rugged and cost effective Switch−Mode Power
Supply (SMPS) featuring low standby power. The Quick
Selection Table, Table 4, details the differences between
references, mainly peak current setpoints, RDS(on) value and
operating frequency.
• Current−mode operation: the controller uses
current−mode control architecture.
• 700 V –_ Power MOSFET: Due to ON Semiconductor
Very High Voltage Integrated Circuit technology, the
circuit hosts a high−voltage power MOSFET featuring
a 34 W or 11.4 W RDS(on) – Tj = 25°C. This value lets
the designer build a power supply up to 7.8 W or
15.5 W operated on universal mains. An internal
current source delivers the startup current, necessary to
crank the power supply.
• Dynamic Self−Supply: Due to the internal high
voltage current source, this device could be used in the
application without the auxiliary winding to provide
supply voltage.
• Short circuit protection: by permanently monitoring
the COMP line activity, the IC is able to detect the
presence of a short−circuit, immediately reducing the
output power for a total system protection. A tSCP timer
is started as soon as the COMP current is below
threshold, ICOMPfault, which indicates the maximum
peak current. If at the end of this timer the fault is still
present, then the device enters a safe, auto−recovery
burst mode, affected by a fixed timer recurrence,
trecovery. Once the short has disappeared, the controller
resumes and goes back to normal operation.
• Built−in VCC Over Voltage Protection: when the
auxiliary winding is used to bias the VCC pin (no DSS),
an internal comparator is connected to VCC pin. In case
the voltage on the pin exceeds a level of VOVP (18 V
typically), the controller immediately stops switching
and waits a full timer period (trecovery) before
attempting to restart. If the fault is gone, the controller
resumes operation. If the fault is still there, e.g. a
broken opto−coupler, the controller protects the load
through a safe burst mode.
• Line detection: An internal comparator monitors the
drain voltage as recovering from one of the following
situations:
♦ Short Circuit Protection,
VCC OVP is confirmed,
UVLO,
♦ TSD
If the drain voltage is lower than the internal threshold
(VHV(EN)), the internal power switch is inhibited. This
avoids operating at too low ac input. This is also called
brown−in function in some fields. For applications not
using standard AC mains (24 Vdc industrial bus for
instance), the B version doesn’t incorporate this line
detection and let the device start as soon as voltage
supply reaches Vstart(min).
Frequency jittering: an internal low−frequency
modulation signal varies the pace at which the
oscillator frequency is modulated. This helps spreading
out energy in conducted noise analysis. To improve the
EMI signature at low power levels, the jittering remains
active in frequency foldback mode.
Soft−Start: a 4 ms soft−start ensures a smooth startup
sequence, reducing output overshoots.
Frequency foldback capability: a continuous flow of
pulses is not compatible with no−load/light−load
standby power requirements. To excel in this domain,
the controller observes the COMP pin current
information and when it reaches a level of ICOMPfold,
the oscillator then starts to reduce its switching
frequency as the feedback current continues to increase
(the power demand continues to reduce). It can go
down to 25 kHz (typical) reached for a feedback level
of ICOMPfold(end) (100 mA roughly). At this point, if the
power continues to drop, the controller enters classical
skip−cycle mode.
Skip: if SMPS naturally exhibits a good efficiency at
nominal load, it begins to be less efficient when the
output power demand diminishes. By skipping
un−needed switching cycles, the NCP106X drastically
reduces the power wasted during light load conditions.
Ipeak set: If current in range 26 mA and 285 mA is
drawn from the pin, the peak current is proportionally
reduced down to 40% of its original value. This feature
enables to designer to set up the peak current to the
value which is ideal for the application.
♦
•
•
•
•
•
•
By routing a portion of the negative voltage present during
the on−time on the auxiliary winding to the LIM/OPP pin,
the user has a simple and non−dissipative means to alter the
maximum peak current setpoint as the bulk voltage
increases.
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13
NCP1060, NCP1063
Application Information
Startup Sequence
When the power supply is first powered from the mains
outlet, the internal current source (typically 8.0 mA) is
biased and charges up the VCC capacitor from the drain pin.
Once the voltage on this VCC capacitor reaches the VCC(on)
level (typically 9.0 V), the current source turns off and
pulses are delivered by the output stage: the circuit is awake
and activates the power MOSFET if the bulk voltage is
above VHV(EN) level (87 V typically) for A version and if
bulk voltage is above Vstart(min) (21 V dc) for B version.
Figure 29 details the simplified internal circuitry.
Vbulk
I1
Rlimit
I start1
ICC1
Drain
5
1
I2
−
+
CVCC
VCC(on)
VCC(min)
+
−
VCC > 18 V ?
àOVP fault
VOVP
8
Figure 29. The Internal Arrangement of the Start−up Circuitry
Being loaded by the circuit consumption, the voltage on
the VCC capacitor goes down. When VCC is below VCC(min)
level (7.5 V typically), it activates the internal current source
to bring VCC toward VCC(on) level and stops again: a cycle
takes place whose low frequency depends on the VCC
capacitor and the IC consumption. A 1.5 V ripple takes place
on the VCC pin whose average value equals (VCC(on) +
VCC(min))/2. Figure 30 portrays a typical operation of the
DSS.
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14
NCP1060, NCP1063
10
9
9.0 V
8
7
V (V)
7.5 V
VCC
6
5
Device
Internal
Pulses
4
3
2
VCCTH
1
0
0
1
2
3
Startup Duration
4
5
6
7
8
9
10
TIME (ms)
Figure 30. The Charge/Discharge Cycle Over a 1 mF VCC Capacitor
trecovery duration (400 ms typically). Then a new start−up
attempt takes place to check whether the fault has
disappeared or not. The OVP paragraph gives more design
details on this particular section.
As one can see, even if there is auxiliary winding to provide
energy for VCC, it happens that the device is still biased by
DSS during start−up time or some fault mode when the
voltage on auxiliary winding is not ready yet. The VCC
capacitor shall be dimensioned to avoid VCC crosses VCC(off)
level, which stops operation. The ΔV between VCC(min) and
VCC(off) is 0.5 V. There is no current source to charge VCC
capacitor when driver is on, i.e. drain voltage is close to zero.
Hence the VCC capacitor can be calculated using
C VCC w
I CC1 @ D max
f OSC @ DV
Fault Condition – Short−circuit on VCC
In some fault situations, a short−circuit can purposely
occur between VCC and GND. In high line conditions (VHV
= 370 VDC) the current delivered by the startup device will
seriously increase the junction temperature. For instance,
since Istart1 equals 5 mA (the min corresponds to the highest
Tj), the device would dissipate 370 x 5 m = 1.85 W. To avoid
this situation, the controller includes a novel circuitry made
of two startup levels, Istart1 and Istart2. At power−up, as long
as VCC is below a 1.4 V level, the source delivers Istart2
(around 500 mA typical), then, when VCC reaches 1.4 V, the
source smoothly transitions to Istart1 and delivers its nominal
value. As a result, in case of short−circuit between VCC and
GND, the power dissipation will drop to 370 x 500 m =
185 mW. Figure 30 portrays this particular behavior.
The first startup period is calculated by the formula C x V
= I x t, which implies a 1 m x 1.4 / 500 m = 2.8 ms startup time
for the first sequence. The second sequence is obtained by
toggling the source to 8 mA with a delta V of VCC(on) –
VCCTH = 9.0 – 1.4 = 7.6 V, which finally leads to a second
startup time of 1 m x 7.6 / 8 m = 0.95 ms. The total startup
time becomes 2.8 m + 0.95 m = 3.75 ms. Please note that this
calculation is approximated by the presence of the knee in
the vicinity of the transition.
(eq. 1)
Take the 60 kHz device as an example. CVCC should be
above
0.8 m @ 72%
+ 21 nF.
54 kHz @ 0.5
A margin that covers the temperature drift and the voltage
drop due to switching inside FET should be considered, and
thus a capacitor above 0.1 mF is appropriate.
The VCC capacitor has only a supply role and its value
does not impact other parameters such as fault duration or
the frequency sweep period for instance. As one can see on
Figure 29, an internal OVP comparator, protects the
switcher against lethal VCC runaways. This situation can
occur if the feedback loop optocoupler fails, for instance,
and you would like to protect the converter against an over
voltage event. In that case, the over voltage protection
(OVP) circuit and immediately stops the output pulses for
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15
NCP1060, NCP1063
Fault Condition – Output Short−circuit
asserted, Ipflag, indicating that the system has reached its
maximum current limit set point. The assertion of this flag
triggers a fault counter tSCP (48 ms typically). If at counter
completion, Ipflag remains asserted, all driving pulses are
stopped and the part stays off in trecovery duration (about
400 ms). A new attempt to re−start occurs and will last
48 ms providing the fault is still present. If the fault still
affects the output, a safe burst mode is entered, affected by
a low duty−cycle operation (11%). When the fault
disappears, the power supply quickly resumes operation.
Figure 31 depicts this particular mode:
As soon as VCC reaches VCC(on), drive pulses are
internally enabled. If everything is correct, the auxiliary
winding increases the voltage on the VCC pin as the output
voltage rises. During the start−sequence, the controller
smoothly ramps up the peak drain current to maximum
setting, i.e. IIPK, which is reached after a typical period of
4 ms. When the output voltage is not regulated, the current
coming through COMP pin is below ICOMPfault level (40 mA
typically), which is not only during the startup period but
also anytime an overload occurs, an internal error flag is
VCC
VCC(on)
VCC(min)
IpFlag
Open loop FB
VCOMP
Fault 48 ms typ.
Timer
400 ms typ.
DRV
internal
Figure 31. In case of short−circuit or overload, the NCP106X protects itself and the power supply via a low
frequency burst mode. The VCC is maintained by the current source and self−supplies the controller.
Auto−recovery Over Voltage Protection
IC against high voltage spikes, which can damage the IC,
and to filter out the Vcc line to avoid undesired OVP
activation. Rlimit should be carefully selected to avoid
triggering the OVP as we discussed, but also to avoid
disturbing the VCC in low / light load conditions.
Self−supplying controllers in extremely low standby
applications often puzzles the designer. Actually, if a SMPS
operated at nominal load can deliver an auxiliary voltage of
an arbitrary 16 V (Vnom), this voltage can drop below 10 V
(Vstby) when entering standby. This is because the
recurrence of the switching pulses expands so much that the
low frequency re−fueling rate of the VCC capacitor is not
enough to keep a proper auxiliary voltage.
The particular NCP106X arrangement offers a simple
way to prevent output voltage runaway when the
optocoupler fails. As Figure 32 shows, a comparator
monitors the VCC pin. If the auxiliary pushes too much
voltage into the CVCC capacitor, then the controller
considers an OVP situation and stops the internal drivers.
When an OVP occurs, all switching pulses are permanently
disabled. After trecovery delay, it resumes the internal drivers.
If the failure symptom still exists, e.g. feedback
opto−coupler fails, the device keeps the auto−recovery OVP
mode. It is recommended insertion of a resistor (Rlimit)
between the auxiliary dc level and the VCC pin to protect the
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16
NCP1060, NCP1063
Drain
VCC (on ) = 9.0 V
VCC (min ) = 7. 5 V
Istart 1
VCC
Shut down
Internal DRV
C VCC
80 ms
filter
VOVP
D1
R limit
C AUX
N AUX
GND
Figure 32. A more detailed view of the NCP106X offers better insight on how to properly wire an auxiliary winding
V OVP
V CC(on)
V CC(min)
VCC
I COMP
48 ms typ.
Fault level
TIMER
400 ms typ.
DRV
internal
Figure 33. describes the main signal variations when the part operates in auto−recovery OVP:
Soft−start
Figure 33: If the VCC current exceeds a certain threshold,
an auto−recovery protection is activated.
The NCP106X features a 4 ms soft−start which reduces
the power−on stress but also contributes to lower the output
overshoot. Figure 34 shows a typical operating waveform.
The NCP106X features a novel patented structure which
offers a better soft−start ramp, almost ignoring the start−up
pedestal inherent to traditional current−mode supplies.
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NCP1060, NCP1063
VCC
VCCON
0V (fresh PON)
Max Ip
Drain current
4 ms
Figure 34. The 4 ms Soft−start Sequence
Jittering
sawtooth is internally generated and modulates the clock up
and down with a fixed frequency of 300 Hz. Figure 35 shows
the relationship between the jitter ramp and the frequency
deviation. It is not possible to externally disable the jitter.
Frequency jittering is a method used to soften the EMI
signature by spreading the energy in the vicinity of the main
switching component. The NCP106X offers a ±6%
deviation of the nominal switching frequency. The sweep
Jitter ramp
63.6 kHz
60 kHz
Internal
sawtooth
56.4 kHz
adjustable
Figure 35. Modulation Effects on the Clock Signal by the Jittering Sawtooth
• UVLO
• TSD
Line Detection (for A version only)
An internal comparator monitors the drain voltage as
recovering from one of the following situations:
• Short Circuit Protection,
• VCC OVP is confirmed,
If the drain voltage is lower than the internal threshold
VHV(EN) (87 Vdc typically), the internal power switch is
inhibited. This avoids operating at too low ac input.
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NCP1060, NCP1063
Frequency Foldback
Frequency [kHz]
The reduction of no−load standby power associated with
the need for improving the efficiency, requires to change the
traditional fixed−frequency type of operation. This device
implements a switching frequency foldback when the
COMP current passes above a certain level, ICOMPfold, set
around 68 mA. At this point, the oscillator enters frequency
foldback and reduces its switching frequency.
The internal peak current set−point is following the
COMP current information until its level reaches IFreeze.
110
100
90
80
70
60
50
40
30
20
10
0
Below this value, the peak current setpoint is frozen to 30%
of the IPK(0). The only way to further reduce the transmitted
power is to diminish the operating frequency down to Fmin
(25 kHz typically). This value is reached at a COMP current
level of ICOMPfold(end) (100 mA typically). Below this point,
if the output power continues to decrease, the part enters skip
cycle for the best noise−free performance in no−load
conditions. Figure 36 and Figure 37 depict the adopted
scheme for the part.
NCP1060
NCP1063
50
60
70
80
90
100
ICOMP [mA]
Figure 36. By observing the current on the COMP pin, the controller reduces its
switching frequency for an improved performance at light load.
900
NCP1060
Current set point [mA]
800
NCP1063
700
600
500
400
300
200
100
0
40
50
60
70
80
90
100
ICOMP [mA]
Figure 37. Ipk set−point is frozen at lower power demand.
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19
110
NCP1060, NCP1063
350
NCP1060
Current set point [mA]
300
NCP1063
250
200
150
100
50
0
40
50
60
70
80
90
100
110
ICOMP [mA]
Figure 38. Ipk set−point is frozen at lower power demand (ILMOP ≥ 285 mA)
Feedback and Skip
this linear operating range, the dynamic resistance is
17.7 kW typically (RCOMP(up)) and the effective pull up
voltage is 2.7 V typically (VCOMP(REF)). When ICOMP is
decreases, the COMP voltage will increase to 3.2 V.
Figure 39 depicts the relationship between COMP pin
voltage and current. The COMP pin operates linearly as the
absolute value of COMP current (ICOMP) is above 40 mA. In
3.5
3
VCOMP [V]
2.5
2
1.5
1
0.5
0
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
ICOMP [μA]
Figure 39. COMP Pin Voltage vs. Current
Figure 40 depicts the skip mode block diagram. When the
COMP current information reaches ICOMPskip, the internal
clock setting the flip−flop is blanked and the internal
consumption of the controller is decreased. The hysteresis of
internal skip comparator is minimized to lower the ripple of
the auxiliary voltage for VCC pin and VOUT of power supply
during skip mode. It easies the design of VCC over load
range.
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20
NCP1060, NCP1063
Jittering
OSC
S
DRV stage
Q
Foldback
Q
R
VCOMP(REF)
ICOMPskip
RCOMP(UP)
SKIP
CS comparator
COMP
Figure 40. Skip Cycle Schematic
Ilimit and OPP Function
The function makes the integrated circuit more flexible. The current drawn out of LIM/OPP pin defines the current set point.
900
NCP1060
Current set point [mA]
800
NCP1063
700
600
500
400
300
200
100
0
0
50
100
150
200
250
300
350
ILMOP [mA]
Figure 41. Ipk set−point dependence on ILMOP current
ROPPU and ROPPL (Figure 42) define current drawn from
LIM/OPP and the negative voltage on auxiliary winding.
The negative voltage is tied up with bulk voltage, so the
higher the bulk voltage is, the deeper is the negative voltage
on auxiliary winding, the higher current is drawn from
LIM/OPP pin and the lower the peak current is. During the
internal MOSFET off period, voltage on auxiliary winding
is positive, but the IC ignores the LIM/OPP current. The
positive LIM/OPP current has no influence on proper IC
function.
There are several known ways to implement Over Power
Protection (OPP), all suffering from particular problems.
These problems range from the added consumption burden
on the converter or the skip−cycle disturbance brought by
the current−sense offset. A way to reduce the power
capability at high line is to capitalize on the negative voltage
swing present on the auxiliary diode anode. During the
power switch on−time, this point dips to –NVin , N being the
turns ratio between the primary winding and the auxiliary
winding. The negative plateau on auxiliary winding will
have an amplitude dependant on the input voltage. Resistors
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21
NCP1060, NCP1063
D4
VCC
OSC
Aux
winding
C2
S
Q
MOSFET
R
Vramp + Vsense
ICOMP
ICOMP to CS setpoint
R OPPU
ILMDEC
LIM/ OPP
0
25 mA
I Freeze
250 mA
Ipk(0 )
ILMOP
ILMOP
IPKL
ILMDEC
R OPPL
Figure 42. The OPP Circuitry Affects the Maximum Peak Current Set Point
Ramp Compensation and Ipk Set−point
NCP1060
In order to allow the NCP106X to operate in CCM with a
duty cycle above 50%, a fixed slope compensation is
internally applied to the current−mode control.
Here we got a table of the ramp compensation, the initial
current set point, and the final current set−point of different
versions of switcher.
NCP1063
fsw
60 kHz
100 kHz
60 kHz
100 kHz
Sa
8.4 mA/ms
14 mA/ms
15.6 mA/ms
26 mA/ms
Ipk(Duty
250 mA
650 mA
300 mA
780 mA
=50%)
Ipk(0)
Figure 43 depicts the variation of IPK set−point vs. the
power switcher duty ratio, which is caused by the internal
ramp compensation.
900
NCP1060
800
NCP1063
Ipk set-point [mA]
700
600
500
400
300
200
100
0
0%
10%
20%
30%
40%
50%
60%
70%
Dutty Ratio [%]
Figure 43. IPK set−point varies with power switch on time, which is caused by the ramp compensation.
FB Pin Function
positive current is defined by internal RCOMP(up) resistor
and VCOMP(ref) voltage. If FB path loop is broken (i.e. the FB
pin is disconnected), an internal current IFB (1 mA typ.) will
pull up the FB pin and the IC stops switching to avoid
uncontrolled output voltage increasing.
In isolated topology, the FB pin should be connected to
GND pin. In this configuration no current flows from OTA
to COMP pin (OTA is disabled) so the OTA has no influence
on regulation at all.
The FB pin is used in non isolated SMPS application only.
Portion of the output voltage is connected into the pin. The
voltage is compared with internal VREF (3.3 V) using
Operation Transconductance Amplifier (Figure 44). The
OTAs output is connected to COMP pin. The OTA output is
accessible through the COMP pin and is used for the loop
compensation, usually an RC network. The current
capability of OTA is limited to −150 mA typically. The
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22
NCP1060, NCP1063
Vin max = 265 Vac or 375 Vdc
Vout = 12 V
Pout = 5 W
Operating mode is CCM
η = 0.8
1. The lateral MOSFET body−diode shall never be
forward biased, either during start−up (because of
a large leakage inductance) or in normal operation
as shown in Figure 45. This condition sets the
maximum voltage that can be reflected during toff.
As a result, the Flyback voltage which is reflected
on the drain at the switch opening cannot be larger
than the input voltage. When selecting
components, you thus must adopt a turn ratio
which adheres to the following equation:
VCOMP (REF )
RCOMP (up )
I COMP
COMP
I FB
IOTAlim
OTA out = 0 A
if FB = 0 V
FB
OTA
VREF
N @ ǒV out ) V fǓ t V in,min
Figure 44. FB Pin Connection
2. In our case, since we operate from a 127 V DC rail
while delivering 12 V, we can select a reflected
voltage of 120 V dc maximum. Therefore, the turn
ratio Np:Ns must be smaller than
Design Procedure
The design of an SMPS around a monolithic device does
not differ from that of a standard circuit using a controller
and a MOSFET. However, one needs to be aware of certain
characteristics specific of monolithic devices. Let us follow
the steps:
Vin min = 90 Vac or 127 Vdc once rectified, assuming a low
bulk ripple
V reflect
+ 120 + 9.6 or Np : Ns t 9.6.
12 ) 0.5
V out ) V f
Here we choose N = 8 in this case. We will see later
on how it affects the calculation.
350
250
150
50.0
> 0 !!
−50.0
1.004M
1.011M
(eq. 2)
1.018M
1.025M
1.032M
Figure 45. The Drain−Source Wave Shall Always be Positive
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23
NCP1060, NCP1063
where K +
DI L
I Lavg
and defines the amount of ripple we want in CCM (see
Figure 46).
• Small K: deep CCM, implying a large primary
inductance, a low bandwidth and a large leakage
inductance.
• Large K: approaching DCM where the RMS losses are
worse, but smaller inductance, leading to a better
leakage inductance.
From Equation 6, a K factor of 1 (50% ripple), gives an
inductance of:
2
(127 @ 0.44)
+ 10.04 mH
60k @ 1 @ 5
V @d
DI L + in
+ 127 @ 0.44 + 92.8 mA peak to peak
L @ f sw
10.04m @ 60k
L+
Figure 46. Primary Inductance Current
Evolution in CCM
The peak current can be evaluated to be:
3. Lateral MOSFETs have a poorly doped
body−diode which naturally limits their ability to
sustain the avalanche. A traditional RCD clamping
network shall thus be installed to protect the
MOSFET. In some low power applications, a
simple capacitor can also be used since
V drain,max + V in ) N @ ǒV out ) V fǓ ) I peak @
I peak +
On IL, ILavg can also be calculated:
I Lavg + I peak *
Ǹ
I d,rms +
+
+
1)
1
Vin,min
L+
Ǹ
DI L 2
3
Ǔ
ǒ
0.44 @ 0.158 2 * 0.158 @ 0.0928 ) 0.0928
3
2
Ǔ
P cond + I d,rms 2 @ R DS(on) + 110 mW
7. Off−time and on−time switching losses can be
estimated based on the following calculations:
P off +
+
(eq. 4)
I peak @ ǒV bulk ) V clampǓ @ t off
(eq. 6)
2T SW
0.158 @ (127 ) 100 @ 2) @ 10n
2 @ 16.7 m
+ 15.5 mW
+ 0.44
Where, assume the Vclamp is equal to 2 times of reflected
voltage.
[email protected]([email protected])
2
f sw @ K @ P in
ǒ
d @ I peak 2 * I peak @ DI L )
If we take the maximum RDS(on) for a 125°C
junction temperature, i.e. 34 W, then conduction
losses worse case are:
5. To obtain the primary inductance, we have the
choice between two equations:
ǒV in @ dǓ
Ǹ
+ 57 mA
N @ ǒV out @ V fǓ
N @ ǒV out @ V fǓ ) V in,min
DI L
+ 158m * 92.8m + 111.6 mA
2
2
6. Based on the above numbers, we can now evaluate
the conduction losses:
Lf
(eq. 3)
C tot
where Lf is the leakage inductance, Ctot the total
capacitance at the drain node (which is increased by
the capacitor you will wire between drain and
source), N the NP:NS turn ratio, Vout the output
voltage, Vf the secondary diode forward drop and
finally, Ipeak the maximum peak current. Worse case
occurs when the SMPS is very close to regulation,
e.g. the Vout target is almost reached and Ipeak is still
pushed to the maximum. For this design, we have
selected our maximum voltage around 650 V (at Vin
= 375 Vdc). This voltage is given by the RCD clamp
installed from the drain to the bulk voltage. We will
see how to calculate it later on.
4. Calculate the maximum operating duty−cycle for
this flyback converter operated in CCM:
d max +
I avg DI L
49.2 m 92.8 m
)
+
)
+ 158 mA
0.44
2
2
d
(eq. 5)
www.onsemi.com
24
NCP1060, NCP1063
P on +
I valley @ ǒV bulk ) N @ (V out ) V f)Ǔ @ t on (eq. 7)
6 @ T SW
9. If the NCP106X operates at DSS mode, then the
losses caused by DSS mode should be counted as
losses of this device on the following calculation:
0.0464 @ (127 ) 100) @ 10 n
6 @ 16.7 m
+ 2.1 mW
P DSS + I CC1 @ V in.max + 0.8m @ 375 + 300 mW (eq. 8)
+
MOSFET Protection
It is noted that the overlap of voltage and current seen on
MOSFET during turning on and off duration is dependent on
the snubber and parasitic capacitance seen from drain pin.
Therefore the toff and ton in Equation 7 and Equation 8 have
to be modified after measuring on the bench.
8. The theoretical total power is then
117 + 15.5 + 2.1 = 127.6 mW
As in any Flyback design, it is important to limit the drain
excursion to a safe value, e.g. below the MOSFET BVdss
which is 700 V. Figure 47 a−b−c present possible
implementations:
Figure 47. a, b, c : Different Options to Clamp the Leakage Spike
a MUR160 represents a good choice. One major drawback
of the RCD network lies in its dependency upon the peak
current. Worse case occurs when Ipeak and Vin are maximum
and Vout is close to reach the steady−state value.
Figure 47c: this option is probably the most expensive of
all three but it offers the best protection degree. If you need
a very precise clamping level, you must implement a zener
diode or a TVS. There are little technology differences
behind a standard zener diode and a TVS. However, the die
area is far bigger for a transient suppressor than that of zener.
A 5 W zener diode like the 1N5388B will accept 180 W peak
power if it lasts less than 8.3 ms. If the peak current in the
worse case (e.g. when the PWM circuit maximum current
limit works) multiplied by the nominal zener voltage
exceeds these 180 W, then the diode will be destroyed when
the supply experiences overloads. A transient suppressor
like the P6KE200 still dissipates 5 W of continuous power
but is able to accept surges up to 600 W @ 1 ms. Select the
zener or TVS clamping level between 40 to 80 volts above the
reflected output voltage when the supply is heavily loaded.
As a good design practice, it is recommended to
implement one of this protection to make sure Drain pin
voltage doesn’t go above 650 V (to have some margin
between Drain pin voltage and BVdss) during most stringent
operating conditions (high Vin and peak power).
Figure 47a: the simple capacitor limits the voltage
according to the lateral MOSFET body−diode shall never be
forward biased, either during start−up (because of a large
leakage inductance) or in normal operation as shown by
Figure 45. This condition sets the maximum voltage that can
be reflected during toff. As a result, the flyback voltage
which is reflected on the drain at the switch opening cannot
be larger than the input voltage. When selecting
components, you must adopt a turn ratio which adheres to
the following Equation 3. This option is only valid for low
power applications, e.g. below 5 W, otherwise chances exist
to destroy the MOSFET. After evaluating the leakage
inductance, you can compute C with (Equation 4). Typical
values are between 100 pF and up to 470 pF. Large
capacitors increase capacitive losses...
Figure 47b: the most standard circuitry is called the RCD
network. You calculate Rclamp and Cclamp using the
following formulae:
R clamp +
C clamp +
2 @ V clamp @ ǒV clamp ) N @ (V out ) V f)Ǔ
L leak @ I leak 2 @ f sw
(eq. 9)
V clamp
V ripple @ f sw @ R clamp
Vclamp is usually selected 50−80 V above the reflected
value N x (Vout + Vf). The diode needs to be a fast one and
www.onsemi.com
25
NCP1060, NCP1063
Power Dissipation and Heatsinking
The NCP106X welcomes two dissipating terms, the DSS
current−source (when active) and the MOSFET. Thus, Ptot
= PDSS + PMOSFET. It is mandatory to properly manage the
heat generated by losses. If no precaution is taken, risks exist
to trigger the internal thermal shutdown (TSD). To help
dissipating the heat, the PCB designer must foresee large
copper areas around the package. Take the PDIP−7 package
as an example, when surrounded by a surface approximately
200 mm2 of 35 mm copper, the maximum power the device
can thus evacuate is:
P max +
T Jmax * T ambmax
R qJA
(eq. 10)
which gives around 870 mW for an ambient of 50°C and a
maximum junction of 150°C. If the surface is not large
enough, the RθJA is growing and the maximum power the
device can evacuate decreases. Figure 48 gives a possible
layout to help drop the thermal resistance.
Figure 48. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient
Bill of material:
C1
C2, R1, D1
C3
OK1
R2
Bulk capacitor, input DC voltage is connected to the capacitor
Clamping elements
Vcc capacitor
Optocoupler
Resistor to setting IPEAK current
Table 4. ORDERING INFORMATION
Device
Frequency
RDS(on)
Brown In
Package Type
Shipping
NCP1060AP060G
60 kHz
34
Yes
50 Units / Rail
NCP1060AP100G
100 kHz
34
Yes
PDIP−7
(Pb−Free)
NCP1060AD060R2G
60 kHz
34
Yes
NCP1060AD100R2G
100 kHz
34
Yes
NCP1060BD060R2G
60 kHz
34
No
NCP1060BD100R2G
100 kHz
34
No
NCP1063AP060G
60 kHz
11.4
Yes
NCP1063AP100G
100 kHz
11.4
Yes
NCP1063AD060R2G
60 kHz
11.4
Yes
NCP1063AD100R2G
100 kHz
11.4
Yes
www.onsemi.com
26
50 Units / Rail
2500 / Tape & Reel
SOIC−10
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
PDIP−7
(Pb−Free)
50 Units / Rail
SOIC−16
(Pb−Free)
2500 / Tape & Reel
50 Units / Rail
2500 / Tape & Reel
NCP1060, NCP1063
PACKAGE DIMENSIONS
PDIP−7 (PDIP−8 LESS PIN 6)
CASE 626A
ISSUE B
D
A
E
H
8
5
E1
1
4
NOTE 8
c
b2
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
M
D1
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTE 6
www.onsemi.com
27
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NCP1060, NCP1063
PACKAGE DIMENSIONS
SOIC−10 NB
CASE 751BQ
ISSUE B
2X
0.10 C A-B
D
D
A
2X
0.10 C A-B
10
F
6
H
E
1
5
0.20 C
10X
B
2X 5 TIPS
L2
b
0.25
A3
L
C
SEATING
PLANE
DETAIL A
M
C A-B D
TOP VIEW
10X
h
X 45 _
0.10 C
0.10 C
M
A
A1
e
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
DETAIL A
SEATING
PLANE
END VIEW
SIDE VIEW
DIM
A
A1
A3
b
D
E
e
H
h
L
L2
M
RECOMMENDED
SOLDERING FOOTPRINT*
1.00
PITCH
10X 0.58
6.50
10X 1.18
1
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
28
MILLIMETERS
MIN
MAX
1.25
1.75
0.10
0.25
0.17
0.25
0.31
0.51
4.80
5.00
3.80
4.00
1.00 BSC
5.80
6.20
0.37 REF
0.40
0.80
0.25 BSC
0_
8_
NCP1060, NCP1063
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
−A−
16
9
1
8
−B−
P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
8 PL
0.25 (0.010)
B
M
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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www.onsemi.com
29
ON Semiconductor Website: www.onsemi.com
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For additional information, please contact your local
Sales Representative
NCP1060/D