LC75056PE CMOS LSI Car Audio DSP with Bongiovi DPS www.onsemi.com Overview LC75056PE is a Digital Sound Processor which integrates audio signal processor, A/D, D/A, and volume into a single chip which are the prerequisites for car audio DSP. Programs are downloaded from internal Flash ROM into DSP RAM. (Caution) On-board programming to the Flash ROM of LC75056PE is not available. (Data is programmable only before delivery by Our company.) PQFP100 14x20 / QIP100E Hardware overview specification Parameter Analog input (stereo) Note ADC 24bit Balanced x2, Single x1 or Balanced x1, Single x3 Balanced x2, Single x1 or Balanced x1, Single x3 2 stereo ch, 2 monaural ch DAC 24bit + EVR 3 stereo ch Digital input (IIS) Maximum 5 stereo ch (slave) Digital output (IIS) Sampling rate converter (SRC) Maximum 4 stereo ch (master) Input through output 1 stereo ch Maximum 4 stereo ch (3 or 4 ch Synchronous input) Main microcontroller serial interface Serial interface (I C or SPI) DSP (24bit) 220MIPS (DSP 2 Core: operation at 110MHz) Analog input (monaural) 2 Supply voltage Logic (DSP) PLL circuit Crystal oscillation, digital I/O power supply CODEC analog power supply : 1.5V : 3.3V : 3.3V : 3.3V * I2C Bus is a trademark of Philips Corporation. * This product is licensed from Bongiovi Acoustics, Inc. and Silicon Storage Technology, Inc. (USA). ORDERING INFORMATION See detailed ordering and shipping information on page 28 of this data sheet. © Semiconductor Components Industries, LLC, 2015 March 2015 - Rev. 2 1 Publication Order Number : LC75056PE/D LC75056PE Specifications Absolute Maximum Ratings at Ta = 25C, DVSS_1 to 3 = COAVSS1 to 6 =AVB = XVSS = AVCOVSS = 0V Parameter Maximum supply voltage Maximum input voltage Symbol Ratings Unit CODEC power supply pin 0.3 to +3.9 VDD max2 Power supply pin for oscillation circuit 0.3 to +3.9 V Digital 3.3V power supply pin 0.3 to +3.9 V V VDD max3 VIN1 Logic (DSP) 0.3 to +1.8 V CODEC Analog input pin 0.3 to VDD max1 +0.3 V VIN2 Oscillation circuit input pin, TEST setting input pin Digital input pin 0.3 to VDD max2 +0.3 V VIN3 Maximum output current Applicable pins VDD max1 0.3 to +6.0 V Allowable power dissipation IO Pd max All output pin 6.0 mA Ta = 85C (Note 1) 900 mW Operating temperature Topr 40 to +85 C Storage temperature Tstg 55 to +125 C Note 1: For a chip mounted on a reference board. (board size: 105 75 1.6mm 4-layer) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Allowable Operating Range at Ta = 40 to 85C, DVSS_1 to 3 = COAVSS1 to 6 =AVB = XVSS = AVCOVSS = 0V Parameter Supply voltage CODEC ANALOG Supply voltage XTAL, DSP_IO Supply voltage PLL Supply voltage Logic Input high level voltage Symbol Applicable pins AVDD CODEC power supply pin DVDD33 AVCOVDD Power supply pin for oscillation circuit Digital 3.3V power supply pin Power supply pin for PLL DVDD Power supply pin for Logic VIH1 All digital input pin except for XIN Input high level voltage VIH2 XIN Input low level voltage VIL1 All digital input pin Crystal oscillation frequency (256fs) Fosc XIN, XOUT (fs = 44.1kHz) *2 min typ max Unit 3.14 3.3 3.47 V 3.14 3.3 3.47 V 3.14 3.3 3.47 V 1.43 1.5 1.58 V 2.0 5.5 *1 DVDD33 0 0.8 2.0 11.2896 V V V MHz *1) Only when power is supplied to all the power supplies, you can supply power to input pin up to 5.5V. When the power is turned off, only supply the power up to 3.6V. *2) Crystal for oscillator CI value: CI 150 The evaluation by the crystal supplier is recommended. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 2 LC75056PE DC Electrical Characteristics at Ta = 40 to 85C, DVSS_1 to 3 = COAVSS1 to 6 =AVB = XVSS = AVCOVSS = 0V Parameter Input high level current Input low level current Output high level voltage Output low level voltage Symbol IIH IIL VOH VOL Output OFF leak current IOFF Crystal oscillator feedback resistance CODEC reference voltage Power supply current Rf VREF IDDA33 IDDD33 IDDD15 Conditions and applicable pin All digital input pin All digital input pin IOH = 2mA: Digital output pin except for DSPIO4, SDAS IOH = 4mA: DSPIO4, SDAS IOL = 2mA: Digital output pin except for DSPIO4, SDAS IOL = 4mA: DSPIO4, SDAS Unloaded: All digital output pin XIN, XOUT min typ max 10 Unit A A 2.4 V 2.4 V 10 0.4 V 0.4 V 10 A 10 1.0 ADC_REF, ADC_REF COAVDD1, 2, 3, 4, 5, 6 AVCOAVDD DVDD33, XVDD DVDD_1, 2 M 0.5AVDD V 110 157 mA 10 120 12.5 173 mA mA AC Electrical Characteristics at AVDD = DVDD33 = AVCOVDD = 3.3V, DVSS_1 to 3 = COAVSS1 to 6 =AVB = XVSS = AVCOVSS = 0V Ta = 25C, fs = 44.1kHz, signal frequency 1kHz, measurement band = 10Hz to 20kHz Parameter (Input selector + ADC) Full-scale analog input level Analog block input impedance Gain setting level Gain setting step Error between gain setting steps S/N Dynamic range THD+N Cross talk 1 Cross talk 2 (ADC digital filter) Pass band frequency Stop band frequency Pass band ripple Stop band attenuation HPF cutoff frequency DC for offset cancellation (Audio DAC) Full-scale analog output level S/N Dynamic range THD+N Cross talk Mute level Symbol Conditions and applicable pin min typ 20 max Unit 0.85AVDD Vp-p k 30 12 +19 +0.5 dB dB dB 95 92 95 92 90 80 dB dB dB dB dB 75 65 dB 90 80 dB 0.4535 fs fs dB dB 1 0.5 w/ A-weighted w/o A-weighted w/ A-weighted w/o A-weighted Input condition: 3dBFS Input condition: 3dBFS, 1kHz Cross talk between AUX Lch and Rch when AUX differential input is used. Input condition: 3dBFS, 1kHz Other than cross talk1 90 87 90 87 0 0.5465 0.04 69 fs: 44.1kHz 0.86 Hz 0.85AVDD w/ A-weighted w/o A-weighted w/ A-weighted w/o A-weighted 3dBFS Input condition: full-scale, 1kHz w/ A-weighted 94 91 94 91 94 100 97 100 97 91 100 100 80 85 Vp-p dB dB dB dB dB dB dB Continued on next page. www.onsemi.com 3 LC75056PE Continued from preceding page. Parameter (ADC digital filter) Pass band frequency Stop band frequency Pass band ripple Stop band attenuation HPF cutoff frequency for DC offset cancellation (EVR) Input impedance Volume setting range Mute level Volume step Volume setting step error Symbol Conditions and applicable pin min typ 0 0.5465 max Unit 0.4535 fs fs dB dB 0.015 62 fs: 44.1kHz 1.7 ZEVRI 20 70 85 Hz 25 0 95 1 0.5 0.5 k dB dB dB dB Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1.5V reference level characteristics at Ta = 40 to 85C, DVDD33 = 3.3V, DVSS_1 to 3 = COAVSS1 to 6 =AVB = XVSS = AVCOVSS = 0V Parameter Symbol FET Control Output voltage DVREF Condition DVDD33 = 3.3V min typ 0 max 3.3 Unit V <Addition> • 1.5V reference level circuit is a circuit that prepared 1.5V power-supply voltage needed in this LSI to be easily generable. The power supply of 1.5V is enabled by using recommendation FET shown in Figure 5-1. <Figure 5-1> 1.5V reference level circuit peripheral block LC75056PE 3.3V DVDD33 DVSS_2 G DVREF FET DVDD_1 * FET Recommended Device No. NTR2101P (ON Semiconductor) D 10nF C2 DVDD_2 S 1.5V 10F C1 * C1 is the capacitor to prevent oscillation. In the range of operating temperature, make sure to maintain low ESR and the capacitance recommended value is 10F because oscillation may occur when the capacitance value changes due to the change of temperature. • As for power supply ON, the order of DVDD33 power supply voltage (3.3V) to FET source supply voltage (3.3V) is recommended. www.onsemi.com 4 LC75056PE Package Dimensions unit : mm PQFP100 14x20 / QIP100E CASE 122BV 0.8±0.2 23.2±0.2 17.2±0.2 100 14.0±0.1 20.0±0.1 12 0.65 0.3±0.05 0.15 0.13 0.1±0.1 (2.7) 3.0 MAX (0.58) 0 to10 0.10 MARKING DIAGRAM SOLDERING FOOTPRINT* 22.30 (Unit: mm) 0.65 0.43 1.30 16.30 XXXXXXX YMDDD DPS NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 5 XXXXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data DPS = Digital Power Station (DPS) LC75056PE COAVSS5 COAVDD6 82 81 AIN1RN 85 AIN1RP AIN1LN 86 COAVDD5 AIN1LP 87 83 AIN2R 88 84 AIN2L 89 AIN3RN 93 COAVSS4 AIN3RP 94 90 COAVSS3 95 AIN3RO COAVDD3 96 COAVDD4 AIN3LP 97 91 AIN3LN 98 92 AIN3LO 99 100 COAVSS2 Pin Assignment COAVDD2 1 80 COAVSS1 2 79 AVB COAVDD1 3 78 EVROUT1L VREFAMPO 4 77 EVRIN1L ADC_VREF 5 76 DACOUT1L DAC_VREF 6 75 DACOUT1R MIN3 7 74 EVRIN1R MIN2N 8 73 EVROUT1R MIN2P 9 72 EVROUT2L MIN1P 10 71 EVRIN2L MIN1N 11 70 DACOUT2L TEST1 12 69 DACOUT2R TEST2 13 68 EVRIN2R DVSS_3 14 67 EVROUT2R DVDD33 15 66 EVROUT3L LC75056PE (Top view) COAVSS6 MODE 16 65 EVRIN3L BUSYO 17 64 DACOUT3L SP_DO/SDAS 18 63 DACOUT3R SP_CL/SCLS 19 62 EVRIN3R SP_DI/GPIO_2 20 61 EVROUT3R SP_SSB/GPIO_3 21 60 AVCOAVSS GPO_1(ERR) 22 59 AVCOAVDD PWDB 23 58 RSTB 24 57 XVDD XOUT DSPIO1 25 56 XIN DVDD_2 26 55 DVSS_2 27 54 39 40 41 42 43 44 45 46 47 48 49 50 IISI3_DATA IISI3_BCLK IISI4_DATA IISI4_LRCK IISI4_BCLK IIS_SUB1 IIS_SUB2 IIS_SUB3 IISO_BCLK IISO_LRCK OUT_SEL1 37 IISI2_LRCK IISI3_LRCK 36 IISI2_DATA 38 35 IISI1_BCLK IISI2_BCLK 34 IISI1_LRCK OUT_SEL2 33 51 32 OUT_SEL3 30 DSPIO4 52 DSPIO2 IISI1_DATA 53 29 31 28 DVDD33 DSPIO3 DVREF XVSS DVSS_1 DVDD_1 www.onsemi.com 6 LC75056PE DVREF DVSS_2 DVDD_2 DVDD33 DVSS_3 DVSS33 DVSS_1 DVDD_1 Block Diagram COAVDD1 1.5V Reference output IISI3_DATA IISI3_LRCK IISI3_BCLK IISI4_DATA IISI4_LRCK OUT_SEL1 OUT_SEL2 OUT_SEL3 24Bit ADC (Mono 2ch) MIN1P MIN2N IISO_BCLK MIN2P MIN3 AIN3RO AIN3RN AIN3LP AIN3RP AIN3LN AIN3LO AIN2R AIN2L AIN1RP AIN1LN AIN1RN AIN1LP COAVDD3 Audio IISO_LRCK MIN1N COAVSS2 24Bit ADC (Stereo_2) IIS_SUB3 P-S Circuit for Digital outputs IIS_SUB2 IIS_SUB Control IISI4_BCLK IIS_SUB1 COAVDD2 Analog Input Source Selectors IISI2_BCLK 24Bit ADC (Stereo_1) IISI2_LRCK Digital Filters for ADC IISI2_DATA Sampling Rate Converters (4ch) IISI1_BCLK Digital inputs Selectors IISI1_LRCK Analog Input Source Selectors COAVSS1 IISI1_DATA COAVSS3 DSP Audio Clock Control Buffer VREFAMPO ADC_VREF COAVDD4 DSPIO1 COAVSS4 DSPIO2 DAC_VREF DSPIO3 DACOUT1L DAC DACOUT1R SP_DI/GPIO_2 Digital Filters for DAC GPO_1(ERR) MODE EVROUT1R EVROUT2L EVR EVRIN2L 24Bit Stereo DACOUT2L DAC DACOUT2R EVRIN2R EVR RSTB EVROUT2R EVROUT3L EVR PWDB DACOUT3L DAC DACOUT3R TEST1 TEST2 EVROUT3R AVB COAVDD6 COAVSS6 AVCOVSS AVCOVDD XIN XVSS XVDD XOUT 7 EVRIN3R EVR VCO www.onsemi.com EVRIN3L 24Bit Stereo COAVSS5 COAVDD5 BUSYO EVRIN1R EVR Host I/F SP_DO/SDAS EVRIN1L 24Bit Stereo SP_CL/SCLS SP_SSB/GPIO_3 EVROUT1L EVR DSPIO4 LC75056PE Pin functions No Pin name Input/output Input/output Functions (RSTB=L) 1 COAVDD2 Power supply for CODEC analog (3.3V) 2 COAVSS1 Power supply for CODEC analog (GND) 3 COAVDD1 Power supply for CODEC analog (3.3V) 4 VREFAMPO AO AO 5 ADC_VREF AO AO 6 DAC_VREF AO AO 7 MNI3 AI AI 8 MNI2N AI AI Reference voltage buffer output pin, used as external reference voltage Reference voltage output pin for CODEC ADC A coupling capacitor is required between this pin and GND. Reference voltage output pin for CODEC DAC A coupling capacitor is required between this pin and GND. Analog single-end input pin for monaural3 When this pin is unused, connect it to GND via capacitor. Negative analog input pin for monaural 2 or Analog single-end input pin for monaural 5. When this pin is unused, connect it to GND via capacitor. Positive analog input pin for monaural 2 or 9 MNI2P AI AI Analog single-end input pin for monaural 4. When this pin is unused, connect it to GND via capacitor. Positive analog input pin for monaural 1 10 MNI1P AI AI 11 MNI1N AI AI 12 TEST1 I I Test mode setting input pin1. Normally connected to GND 13 TEST2 I I Test mode setting input pin2. Normally connected to GND 14 DVSS_3 15 DVDD33 16 MODE I 17 BUSYO O When this pin is unused, connect it to GND via capacitor. Negative analog input pin for monaural 1 When this pin is unused, connect it to GND via capacitor. Power supply for digital (GND) Power supply for digital (3.3V) Select pin for serial communication mode (“0”: I2C, “1”: SPI) O (H) System busy signal output pin for HOST CPU communication (High level: the system is busy) Data output pin for SPI (slave) communication or 18 SP_DO/SDAS I/O I 19 SP_CL/SCLS I I 20 SP_DI/GPIO_2 I/O I 21 SP_SSB/GPIO_3 I/O I 22 GPO_1 (ERR) O O(L) 23 PWDB I I 24 RSTB 25 DSPIO1 26 DVDD_2 Power supply for internal logic (1.5V) 27 DVSS_2 Power supply for digital (GND) data input/ output pin for IIC (Slave) communication Clock input pin for data transfer for SPI (slave) communication or data transfer clock input pin for IIC (Slave) communication Data input pin for SPI (slave) communication or General-purpose input/output pin2 for Audio DSP Enable signal input pin for SPI (slave) communication (Active: low level) or General-purpose input/output pin3 for audio DSP General-purpose output pin 1 for integrated DSP (will be designed to correspond to communication error signal output) Power-down mode setting pin. Normally high level. I I System reset pin. Make sure to set to low level when turning on power. I/O I Audio DSP general input/output pin 1 28 DVREF 29 DVDD33 O Control output pin for 1.5V level 30 DSPIO2 I/O I Audio DSP general-purpose input/output pin2 31 DSPIO3 I/O I Audio DSP general-purpose input/output pin3 32 DSPIO4 I/O I Audio DSP general-purpose input/output pin4 or 256fs_clock out pin. 33 IISI1_DATA I I IIS data input pin1 34 IISI1_LRCK I I IIS word clock input pin1 35 IISI1_BCLK I I IIS bit clock input pin1 36 IISI2_DATA I I IIS data input pin2 37 IISI2_LRCK I I IIS word clock input pin2 38 IISI2_BCLK I I IIS bit clock input pin2 39 IISI3_DATA I I IIS data input pin3 40 IISI3_LRCK I I IIS word clock input pin3 41 IISI3_BCLK I I IIS bit clock input pin3 42 IISI4_DATA I I IIS data input pin4 Power supply for digital (3.3V) Continued on next page. www.onsemi.com 8 LC75056PE Continued from preceding page. No Pin name Input/output Input/output Functions (RSTB=L) 43 IISI4_LRCK I I IIS word clock input pin4 44 IISI4_BCLK I I IIS bit clock input pin4 45 IIS_SUB1 I/O I 46 IIS_SUB2 I/O I 47 IIS_SUB3 I/O I 48 IISO_BCLK O O (L) 49 IISO_LRCK O O (L) 50 51 OUT_SEL1 OUT_SEL2 O O O O (L) O (L) O (L) IIS data input pin5 or IIS data output pin1 or IIS data output pin4 IIS data input pin6 or IIS word clock input pin5 or IIS data output pin2 or IIS word clock output pin4 IIS data input pin7 or IIS bit clock input pin5 or IIS data output pin3 or IIS bit clock output pin4 IIS bit clock output pin (for IIS data output 1 to 3) IIS word clock output pin (for IIS data output 1 to 3) IIS data output pin1 or IIS data output pin4 or internal signal output pin1 (During reset, this pin is fixed to low level output.) IIS data output pin2 or IIS word clock output pin4 or internal signal output pin2 (During reset, this pin is fixed to low level output.) IIS data output pin3 or IIS bit clock output pin4 or internal signal output pin3 52 OUT_SEL3 53 DVDD_1 54 DVSS_1 Power supply for digital (GND) 55 XVSS Crystal for oscillation circuit power supply. (GND) 56 XIN Oscillation 57 XOUT Oscillation 58 XVDD Crystal for oscillation circuit power supply (3.3V) 59 AVCOAVDD VCO analog power supply for CODEC main clock generation(3.3V) 60 AVCOAVSS (During reset, this pin is fixed to low level output.) Power supply for internal logic (1.5V) Crystal oscillation circuit input (11.2896MHz or 12.288MHz) Crystal oscillation circuit output VCO analog power supply for CODEC main clock generation (GND) Electronic volume output pin. 61 EVROUT3R AO AO When output of EVR3 is OFF, EVRIN3R input signal output to EVROUT3R via 50k register. Electronic volume input pin. Make sure to connect this pin with DACOUT3R 62 EVRIN3R AI AI (DAC output) via coupling capacitor. When this pin is unused, leave it open or connect it to GND via capacitor. 63 DACOUT3R AO AO 64 DACOUT3L AO AO 65 EVRIN3L AI AI DAC analog output pin. (R-channel output) When output of DAC3 is OFF, pin output becomes GND. DAC analog output pin. (L-channel output) When output of DAC3 is OFF, pin output becomes GND. Electronic volume input pin. Make sure to connect this pin with DACOUT3L (DAC output) via coupling capacitor. When this pin is unused, leave it open or connect it to GND via capacitor. Electronic volume output pin. 66 EVROUT3L AO AO When output of EVR3 is OFF, EVRIN3L input signal output to EVROUT3L via 50k register. Electronic volume output pin. 67 EVROUT2R AO AO When output of EVR2 OFF, EVRIN2R input signal output to EVROUT2R via 50k register. Electronic volume input pin. Make sure to connect this pin with DACOUT2R 68 EVRIN2R AI AI (DAC output) via coupling capacitor. When this pin is unused, leave it open or connect it to GND via capacitor. 69 DACOUT2R AO AO 70 DACOUT2L AO AO 71 EVRIN2L AI AI DAC analog output pin. (R-channel output) When output of DAC2 is OFF, pin output becomes GND. DAC analog output pin. (L-channel output) When output of DAC2 is OFF, pin output becomes GND. Electronic volume input pin. Make sure to connect this pin with DACOUT2L (DAC output) via coupling capacitor. When this pin is unused, leave it open or connect it to GND via capacitor. Electronic volume output pin. 72 EVROUT2L AO AO When output of EVR2 is OFF, EVRIN2L input signal output to EVROUT2L via 50k register. Electronic volume output pin. 73 EVROUT1R AO AO When output of EVR1 is OFF, EVRIN1R input signal output to EVROUT1R via 50k register. Continued on next page. www.onsemi.com 9 LC75056PE Continued from preceding page. No Pin name Input/output Input/output Functions (RSTB=L) Electronic volume input pin. Make sure to connect this pin with DACOUT1R 74 EVRIN1R AI AI (DAC output) via coupling capacitor. When this pin is unused, leave it open or connect it to GND via capacitor. 75 DACOUT1R AO AO 76 DACOUT1L AO AO 77 EVRIN1L AI AI DAC analog output pin. (R-channel output) When the output setting of DAC1 is OFF, the pin output becomes GND. DAC analog output pin. (L-channel output) When the output setting of DAC1 is OFF, the pin output becomes GND. Electronic volume input pin. Make sure to connect this pin with DACOUT1L (DAC output) via coupling capacitor. When this pin is unused, leave it open or connect it to GND via capacitor. Electronic volume output pin. 78 EVROUT1L AO AO When the output setting of EVR1 is OFF, EVRIN1L input signal output to EVROUT1L via 50k register. CODEC Substrate GND pin. 79 AVB Make sure to connect this pin to GND with low impedance. Note that when the pin is open, latch-up may occur. 80 COAVSS6 81 COAVDD6 Power supply for CODEC analog (GND) Power supply for CODEC analog (3.3V) 82 COAVSS5 Power supply for CODEC analog (GND) 83 COAVDD5 Power supply for CODEC analog (3.3V) 84 AIN1RP R-channel for stereo1 Positive analog input pin. or AI AI R-channel for stereo 4 analog input pin. When this pin is unused, connect it to GND via capacitor. R-channel for stereo 1 Negative analog input pin. or 85 AIN1RN AI AI L-channel for stereo 4 analog input pin. When this pin is unused, connect it to GND via capacitor. L-channel for stereo 1 Negative analog input pin. or 86 AIN1LN AI AI R-channel for stereo 5 analog input pin. When this pin is unused, connect it to GND via capacitor. L-channel for stereo1 Positive analog input pin. or 87 AIN1LP AI AI L-channel for stereo 5 analog input pin. When this pin is unused, connect it to GND via capacitor. 88 AIN2R AI AI 89 AIN2L AI AI 90 COAVSS4 91 COAVDD4 92 AIN3RO R-channel for stereo 2 analog input pin. When this pin is unused, connect it to GND via capacitor. L-channel for stereo 2 analog input pin. When this pin is unused, connect it to GND via capacitor. Power supply for CODEC analog (GND) Power supply for CODEC analog (3.3V) AO AO 93 AIN3RN AI AI 94 AIN3RP AI AI 95 COAVSS3 96 COAVDD3 R-channel for stereo 3 Op Amp output pin R-channel for stereo 3 Op Amp inverting input pin. When this pin is unused, connect it to GND via capacitor. R-channel for stereo 3 Op Amp non-inverting input pin. When this pin is unused, connect it to GND via capacitor. Power supply for CODEC analog (GND) Power supply for CODEC analog (3.3V) 97 AIN3LP AI AI 98 AIN3LN AI AI 99 AIN3LO AO AO 100 COAVSS2 L-channel for stereo 3 Op Amp non-inverting input pin. When this pin is unused, connect it to GND via capacitor. L-channel for stereo 3 Op Amp inverting input pin. When this pin is unused, connect it to GND via capacitor. L-channel for stereo 3 Op Amp output pin Power supply for CODEC analog (GND) (Caution) * Make sure to connect decoupling capacitor between VDD and VSS. * The unused input pins that are not particularly specified above should be connected to GND. * The unused output pins that are not particularly specified above should be left open (do not connect to anything else). * Make sure to connect AVB (#79) to GND.(When the pin is open, latch-up may occur). www.onsemi.com 10 LC75056PE Input/Output PIN equivalent circuit I/O Equivalent circuit Pin Digital input TEST1 : 12 Comment 5V-Tolerant TEST2 : 13 MODE : 16 SP_CL/SCLS : 19 Digital input 5V-Tolerant PWDB : 23 IISI1_DATA : 33 IISI1_LRCK : 34 IISI1_BCLK : 35 IISI2_DATA : 36 IISI2_LRCK : 37 IISI2_BCLK : 38 IISI3_DATA : 39 IISI3_LRCK : 40 IISI3_BCLK : 41 IISI4_DATA : 42 IISI4_LRCK : 43 IISI4_BCLK : 44 RSTB : 24 Digital input 5V-Tolerant 3.3V Output (Inverting) Digital output BUSYO : 17 5V-Tolerant GPO_1(ERR) : 22 IISO_BCLK : 48 IISO_LRCK : 49 OUT_SEL1 : 50 OUT_SEL2 : 51 OUT_SEL3 : 52 Digital SP_DI/GPIO_2 : 20 input/output SP_SSB/GPIO_3 : 21 5V-Tolerant DSPIO1 : 25 DSPIO2 : 30 DSPIO3 : 31 IIS_SUB1 : 45 IIS_SUB2 : 46 IIS_SUB3 : 47 Digital SP_DO/SDAS : 18 input/output DSPIO4 : 32 www.onsemi.com 11 5V-Tolerant LC75056PE I/O Equivalent circuit Pin Oscillation circuit XIN : 56 XOUT : 57 56 57 I/O Equivalent circuit Pin DACOUT3R : 63 DAC DACOUT3L : 64 DACOUT2R : 69 DACOUT2L : 70 DACOUT1R : 75 DACOUT1L : 76 EVR In/Out VINDA EVRIN3R : 62 EVRIN3L : 65 EVRIN2R : 68 EVRIN2L : 71 EVRIN1R : 74 EVRIN1L : 77 VINDA VOUT VOUT EVROUT3R : 61 EVROUT3L : 66 EVROUT2R : 67 DAC_VREF EVROUT2L : 72 EVROUT1R : 73 EVROUT1L : 78 I/O Equivalent circuit VREF AMP Pin VREFAMPO : 4 Output Inner ADC_VREF VREF Output ADC_VREF : 5 DAC_VREF : 6 www.onsemi.com 12 LC75056PE I/O Equivalent circuit Pin Analog input INN (differential) AIN3RN : 93 AIN3LN : 98 INN INP AIN3RP : 94 AIN3LP : 97 COMPO INP AIN3RO : 92 COMPO Analog AIN3LO : 99 AINN Selector input AIN1RN : 85 (stereo) AIN1LN : 86 AIN2 AINN AIN2R : 88 AIN2L : 89 AIN2 AINP AIN1RP : 84 AINP Inner ADC_VREF www.onsemi.com 13 AIN1LP : 87 LC75056PE I/O Equivalent circuit Pin Analog MIN3 : 7 Selector input MIN2P : 9 (monaural) MIN1P : 10 7 MIN1N : 11 MIN2N : 8 9 10 11 8 Inner ADC_VREF www.onsemi.com 14 LC75056PE Power On/Off Timing (1) Power supply ON timing order tpup3315 3.3V Power supply *1 (1.5V Power ) 0ms (min) 1ms PWDB RSTB After BUSYO=Low, command acceptable BUSYO 100 ms (max) max time from RSTB=“H” to BUSY=“L” *1) When a 1.5V power supply is applied in external power source directly, Please refer to this sequential order. RSTB signal should be set in Low level more than 1ms from either late power supply turned on or positive edge of the PWDB signal.. In addition, the reset time is less than 100msec. When a 1.5V power supply is produced using a onchip 1.5V reference level and external FET, It is recommended that 3.3V power supply of LC75056 (DVDD33) and 3.3V power of external FET are turned on the following order. 3.3V (DVDD33) tpup3333 3.3V (FET) Parameter Symbol Power on (3.3V 1.5V) tpup3315 Conditions Min 0 Power on (3.3V 3.3V) tpup3333 0 Typ Max Unit 100 msec (2) Power supply OFF timing order 3.3V power supply tpdn1533 *2 (1.5V Power ) *2) When a 1.5V power supply is applied in external power source directly, Please refer to this sequential order. Parameter Symbol Power off (1.5V 3.3V) tpdn1533 Conditions Min 0 Typ Max Unit 100 msec In addition, 5V-Tolerant input pin of LC75056 can input 3.6V voltage even if in power supply OFF condition. Furthermore, it can be applied to 5V after regular voltage was applied to each power supply. Be careful because the I/O direction of the pin is not decided before a 1.5V power supply being input. In the voltage of each power supply, the voltage of the 3.3V power supply must be higher than the voltage of the 1.5V power supply. www.onsemi.com 15 LC75056PE Audio input Function (1) Digital audio input LC75056 has 4ch sampling rate converter as digital audio input, and Implement an independent selector circuitry every channel. (2) Digital input format 1) Pin Name 2) Mode 3) Format 4) Bit length 5) BCLK Frequency 6) Input fs IISI1_DATA, IISI1_LRCK, IISI1_BCLK, IISI2_DATA, IISI2_LRCK, IISI2_BCLK, IISI3_DATA, IISI3_LRCK, IISI3_BCLK, IISI4_DATA, IISI4_LRCK, IISI4_BCLK, IIS_SUB1(*1), IIS_SUB2(*1), IIS_SUB3(*1) MASTER MODE, SLAVE MODE IIS MODE, LEFT JUSTIFIED MODE, RIGHT JUSTIFIED MODE (*2) 16bit, 20bit, 24bit (*2) max 64fs (selectable from 32fs, 48fs, 64fs) 8kHz to 96kHz (Internal automatic distinction) (*1) As for the pin of IIS_SUB1/2/3, input or output is selectable. (*2) These modes can be set independently in IIS1 and IIS2. The setting method is shown in software specifications. (3) IIS MODE input timing LEFT CHANNEL LRCK RIGHT CHANNEL BCLK 1BCL DATA 1 2 1BCL 3 n-1 n MSB 1 LSB 2 3 n-1 n MSB LSB (4) LEFT JUSTIFIED MODE Input Timing RIGHT CHANNEL LRCK LEFT CHANNEL BCLK DATA 1 2 3 n-1 n MSB 1 2 LSB 3 n-1 n MSB LSB (5) RIGHT JUSTIFIED MODE Input Timing LRCK RIGHT CHANNEL LEFT CHANNEL BCLK DATA 1 2 MSB 3 n-1 n LSB 1 MSB (6) Combination of IIS Input/Output About IIS application pin, the following configurations are enabled. • 4 independent input and 4 output • 5 independent input and 3 output • 3 independent input and 3 multi-channel input and 3 output The setting method is shown in software specifications. www.onsemi.com 16 2 3 n-1 n LSB LC75056PE (7) Input timing chart tBCH tBCL tBCY BRCK tLRH tLRSU tDH tDS LRCK DATA Parameter symbol LRCK Cycle Time - BCLK Cycle Time tBCY Conditions Min Typ Max 8 96 BCLK : 64FS 512 6144 BCLK : 32FS 256 3072 Unit kHz kHz BCLK pulse width “H” tBCH 60 nsec BCLK pulse width “L” tBCL 60 nsec LRCK setup time to BCLK rising edge tLRSU 30 nsec LRCK hold time to BCLK rising edge tLRH 30 nsec DATA setup time to BCLK rising edge tDS 30 nsec DATA hold time to BCLK rising edge tDH 30 nsec (8) Sampling rate Converter (SRC) The sampling rate converter converts the sampling frequency into internal 44.1kHz or 48kHz for IIS digital input. It is decided which frequency it is converted into by crystal to use. In the case of 44.1kHz Crystal oscillator is 11.2896MHz (44.1kHz × 256) In the case of 48kHz: Crystal oscillator is 12.288MHz (48kHz × 256) Setting of the control information is necessary. About the setting method, it is shown in software specification. 1) Input sampling frequency 2) Output sampling frequency 3) number of the channels: 8kHz to 96kHz 44.1kHz or 48kHz 4 stereo channel (8 channel) It takes 2782fs (based on fs of either slow input or output) period after starting input and output of the digital audio before SRC output is stable (THD+N is stable). Because noise may occur during this period, please do mute processing. www.onsemi.com 17 LC75056PE (9) Analog audio input LC75056 has 2 ADCs (main/sub) for stereo sounds and 2 ADCs (INTA/INTB) for interruption monaural voices as analog audio in. In addition, a source select circuitry with gain setting is implemented in each ADC. As stereo input, one of single end input or op-amp input or the differential input can be chosen. As monaural voice inputting, one of single end input or the differential input can be chosen. 1) Main and Sub ADC input In audio main/sub ADC, a source selector of the single end input/op-amp input/differential input, and the Amp that can set a gain for each input individually are implemented. The gain set point of the main/sub is settable every each input source. Each amplifier gain is settable independently in the range of -12dB to +19dB (1dB step). In addition, please do mute processing because a noise may occur when gain setting is changed. About the setting command, it is shown on software specifications. single end input Lch Single end: 3 Differential: 1 Single end: 1 Differential: 2 differential input Rch AIN1LP AIN1LN AIN1RN AIN1RP AIN2L AIN2R AIN2L AIN2R Lch Rch AIN3LP, AIN3LN AIN3RP, AIN3RN AIN1LP, AIN1LN AIN1RP, AIN1RN AIN3LP, AIN3LN AIN3RP, AIN3RN About the method of these setting, it is appointed on software specifications. (i) Single end input: 3, differential input: 1 Single end (AIN4) Single end (AIN5) Single end (AIN2) Differential (AIN3) R L R L (ii) Single end input: 1, differential input: 2 AIN1RP AIN1RN AIN1LN AIN1LP AIN2R AIN2L AIN3RO AIN3RN AIN3RP AIN3LP AIN3LN AIN3LO Differential (AIN1) Single end (AIN2) Differential (AIN3) www.onsemi.com 18 AIN1RP AIN1RN AIN1LN AIN1LP AIN2R AIN2L AIN3RO AIN3RN AIN3RP AIN3LP AIN3LN AIN3LO LC75056PE 2) Monaural ADC input Audio system ADC for interrupt sound (INTA/INTB) has the amplifier which can set a gain for a source selector of the single-end input/differential input and each input individually. The gain setting of INTA/INTB is settable every each input source. The range of the gain is -12 to +19dB (1dB steps), and set from the outside. In addition, perform mute processing by all means because the noise outbreak is possible at the time of the gain setting change. About the method of the gain setting change, it is appointed on software specifications. By a number and the kind of the interrupt sound, the following combination is enabled. Combination single end input differential input MIN2N Single end: 3 MIN2P Differential: 1 MIN1P, MIN1N MIN3 MIN1P, MIN1N Single end: 1 MIN3 Differential: 2 MIN2P, MIN2N About the method of these setting, it is appointed on software specifications. (i) Single end input: 3, differential input: 1 (ii) Single end input: 1, differential input: 2 MIN1N Differential input (MIN1) MIN1N Differential input (MIN1) MIN1P Single end (MIN4) MIN2P Single end (MIN5) MIN2N MIN3 Single end (MIN3) MIN1P MIN2P Differential input (MIN2) MIN2N MIN3 Single end (MIN3) (10) Internal digital filter characteristic in A/D and D/A converter block 1) A/D converter block ADC Digtal Filter Frequency Response ADC Digtal Filter Frequency Response (passband) 0.2 0 0.15 amplitude [db] amplitude [db] -20 -40 -60 -80 -100 -120 0.1 0.05 0 -0.05 -0.1 -0.15 -140 -0.2 0 1 2 3 4 0 5 Frequency [×fs] 10 15 20 Frequency [kfs] (fs=44.1kHz) 2) D/A converter block (8- TIMES OVER SAMPLING DIGITAL FILTER) ADC Digtal Filter Frequency Response ADC Digtal Filter Ripple 0 0 -0.02 -40 -0.03 Gain [dBFS] Gain [dBFS] -0.01 -20 -60 -80 -100 -0.04 -0.05 -0.06 -0.07 -0.08 -120 -0.09 -140 -0.1 0 0.5 1 1.5 2 2.5 3 3.5 0 4 Frequency [fs] 5 10 15 Frequency [kfs] (fs=44.1kHz) www.onsemi.com 19 20 LC75056PE Audio output Function Digital audio output LC75056 has the digital output function of up to four systems. The digital output is fixed with IIS24bit/64fs format. (1) IIS output format (DSP processing) 1) Pin Name IISO_BCLK, IISO_LRCK, OUT_SEL1, OUT_SEL2, OUT_SEL3, IIS_SUB1(*1), IIS_SUB2(*1), IIS_SUB3(*1) 2) Format IIS MODE 3) Mode MASTER mode 4) Bit length 24bit 5) BCLK Frequency 64fs (*1) As for the pin of IIS_SUB1/2/3, input or output is selectable. Timing Chart LEFT CHANNEL LRCK RIGHT CHANNEL BCLK 1BCL DATA 1 MSB 2 1BCL 3 n-1 n LSB 1 2 3 MSB n-1 n LSB (2) Through output format LC75056 has a digital through output function other than four above digital output. With this mode, input data are output from the OUT_SEL1/2/3 terminal regardless of DSP processing. It is set from the outside which data are output from these terminals. 1) Selectable data 2) Pin Assign 3) Format IISI1_DATA, IISI1_LRCK, IISI1_BCLK, IISI2_DATA, IISI2_LRCK, IISI2_BCLK, IISI3_DATA, IISI3_LRCK, IISI3_BCLK, IISI4_DATA, IISI4_LRCK, IISI4_BCLK, IIS_SUB1(*1), IIS_SUB2(*1), IIS_SUB3(*1) OUT_SEL1 : DATA OUT_SEL2 : LRCK OUT_SEL3 : BCLK As for the IIS output, an input signal is just output. When it is used by the through output, there are not the rules such as formats in particular. (*1) It is only on the condition that IIS_SUB1/2/3 is used as input. www.onsemi.com 20 LC75056PE MICON Interface As communication interface of a host microcomputer and this LSI, one of IIC method or SPI methods is selectable. The choice of the communication mode is decided by MODE pin. MODE: “0”: IIC Interface “1”: SPI Interface (1) I2C Interface The IIC slave transmission and reception interface of this LSI is based on IIC Interface Specification ver.2.1. (Standard mode: 100Kbps, High speed mode: 400Kbps) The slave address of this LSI is 0x15 (value of upper 7 bits). The data to transfer assume 8 bits 1 unit. The format of the data transmission is performed according to the following. In addition, each byte data are the MSB first. Data write (6byte transmission example) : Signals from LC75056PE to a master SP_CL/SCLS SP_DO/SDAS W A C23 C22 C21 C20 C19 C18 C17 C16 A C15 C14 C13 C12 C11 C10 C9 C8 Slave address (0x15) Start write data data Ack D23 D22 D21 D20 D19 D18 D17 D16 A D15 D14 D13 D12 D11 D10 D9 D8 A Ack D7 D6 D5 D4 D3 D2 D1 D0 data A data Ack data C7 C6 C5 C4 C3 C2 C1 C0 A Ack A data Ack Ack Stop (or Repeated Start) Ack Make sure to perform communication when BUSYO pin is “L”. If communication is started when BUSYO pin is “H”, the operation of LC75056 will not be guaranteed. Data read : Signals from LC75056PE to a master SP_CL/SCLS SP_DO/SDAS W A C23 C22 C21 C20 C19 C18 C17 C16 A C15 C14 C13 C12 C11 C10 C9 C8 Slave address data C7 C6 C5 C4 C3 C2 C1 C0 data Write Ack Start A A data Ack Ack Stop Ack Wait until BUSYO becomes "L". R A D23 D22 D21 D20 D19 D18 D17 D16 A D15 D14 D13 D12 D11 D10 D9 D8 Slave address Start data A D7 D6 D5 D4 D3 D2 D1 D0 data Read Ack data Ack A D7 D6 D5 D4 D3 D2 D1 D0 data Ack The content of each data is specified by the software specification. www.onsemi.com 21 Ack Ack D23 D22 D21 D20 D19 D18 D17 D16 A D15 D14 D13 D12 D11 D10 D9 D8 data A A data Ack Nak Stop (or Repeated Start) LC75056PE Data access timing g a d h a i k SP_CL/SCLS b j c SP_DO/SDAS h Start e g Repeated Start f Standard mode Symbol Fast mode (100kbps) Timing Parameter Min (400kbps) Max unit Min Max - a Start (Repeated-Start) condition hold time 4000 600 b SP_CL/SCLS “P_ level pulse width 4700 1300 - ns c SP_CL/SCLS “HP level pulse width 4000 600 - ns d Start (Repeated-Start) condition setup time 4700 600 - ns e SP_DO/SDAS hold time 0 0 900 ns f SP_DO/SDAS setup time 250 100 - ns g SP_CL/SCLS, SP_DO/SDAS rise time 20+0.1Cb(1) 300 ns (1) - 3450 1000 300 20+0.1Cb ns h SP_CL/SCLS, SP_DO/SDAS fall time 300 ns i Stop condition setup time 4000 600 - ns j Bus release time 4700 1300 - ns k Allowable spikes pulse width - 0 - ns Cb = total capacitance of one bus line in pF. (2) SPI Interface The SPI slave sending and receiving interface of this LSI communicates by using four terminals (SP_SSB/GPIO_3, SP_CL/SCLS, SP_DI/GPIO_2, and SP_DO/SDAS). The fast transfer in 2Mbps or less is possible unlike I2C method. The slave address is 0x15 (six bit value) when the data transfer is done to this LSI, and one unit of data is 8 bits. The data transfer is formatted as follows. Each byte data are the MSB first. Data write (Ex. 6byte transmission) : Signals from LC75056PE to a master SP_SSB/GPIO_3 SP_CL/SCLS SP_DI/GPIO_2 W A C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 SP_D0/SDAS Start Slave address (0x15) Write data data data Ack D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 data data data Stop Make sure to perform communication when BUSYO pin is “L”. If communication is started when BUSYO pin is “H”, the operation of LC75056 will not be guaranteed. www.onsemi.com 22 LC75056PE Data read : Signals from LC75056PE to a master SP_SSB/GPIO_3 SP_CL/SCLS SP_DI/GPIO_2 W SP_DO/SDAS C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 data data data A Slave address write Start Stop Ack Wait until BUSYO becomes "L". SP_SSB/GPIO_3 SP_CL/SCLS SP_DI/GPIO_2 R A D23 D22 D21 D20 D19 D18 D17 D16 SP_DO/SDAS Start Slave address read D15 D14 D13 D12 D11 D10 D9 D8 data D7 D6 D5 D4 D3 D2 D1 D0 data data Ack D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 data data The content of each data is specified by the software specification. www.onsemi.com 23 D7 D6 D5 D4 D3 D2 D1 D0 data Stop LC75056PE Data write timing a b g SP_SSB/GPO_3 SP_CL/SCLS c d SP_DI/GPO_2 e f Data read timing a b SP_SSB/GPO_3 SP_CL/SCLS c d SP_DO/SDAS h Symbol i Parametre Min Typ Max Unit a SP_SSB setup time 500 ns b SP_SSB hold time 250 ns c SP_CL Low level pulse width 250 ns d SP_CL High level pulse width 250 ns e SP_DI setup time 100 ns f SP_DI hold time 100 ns g Command transfer interval 500 ns h SP_DO access time i SP_DO hold time 0 120 www.onsemi.com 24 100 ns ns LC75056PE Application Schematics CD23 CD25 CD27 CD28 St-Comp2 or St-Sing2,3 CD22 CD24 C17 CD26 R12 R15 R14 R13 C18 R10 R11 CD29 CD31 R17 R16 Separation with the buffer is recommended when crosstalk is concerned about. CD30 St-Sing1 St-Comp1 AVDD C16 CD2 C4 CD1 C3 M-Sing1 M-Comp2 or M-Sing2,3 M-Comp1 CD3 CD5 CD7 Host-I/F I2C: “0”/SPI: “1” D3.3 C5 R1 R2 R19 R3 Host I/F R4 R5 D3.3 R6 1 2 3 C 4 5 6 7 CD4 8 9 CD6 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 C6 28 29 30 CD32 C15 COAVSS2 AIN3LO AIN3LN AIN3LP COAVDD3 COAVSS3 AIN3RP AIN3RN AIN3RO COAVDD4 COAVSS4 AIN2L AIN2R AIN1LP AIN1LN AIN1RN AIN1RP COAVDD5 COAVSS5 COAVDD6 C1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 C19 COAVDD2 COAVSS1 COAVDD1 VREFAMPO ADC_VREF DAC_VREF MIN3 MIN2N MIN2P MIN1P MIN1N TEST1 TEST2 DVSS_3 DVDD33 MODE BUSYO SP_DO/SDAS SP_CL/SCLS SP_DI/GPIO_2 SP_SSB/GPIO_3 GPO_1(ERR) PWDB RSTB DSPIO1 DVDD_2 DVSS_2 DVREF DVDD33 DSPIO2 LC75056PE COAVSS6 AVB EVROUT1L EVRIN1L DACOUT1L DACOUT1R EVRIN1R EVROUT1R EVROUT2L EVRIN2L DACOUT2L DACOUT2R EVRIN2R EVROUT2R EVROUT3L EVRIN3L DACOUT3L DACOUT3R EVRIN3R EVROUT3R AVCOAVSS AVCOAVDD XVDD XOUT XIN XVSS DVSS_1 DVDD_1 OUT_SEL3 OUT_SEL2 AVSS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 C10 53 52 51 CD21 CD20 CD19 FL / FR CD18 CD17 CD16 CD15 RL / RR CD14 CD13 CD12 CD11 CD10 C14 L1 R9 Cen / SW D3.3 X1 *2) C11 C12 C13 C7 D G C8 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Q1 DSPIO3 DSPIO4 IISI1_DATA IISI1_LRCK IISI1_BCLK IISI2_DATA IISI2_LRCK IISI2_BCLK IISI3_DATA IISI3_LRCK IISI3_BCLK IISI4_DATA IISI4_LRCK IISI4_BCLK IIS_SUB1 IIS_SUB2 IIS_SUB3 IISO_BCLK IISO_LRCK OUT_SEL1 CD8 S C9 CD9 R7 DVSS R8 R18 D-in (1-4) AVSS DVSS D-in or D-out Note 1) This application schematics is just for reference and the characteristics are not guaranteed. Note 2) The confirmation of the constant for the oscillator and the evaluation request to the oscillator vendor are recommended. www.onsemi.com 25 D-out (1-3) LC75056PE BOM for Application Schematics Model Locations Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Name Parameter 0.1F 1608 10F 3216 C1, C2, C3, C4, C5, C6, C7, C10, C13, C14, C15, C16, C17, C18, C19 C9 18pF 1608 C11, C12 Ceramic Capacitor Electrolytic Capacitor Electrolytic Capacitor 10nF 1608 C8 47F DC50V±20 % DC50V±20 % Electrolytic Capacitor 2.2F Chip Resistor 10k 1608 Chip Resistor 30k 1608 R11, R16 Chip Resistor 30k 1608 R12, R15 Chip Resistor 15k 1608 R13, R14 Chip Resistor 15k 1608 R10, R17 Chip Resistor 0 1608 R9, R18 Chip Resistor 100 1608 R2, R4 Chip Resistor 33 1608 R3 MPZ1608R39 1A 1608 L1 NTR2101P Q1 CX8045GA X1 FET Cristal Oscillator 11.2896MHz 12.288MHz Notice The confirmation of the constant for the oscillator and the evaluation request to the oscillator vendor are recommended. CD1, CD2, CD8, CD9, CD32 CD10, CD11, CD12, CD13, CD14, CD15, CD16, CD17, CD18, CD19, CD20, CD21 CD3, CD4, CD5, CD6, CD7, CD22, CD23, CD24, CD25, CD26, CD27, CD28, CD29, CD30, CD31 R1, R5, R6, R7, R8, R19 Chip Bead 4.7F Condition DC50V±20 % The polarity depends on the constitution of other circuits. Selectable by System constitution. Notice: *) The locations of the bypass capacitors (C1, C2, C5, C6, C10, C14, C15, C16, C17, C18) must be arranged close to the each LSI pin and in the aspect of the same side as the LC75056PE. *) The location of the Q1 (FET) must be arranged close to the LC75056PE. *) The locations of C7, CD8, C9, and CD9 must be arranged close to the Q1 (FET). *) The length of the Lch and Rch of each Audio input/output wiring same as much as possible is recommended. (It is similar in the case of the length of the +ch and –ch of each differential input/output.) www.onsemi.com 26 LC75056PE (Appendix : Audio processing mode) This software has nine modes of operation as following table. Depending on the number of the channels processing Bongiovi DPS and another function to use, please select one mode. A channel name (ex. FL/FR/RL/RR/CE/SW, RSEL/RSER, IntA/IntB) listing in each cell is the processing channel of each function. Audio processing mode DPS OFF Function DPS 2 channel DPS 4 channel DPS 5 channel DPS 6 channel Mode(8) Mode(0) Mode(1) Mode(2) Mode(3) Mode(4) Mode(5) Mode(6) Mode(7) Input Selector Enable Enable Enable Enable Enable Enable Enable Enable Enable Input Gain Enable Enable Enable Enable Enable Enable Enable Enable Enable DownMix Enable Enable Enable Enable Enable Enable Enable Enable Enable High band retriever (HBR) FL/FR FL/FR FL/FR FL/FR disable disable disable disable disable Selector Int Selector Enable Enable Enable Enable Enable Enable Enable Enable Enable Noise Gate disable disable 6 channel FL/FR/RL/RR/ CE/SW 6 channel FL/FR/RL/RR/ CE/SW 6 channel FL/FR/RL/RR/ CE/SW 6 channel FL/FR/RL/RR/ CE/SW 6 channel FL/FR/RL/RR/ CE/SW 6 channel FL/FR/RL/RR/ CE/SW 6 channel FL/FR/RL/RR/ CE/SW Bongiovi DPS disable disable 2 channel FL/FR 2 channel FL/FR 4 channel FL/FR/RL/RR 4 channel FL/FR/RL/RR 4 channel FL/FR/RL/RR 5 channel FL/FR/RL/RR CE 6 channel FL/FR/RL/RR/ CE/SW Input ATT(2) FL/FR/RL/RR/ CE/SW FL/FR/RL/RR/C E/SW FL/FR FL/FR FL/FR/RL/RR FL/FR/RL/RR FL/FR/RL/RR FL/FR/RL/RR disable Tone Control FL/FR/RL/RR/ CE/SW Bas/Mid/Tre (3Band) FL/FR/RL/RR/C E/SW Bas/Mid/Tre (3Band) FL/FR Bas/Mid/Tre (3Band) FL/FR Bas/Mid/Tre (3Band) FL/FR/RL/RR Bas/Tre (2Band) FL/FR/RL/RR Bas/Mid/Tre (3Band) FL/FR/RL/RR Bas/Mid/Tre (3Band) disable disable Loudness FL/FR/RL/RR/ CE/SW low/high (2Band) FL/FR/RL/RR/C E/SW low/high (2Band) FL/FR low/high (2Band) FL/FR low/high (2Band) disable FL/FR/RL/RR low/high (2Band) FL/FR/RL/RR low/high (2Band) disable disable Input ATT(3) FL/FR/RL/RR/ CE/SW FL/FR/RL/RR/C E/SW FL/FR FL/FR disable FL/FR/RL/RR disable disable disable Equalizer FL/FR/RL/RR/ CE/SW 7Band FL/FR/RL/RR/C E/SW 7Band FL/FR 7Band FL/FR 7Band disable FL/FR/RL/RR 7Band disable disable disable Surround FL/FR/RL/RR FL/FR/RL/RR FL/FR FL/FR disable disable disable disable disable Bass Enhancement (NewSlive) FL/FR/RL/RR disable FL/FR disable FL/FR/RL/RR disable disable disable disable SW generator disable FL/FR/RL/RR disable FL/FR disable disable FL/FR/RL/RR disable disable Volume(1): Main Volume IntA/IntB FL/FR/RL/RR/ CE/SW RSEL/RSER IntA/IntB FL/FR/RL/RR/C E/SW RSEL/RSER IntA/IntB FL/FR RSEL/RSER IntA/IntB FL/FR RSEL/RSER IntA/IntB FL/FR/RL/RR RSEL/RSER IntA/IntB FL/FR/RL/RR RSEL/RSER IntA/IntB FL/FR/RL/RR RSEL/RSER IntA/IntB FL/FR/RL/RR/ CE/SW RSEL/RSER Delay FL/FR/RL/RR/ CE/SW FL/FR/RL/RR/C E/SW FL/FR FL/FR FL/FR/RL/RR FL/FR/RL/RR FL/FR/RL/RR FL/FR/RL/RR/ CE/SW FL/FR/RL/RR/ CE/SW Volume(2) Balance/Fader FL/FR/RL/RR/ CE/SW FL/FR/RL/RR/C E/SW FL/FR FL/FR FL/FR/RL/RR FL/FR/RL/RR FL/FR/RL/RR FL/FR/RL/RR/ CE/SW FL/FR/RL/RR/ CE/SW Mute IntA/IntB FL/FR/RL/RR/ CE/SW RSEL/RSER IntA/IntB FL/FR/RL/RR/C E/SW RSEL/RSER IntA/IntB FL/FR RSEL/RSER IntA/IntB FL/FR RSEL/RSER disable IntA/IntB FL/FR/RL/RR RSEL/RSER IntA/IntB FL/FR/RL/RR RSEL/RSER IntA/IntB FL/FR/RL/RR/ CE/SW RSEL/RSER disable Limiter FL/FR/RL/RR/ CE/SW FL/FR/RL/RR/C E/SW FL/FR FL/FR disable disable disable FL/FR/RL/RR/ CE/SW disable Volume(3) Fixed Level Control IntA/IntB FL/FR/RL/RR/ CE/SW RSEL/RSER IntA/IntB FL/FR/RL/RR/C E/SW RSEL/RSER IntA/IntB FL/FR RSEL/RSER IntA/IntB FL/FR RSEL/RSER IntA/IntB FL/FR/RL/RR RSEL/RSER IntA/IntB FL/FR/RL/RR RSEL/RSER IntA/IntB FL/FR/RL/RR RSEL/RSER IntA/IntB FL/FR/RL/RR/ CE/SW RSEL/RSER disable Mixing FL/FR/RL/RR/ CE/SW FL/FR/RL/RR/C E/SW FL/FR FL/FR FL/FR/RL/RR FL/FR/RL/RR FL/FR/RL/RR FL/FR/RL/RR/ CE/SW FL/FR/RL/RR/ CE/SW Enable Enable Enable Enable Enable Enable Enable Enable Enable Output Selector www.onsemi.com 27 IntA FL/FR/RL/RR/ CE/SW LC75056PE ORDERING INFORMATION Device LC75056PE-H Package Shipping (Qty / Packing) PQFP100 14x20 / QIP100E (Pb-Free / Halogen Free) 50 / Tray Foam ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. www.onsemi.com 28