ASM3P2760 - Peak EMI Reducing Solution

ASM3P2760A
Peak EMI Reducing Solution
Product Description
The ASM3P2760A is a versatile spread spectrum frequency
modulator designed specifically for a wide range of clock frequencies.
The ASM3P2760A reduces electromagnetic interference (EMI) at the
clock source, allowing system wide reduction of EMI of all clock
dependent signals. The ASM3P2760A allows significant system cost
savings by reducing the number of circuit board layers, ferrite beads
and shielding that are traditionally required to pass EMI regulations.
The ASM3P2760A uses the most efficient and optimized
modulation profile approved by the FCC and is implemented by using
a proprietary all digital method.
The ASM3P2760A modulates the output of a single PLL in order to
“spread” the bandwidth of a synthesized clock, and more importantly,
decreases the peak amplitudes of its harmonics. This results in
significantly lower system EMI compared to the typical narrow band
signal produced by oscillators and most frequency generators.
Lowering EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation.’
Features
•
•
•
•
•
•
•
•
•
•
Generates an EMI Optimized Clock Signal at the Output
Integrated Loop Filter Components
Operates with a 2.5/3.3 V Supply
Operating Current less than 4 mA
CMOS Design
Input Frequency Range:
♦ 6 MHz to 12 MHz for 2.5 V
♦ 6 MHz to 13 MHz for 3.3 V
Generates a 1x Low EMI Spread Spectrum Clock of the Input
Frequency
Frequency Deviation: ±0.65% @ 8 MHz
Available in TSOP−6 Package
This Device is Pb-Free and is RoHS Compliant
The ASM3P2760A is targeted towards all portable devices like
MP3 players and digital still cameras.
Cycle-to-Cycle Jitter
XOUT
2
XIN/CLKIN
3
ASM3P2760A
6
VSS
5
ModOUT
4
VDD
MARKING DIAGRAM
E4LAYWG
G
1
E4L
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb-Free Package
ORDERING INFORMATION
±200 ps (Typ)
Modulation Rate Equation
FIN/256
July, 2015 − Rev. 3
1
Specification
45/55%
© Semiconductor Components Industries, LLC, 2015
PD
VDD = 2.5/3.3 V
Output Duty Cycle
Frequency Deviation
PIN CONNECTION
See detailed ordering and shipping information on page 6 of
this data sheet.
Table 1. KEY SPECIFICATIONS
Description
1
TSOP−6
CASE 318G
(Note: Microdot may be in either location)
Applications
Supply Voltages
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±0.65% @ 8 MHz
1
Publication Order Number:
ASM3P2760/D
ASM3P2760A
VDD
PD
PLL
Modulation
XIN/CLKIN
Frequency
Divider
Crystal
Oscillator
XOUT
Loop
Filter
Phase
Detector
Feedback
Divider
VCO
Output
Divider
ModOUT
VSS
Figure 1. Block Diagram
PD
1
XOUT
2
XIN/CLKIN
3
ASM3P2760A
6
VSS
5
ModOUT
4
VDD
Figure 2. Pin Configuration
Table 2. PIN DESCRIPTION
Pin#
Pin Name
Type
Description
1
PD
I
Power-Down Control Pin. Pull Low to Enable Power-Down Mode. Connect to VDD if Not Used
2
XOUT
O
Crystal Connection. If Using an External Reference, this Pin Must be Left Unconnected
3
XIN/CLKIN
I
Crystal Connection or External Reference Frequency Input. This Pin has Dual Functions.
It can be Connected either to an External Crystal or an External Reference Clock
4
VDD
P
Power Supply for the Entire Chip
5
ModOUT
O
Spread Spectrum Clock Output
6
VSS
P
Ground Connection
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
VDD, VIN
Parameter
Rating
Unit
Voltage on any Pin with Respect to Ground
−0.5 to +4.6
V
Storage Temperature
−65 to +125
°C
TS
Maximum Soldering Temperature (10 s)
260
°C
TJ
Junction Temperature
150
°C
2
kV
TSTG
TDV
Static Discharge Voltage (as per JEDEC STD22−A114−B)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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2
ASM3P2760A
Table 4. RECOMMENDED OPERATING CONDITIONS
Parameter
VDD
Description
Supply Voltage
Min
Max
Unit
2.375
3.6
V
TA
Operating Temperature (Ambient Temperature)
0
70
°C
CL
Load Capacitance
−
15
pF
CIN
Input Capacitance
−
7
pF
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 5. DC ELECTRICAL CHARACTERISTICS FOR 2.5 V SUPPLY
Symbol
Parameter
Min
Typ
Max
Unit
VIL
Input Low Voltage
VSS − 0.3
−
0.8
V
VIH
Input High Voltage
2.0
−
VDD + 0.3
V
IIL
Input Low Current
−
−
−35
mA
IIH
Input High Current
−
−
35
mA
IXOL
XOUT Output Low Current (@ 0.5 V, VDD = 2.5 V)
−
3
−
mA
IXOH
XOUT Output High Current (@ 1.8 V, VDD = 2.5 V)
−
3
−
mA
VOL
Output Low Voltage (VDD = 2.5 V, IOL = 8 mA)
−
−
0.6
V
VOH
Output High Voltage (VDD = 2.5 V, IOH = 8 mA)
1.8
−
−
V
IDD
Static Supply Current (Note 1)
−
−
10
mA
ICC
Dynamic Supply Current (2.5 V, 8 MHz and No Load)
VDD
Operating Voltage
tON
ZOUT
2.5
mA
2.375
2.5
2.625
V
Power-Up Time (First Locked Cycle after Power-Up) (Note 2)
−
−
5
ms
Output Impedance
−
50
−
W
Min
Typ
Max
Unit
Input Frequency
6
−
12
MHz
Output Frequency
6
−
12
MHz
Frequency Deviation
Input Frequency = 6 MHz
Input Frequency = 12 MHz
−
−
±1.0
±0.45
−
−
1. XIN/CLKIN pin and PD pin are pulled low.
2. VDD and XIN/CLKIN input are stable, PD pin is made high from low.
Table 6. AC ELECTRICAL CHARACTERISTICS FOR 2.5 V SUPPLY
Symbol
CLKIN
ModOUT
fD
Parameter
%
tLH*
Output Rise Time (Measured at 0.7 V to 1.7 V)
0.4
1.2
1.4
ns
tHL*
Output Fall Time (Measured at 1.7 V to 0.7 V)
0.4
0.9
1.1
ns
tJC
Jitter (Cycle-to-Cycle)
−
±200
−
ps
tD
Output Duty Cycle
45
50
55
%
* tLH and tHL are measured into a capacitive load of 15 pF.
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3
ASM3P2760A
Table 7. DC ELECTRICAL CHARACTERISTICS FOR 3.3 V SUPPLY
Symbol
Min
Typ
Max
Unit
VIL
Input Low Voltage
VSS − 0.3
−
0.8
V
VIH
Input High Voltage
2.0
−
VDD + 0.3
V
IIL
Input Low Current
−
−
−35
mA
IIH
Input High Current
−
−
35
mA
IXOL
XOUT Output Low Current (@ 0.4 V, VDD = 3.3 V)
−
3
−
mA
IXOH
XOUT Output High Current (@ 2.5 V, VDD = 3.3 V)
−
3
−
mA
VOL
Output Low Voltage (VDD = 3.3 V, IOL = 8 mA)
−
−
0.4
V
VOH
Output High Voltage (VDD = 3.3 V, IOH = 8 mA)
2.5
−
−
V
IDD
Static Supply Current (Note 1)
−
−
10
mA
ICC
Dynamic Supply Current (3.3 V, 8 MHz and No Load)
VDD
Operating Voltage
tON
Power-Up Time (First Locked Cycle after Power-Up) (Note 2)
Output Impedance
ZOUT
Parameter
3.0
2.7
mA
3.3
3.6
V
−
−
5
ms
−
45
−
W
Min
Typ
Max
Unit
Input Frequency
6
−
13
MHz
Output Frequency
6
−
13
MHz
Frequency Deviation
Input Frequency = 6 MHz
Input Frequency = 13 MHz
−
−
±1.0
±0.4
−
−
1.3
1.5
ns
1. XIN/CLKIN pin and PD pin are pulled low.
2. VDD and XIN/CLKIN input are stable, PD pin is made high from low.
Table 8. AC ELECTRICAL CHARACTERISTICS FOR 3.3 V SUPPLY
Symbol
CLKIN
ModOUT
fD
Parameter
%
tLH*
Output Rise Time (Measured at 0.8 V to 2.0 V)
0.5
tHL*
Output Fall Time (Measured at 2.0 V to 0.8 V)
0.4
1.0
1.2
ns
tJC
Jitter (Cycle-to-Cycle)
−
±200
−
ps
tD
Output Duty Cycle
45
50
55
%
* tLH and tHL are measured into a capacitive load of 15 pF.
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4
ASM3P2760A
Table 9. TYPICAL CRYSTAL SPECIFICATIONS
Fundamental AT Cut Parallel Resonant Crystal
Rating
Nominal Frequency
8 MHz
±50 ppm or Better at 25°C
Frequency Tolerance
Operating Temperature Range
−25 to +85°C
Storage Temperature
−40 to +85°C
Load Capacitance (CP)
18 pF
Shunt Capacitance
7 pF Maximum
25 W
ESR
NOTE: CL is Load Capacitance and Rx is used to prevent oscillations at overtone frequency of the Fundamental frequency.
R
Crystal
Rx
CL
CL
CL = 2 ⋅ (CP − CS)
Where: CL = Load Capacitance of Crystal
CS = Stray Capacitance due to CIN, PCB, Trace, etc.
Figure 3. Typical Crystal Interface Circuit
VDD
C1
0.1 mF
C2
2.2 mF
VDD
ASM3P2760A
Rs
ModOUT
VSS
Figure 4. Typical Application Schematic
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5
ModOUT Clock
ASM3P2760A
Table 10. ORDERING INFORMATION
Part Number
Marking
Package
Temperature
Shipping†
ASM3P2760AF-06OR
E4L
TSOP−6
(Pb-Free)
0 to 70°C
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE V
D
H
ÉÉ
ÉÉ
6
E1
1
NOTE 5
5
2
4
L2
GAUGE
PLANE
E
3
L
M
b
A1
SEATING
PLANE
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
DETAIL Z
e
0.05
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
A
c
DETAIL Z
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
2.75
3.00
1.50
1.70
0.95
1.05
0.40
0.60
0.25 BSC
10°
−
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
6X
3.20
0.95
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
ASM3P2760A
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
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7
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
ASM3P2760/D