P3C1256L - Pyramid Semiconductor

P3C1256L
LOW POWER 32K x 8
STATIC CMOS RAM
FEATURES
VCC Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Access Times
—55/70/85
Wide Range Power Supply: 2.7V to 3.6V
Easy Memory Expansion Using CE and OE Inputs
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
— 28-Pin 600 mil DIP
— 28-Pin 330 mil SOP
— 28-Pin TSOP
Common Data I/O
DESCRIPTION
The P3C1256L is a 262,144-bit low power CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access and
cycle times. Inputs are fully TTL-compatible. The RAM
operates with a wide range power supply (2.7V to 3.6V).
Access times of 55 ns and 70 ns are available. CMOS is
utilized to reduce power consumption to a low level.
with matching access and cycle times. Memory locations
are specified on address pins A0 to A14. Reading is accomplished by device selection (CE and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE or OE is HIGH or WE is LOW.
The P3C1256L device provides asynchronous operation
Functional Block Diagram
Pin ConfigurationS
DIP (P6), SOP (S11-3)
TOP VIEW
Document # SRAM143 REV A
Revised October 2011
P3C1256L - 32K x 8 STATIC CMOS RAM
RECOMMENDED OPERATING temperature and supply voltage
Temperature Range (Ambient)
Supply Voltage
Commercial (0°C to 70°C)
2.7V ≤ VCC ≤ 3.6V
Industrial (-40°C to 85°C)
2.7V ≤ VCC ≤ 3.6V
Military (-55°C to 125°C)
2.7V ≤ VCC ≤ 3.6V
Maximum Ratings(1)
Sym
Parameter
Min
Max
Unit
VCC
Supply Voltage with Respect to GND
-0.5
7.0
V
VTERM
Terminal Voltage with Respect to GND (up to 7.0V)
-0.5
VCC + 0.5
V
TA
Operating Ambient Temperature
-55
125
°C
STG
Storage Temperature
-65
150
°C
IOUT
Output Current into Low Outputs
25
mA
ILAT
Latch-up Current
> 200
mA
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(2)
Sym Parameter
Test Conditions
Min
VOH
Output High Voltage (I/O0 - I/O7)
IOH = -1mA, VCC = 3.0V
2.4
VOL
Output Low Voltage (I/O0 - I/O7)
IOL = 2.1mA
VIH
Input High Voltage
VIL
Input Low Voltage
ILI
Input Leakage Current
GND ≤ VIN ≤ VCC
Max
Unit
V
0.4
V
2.2
VCC + 0.3
V
-0.5(3)
0.8
V
Com
-2
+2
Ind
-5
+5
Com
-2
+2
Ind
-5
+5
µA
3
mA
100
µA
µA
Mil
ILO
Output Leakage Current
GND ≤ VOUT ≤ VCC
CE = VIH
ISB
VCC Current
TTL Standby Current
(TTL Input Levels)
VCC = 3.6V, IOUT = 0 mA
ISB1
VCC Current
CMOS Standby Current
(CMOS Input Levels)
VCC = 3.6V, IOUT = 0 mA
CE = VIH
CE ≥ VCC - 0.2V
Mil
N/A = Not applicable
Document # SRAM143 REV A
Page 2
P3C1256L - 32K x 8 STATIC CMOS RAM
CAPACITANCES(4)
(VCC = 3.3V, TA = 25°C, f = 1.0MHz)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max
Unit
VIN=0V
7
pF
VOUT=0V
9
pF
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Sym
ICC
Parameter
Dynamic Operating Current*
Temperature Range
*
**
-55
-70
-85
-55
Commercial
70
70
70
Industrial
85
85
85
Military
100
100
100
Unit
-70
-85
15
15
15
mA
25
25
25
mA
35
35
35
mA
* Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously
enabled for writing, i.e. CE and WE ≤ VIL (max), OE is high. Switching inputs are 0V and 3V.
** As above but @ f=1 MHz and VIL/VIH = 0V/VCC.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Sym
Parameter
-55
Min
-70
Max
Max
70
Min
Max
Read Cycle Time
tAA
Address Access Time
55
70
85
ns
tAC
Chip Enable Access Time
55
70
85
ns
tOH
Output Hold from Address Change
5
5
5
ns
tLZ
Chip Enable to Output in Low Z
5
5
5
ns
tHZ
Chip Disable to Output in High Z
20
25
30
ns
tOE
Output Enable Low to Data Valid
30
35
40
ns
tOLZ
Output Enable Low to Low Z
tOHZ
Output Enable High to High Z
tPU
Chip Enable to Power Up Time
tPD
Chip Disable to Power Down Time
5
85
Unit
tRC
Document # SRAM143 REV A
55
Min
-85
5
20
0
5
25
0
55
ns
ns
30
0
70
ns
ns
85
ns
Page 3
P3C1256L - 32K x 8 STATIC CMOS RAM
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (ADDRESS CONTROLLED)(5,7)
Notes:
1.Stresses greater than those listed under Maximum Ratings may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to Maximum rating conditions for extended
periods may affect reliability.
2.Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3.Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
Document # SRAM143 REV A
4.This parameter is sampled and not 100% tested.
5.WE is HIGH for READ cycle.
6.CE is LOW and OE is LOW for READ cycle.
7.ADDRESS must be valid prior to, or coincident with CE transition
LOW.
8.Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
9.Read Cycle Time is measured from the last valid address to the first
transitioning address.
Page 4
P3C1256L - 32K x 8 STATIC CMOS RAM
AC CHARACTERISTICS—WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
Parameter
-55
Min
-70
Max
Min
-85
Max
Min
Max
Unit
tWC
Write Cycle Time
55
70
85
ns
tCW
Chip Enable Time to End of Write
50
60
75
ns
tAW
Address Valid to End of Write
50
60
75
ns
tAS
Address Setup Time
0
0
0
ns
tWP
Write Pulse Width
40
50
60
ns
tAH
Address Hold Time
0
0
0
ns
tDW
Data Valid to End of Write
25
30
35
ns
tDH
Data Hold Time
0
0
0
ns
tWZ
Write Enable to Output in High Z
tOW
Output Active from End of Write
25
5
30
5
35
5
ns
ns
TIMING WAVEFORM OF WRITE Cycle No. 1 (WE Controlled)(10,11)
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. OE is LOW for this WRITE cycle to show tWZ and tOW.
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
Document # SRAM143 REV A
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Page 5
P3C1256L - 32K x 8 STATIC CMOS RAM
Timing Waveform of Write Cycle No. 2 (CE Controlled)(10)
AC TEST CONDITIONS
Input Pulse Levels
TRUTH TABLE
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
Figure 1. Output Load
Mode
I/O
Power
CE
OE
WE
Standby
H
X
X
High Z
Standby
Standby
X
X
X
High Z
Standby
DOUT Disabled
L
H
H
High Z
Active
Read
L
L
H
DOUT
Active
Write
L
X
L
High Z
Active
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the high speed of the P3C1256L, care must be taken when
testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
Document # SRAM143 REV A
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at
the comparator input, and a 589Ω resistor must be used in series with
DOUT to match 639Ω (Thevenin Resistance).
Page 6
P3C1256L - 32K x 8 STATIC CMOS RAM
DATA RETENTION CHARACTERISTICS
Sym
Parameter
Test Conditions
Typ.*
VCC =
Min
2.0V
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to Data Retention Time
tR†
Operation Recovery Time
Max
VCC =
3.0V
2.0V
Unit
3.0V
2.0
10
CE ≥ VCC - 0.2V,
VIN ≥ VCC - 0.2V
or VIN ≤ 0.2V
V
15
80
120
µA
0
ns
tRC§
ns
* TA = +25°C
tRC§ = Read Cycle Time
† = This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document # SRAM143 REV A
Page 7
P3C1256L - 32K x 8 STATIC CMOS RAM
ORDERING INFORMATION
Document # SRAM143 REV A
Page 8
P3C1256L - 32K x 8 STATIC CMOS RAM
PLASTIC DUAL IN-LINE PACKAGE
P6
Pkg #
# Pins
28 (600 mil)
Symbol
Min
Max
A
0.090
0.200
A1
0.000
0.070
b
0.014
0.020
b2
0.015
0.065
C
0.008
0.012
D
1.380
1.430
E
0.485
0.550
E1
0.600
0.625
e
eB
L
0.100 BSC
0.600 TYP
0.100
0.180
0°
15°
SOIC/SOP SMALL OUTLINE IC PACKAGE
Pkg #
S11-3
# Pins
28 (330 Mil)
Symbol
Min
Max
A
0.094
0.120
A1
0.002
0.014
B
0.014
0.020
C
0.008
0.012
D
0.702
0.728
e
0.050 BSC
E
0.291
0.340
H
0.463
0.477
h
0.010
0.029
L
0.020
0.050
0°
8°
Document # SRAM143 REV A
Page 9
P3C1256L - 32K x 8 STATIC CMOS RAM
TSOP THIN SMALL OUTLINE PACKAGE
T1
Pkg #
# Pins
28
Symbol
Min
Max
A
0.039
0.047
A2
0.036
0.040
b
0.007
0.011
D
0.461
0.469
E
0.311
0.319
e
HD
0.022 BSC
0.520
0.535
Document # SRAM143 REV A
Page 10
P3C1256L - 32K x 8 STATIC CMOS RAM
REVISIONS
DOCUMENT NUMBER
SRAM143
DOCUMENT TITLE
P3C1256L LOW POWER 32K x 8 STATIC CMOS RAM
REV
ISSUE DATE
ORIGINATOR
OR
Jul-2011
JDB
New Data Sheet
A
Oct-2011
JDB
Added wide range power supply
Document # SRAM143 REV A
DESCRIPTION OF CHANGE
Page 11