P4C150 ULTRA HIGH SPEED 1K X 4 RESETTABLE STATIC CMOS RAM FEATURES Separate Input and Output Ports Full CMOS, 6T Cell Three-State Outputs High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military) Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 24-Pin 300 mil DIP – 24-Pin 300 mil SOIC – 28-Pin LCC (350 x 550 mils) – 24-Pin CERPACK Chip Clear Function Low Power Operation Single 5V ± 10% Power Supply DESCRIPTION The P4C150 is a 4,096-bit ultra high-speed static RAM organized as 1K x 4 for high speed cache applications. The RAM features a reset control to enable clearing all words to zero within two cycle times. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs and outputs are fully TTLcompatible. The RAM operates from a single 5V ± 10% tolerance power supply. Time required to reset is only 20 ns for the 10 ns SRAM. CMOS is used to reduce power consumption to a low level. The P4C150 is available in 24-pin 300 mil DIP and SOIC packages providing excellent board level densities. The device is also available in a 28-pin LCC package as well as a 24-pin FLATPACK for military applications. Access times as fast as 10 nanoseconds are available permitting greatly enhanced system operating speeds. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS DIP (P4, C4, D4), SOIC (S4) CERPACK (F3) SIMILAR LCC (L5) Document # SRAM105 REV A 1 Revised October 2005 P4C150 MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND – 0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) – 0.5 to VCC +0.5 V TA Operating Temperature – 55 to +125 °C Symbol Parameter Value Unit TBIAS Temperature Under Bias – 55 to +125 °C TSTG Storage Temperature – 65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) RECOMMENDED OPERATING CONDITIONS (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Symbol Parameter Conditions Typ. Unit Grade(2) Ambient Temp Gnd VCC Commercial 0°C to 70°C 0V 5.0V ± 10% CIN Input Capacitance VIN = 0V 5 pF -55°C to +125°C 0V 5.0V ± 10% COUT Output Capacitance VOUT= 0V 7 pF Military DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage (2) Symbol P4C150 Test Conditions Parameter Max. Min. Unit VOH Output High Voltage (TTL Load) IOH = –4 mA, VCC = Min. V VOL Output Low Voltage (TTL Load) IOL = +8 mA, VCC = Min VIH Input High Voltage 2.2 VCC =+0.5 V VIL Input Low Voltage –0.5(3) 0.8 V ILI Input Leakage Current VCC = Max., VIN = GND to VCC –5 +5 µA ILO Output Leakage Current VCC = Max., CS = VIH, VOUT = GND to VCC –5 +5 µA 2.4 0.4 V POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter ICC Dynamic Operating Current Temperature Range -10 -12 -15 -20 -25 -35 Unit Commercial 130 130 120 115 100 N/A mA Military N/A N/A 145 135 125 120 mA Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. Document # SRAM105 REV A 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than – 3.0V and – 100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Page 2 of 11 P4C150 AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. Parameter -12 -10 -20 -15 -25 -35 Min Max Min Max Min Max Min Max Min Max Min Max 12 tRC Read Cycle Time tAA Address Access Time 10 12 15 20 25 35 ns tAC Chip Select Access Time 8 10 12 14 15 35 ns tOH Output Hold from Address Change 2 2 2 2 2 2 ns tLZ Chip Enable to Output in Low Z 2 2 2 2 2 2 ns tHZ Chip Disable to Output in High Z 4 6 8 10 13 15 ns tOE Output Enable to Data Valid 7 9 10 14 15 20 ns tOLZ Output Enable to Output in Low Z tOHZ Output Disable to Output in High Z 10 2 15 2 5 20 2 7 25 2 9 35 Unit 2 11 ns 2 13 ns 16 ns TIMING WAVEFORM OF READ CYCLE NO. 1(5,6) CS CONTROLLED)(5, 7) TIMING WAVEFORM OF READ CYCLE NO. 2 (CS Notes: 5.WE is HIGH for READ cycle. 6.CS and OE are LOW for READ cycle. 7.ADDRESS must be valid prior to, or concident with, CS transition LOW, tAA must still be met. Document # SRAM105 REV A 8. Transition is measured ±200 mV from steady state voltage prior to change, with loading as specified in Figure 1. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. Page 3 of 11 P4C150 TIMING WAVEFORM OF READ CYCLE NO. 3 (OE OE Controlled)(5) AC CHARACTERISTICS—RESET CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol Parameter -10 -12 -15 -20 -25 -35 Min Max Min Max Min Max Min Max Min Max Min Max Unit tRRC Reset Cycle Time 20 24 30 40 50 70 ns tWER Write Enable High to Beginning of Reset 0 0 0 0 0 0 ns tCR Chip Select Low to Beginning of Reset 0 0 0 0 0 0 ns tRP 10 12 15 20 25 30 ns tHCR Reset Pulse Width Chip Select Hold after End of Reset 0 0 0 0 0 0 ns tHWR Write Enable Hold after End of Reset 10 12 15 20 25 35 ns tRLZ Reset High to Output in Low Z 0 0 0 0 0 0 ns tRHZ Reset Low to Output in High Z 0 0 ns 8 0 10 0 12 0 16 0 20 TIMING WAVEFORM OF RESET CYCLE Document # SRAM105 REV A Page 4 of 11 P4C150 AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. Parameter -10 -25 -12 -15 -20 -35 Unit Min Max Min Max Min Max Min Max Min Max Min Max tWC Write Cycle Time 10 12 15 20 25 35 ns tCW Chip Enable Time to End of Write 8 10 11 13 15 20 ns tAW Address Valid to End of Write 8 10 13 16 20 25 ns tAS Address Set-up Time 0 1 1 1 2 2 ns tWP Write Pulse Width 8 10 11 13 15 20 ns tAH 0 1 1 1 2 2 ns tDW Address Hold Time from End of Write Data Valid to End of Write 5 8 11 13 15 20 ns tDH Data Hold Time 0 1 1 1 2 2 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 8 5 2 2 12 2 15 3 25 20 3 3 ns ns WE CONTROLLED)(10) TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CS CONTROLLED)(10) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS Notes: 10. CS and WE must be LOW for WRITE cycle. 11. If CS goes HIGH simultaneously with WE high, the output remains in a high impedance state. Document # SRAM105 REV A 12. Write Cycle Time is measured from the last valid address to the first transition address. Page 5 of 11 P4C150 AC TEST CONDITIONS Input Pulse Levels TRUTH TABLE GND to 3.0V Mode RS CS OE WE Output Input Rise and Fall Times 3ns Not Selected X H X X High Z Input Timing Reference Level 1.5V RESET L L X H High Z Output Timing Reference Level 1.5V Output Disabled H L H H High Z READ H L L H DOUT WRITE H L X L High Z Output Load See Figures 1 and 2 Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Due to the ultra-high speed of the P4C150, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required Document # SRAM105 REV A between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Page 6 of 11 P4C150 ORDERING INFORMATION SELECTION GUIDE The P4C150 is available in the following temperature, speed and package options. Speed (ns) Temperature Package Range 10 12 15 20 Commercial Temperature Military Temperature Military Processed* 25 35 Plastic DIP -10PC -12PC -15PC -20PC -25PC N/A Plastic SOIC -10SC -12SC -15SC -20SC -25SC N/A Side Brazed DIP N/A N/A -15CM -20CM -25CM -35CM CERDIP N/A N/A -15DM -20DM -25DM -35DM CERPACK N/A N/A -15FM -20FM -25FM -35FM LCC N/A N/A -15LM -20LM -25LM -35LM Side Brazed DIP N/A N/A -15CMB -20CMB -25CMB -35CMB CERDIP N/A N/A -15DMB -20DMB -25DMB -35DMB CERPACK N/A N/A -15FMB -20FMB -25FMB -35FMB LCC N/A N/A -15LMB -20LMB -25LMB -35LMB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not Available Document # SRAM105 REV A Page 7 of 11 P4C150 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 α C4 SIDE BRAZED DUAL IN-LINE PACKAGE 24 (300 mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 1.280 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 - D4 CERDIP DUAL IN-LINE PACKAGE 24 (300 mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 1.280 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0° 15° Document # SRAM105 REV A Page 8 of 11 P4C150 Pkg # # Pins Symbol A b c D E e k L Q S S1 Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE F3 CERPACK CERAMIC FLAT PACKAGE 24 Min Max 0.060 0.090 0.015 0.022 0.004 0.009 0.630 0.330 0.380 0.050 BSC 0.008 0.015 0.250 0.370 0.026 0.045 0.085 0.005 - L5 RECTANGULAR LEADLESS CHIP CARRIER 28 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.342 0.358 0.200 BSC 0.100 BSC 0.358 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 5 9 Document # SRAM105 REV A Page 9 of 11 P4C150 Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α Pkg # # Pins Symbol A A1 b2 C D e E H h L α P4 PLASTIC DUAL IN-LINE PACKAGE 24 (300 Mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.070 0.008 0.014 1.230 1.280 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 0° 15° S4 SOIC/SOP SMALL OUTLINE IC PACKAGE 24 (300 Mil) Min Max 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.012 0.598 0.614 0.050 BSC 0.291 0.299 0.394 0.419 0.010 0.029 0.016 0.050 0° 8° Document # SRAM105 REV A Page 10 of 11 P4C150 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM105 P4C150 ULTRA HIGH SPEED 1K x 4 RESETTABLE STATIC CMOS RAM REV. ISSUE DATE ORIG. OF CHANGE OR 1997 DAB New Data Sheet A Oct-05 JDB Change logo to Pyramid Document # SRAM105 REV A DESCRIPTION OF CHANGE Page 11 of 11