P4C1024 HIGH SPEED 128K x 8 DUAL CHIP ENABLE CMOS STATIC RAM FEATURES High Speed (Equal Access and Cycle Times) — 15/20/25/35 ns (Commercial/Industrial) — 20/25/35/45/55/70/85/100/120 ns (Military) Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE1, CE2 and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology DESCRIPTION The P4C1024 is a 1,048,576-bit high-speed CMOS static RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. Access times of 15 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P4C1024 is a member of a family of PACE RAM™ products offering fast access times. FUNCTIONAL BLOCK DIAGRAM Fast tOE Automatic Power Down Packages —32-Pin 300 mil DIP and SOJ —32-Pin 400 mil SOJ —32-Pin 600 mil Ceramic DIP —32-Pin 400 mil Ceramic DIP —32-Pin Solder Seal Flatpack —32-Pin LCC (450 x 550 mil) —32-Pin LCC (400 x 820 mil) [Two-Sided] —32-Pin Ceramic SOJ The P4C1024 device provides asynchronous operations with matching access and cycle times. Memory locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/ output pins stay in the HIGH Z state when either CE1 or OE is HIGH or WE or CE2 is LOW. PIN CONFIGURATION DIP (P300, C10, C11), SOJ (J300, J400, CJ1), LCC (L1), SOLDER SEAL FLATPACK (FS-3) SIMILAR LCC (L6) Document # SRAM124 REV C Revised December 2011 P4C1024 Maximum Ratings(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND –0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) –0.5 to VCC +0.5 V TA Operating Temperature –55 to +125 °C ecommended Operating R TEMPERATURE and Supply Voltage Grade(2) Ambient Temperature GND VCC 0V 0V 0V 5.0V ± 10% 5.0V ± 10% 5.0V ± 10% Military –55°C to +125°C –40°C to +85°C Industrial Commercial 0°C to +70°C Symbol Parameter Value Unit TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz Symbol Parameter Conditions Typ. Unit CIN Input Capacitance COUT Output Capacitance VOUT = 0V VIN = 0V 8 pF 10 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter P4C1024 Min Max 2.2 VCC +0.5 Test Conditions VIH Input High Voltage VIL Input Low Voltage VHC VLC CMOS Input High Voltage VCD Input Clamp Diode Voltage VCC = Min., IIN = –18 mA Output Low Voltage IOL = +8 mA, VCC = Min. (TTL Load) Output High Voltage IOH = –4 mA, VCC = Min. (TTL Load) VCC = Max. Mil. Input Leakage Current VIN = GND to VCC Ind./Com’l. VOL VOH ILI ILO ISB ISB1 –0.5(3) 0.8 P4C1024L Unit Min Max 2.2 VCC +0.5 V –0.5(3) 0.8 VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5 CMOS Input Low Voltage –0.5 (3) 0.2 –0.5 V V 0.2 V –1.2 –1.2 V 0.4 0.4 V (3) 2.4 2.4 V –10 –5 +10 +5 –5 n/a +5 n/a µA –10 –5 +10 +5 –5 n/a +5 n/a µA ___ ___ 35 ___ ___ 25 n/a mA Standby Power Supply Current (TTL Input Levels) CE1 ≥ VIH or Mil. CE2 ≤VIL, Ind./Com’l. VCC= Max, f = Max., Outputs Open Standby Power Supply Current (CMOS Input Levels) CE1 ≥ VHC or Mil. CE2 ≤VLC, Ind./Com’l. VCC= Max, f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC ___ ___ 25 ___ ___ 2 n/a mA Output Leakage Current VCC = Max., CE = VIH, VOUT = GND to VCC Notes: 1.Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Maximum rating conditions for extended Document # SRAM124 REV C Mil. Ind./Com’l. 30 20 periods may affect reliability. 2.Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3.Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4.This parameter is sampled and not 100% tested. Page 2 of 14 P4C1024 POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter ICC Dynamic Operating Current* Temperature Range -15 -20 -25 -35 -45 -55 -70 -85 -100 -120 Unit Commercial 190 160 150 145 N/A N/A N/A N/A N/A N/A mA Industrial N/A 175 165 160 155 N/A N/A N/A N/A N/A mA Military N/A 150 140 135 130 125 115 110 105 100 mA *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH DATA RETENTION CHARACTERISTICS (P4C1024L, Military Temperature Only) Typ.* Max Symbol Parameter Test Condition Min VCC= VCC= 2.0V 3.0V 2.0V 3.0V VDR VCC for Data Retention 2.0 ICCDR Data Retention Current CE1 ≥ VCC – 0.2V or tCDR CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V Chip Deselect to 0 Data Retention Time tR† Operation Recovery Time 50 200 400 600 Unit V µA ns or VIN ≤ 0.2V tRC§ ns *TA = +25°C § † tRC = Read Cycle Time This parameter is guaranteed but not tested. Data Retention Waveform Document # SRAM124 REV C Page 3 of 14 P4C1024 AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) -15 Sym Parameter -20 -25 -35 -45 -55 -70 -85 -100 -120 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit tRC Read Cycle Time 15 tAA Address Access Time 15 20 25 35 45 55 70 85 100 120 ns tAC Chip Enable Access Time 15 20 25 35 45 55 70 85 100 120 ns tOH Output Hold from Address Change 3 3 3 3 3 3 3 3 3 3 ns tLZ Chip Enable to Output in Low Z 3 3 3 3 3 3 3 3 3 3 ns tHZ Chip Disable to Output in High Z 8 9 11 15 20 25 30 35 40 50 ns tOE Output Enable Low to Data Valid 7 9 11 15 20 25 30 35 40 50 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 20 0 25 0 7 0 0 9 0 12 Document # SRAM124 REV C 35 0 11 0 20 45 0 15 0 20 55 0 20 0 20 70 0 25 0 25 85 0 30 0 30 100 0 35 0 35 120 0 40 0 40 ns ns 50 0 45 ns ns 50 ns Page 4 of 14 P4C1024 TIMING WAVEFORM OF Read Cycle No. 1 (OE controlled)(5) TIMING WAVEFORM OF Read Cycle No. 2 (ADDRESS controlled)(5,6) TIMING WAVEFORM OF Read Cycle No. 3 (CE1, CE2 controlled)(5,7,10) Notes: 5.WE is HIGH for READ cycle. 6.CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle. 7.ADDRESS must be valid prior to, or coincident with CE1 transition LOW and CE2 transition HIGH. 8.Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. Document # SRAM124 REV C 9.READ Cycle Time is measured from the last valid address to the first transitioning address. 10. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them. Page 5 of 14 P4C1024 AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol Parameter -15 -20 -25 -35 -45 -55 -70 -85 -100 -120 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit tWC Write Cycle Time 15 20 25 35 45 55 70 85 100 120 ns tCW Chip Enable Time to End of Write 12 15 18 22 30 35 45 50 60 75 ns tAW Address Valid to End of Write 12 15 20 25 35 45 60 70 85 100 ns tAS Address Set-up Time 0 0 0 0 0 0 0 0 0 0 ns tWP Write Pulse Width 12 15 18 22 25 30 40 45 55 70 ns tAH Address Hold Time 0 0 0 0 0 0 0 0 0 0 ns tDW Data Valid to End of Write 7 8 10 15 20 25 30 35 45 60 ns tDH Date Hold Time 0 0 0 0 0 0 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 8 3 10 3 11 3 15 3 18 3 20 3 25 3 30 3 40 3 50 3 ns ns TIMING WAVEFORM OF WRITE Cycle No. 1 (WE Controlled)(11) Notes: 11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle. 12. OE is LOW for this WRITE cycle to show tWZ and tOW. 13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH, the output remains in a high impedance state. Document # SRAM124 REV C 14. Write Cycle Time is measured from the last valid address to the first transitioning address. Page 6 of 14 P4C1024 Timing Waveform of Write Cycle No. 2 (CE Controlled)(11) TRUTH TABLE AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Mode Input Rise and Fall Times 3ns Standby Input Timing Reference Level 1.5V Standby Output Timing Reference Level 1.5V DOUT Disabled See Fig. 1 and 2 Output Load Figure 1. Output Load CE1 CE2 OE WE H I/O Power X X X High Z Standby L X X High Z Standby L H H H High Z Active Read L H H DOUT Write L H L X L High Z Active Active X Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P4C1024, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. Document # SRAM124 REV C To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Page 7 of 14 P4C1024 ORDERING INFORMATION Document # SRAM124 REV C Page 8 of 14 P4C1024 # Pins SOJ SMALL OUTLINE IC PACKAGE (300 mil) J300 Pkg # 32 (300 mil) Symbol Min Max A 0.128 0.148 A1 0.082 - b 0.016 0.020 C 0.007 0.010 D 0.820 0.830 e 0.050 BSC E 0.335 BSC E1 E2 Q 0.295 0.267 BSC 0.025 - SOJ SMALL OUTLINE IC PACKAGE (400 mil) J400 Pkg # # Pins 0.305 32 (400 mil) Symbol Min Max A 0.128 0.148 A1 0.082 - b 0.015 0.020 C 0.007 0.013 D 0.820 0.830 e 0.050 BSC E 0.435 0.445 E1 0.395 0.405 E2 Q 0.370 BSC 0.025 - Document # SRAM124 REV C Page 9 of 14 P4C1024 # Pins Symbol PLASTIC DUAL IN-LINE PACKAGE P300 Pkg # 32 (300 mil) Min Max A - 0.200 A1 0.015 - b 0.014 0.022 b2 0.048 0.054 C 0.008 0.014 D 1.580 1.620 E1 0.270 0.300 E 0.300 0.310 e 0.100 BSC eB 0.320 0.390 L 0.120 0.140 0° 15° α SOLDER SEAL FLAT PACKAGE FS-3 Pkg # # Pins 32 Symbol Min Max A 0.097 0.125 b 0.015 0.019 c 0.003 0.009 D - 0.830 E 0.400 0.420 E1 - 0.450 E2 0.180 - E3 0.030 - e 0.050 BSC L 0.250 0.370 Q 0.020 0.045 S - 0.045 S1 0.000 - M - N 0.002 32 Document # SRAM124 REV C Page 10 of 14 P4C1024 SIDEBRAZED DUAL IN-LINE PACKAGE (600 mil) C10 Pkg # # Pins 32 (600 mil) Min Max A - 0.225 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D - 1.680 E 0.510 Symbol 0.620 eA 0.600 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.070 S1 0.005 - S2 0.005 - SIDEBRAZED DUAL IN-LINE PACKAGE (400 mil) C11 Pkg # # Pins 32 (400 mil) Symbol Min Max A - 0.232 b 0.014 0.023 b2 0.038 0.065 C 0.008 0.018 D - 1.700 E 0.350 0.410 eA 0.400 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.060 S1 0.005 - S2 0.005 - Document # SRAM124 REV C Page 11 of 14 P4C1024 2-SIDED LEADLESS CHIP CARRIER L1 Pkg # # Pins 32 Symbol Min Max A 0.080 0.100 b 0.022 0.028 b1 0.006 0.022 b2 0.040 - D 0.820 0.840 E 0.392 0.400 e 0.050 BSC h 0.012 REF L 0.070 0.080 L1 0.090 0.110 L2 0.003 0.015 N 32 RECTANGULAR LEADLESS CHIP CARRIER L6 Pkg # # Pins 32 Symbol Min Max A 0.060 0.075 A1 0.050 0.065 B1 0.022 0.028 D 0.442 0.458 D1 0.300 BSC D2 0.150 BSC D3 - 0.458 E 0.540 0.560 E1 0.400 BSC E2 0.200 BSC E3 - 0.558 e 0.050 BSC h 0.040 REF j 0.020 REF L 0.045 0.055 L1 0.045 0.055 L2 0.075 0.095 ND 7 NE 9 Document # SRAM124 REV C Page 12 of 14 P4C1024 CERAMIC SOJ SMALL OUTLINE IC PACKAGE CJ1 Pkg # # Pins 32 Symbol Min Max A 0.120 0.165 A1 0.088 0.120 A2 0.070 REF B 0.010 REF B1 0.030R TYP B2 0.020 REF B3 0.025 0.045 D 0.816 0.838 D1 0.750 REF E 0.419 0.431 E1 0.430 0.445 E2 0.360 0.380 e 0.050 BSC e1 0.038 e2 0.005 TYP j 0.005 TYP S 0.030 0.040 S1 0.020 TYP Document # SRAM124 REV C Page 13 of 14 P4C1024 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM124 P4C1024 HIGH SPEED 128K x 8 DUAL CHIP ENABLE CMOS STATIC RAM REV. ISSUE DATE ORIG. OF CHANGE OR 1997 DAB New Data Sheet A Oct-05 JDB Change logo to Pyramid B Jan-11 JDB Added L1 package, corrected data retention table C Dec-11 JDB Removed Selection Guide, combined commercial and industrial temps in features section Document # SRAM124 REV C DESCRIPTION OF CHANGE Page 14 of 14