P4C164LL - Pyramid Semiconductor

P4C164LL
VERY LOW POWER 8Kx8
STATIC CMOS RAM
FEATURES
VCC Current (Commercial/Industrial)
— Operating: 55 mA
— CMOS Standby: 3 µA
Access Times
—80/100 (Commercial or Industrial)
—90/120 (Military)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE1, CE2 and OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—28-Pin 300 and 600 mil DIP
—28-Pin 330 mil SOP
DESCRIPTION
The P4C164LL is a 64K density low power CMOS static
RAM organized as 8Kx8. The CMOS memory requires
no clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply.
Access times of 80 and 100 ns are available for commercial
and industrial temperatures; access times of 90 and 100
ns are available for military temperature. CMOS is utilized
to reduce power consumption to a low level.
The P4C164LL device provides asynchronous operation
with matching access and cycle times.
Functional Block Diagram
Memory locations are specified on address pins A0 to A12.
Reading is accomplished by device selection (CE1 LOW,
CE2 HIGH ) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/
output pins stay in the HIGH Z state when either CE1 or
OE is HIGH or WE or CE2 is LOW.
Package options for the P4C164LL include 28-pin 300 and
600 mil DIP and 28-pin 330 mil SOP packages.
Pin ConfigurationS
DIP (P5, P6, C5-1), SOP (S5)
TOP VIEW
Document # SRAM116 REV 04
Revised June 2014
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Grade
Ambient Temp
Supply Voltage
0°C to 70°C
4.5V ≤ VCC ≤ 5.5V
Industrial
-40°C to +85°C
4.5V ≤ VCC ≤ 5.5V
Military
-55°C to +125°C
4.5V ≤ VCC ≤ 5.5V
Commercial
Maximum Ratings(1)
Symbol
Parameter
Min
Max
Unit
Supply Voltage with Respect to GND
-0.5
7.0
V
Terminal Voltage with Respect to GND (up to 7.0V)
-0.5
VCC + 0.5
V
TA
Operating Ambient Temperature
-55
125
°C
STG
Storage Temperature
-65
150
°C
IOUT
Output Current into Low Outputs
25
mA
ILAT
Latch-up Current
VCC
VTERM
> 200
mA
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(2)
Sym Parameter
Test Conditions
Min
2.4
VOH
Output High Voltage
(I/O0 - I/O7)
IOH= -1mA, VCC = 4.5V
VOL
Output Low Voltage
(I/O0 - I/O7)
IOL = 2.1mA
VIH
Input High Voltage
VIL
Input Low Voltage
ILI
Input Leakage Current
ILO
Output Leakage Current
ISB
VCC Current
TTL Standby Current
(TTL Input Levels)
VCC = 5.5V, IOUT = 0 mA
ISB1
VCC Current
CMOS Standby Current
(CMOS Input Levels)
VCC = 5.5V, IOUT = 0 mA
Com / Ind
GND ≤ VIN ≤ VCC
Document # SRAM116 REV 04
Unit
V
0.4
V
2.2
VCC + 0.3
V
-0.5(3)
0.8
V
-2
+2
µA
GND ≤ VOUT ≤ VCC
CE1 ≥ VIH
Military
-5
+5
Com / Ind
-2
+2
-10
+10
µA
Military
CE1 = VIH or CE2 = VIL
CE1 ≥ VCC - 0.2V or CE2 ≤ 0.2V
Notes:
1.Stresses greater than those listed under Maximum Ratings may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to Maximum rating conditions for extended
periods may affect reliability.
Max
Com / Ind
100
Military
400
µA
Com / Ind
3
µA
Military
25
2.Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3.Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4.This parameter is sampled and not 100% tested.
Page 2
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
CAPACITANCES(4)
Symbol
CIN
Parameter
Test Conditions
Max
Unit
VIN = 0V
7
pF
VOUT = 0V
9
pF
Input Capacitance
COUT
Output Capacitance
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
ICC
Parameter
Temperature Range
Dynamic Operating Current
Com / Ind / Military
*
-80
-90
-100
-120
Unit
55
55
55
55
mA
* Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously
enabled for writing, i.e. CE1 and WE ≤ VIL (max), OE is high. Switching inputs are 0V and 3V.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Sym
Parameter
-80
Min
-90
Max
Max
90
Min
-120
Max
Max
tAA
Address Access Time
80
90
100
120
ns
tAC
Chip Enable Access Time
80
90
100
120
ns
tOH
Output Hold from Address Change
10
10
10
10
ns
tLZ
Chip Enable to Output in Low Z
10
10
10
10
ns
tHZ
Chip Disable to Output in High Z
30
30
30
30
ns
tOE
Output Enable Low to Data Valid
40
40
40
40
ns
tOLZ
Output Enable Low to Low Z
tOHZ
Output Enable High to High Z
tPU
Chip Enable to Power Up Time
tPD
Chip Disable to Power Down Time
5
20
0
5
20
0
80
120
Unit
Read Cycle Time
5
100
Min
tRC
Document # SRAM116 REV 04
80
Min
-100
5
20
0
90
ns
ns
20
0
100
ns
ns
120
ns
Page 3
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(1)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE1, CE2 CONTROLLED)
Notes:
5.WE is HIGH for READ cycle.
6.CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
7.ADDRESS must be valid prior to, or coincident with CE1 transition LOW
and CE2 transition HIGH.
8.Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
Document # SRAM116 REV 04
9.Read Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them.
Page 4
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
AC CHARACTERISTICS—WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
-80
-90
-100
-120
Symbol
Parameter
tWC
Write Cycle Time
80
90
100
120
ns
tCW
Chip Enable Time to End of Write
70
80
80
100
ns
tAW
Address Valid to End of Write
70
80
80
100
ns
tAS
Address Setup Time
0
0
0
0
ns
tWP
Write Pulse Width
60
60
60
60
ns
tAH
Address Hold Time
0
0
0
0
ns
tDW
Data Valid to End of Write
40
40
40
40
ns
tDH
Data Hold Time
0
0
0
0
ns
tWZ
Write Enable to Output in High Z
tOW
Output Active from End of Write
Min
Max
Min
30
10
Max
Min
30
10
Max
Min
30
10
Max
30
10
Unit
ns
ns
TIMING WAVEFORM OF WRITE Cycle No. 1 (WE Controlled)(6)
Notes:
11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle.
12. OE is LOW for this WRITE cycle to show tWZ and tOW.
13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH,
the output remains in a high impedance state
Document # SRAM116 REV 04
14. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Page 5
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
Timing Waveform of Write Cycle No. 2 (CE Controlled)(6)
AC TEST CONDITIONS
Input Pulse Levels
TRUTH TABLE
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
Mode
I/O
Power
CE1
CE2
OE
WE
Standby
H
X
X
X
High Z
Standby
Standby
X
L
X
X
High Z
Standby
DOUT Disabled
L
H
H
H
High Z
Active
Read
L
H
L
H
DOUT
Active
Write
L
H
X
L
High Z
Active
Figure 1. Output Load
Figure 2. Thevenin Equivalent
Note:
Because of the ultra-high speed of the P4C164LL, care must be taken
when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at
the comparator input, and a 589Ω resistor must be used in series with
DOUT to match 639Ω (Thevenin Resistance).
* including scope and test fixture.
Document # SRAM116 REV 04
Page 6
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Test Condition
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to Data Retention Time CE2 ≤ 0.2V, VIN ≥ VCC - 0.2V or
tR†
Operation Recovery Time
Min
Typ. * VCC =
2.0V
3.0V
Max VCC =
2.0V
3.0V
2.0
CE1 ≥ VCC - 0.2V or
VIN ≤ 0.2V
Unit
V
1
2
3
4
µA
0
ns
tRC§
ns
* TA = +25°C
§tRC = Read Cycle Time
† This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
ORDERING INFORMATION
Document # SRAM116 REV 04
Page 7
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
PLASTIC DUAL IN-LINE PACKAGE (300 mil)
P5
Pkg #
# Pins
28 (300 mil)
Symbol
Min
Max
A
-
0.210
A1
-
b
0.014
0.023
b2
0.045
0.070
C
0.008
0.014
D
1.345
1.400
E1
0.270
0.300
E
0.300
0.380
e
0.100 BSC
eB
-
0.430
L
0.115
0.150
0°
15°
α
PLASTIC DUAL IN-LINE PACKAGE (600 mil)
Pkg #
P6
# Pins
28 (600 mil)
Symbol
Min
Max
A
0.090
0.200
A1
0.000
0.070
b
0.014
0.020
b2
0.015
0.065
C
0.008
0.012
D
1.380
1.480
E1
0.485
0.550
E
0.600
0.625
e
0.100 BSC
eB
0.600 TYP
L
0.100
0.200
α
0°
15°
Document # SRAM116 REV 04
Page 8
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
SOIC/SOP SMALL OUTLINE IC PACKAGE
S5
Pkg #
# Pins
28 (330 mil)
Symbol
Min
Max
A
0.079
0.120
A1
0.000
0.008
B
0.012
0.020
C
0.004
0.012
D
0.701
0.728
e
0.050 BSC
E
0.331
0.346
H
0.457
0.488
L
0.016
0.050
α
0°
8°
CERAMIC DUAL IN-LINE PACKAGE (600 mil)
Pkg #
C5-1
# Pins
28 (600 mil)
Symbol
Min
Max
A
-
0.232
b
0.014
0.026
b2
0.045
0.065
C
0.008
0.018
D
-
1.490
E
0.500
0.610
eA
0.600 BSC
e
0.100 BSC
L
0.125
0.200
Q
0.015
0.060
S1
0.005
-
S2
0.005
-
Document # SRAM116 REV 04
Page 9
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
REVISIONS
DOCUMENT NUMBER
SRAM116
DOCUMENT TITLE
P4C164LL - VERY LOW POWER 8Kx8 STATIC CMOS RAM
REV
ISSUE DATE
ORIGINATOR
OR
Oct-2005
JDB
New Data Sheet
A
Aug-2006
JDB
Added Lead Free Designation
B
Jun-2007
JDB
Corrected SOP package details
C
Mar-2010
JDB
Added Military temperature range
04
Jun-2014
JDB
Updated SOIC/SOP Package dimensions
Document # SRAM116 REV 04
DESCRIPTION OF CHANGE
Page 10