PYA28C64(X) - Pyramid Semiconductor

PYA28C64(X)
8K X 8 EEPROM
FEATURES
Access Times of 150, 200, 250 and 350ns
Single 5V±10% Power Supply
Fast Byte Write (200µs or 1 ms)
Low Power CMOS:
- 60 mA Active Current
- 150 µA Standby Current
Fast Write Cycle Time
CMOS & TTL Compatible Inputs and Outputs
Endurance:
- 10,000 Write Cycles
- 100,000 Write Cycles (optional)
Data Retention: 10 Years
Available in the following package:
– 28-Pin 600 mil Ceramic DIP
– 32-Pin Ceramic LCC (450x550 mils)
RDY/BUSY pin is not connected for the
PYA28C64X
DESCRIPTION
PIN CONFIGURATIONS
The PYA28C64 is a 5 Volt 8Kx8 EEPROM. The PYA28C64
features DATA and RDY/BUSY (PYA28C64 only) to indicate
early completion of a Write Cycle. Data Retention is 10
Years. The device is available in a 28-Pin 600 mil wide
Ceramic DIP and 32-Pin LCC.
DIP (C5-1)
FUNCTIONAL BLOCK DIAGRAM
LCC (L6)
NOTE: The RDY/BUSY pin is not connected for the PYA28C64X.
Document # EEPROM105 REV B
Revised June 2012
PYA28C64 - 8K x 8 EEPROM
OPERATION
READ
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
BYTE WRITE
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The PYA28C64 supports both a
CE and WE controlled write cycle. That is, the address is
latched by the falling edge of either CE or WE, whichever
occurs last. Similarly, the data is latched internally by the
rising edge of either CE or WE, whichever occurs first. A
byte write operation, once initiated, will automatically continue to completion.
CHIP CLEAR
The contents of the entire memory of the PYA28C64 may
be set to the high state by the CHIP CLEAR operation.
By setting CE low and OE to 12 volts, the chip is cleared
when a 10 msec low pulse is applied to WE.
DEVICE IDENTIFICATION
An extra 32 bytes of EEPROM memory are available to
the user for device identification. By raising A9 to 12 ±
0.5V and using address locations 1FE0H to 1FFFH the
additional bytes may be written to or read from in the
same manner as the regular memory array.
MAXIMUM RATINGS(1)
Sym
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
-0.3 to +6.25
V
VTERM
Terminal Voltage with
Respect to GND (up to
6.25V)
-0.5 to +6.25
V
TA
Operating Temperature
-55 to +125
°C
TBIAS
Temperature Under Bias
-55 to +125
°C
TSTG
Storage Temperature
-65 to +150
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
RECOMMENDED OPERATING CONDITIONS
Grade(2)
Ambient Temp
GND
VCC
Military
-55°C to +125°C
0V
5.0V ± 10%
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Sym
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Typ
Unit
VIN = 0V
10
pF
VOUT = 0V
10
pF
DATA POLLING
The PYA28C64 features DATA Polling as a method to indicate to the host system that the byte write cycle has
completed. DATA Polling allows a simple bit test operation to determine the status of the PYA28C64, eliminating additional interrupts or external hardware. During the
internal programming cycle, any attempt to read the last
byte written will produce the complement of that data on
I/O7 (i.e., write data=0xxx xxxx, read data=1xxx xxxx).
Once the programming cycle is complete, I/O7 will reflect
true data.
READY/BUSY
Pin 1 is an open drain RDY/BUSY output that can be
used to detect the end of a write cycle. RDY/BUSY is
actively pulled low during the write cycle and is released
at the completion of the write. The open drain connection allows for OR-tying of several devices to the same
RDY/BUSY line. The RDY/BUSY pin is not connected
for the PYA28C64X.
Document # EEPROM105 REV B
Page 2
PYA28C64 - 8K x 8 EEPROM
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(2)
Sym Parameter
Test Conditions
PYA28C64
Min
Max
Unit
VIH
Input High Voltage
2.0
VCC + 0.3
V
VIL
Input Low Voltage
-0.5(3)
0.8
V
VHC
CMOS Input High Voltage
VCC - 0.2
VCC + 0.5
V
VLC
CMOS Input Low Voltage
-0.5(3)
0.2
V
VOL
Output Low Voltage (TTL Load)
IOL = +2.1 mA, VCC = Min
0.45
V
VOH
Output High Voltage (TTL Load)
IOH = -0.4 mA, VCC = Min
ILI
Input Leakage Current
ILO
Output Leakage Current
VCC = Max
VIN = GND to VCC
VCC = Max, CE = VIH,
VOUT = GND to VCC
2.4
V
-10
+10
µA
-10
+10
µA
—
5
mA
—
150
µA
—
60
mA
CE ≥ VIH, OE = VIL,
ISB
Standby Power Supply Current (TTL Input Levels)
VCC = Max,
f = Max, Outputs Open
CE ≥ VHC,
ISB1
Standby Power Supply Current (CMOS Input Levels)
VCC = Max,
f = 0, Outputs Open,
VIN ≤ VLC or VIN ≥ VHC
CE = OE = VIL,
ICC
Supply Current
WE = VIH,
All I/O's = Open,
Inputs = VCC = 5.5V
Notes:
1.Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
Document # EEPROM105 REV B
2.Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than -3.0V and -100mA,
respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
Page 3
PYA28C64 - 8K x 8 EEPROM
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-150
-200
-250
-350
Sym
Parameter
tAVAV
Read Cycle Time
tAVQV
Address Access Time
150
200
250
350
ns
tELQV
Chip Enable Access Time
150
200
250
350
ns
tOLQV
Output Enable Access Time
80
100
100
100
ns
tELQX
Chip Enable to Output in Low Z
tEHQZ
Chip Disable to to Output in High Z
tOLQX
Output Enable to Output in Low Z
tOHQZ
Output Disable to Output in High Z
tAVQX
Output Hold from Address Change
Min
Max
150
Min
200
0
0
Min
0
0
ns
0
ns
ns
70
0
Unit
ns
70
65
0
Max
0
65
60
0
Min
350
0
60
55
Max
250
0
55
0
Max
ns
ns
TIMING WAVEFORM OF READ CYCLE
Document # EEPROM105 REV B
Page 4
PYA28C64 - 8K x 8 EEPROM
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
150 / 200 / 250 / 350
Symbol
Parameter
tELRH
tWLRH
Write Cycle Time
tAVEL
tAVWL
Address Setup Time
10
ns
tELAX
tWLAX
Address Hold Time
50
ns
tWLEL
Write Setup Time
0
ns
tWHEH
Write Hold Time
0
ns
tOHEL
tOHWL
OE Setup Time
10
ns
tWHOL
tEHOL2
OE Hold Time
10
ns
tELEH
tWLWH
WE Pulse Width
100
tDVEH
tDVWH
Data Setup Time
50
ns
tEHDX
tWHDX
Data Hold Time
10
ns
tELWL
CE Setup Time
0
ns
tEHWH
CE Hold Time
0
ns
tEHRL
tWHRL
Time to device busy
Document # EEPROM105 REV B
Min
Max
1
1000
50
Unit
ms
ns
ns
Page 5
PYA28C64 - 8K x 8 EEPROM
TIMING WAVEFORM OF BYTE WRITE CYCLE (CE CONTROLLED)
TIMING WAVEFORM OF BYTE WRITE CYCLE (WE CONTROLLED)
Document # EEPROM105 REV B
Page 6
PYA28C64 - 8K x 8 EEPROM
AC TEST CONDITIONS
Input Pulse Levels
TRUTH TABLE
GND to 3.0V
Input Rise and Fall Times
10ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figure 1
Mode
CE
OE
WE
I/O
Read
L
L
H
DOUT
Write
L
H
L
DIN
Write Inhibit
X
L
X
—
Write Inhibit
X
X
H
—
Standby
H
X
X
High Z
Output Disable
X
H
X
High Z
Figure 1. Output Load
Document # EEPROM105 REV B
Page 7
PYA28C64 - 8K x 8 EEPROM
ORDERING INFORMATION
Document # EEPROM105 REV B
Page 8
PYA28C64 - 8K x 8 EEPROM
SIDE BRAZED DUAL IN-LINE PACKAGE (600 mils)
C5-1
Pkg #
# Pins
28 (600 mil)
Symbol
Min
Max
A
-
0.232
b
0.014
0.026
b2
0.045
0.065
C
0.008
0.018
D
-
1.490
E
0.500
0.610
eA
0.600 BSC
e
0.100 BSC
L
0.125
0.200
Q
0.015
0.060
S1
0.005
-
S2
0.005
-
Pkg #
L6
# Pins
32
RECTANGULAR LEADLESS CHIP CARRIER
Symbol
Min
Max
A
0.060
0.075
A1
0.050
0.065
B1
0.022
0.028
D
0.442
0.458
D1
0.300 BSC
D2
0.150 BSC
D3
-
0.458
E
0.540
0.560
E1
0.400 BSC
E2
0.200 BSC
E3
-
0.558
e
0.050 BSC
h
0.040 REF
j
0.020 REF
L
0.045
0.055
L1
0.045
0.055
L2
0.075
0.095
ND
7
NE
9
Document # EEPROM105 REV B
Page 9
PYA28C64 - 8K x 8 EEPROM
REVISIONS
DOCUMENT NUMBER
EEPROM105
DOCUMENT TITLE
PYA28C64(X) - 8K x 8 EEPROM
REV
ISSUE DATE
ORIGINATOR
OR
Jul 2010
JDB
New Data Sheet
A
Nov 2011
JDB
Updated Ordering Info
B
Jun 2012
JDB
Updated Ordering Info; Changed "Simple Byte Write" to " Fast Byte
Write (200µs or 1 ms)" on p.1
Document # EEPROM105 REV B
DESCRIPTION OF CHANGE
Page 10