PI6C4921506 High Performance LVDS Fanout Buffer Features Description ÎÎ6 LVDS outputs The PI6C4921506 is a high performance fanout buffer devicewhich supports up to 1.5GHz frequency. The device also uses Pericom's proprietary input detection technique to make sure illegal input conditions will be detected and reflected by output states. This device is ideal for systems that need to distribute low jitter clock signals to multiple destinations. ÎÎUp to 1.5GHz output frequency ÎÎUltra low additive phase jitter: < 0.03 ps (typ) (differential 156.25MHz, 12KHz to 20MHz integration range) ÎÎSingle differential input ÎÎLow delay from input to output (Tpd typ. < 1.5ns) ÎÎSeparate Input output supply voltage for level shifting Applications ÎÎ2.5V / 3.3V power supply ÎÎNetworking systems including switches and Routers ÎÎIndustrial temperature support ÎÎHigh frequency backplane based computing and telecom ÎÎTSSOP-24 package platforms Pin Configuration (24-Pin TSSOP) Block Diagram 1 24 GND CLK 2 23 GND VDD 3 22 VDD VDDO 4 21 VDDO Q0 5 20 nQ5 nQ0 6 19 Q5 GND 7 18 GND Q1 8 17 nQ4 nQ1 9 16 Q4 VDDO 10 15 VDDO Q2 11 14 nQ3 nQ2 12 13 Q3 nCLK 15-0080 1 www.pericom.com Rev B 06/18/15 PI6C4921506 High Performance LVDS Fanout Buffer Pinout Table Pin # Pin Name Type nCLK 1, 2 CLK Description Input Differential clock input 3, 22 VDD Power Power supply 4, 10, 15, 21 VDDO Power IO power supply Output LVDS output clock Power Ground Output LVDS output clock Output LVDS output clock Output LVDS output clock Output LVDS output clock Output LVDS output clock Q0 5, 6 nQ0 7, 18, 23, 24 GND Q1 8, 9 nQ1 Q2 11, 12 nQ2 Q3 13, 14 nQ3 Q4 16, 17 nQ4 Q5 19, 20 nQ5 Clock Input Function Table Inputs CLK Outputs nCLK Q0:Q5 Input to Output Mode nQ0:nQ5 Polarity 0 1 LOW HIGH Differential to Differential Non Inverting 1 0 HIGH LOW Differential to Differential Non Inverting 0 Biased LOW HIGH Single Ended to Differential Non Inverting 1 Biased HIGH LOW Single Endded to Differential Non Inverting Biased 0 HIGH LOW Single Endded to Differential Inverting Biased 1 LOW HIGH Single Endded to Differential Inverting 15-0080 2 www.pericom.com Rev B 06/18/15 PI6C4921506 High Performance LVDS Fanout Buffer Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested) Supply Voltage, VDD................................................................. 4.65V Note: Inputs, VI............................................................. 0.5V to VDD +0.5V Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Outputs, IO (LVDS) Continuous Current............................................................ 10mA Surge Current....................................................................... 15mA Package Thermal Impedence, ΘJA........................ 70°C/W (0 mps) Storage temperature, TSTG (Junction-to-Ambient) ...................................................................................... -65 to +150ºC Power Supply DC Characteristics (VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C) Symbol Parameter VDD Test Condition Min. Typ. Max. Units Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 70 mA IDDO Output Supply Current 100 mA Power Supply DC Characteristics (VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C) Symbol Parameter VDD Test Condition Min. Typ. Max. Units Positive Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 65 mA IDDO Output Supply Current 102 mA Max. Units Differential DC Characteristics (VDD = VDDO = 3.3V±5% or 2.5V±5%, TA = -40°C TO 85°C) Symbol Parameter Test Condition Min. Typ. IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage(1) 0.15 1.3 V VCMR Common Mode Input Voltage(1, 2) GND+0.5 VDD-0.85 V CLK VIN = VDD 10 μA nCLK VIN = VDD 150 μA CLK VIN = 0V -150 μA nCLK VIN = 0V -10 μA Note: 1. VIL should not be less than -0.3V 2. Common mode voltage is defined as VH 15-0080 3 www.pericom.com Rev B 06/18/15 PI6C4921506 High Performance LVDS Fanout Buffer LVDS DC Characteristics (VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C) Symbol Parameter VOD Differential Output Voltage ΔVOD VOD Magnitude Change VOS Offset Voltage ΔVOS VOS Magnitude Change Test Condition Min. Typ. 326 1.2 Max. Units 526 mV 50 mV 1.3 V 50 mV Max. Units 505 mV 50 mV 1.3 V 50 mV Max. Units 1.5 GHz 1100 ps 55 ps Note: Please refer to Parameter Measurement Information for output information. LVDS DC Characteristics (VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C) Symbol Parameter VOD Differential Output Voltage ΔVOD VOD Magnitude Change VOS Offset Voltage ΔVOS VOS Magnitude Change Test Condition Min. Typ. 305 1.15 Note: Please refer to Parameter Measurement Information for output information. AC Characteristics (VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C) Symbol Parameter Test Condition Min. Typ. f MAX Output Frequency tPD Propagation Delay(1) tsk(o) Output Skew(2, 3) tjit Buffer Additive Phase Jitter, RMS 622.08MHz, Integration Range: 12kHz – 20MHz tR / tF Output Rise/Fall Time 20% to 80% 50 250 ps odc Output Duty Cycle ≤ 622MHz 47 53 % 800 0.067 ps Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. 1. Measured from the differential input crossing point to the differential output crossing point. 2. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured from at the output differential cross points. 3. This parameter is defined in accordance with JEDEC Standard 65. 15-0080 4 www.pericom.com Rev B 06/18/15 PI6C4921506 High Performance LVDS Fanout Buffer AC Characteristics (VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C) Symbol Parameter f MAX Output Frequency tPD Propagation Delay(1) tsk(o) Output Skew(2, 3) tjit Buffer Additive Phase Jitter, RMS 622.08MHz, Integration Range: 12kHz – 20MHz tR / tF Output Rise/Fall Time 20% to 80% 50 250 ps odc Output Duty Cycle ≤ 622MHz 47 53 % 15-0080 Test Condition Min. Typ. 800 5 Max. Units 1.5 GHz 1200 ps 55 ps 0.067 www.pericom.com ps Rev B 06/18/15 PI6C4921506 High Performance LVDS Fanout Buffer Output Skew Propagation Delay Output Skew TSK Propagation Delay TPD VIH CLK/nCLK CLK/ nCLK TPLH TPHL Q VOH TPLHx TPHLx Qn VOL TSK TSK VOL TR TF VIL VOH Qn+1 VOH VOL TPLHy TPHLy TSK = TPLHy - TPLHx or TSK = TPHLy - TPHLx TSK = TPLH2 - TPLH1 or TSK = TPHL2 - TPHL1 Part to Part Skew Part-to-Part Skew VIH CLK/nCLK TPLH1 TPHL1 Part1 Q VIL VOH VOL TSK TSK Part2 Q VOH VOL TPLH2 TPHL2 TSK = TPLH2 - TPLH1 or TSK = TPHL2 - TPHL1 15-0080 6 www.pericom.com Rev B 06/18/15 PI6C4921506 High Performance LVDS Fanout Buffer Configuration Test Load Board Termination for LVDS outputs LVDS Buffer VDDQx Z o = 50 L = 0 ~ 10 in. 100 Z o = 50 15-0080 7 www.pericom.com Rev B 06/18/15 PI6C4921506 High Performance LVDS Fanout Buffer Packaging Mechanical: 24-Contact TSSOP (L) DATE: 05/03/12 DESCRIPTION: 24-pin, 173mil Wide TSSOP Notes: 1. Refer JEDEC: MO-153F/AD 2. Controlling dimensions in millimeters 3. Package outline exclusive of mold flash and metal burr 12-0374 PACKAGE CODE: L DOCUMENT CONTROL #: PD-1312 REVISION: F Please check for the latest package information on the Pericom web site at www.pericom.com/packaging/ Ordering Information Ordering Number Package Code Package Description PI6C4921506LIE L Pb-free & Green 24-Contact TSSOP PI6C4921506LIEX L Pb-free & Green 24-Contact TSSOP, Tape & Reel • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • E = Pb-free and Green • X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 15-0080 8 www.pericom.com Rev B 06/18/15