PI3VDP12412 4-Lane DisplayPort™ Rev 1.2 Compliant Switch Features Description ÎÎ4-lane, 1:2 mux/demux that will support RBR, HBR1, or Pericom Semiconductor’s PI3VDP12412 mux/demux is targeted for next generation digital video signals. This device can be used to connect a DisplayPort™ Source to two Independent DisplayPort Sinks or to connect two DisplayPort sources to a single DP display. HBR2 ÎÎ1-channel 1:2 mux/demux for DP_HPD signal ÎÎ1-differential channel 1:2 mux/demux for DP_Aux signal with support up to 720Mbps PI3VDP12412 supports DisplayPort 1.2 which requires a data rate of 5.4 Gbps. PI3VDP12412 offers excellent signal integrity at this high data rate with very low insertion loss, good return loss, and very small crosstalk. ÎÎ-1.6dB Insertion Loss for Dx channels @ 2.7 GHz (TQFN) ÎÎ-3dB Bandwidth for Dx channels: 4.6GHz (TQFN) ÎÎReturn loss for Dx channels @ 2.7GHz: -16dB (TQFN) ÎÎLow Bit-to-Bit Skew , 5ps typ (between '+' and '-' bits) PI3VDP12412 is available in two package types, a 5 mm x 5 mm 48 BGA and a 3.5 mm x 9 mm 42 TQFN. The BGA consumes less board space. The TQFN achieves slightly better signal integrity. ÎÎLow Crosstalk for high speed channels: [email protected] Gbps ÎÎLow Off Isolation for high speed channels: [email protected] Gbps ÎÎVDD Operating Range: 3.3V +/-10% ÎÎESD Tolerance: 2kV HBM Application ÎÎLow channel-to-channel skew, 35ps max Routing of DisplayPort signals with low signal attenuation between source and sink. ÎÎPackaging (Pb-free & Green): àà 42 TQFN (ZHE) àà 48 BGA (NEE) Block Diagram D0+ D0 D1+ D1 - D0+A D0-A D1+A D1-A D2+ D2D3+ D3- D2+A D2-A D3+A D3-A D0+B D0-B D1+B D1-B D2+B D2-B D3+B D3-B AUX+ AUXHPD AUX+ A AUX-A HPD A AUX+ B AUX- B HPD B SCL_A (BGA package only) SDA_A (BGA package only) SCL_B (BGA package only) SDA_B (BGA package only) GPU_SEL Logic Control DDC_AUX_SEL (BGA package only) AUX_HPD_SEL (TQFN package only) OE 12-0293 1 12/17/12 PI3VDP12412 4-Lane DisplayPort™ Rev 1.2 Compliant Switch D1+ A D0+A D1- A 40 Truth Table for 42 pin package OE AUX_ GPU_ HPD_ SEL Function SEL 39 GND 41 42 D0-A Pin Assignment (TQFN-42, ZHE) High Low Low Port A active for all channels High Low High Port A for HS, port B for HPD/AUX High High Low Port B for HS, port A for HPD/AUX D2-A 1 38 GPU_SEL D0D0+ AUX_HPD_SEL 2 37 3 36 D2+A D3-A 4 35 D3+A High High High Port B active for all channels 5 34 x x All I/O's are hi-z and IC is power down 6 33 7 32 Vdd D0-B D0+B D1-B D1+B Low D1D1+ D2D2+ D3D3+ Vdd 8 31 (43) 9 30 GND 10 29 11 28 D2-B D2+B D3-B 15 24 16 23 OE AUX-A AUX+A 17 22 21 GND AUX+B Vdd 20 25 19 D3+B 14 AUX-B 26 AUX+ HPD_B HPD_A GND 18 27 13 HPD 12 AUX- Pin Assignment (48-Ball BGA, NEE) 1 2 A GPU GPU_SEL Vdd B D0- _SEL C D0+ 3 GND 4 5 6 D0-A D1-A D2-A D0+A D1+A D2+A 7 OE 8 9 D3+A D3-A D0+B D0-B DDC_ AUX_ SEL GND D D1- D1+ D1+B D1-B E D2- D2+ D2+B D2-B D3+ D3+B D3-B GND GND F D3- G H AUX- AUX+ J HPD HPD_A 12-0293 HPD_B GND Vdd SCL_B SDA_B AUX+B AUX-B GND SCL_A SDA_A OE GPU_ SEL DDC_ AUX_ SEL Function High Low Low Port A active for AUX, HPD & HS channel High Low High Port A active for DDC, HPD, & HS channel High High Low Port B active for AUX, HPD & HS channel High High High Port B active for DDC, HPD & HS channel Low x x all I/Os are hi-z and IC is power down AUX+A AUX-A 2 12/17/12 PI3VDP12412 4-Lane DisplayPort™ Rev 1.2 Compliant Switch 42ZHE 48NEE pin# pin# pin Name Signal Type Description switch logic control. different function for different package options: 42pin TQFN package: If HIGH, then path B is selected for high speed channels only If LOW, then path A is selected for high speed channels only 2 A1 GPU_SEL I 48ball BGA package: If HIGH, then path B is selected for all channels If LOW, then path A is selected for all channels 3 B1 D0- I/O negative differential signal 0 for COM port 4 B2 D0+ I/O positive differential signal 0 for COM port 6 D1 D1- I/O negative differential signal 1 for COM port 7 D2 D1+ I/O positive differential signal 1 for COM port 8 E1 D2- I/O negative differential signal 2 for COM port 9 E2 D2+ I/O positive differential signal 2 for COM port 10 F1 D3- I/O negative differential signal 3 for COM port 11 F2 D3+ I/O positive differential signal 3 for COM port 1 B3 GND Ground Ground 13 H1 AUX- I/O negative differential signal for AUX COM port 14 H2 AUX+ I/O positive differential signal for AUX COM port 18 J1 HPD I/O HPD for COM port 16 J2 HPD_A I/O HPD for port A 15 H3 HPD_B I/O HPD for port B 17 C8 GND Ground Ground 12 J4 VDD Pwr 3.3V +/-10% power supply G2 GND Ground Ground 20 H6 AUX+B I/O positive differential signal for AUX, port B 19 J6 AUX-B I/O negative differential signal for AUX, port B 23 H9 AUX+A I/O positive differential signal for AUX, port A 24 J9 AUX-A I/O negative differential signal for AUX, port A 22 G8 GND Ground Ground 26 F8 D3+B I/O positive differential signal 3 for portB 27 F9 D3-B I/O negative differential signal 3 for portB 28 E8 D2+B I/O positive differential signal 2 for portB 29 E9 D2-B I/O negative differential signal 2 for portB 30 D8 D1+B I/O positive differential signal 1 for portB 31 D9 D1-B I/O negative differential signal 1 for portB 32 B8 D0+B I/O positive differential signal 0 for portB 12-0293 3 (Continued) 12/17/12 PI3VDP12412 4-Lane DisplayPort™ Rev 1.2 Compliant Switch 42ZHE 48NEE pin# pin# pin Name Signal Type Description 33 B9 D0-B I/O negative differential signal 0 for portB 35 A8 D3+A I/O positive differential signal 3 for port A 36 A9 D3-A I/O negative differential signal 3 for port A H4 GND Ground 37 B6 D2+A I/O positive differential signal 2 for port A 38 A6 D2-A I/O negative differential signal 2 for port A 39 B5 D1+A I/O positive differential signal 1 for port A 40 A5 D1-A I/O negative differential signal 1 for port A 41 B4 D0+A I/O positive differential signal 0 for port A 42 A4 D0-A I/O negative differential signal 0 for port A 21 A2 VDD Pwr Power VDD Pwr Power I toggles between passing DDC channels through or AUX channels through If HIGH, then path DDC signals are passed through (depending on port selection via GPU_SEL) If LOW, then path AUX signals are passed through (depending on port selection via GPU_SEL) 34 N/A C2 DDC_ AUX_SEL 5 N/A AUX_HPD_ I SEL switches only the AUX and HPD channels from port A vs. port B N/A H5 SCL_B I/O DDC_clock channel for port B N/A H7 GND Ground N/A H8 SCL_A I/O DDC_clock channel for port A N/A J5 SDA_B I/O DDC_data channel for port B N/A J8 SDA_A I/O DDC_data channel for port A 25 B7 OE I Output enable. if OE is high, IC is enabled. If OE is low, then IC is power down and all I/Os are hi-z 43 N/A Center pad Ground Ground 12-0293 4 12/17/12 PI3VDP12412 4-Lane DisplayPort™ Rev 1.2 Compliant Switch Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to Storage Temperature ........................................................... –65°C to +150°C the device. This is a stress rating only and functional Supply Voltage to Ground Potential ....................................–0.5V to +4.2V operation of the device at these or any other conditions DC Input Voltage .......................................................................–0.5V to VDD above those indicated in the operational sections of this DC Output Current ..............................................................................120mA specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect Power Dissipation .................................................................................... 0.5W reliability. DC Electrical Characteristics for Switching over Operating Range (TA = –40°C to +105°C, VDD = 3.3V ±10%) Parameter Description Test Conditions(1) Min Typ(2) VIH Input HIGH Voltage Guaranteed HIGH level 1.5 VIL Input LOW Voltage Guaranteed LOW level VIK Clamp Diode Voltage (HS Channel) VDD = Max., IIN = –18mA –1.6V –1.8 VIK Clamp Diode Voltage (Aux, Cntrl ) VDD = Max., IIN = –18mA –0.7 –1.5 IIH Input HIGH Current VDD = Max., VIN = VDD ±5 IIL Input LOW Current VDD = Max., VIN = GND ±5 IOFF_SB I/O leakage when part is off for sideVDD = 0V, VINPUT = 0V to 3.6V band signals only (DDC, AUX, HPD) RON_HS On resistance between input to output for high speed signals VDD = 3.0V, Vinput = -0.35V to 2V, IINPUT = 20mA 10.0 Ohm RON_AUX On resistance between input to output for side-band signals (AUX) VDD = 3.0V, Vinput = 0 to 3.3V, IINPUT = 20mA 7 Ohm RON_DDC On resistance between input to output for DDC channel VDD = 3.0V, Vinput = 0V, IINPUT = 20mA 10 Ohm Aux_ss Signal Swing Tolerance in Aux path VDD = 3.0V HPD_I Input voltage on HPD path HPD_O Output voltage tolerance on HPD path Max 0.75 Units V µA 20 –0.5 HPD input from 3.3V to 5.25V 3.6 V 5.5 V 3.3 3.6 V Typ(2) Max Units 1 mA Power Supply Characteristics (TA = –40°C to +105°C) Parameter Description Test Conditions(1) IDD Power Supply Current VDD = 3.3V, OE = 3.3V, VIN = GND or VDD 0.4 IDDQ Quiescent Power Supply Current VDD = 3.3V, OE = GND 1 Min µA 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at V DD = 3.3V, TA = 25°C ambient and maximum loading. 12-0293 5 12/17/12 PI3VDP12412 4-Lane DisplayPort™ Rev 1.2 Compliant Switch Dynamic Electrical Characteristics over Operating Range (TA = -40º to +105ºC, VDD = 3.3V ±10%) Parameter Description Test Conditions1 XTALK Crosstalk on High Speed Channels See Fig. 1 for Measurement Setup OIRR OFF Isolation on High Speed Channels See Fig. 2 for Measurement Setup, ILOSS Differential Insertion Loss on High Speed Channels R loss Differential Return Loss on high speed channels BW_Dx± Bandwidth -3dB for Main high speed path (Dx±) BW_AUX/ -3dB BW for AUX and HPD HPD signals Min Typ2 MAX f= 2.7 GHz -28 -25 f = 1.35 GHz -32 -28 f= 2.7 GHz -22 -20 f = 1.35 GHz -30 -27 TQFN package @5.4Gbps (see figure 3) BGA package @ 2.7GHz (5.4Gbps) See figure 3 -1.8 -1.6 -2.0 -1.8 -16.0 -14 BGA package -14 -12.5 4.1 4.6 BGA package 3.7 4.1 1.35 1.5 See figure 3 dB dB TQFN package TQFN package Units dB GHz GHz Tsw a-b time it takes to switch from port A to port B 1 us Tsw b-a time it takes to switch from port B to port A 1 us Tstartup VDD valid to channel enable 10 us Twakeup Enabling output by changing OE from low to High 10 us 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at V DD = 3.3V, TA = 25°C ambient and maximum loading. Switching Characteristics (TA= -40º to +105ºC, VDD = 3.3V±10%) Parameter Description Tpd Propagation delay (input pin to output pin) on all channels 80 tb-b Bit-to-bit skew within the same differential pair of Dx± channels 5 tch-ch Channel-to-channel skew of Dx± channels 12-0293 Min. 6 Typ. Max. Units ps 7 ps 35 ps 12/17/12 PI3VDP12412 4-Lane DisplayPort™ Rev 1.2 Compliant Switch BALANCED PORT1 BALANCED PORT2 + + 50 – – 50 + + 50 – – 50 DUT Fig 1. Crosstalk Setup BALANCED PORT1 + + 50 – – 50 + BALANCED PORT2 – DUT Fig 2. Off-isolation setup BALANCED PORT1 + + – – BALANCED PORT2 DUT Fig 3. Differential Insertion Loss 12-0293 7 12/17/12 PI3VDP12412 4-Lane DisplayPort™ Rev 1.2 Compliant Switch Test Circuit for Dynamic Electrical Characteristics Agilent N5230A 300kHz-20GHz PNA-L Network Analyzer DUT Fig 4. Crosstalk 12-0293 8 12/17/12 PI3VDP12412 4-Lane DisplayPort™ Rev 1.2 Compliant Switch Fig 5. Off Isolation Fig 6. Insertion Loss 12-0293 9 12/17/12 PI3VDP12412 4-Lane DisplayPort™ Rev 1.2 Compliant Switch Test Circuit for Electrical Characteristics(1-5) 2 * VDD VDD 200-ohm Pulse Generator VIN VOUT D.U.T 4pF CL RT 200-ohm Notes: 1. CL = Load capacitance: includes jig and probe capacitance. 2. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator 3. Output 1 is for an output with internal conditions such that the output is low except when disabled by the output control. 4. Output 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 5. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, t R ≤ 2.5ns, t F ≤ 2.5ns. 6. The outputs are measured one at a time with one transition per measurement. Switching Waveforms SEL 50% 50% VDD 0V Output 1 tPZL tPLZ VOH 10% tPZH tPHZ 90% VOL VOH VOL Output 2 Voltage Waveforms Enable and Disable Times Switch Positions Test Switch tPLZ , tPZL (output on B-side) 2*VDD tPHZ , tPZH (output on B-side) Prop Delay 12-0293 GND Open 10 12/17/12 PI3VDP12412 4-Lane DisplayPort™ Rev 1.2 Compliant Switch DATE: 07/15/11 Notes: 1. Controlling dimensions in millimeters 2. Ref: JEDEC MO-195C DESCRIPTION: 48-Pin, Thin Fine Pitch Ball Grid Array TFBGA PACKAGE CODE: NE48 DOCUMENT CONTROL #: PD-2101 REVISION: -- 12-0332 Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 12-0293 11 12/17/12 PI3VDP12412 4-Lane DisplayPort™ Rev 1.2 Compliant Switch Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information Ordering Code Package Code Package Description PI3VDP12412ZHE ZH Pb-free & Green, 42-contact TQFN PI3VDP12412NEE NE Pb-free & Green, 48-ball BGA Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • "E" denotes Pb-free and Green • Adding an "X" at the end of the ordering code denotes tape and reel packaging 12-0293 12 12/17/12