PI3HDMI2310

PI3HDMI2310
3-Port HDMI™ Signal Switch with I2C Control
Features
Description
3:1 HDMI™ Switch Mux
Pericom Semiconductor’s PI3HDMI series of switch circuits are
targeted for high-resolution video networks that are based on
DVI/HDMI™ standards. The PI3HDMI2310 is a 3-to-1 HDMI
Mux/DeMux signal switch. It is designed for low bit-to-bit skew
and high channel-to-channel noise isolation. The maximum data
rate support is up to 5Gbps which can meet HDMI 1.3a standard and support the resolution requirement of next generation
HDTV and PC graphics.
Non-Blocking EQ path for ideal EQ control in main
Receiver chipset
-3dB bandwidth up to 5Gbps to support HDMI 1.3a (16-bit
color depth per channel)
HDMI 1.4 data rate ready
DDC active signal buffer or passive switch selectable
PI3HDMI2310 is designed specifically for ATC-Sink requirements. All switch control settings are through I2C bus to provide
flexible design and reducing peripheral components. Selectable
active signal buffer for DDC bus can optimize the bi-directional
data transmission for long trace or cable applications.
I2C Register control for switch configuration
Automatic HDCP reset circuitry for quick communication
when switching from one port to another
HPD polarity control and signal trigger through I2C register
setting
All input pins are protected with Pericom’s ESD protection
circuits supporting ESD damage as high as 8kV contact per
IEC61000-4-2 Level 4 specification.
Connector Plug-in detection and Interrupt Flag setting
Selectable HPD 5V signal level shifter with open drain
output stage or output buffer
3.3V power supply and standby power supply
TMDS output enable control
Low power consumption to support Energy Star
Compliance
ESD protection on all I/O pins
 8kV contact per IEC61000-4-2, level 4
Packaging (Pb-free & Green available):
 80-contact LQFP
09-0102
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PS9094
11/30/09
PI3HDMI2310
3-Port HDMI™ Signal Switch with I2C Control
Block Diagram
HPD[A:C]
D[0:3]+A
D[0:3] -A
HPD_SINK
100Kȍ
3:1
Mux
D[0:3]+
D[0:3]I2C
Controller
SCL_CTL
SDA_CTL
Output
Enable
D[0:3]+C
D[0:3] - C
5V_PortA
5V_PortB
5V_PortC
Control & Status
Register
Selectable,
DDC Buffer or
Passive Switch
WP_SET
DDC_WP[A:C]
SCL_A
SDA_A
SCL_SINK
3:1
Mux
SCL_C
SDA_C
SDA_SINK
VSEL
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PS9094
11/30/09
PI3HDMI2310
3-Port HDMI™ Signal Switch with I2C Control
Pin Assignment – 80-Contact LQFP
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
5V_PORTA
5V_PORTB
5V_PORTC
NC
SDA_CTL
SCL_CTL
D0D0+
D1D1+
VDD
D2D2+
D3D3+
A0
A1
HPD_SINK
HPD_A
HPD_B
NC
NC
NC
GND
VDD
SDA_A
SDA_B
SDA_C
GND
SDA_SINK
SVDD
SCL_A
SCL_B
SCL_C
GND
GND
SCL_SINK
NC
HPD_C
GND
D0+B
D1-B
D1+B
D2-B
D2+B
D3-B
D3+B
D0-C
D0+C
D1-C
D1+C
D2-C
D2+C
D3-C
D3+C
NC
NC
NC
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
D0-B
VDD
D3+A
D3-A
D2+A
D2-A
VDD
D1+A
D1-A
SVDD
D0+A
D0-A
OE
VSEL
WP_SET
GND
DDC_WPA
DDC_WPB
DDC_WPC
NC
PI3HDMI2310 IN LQFP80 12X12mm (0.5mm pin pitch) Package (FF80)
Note: VSEL is for I2C buffer VIL selections
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PS9094
11/30/09
PI3HDMI2310
3-Port HDMI™ Signal Switch with I2C Control
Pinout Table
Pin Name
I/O Type
Description
VDD
I/O
3.3V power supply. When VDD is off, the TMDS channels will be powered down.
SVDD
I/O
3.3V standby power supply. SVDD is for all side band signals, I2C register and I2C bus.
Sink side hot plug detector input.
HPD_SINK
I
High: 5-V power signal asserted from source to sink and EDID is ready.
Low: No 5-V power signal asserted from source to sink, or EDID is not ready.
HPD_A
O
Port A HPD output
HPD_B
O
Port B HPD output
HPD_C
O
Port C HPD output
I
Port A TMDS inputs
I
Port B TMDS inputs
I
Port C TMDS inputs
D0+A
D0-A
D1+A
D1-A
D2+A
D2-A
D3+A
D3-A
D0+B
D0-B
D1+B
D1-B
D2+B
D2-B
D3+B
D3-B
D0+C
D0-C
D1+C
D1-C
D2+C
D2-C
D3+C
D3-C
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PS9094
11/30/09
PI3HDMI2310
3-Port HDMI™ Signal Switch with I2C Control
Pin Name
I/O Type
Description
O
TMDS outputs
SCL_A
I/O
Port A DDC Clock
SCL_B
I/O
Port B DDC Clock
SCL_C
I/O
Port C DDC Clock
SDA_A
I/O
Port A DDC Data
SDA_B
I/O
Port B DDC Data
SDA_C
I/O
Port C DDC Data
SCL_SINK
I/O
Sink side DDC Clock
SDA_SINK
I/O
Sink side DDC Data
SCL_CTL
I/O
I2C Clock
SDA_CTL
I/O
I2C Data
WP_SET
I
D0+
D0D1+
D1D2+
D2D3+
D3-
WP_SET = 0 (Default), Set B1b[1] as INT Flag.
WP_SET = 1, DDC_WP[A:C] is programmable by B1b[1].
DDC_WPA,
DDC_WPB,
O
Open drain output. When WP_SET = 1, general purpose logic configured by B1b[1]
OE
I
Output Enable control. Active low.
A1
I
I2C Address 1
A0
I
I2C Address 0
I
Connector 5V port.
DDC_WPC
5V_PortA,
5V_PortB,
5V_PortC
DDC buffer VIL selection.
VSEL
I
VSEL = 0V, VIL = 0.5V
VSEL = 0.5 VDD, VIL=0.45V
VSEL = VDD, VIL=0.6V
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PS9094
11/30/09
PI3HDMI2310
3-Port HDMI™ Signal Switch with I2C Control
Truth Table
WP_SET
B1_b[1]
DDC_WP[A:C]
1
0
Hi_Z
1
1
0
0
X
Hi_Z
I2C Control Register
Address Byte
b7
b6
b5
b4
b3
1
0
1
0
1
b2
b1
b0
A1
A0
Hardware Selectable
Hardware Selectable
0/1 *
* 0:Write; 1:Read
Data Byte 0: Control Register
Bit
Description
Type
Power Up
Condition
7
HDMI input port selection
W
0
Logic Settings
00 = Port A
01 = Port B
6
HDMI input port selection
W
0
10 = Port C
11 = Not Defined
5
HPD Logic Selection
W
1
4
HPD Input Selection
RW
0
3
-
-
-
0 = Inverted
1 = Non Inverted
0 = HPD_SINK
1 = I2C Register Setting B0b[2:0]
I. Byte0 b[4] = 1
2
HPD Port C Logic Setting
W
0
HPD Port C Register setting
II. Byte0 b[4] = 0
Test mode
I. Byte0 b[4] = 1
1
HPD Port B Logic Setting
W
0
HPD Port B Register setting
II. Byte0 b[4] = 0
Test mode
I. Byte0 b[4] = 1
0
HPD Port A Logic Setting
W
0
HPD Port A Register setting
II. Byte0 b[4] = 0
Test mode
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PS9094
11/30/09
PI3HDMI2310
3-Port HDMI™ Signal Switch with I2C Control
Data Byte 1: Control Register
Bit
Description
Type
Power Up
Condition
7
HPD Output Stage selection
W
0
6
Output Enable
W
1
Logic Settings
0 = Open Drain
1 = Output Buffer
0 = Output Disable (also drives switch into
power down mode)
1 = Output Enable
5
-
-
-
4
5V_Port C connect
R
0
3
5V_Port B connect
R
0
2
5V_Port A connect
R
0
0 = Disconnected
1 = Connected; Set INT Flag
0 = Disconnected
1 = Connected; Set INT Flag
0 = Disconnected
1 = Connected; Set INT Flag
When WP_SET = 0, B1b[1] is configured as
INT flag.
1
INT Flag
R/W
0
0 = INT Flag Clear
1 = INT Flag Set
When WP_SET = 1, B1b[1] is configured as
DDC_WP input setting.
0
DDC channel selection
W
0
0 = Passive switch
1 = Active switch buffer
* External hardware control pin WP_SET will set B1b1 to be INT Flag or DDC_WP[A:C] input.
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PS9094
11/30/09
PI3HDMI2310
3-Port HDMI™ Signal Switch with I2C Control
Bus transactions
Data transfers follow the format shown in Fig.1. After the START condition (S), a slave address is
sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W) - a ‘zero’
indicates a transmission (WRITE), a ‘one’ indicates a request for data (READ). A data transfer is always terminated by a STOP condition (P) generated by the master. However, if a master still wishes to
communicate on the bus, it can generate a repeated START condition (Sr) and address another slave
without first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer.
Figure 1: A Complete Data Transfer
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PS9094
11/30/09
PI3HDMI2310
3-Port HDMI™ Signal Switch with I2C Control
Data is transmitted to the PI3HDMI2310 registers using the Write mode as shown in Figure 2. Data is
read from the PI3HDMI2310 registers using the Read mode as shown in Figure 3.
Figure 2 : Write to Control Register
Figure 2 : Read to Control Register
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PS9094
11/30/09
PI3HDMI2310
3-Port HDMI™ Signal Switch with I2C Control
HPD Output Buffer
HPD
Output
Buffer
300K Ohm
Weak Pull-down
Data Channel Pull-down Resistor Control
Pull-down resistor active conditions:
1. The Data Channel is unselected
2. Output enable control OE is disable(OE=High) or B1b[6]=Low, pull down on all channels
3. No normal operation voltage input (but standby voltage SVDD is still On), pull down on all channels
Output Enable control
Output Disable can be asserted through external OE pin or through I2C.
OE
OE_I2C B1b[6]
Operation
Low
High
Enable
Low
Low
Disable
High
X
Disable
Default value: OE = Low ; Byte 1 b[6] = High
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PS9094
11/30/09
PI3HDMI2310
3-Port HDMI™ Signal Switch with I2C Control
Absolute Maximum Ratings (Over operating free-air temperature range)
Item
Rating
Supply Voltage to Ground Potential
5.5V
All Inputs and Outputs
-0.5V to VDD+0.5V
Ambient Operating Temperature
-40 to +85°C
Storage Temperature
-65 to +150°C
Junction Temperature
150°C
Soldering Temperature
260°C
Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Recommended Operation Conditions
Parameter
Min.
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Typ.
Max.
Unit
-40
+85
°C
+3.0
+3.6
V
DC Specifications
VDD = 3.3V ±10%, Ambient Temperature 0 to +70°C
Symbol
Parameter
Conditions
VDD
Operating Voltage
IDD
Supply Current
IDDQ
Quiescent Supply Current
Output Disable
VOH_DDC
DDC passive switch
Output High Voltage
Test condition as IO = 0 (open
load), VI = 5.5V
Min
Nom
Max
Units
3.0
3.3
3.6
V
5
6
Output Enable
mA
1.7
SVDD -1.0
0.4
Source side, IOL = 3mA
VOL_DDC
DDC Buffer Output
Low Voltage
Sink side, IOL = 3mA
External pull-up to 3.3V from
1.5kΩ to 4.7kΩ
VIH_DDC
09-0102
DDC Buffer Input High
Voltage
2
0.65
0.75
Source side (VSEL = 0)
1.7
Sink side (VSEL = 0)
0.5
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V
0.95
PS9094
11/30/09
PI3HDMI2310
3-Port HDMI™ Signal Switch with I2C Control
Symbol
Parameter
VIL_DDC
DDC Buffer Input Low
Voltage
Conditions
Min
Nom
Source side
Max
Units
0.8
Sink side (VSEL = 0)
0.45
0.5
0.6
VIH_V5_A,
Input High Voltage of
5V ports
VIH_V5_B,
2.4
VIH_V5_C
VIL_V5_A,
V
Input Low Voltage of 5V
ports
VIL_V5_B,
0.8
VIL_V5_C
VOL_HPD
VOH_HPD
IOFF (HPD)
Buffer Output Low
Voltage
IOL = 4 mA
Open Drain Output
Low Voltage
IOL = 4 mA
0
Buffer Output High
Voltage
IOH = 3 mA
2.4
0.4
0.4
VDD = 0V, VIN = 3.6V
12
20
VDD = 0V, VIN = 5.5V
20
35
Off Leakage Current
μA
Open Drain Output
Leakage Current
IOZ_HPD
VDD = 3.6V, VIN = 3.6V
12
15
VDD = 3.6V, VIN = 5.5V
21
38
VOL_DDC_WP
Open Drain Output
Low Voltage
IOL = 4 mA
CIO1
Input/output capacitance (Passive Switch)
VDD = 0V or 3.0V, Frequency =
100kHz
6
0.4
V
9
pF
Note:
1. Measured at Vbias = 0V or 5V, Vrms = 0.2V;
Vbias = 1.65V, Vrms = 0.84V;
Vbias = 2.5V, Vrms = 1.2V.
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11/30/09
PI3HDMI2310
3-Port HDMI™ Signal Switch with I2C Control
Dynamic Specifications
VDD = 3.3V ±10%, TA -40 to +85°C, GND = 0V
Parameter
Description
Conditions
XTALK
Crosstalk on High-speed
Channels
Min
Typ
f = 1.13 GHz
-34
f = 825 MHz
-36
Max
Units
dB
OFF Isolation on High-speed
Channels
OIRR
Defferential Insertion Loss on
High-speed Channels
ILOSS
BW
f = 1.13 GHz
-28
f = 825 MHz
-32
DR = 1.65Gbps
-1.5
DR = 2.0Gbps
-1.73
DR = 2.25Gbps
-1.82
DR = 3.0Gbps
-1.99
DR = 3.4Gbps
-2.08
-3dB BW for TMDS channels
dB
2.5
GHz
Capacitance Measurement (VDD = 3.3V, TA =25°C)
Test Condition
Capacitance
SDA_CTL
3.0
SCL_CTL
2.3
HPD_Sink
1.7
Units
pF
Vbias=0.6V
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PS9094
11/30/09
PI3HDMI2310
3-Port HDMI™ Signal Switch with I2C Control
Packaging Mechanical: 80-Contact LQFP (FF)
DATE: 03/18/09
DESCRIPTION: 80-contact, Low Profile Quad Flat Package (LQFP)
PACKAGE CODE: FF (FF80)
REVISION: A
DOCUMENT CONTROL #: PD-2064
07-0100
For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information
Ordering Code
Package Code
Package Type
PI3HDMI2310FFE
FF
Pb-free & Green, 80-Contact, LQFP
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffi x = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336
09-0102
All trademarks are property of their respective owners.
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