PI3HDMI1421

PI3HDMI1421
HDMI™ Revision 1.4 Compliant 2:1/1:2 Mux/Demux
Features
Description
ÎÎCompliant with HDMI 1.4a specification up to 3.4 Gbps
PI3HDMI1421 is industries lowest power HDMI mux/demux
supporting up to 3.4Gbps signal throughput per channel. the PI3HDMI1421 supports switching all TMDS channels, HPD channel, and the DDC channels. The part can behave as 1:2 demux
or a 2:1 mux, since all signal paths are passive and therefore can
support bi-directional data-traffic.
ÎÎLow Intra-pair and Inter-pair skews
ÎÎSingle 3.3 V Power Supply
ÎÎ-40°C to 85°C Operating Temperature Range
ÎÎIntegrated DP++ passive level shifter (48pin version only)
ÎÎHPD Detection
àà TMDS path auto-turn-off when HPD is not present
With integrated ESD protection up to +/-4kV contact per
IEC61000-4-2, the PI3HDMI1421 is ideal for consumer applications.
ÎÎSupports DC and AC Coupled inputs (48-contact TQFN
version only)
ÎÎIntegrated ESD protection to +/-4KV Contact on all I/O pins
per IEC61000-4-2 standard
ÎÎPackage (Pb-free and Green available)
àà 48-contact TQFN, 7mm x 7mm (ZBE)
àà 42-contact TQFN, 9mm x 3.5mm (ZHE)
Applications
ÎÎHDMI Sink (monitor or DTV)
ÎÎPC Motherboard / Graphics Card
ÎÎDigital Set-Top-Box
ÎÎ1-to-2 DP & HDMI/DVI Switch Box
ÎÎDVD player
ÎÎHDMI/DVI monitor or TV
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PI3HDMI1421
HDMI™ Revision 1.4 Compliant 2:1/1:2 Mux/Demux
Functional Block Diagram
Bi-directional Switch
2:1 or 1:2
Ay+
AyVbias (48pin only)
BDy+
BDy-
500ohm
500ohm
OE#
SW
CDy+
CDy-
mux_demux_en
120k Ω
BiDirectional
Buffer
SW
Bi-directional Switch
2:1 or 1:2
DDC_VG
SCL_A / SDA_A
y = 1, 2, 3, 4
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Bi-directional Switch
2:1 or 1:2
HPD_A
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HPD (B or C)
mux_demux_en
120k Ω
SCL (B or C)
SDA (B or C)
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PI3HDMI1421
HDMI™ Revision 1.4 Compliant 2:1/1:2 Mux/Demux
CD3-
CD3+
VDD
CD2-
CD2+
GND
CD1-
CD1+
DDC_VG
VBIAS
A1+
A1-
Pin Configuration (TQFN-48)
36 35 34 33 32 31 30 29 28 27 26 25
39
22
GND
A3+
40
21
SCLC
A3-
41
20
SDAC
GND
42
19
HPDC
A4+
43
18
DNC
A4-
44
17
BD1+
SCL_A
45
16
BD1-
SDA_A
46
15
VDD
HPD_A
47
14
BD2+
Test
48
13
BD2-
4
5
6
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7
8
9
10 11 12
BD3+
3
BD3-
2
GND
1
BD4+
VDD
BD4-
CD4-
VDD
23
SCLB
38
SDAB
A2-
HPDB
CD4+
mux_demux_en
24
OE#
37
SW
A2+
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PI3HDMI1421
HDMI™ Revision 1.4 Compliant 2:1/1:2 Mux/Demux
CD2+
CD1-
CD1+
DDC_VG
Pin Configuration (TQFN-42)
42 41 40 39
A1+
1
38
CD2-
A1-
2
37
CD3+
A2+
3
36
CD3-
A2-
4
35
CD4+
VDD
5
34
CD4-
A3+
6
33
GND
A3-
7
32
SCLC
GND
8
31
SDAC
A4+
9
30
HPDC
A4-
10
29
BD1+
SCL_A
11
28
BD1-
SDA_A
12
27
VDD
HPD_A
13
26
BD2+
SW
14
25
BD2-
OE#
15
24
BD3+
mux_demux_en
16
23
BD3-
HPDB
17
22
BD4+
GND
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BD4-
VDD
SCLB
SDAB
18 19 20 21
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PI3HDMI1421
HDMI™ Revision 1.4 Compliant 2:1/1:2 Mux/Demux
Pin Description
Name
I/O
Description
mux_demux_en
I
H=1:2 demux; L=2:1 mux
DNC
-
Leave pin no connect (do not tie to GND or VDD)
Ay+
I/O
y = 1, 2, 3, 4, for positive differential data or clock inputs.
Ay-
I/O
y = 1, 2, 3, 4, for negative differential data or clock inputs.
xDy+
I/O
x = B,C; y = 1, 2, 3, 4 for positive differential outputs.
xDy-
I/O
x = B,C; y = 1, 2, 3, 4 for negative differential outputs.
HPDx
I/O
When mux_demux_en=High, internal pull-down at ~120Kohm is enabled.
HPDx is 5V tolerant.
HPD_A
I/O
SDA_A, SCL_A
I/O
SDAx, SCLx
I/O
Test
I
When mux_demux_en=Low, internal pull-down at ~120Kohm is enabled.
HPD_A is 5V tolerent.
DDC channel pins to SOURCE
These pins are 5 V tolerant and should be connected to Source side.
x = B, C. These pins are DDC channel pins SDAx/SCLx.
These pins are 5V tolerant and should be connected to Sink side.
For normal operation, please tie to GND
Output Port control
SW
I
SW
Port A connects to B
Port A connects to C
HPD_A
0
Enable
Hi-Z
HPDB
1
Hi-Z
Enable
HPDC
OE# = HIGH, the chip is in power down mode.
OE#
VBIAS (48pin package only)
I
OE# = LOW, the chip is in normal operation mode.
For HDMI/DVI source demultiplexer: Connect to VDD or do not connect.
I
For dual mode DP source demultiplexer: Connect to GND.
High speed channel Ax with 500ohm pulled to ground when Vbias is connected to GND
GND
Ground connection
VDD
Pwr
Power supply at 3.3V
DDC_VG
I
GATE voltage for DDC FETs (connect to voltage from 2.5V to 3.6V)
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PI3HDMI1421
HDMI™ Revision 1.4 Compliant 2:1/1:2 Mux/Demux
ABSOLUTE MAXIMUM RATINGS
Parameters
Comments
Unit
Supply Voltage Range
-0.5V to 4V
Normal I/O Voltage Range
-0.5V to 4V
5V Safe I/O Voltage Range
ESD Pins Ax+/- and xDx+/Pins SCL/SDA_A, HPD_A, SCL/SDAx,
HPDx
SCL_A, SDA_A, SCLx, SDAx, HPD_A,
HPDx
-0.5V to 6V
Contact per IEC-61000-4-2
±4kV
HBM per JESD22
±4kV
Contact per IEC-61000-4-2 HBM per
JESD22
±4kV
±4kV
Normal Operating Conditions
Parameter
Min
Typ
Max
Unit
Supply Voltage, VDD
3.0
3.3
3.6
V
Ambient Temperature
-40
+85
°C
Supply Current, ICC (When HPDx = high and OE# = low)
150
uA
Supply Current, ICC (When HPDx = low and OE# = low)
10
uA
Power down Supply Current, (When OE# = high)
10
uA
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PI3HDMI1421
HDMI™ Revision 1.4 Compliant 2:1/1:2 Mux/Demux
Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
TMDS differential pins
-3dB BW -3dB bandwidth
See fig 5
3.7
GHz
8.5
ohm
All Ax = 2.7V to 3.6V
3.5
pF
@ 2.25Gbps, see fig 5
-1.5
@ 3.4Gbps, see fig 5
-1.8
All Ax = 2.7V to 3.6V
Ron
Resistance through switch path when
ON (A to B or A to C)
Con
Capacitance through switch path
when ON (A to B or A to C)
IN
insertion loss
Xtalk
Crosstalk
@ 3.4Gbps. see fig 3
-38
dB
Isooff
Off Isolation
@ 3.4Gbps. see fig 4
-29
dB
TSK
Inter-pair Skew
20
ps
TSK
Intra-pair Skew
10
ps
IOFF
Off Leakage Current
12
20
μA
Typ
Max
Unit
VIN = 3.0V, I = 20mA
dB
Control Pins
Symbol
Parameter
Test Conditions
Min
IIH
High level digital input current(1)
VIH = 2V or VDD
-10
10
µA
IIL
Low level digital input current(1)
VIH
Input High Voltage
VIL
Input Low Voltage
VIK
Input Clamp Voltage
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VIL = GND or 0.8V
-10
10
2.4
0.8
V
-1.2
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PI3HDMI1421
HDMI™ Revision 1.4 Compliant 2:1/1:2 Mux/Demux
DDC I/O Pins
Symbol
Parameter
Test Conditions
Min
ILK
Input leakage current
VI = 0.1 VDD to VDD to isolated DDC inputs
-20
CIO
Input/Output capacitance
VI peak-peak = 1V, 100 KHz
RON
Switch resistance
IO = 3mA, VO = 0.4V, DDC
VIH
Single-ended high level input voltage
2.4
VIL
Single-ended low level input voltage
GND
IOFF
Off Leakage Current
Typ
12
Max
Unit
20
µA
5
pF
15
Ω
V
0.8
20
V
μA
HPDx
Symbol
Parameter
Test Conditions
Min
IIH
High level digital input current
VIH = 2V or VDD
+20
+40
IIL
Low level digital input current
VIL = GND or 0.8V
-20
20
VOL
Single-ended low level output voltage
IOL = +4mA
GND
0.4
VOH
Single-ended high level output voltage
IOH = -4mA
2.4
V
VIH
Single-ended high level input voltage
2.4
V
VIL
Single-ended low level input voltage
GND
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Typ
Max
0.8
Unit
µA
V
V
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PI3HDMI1421
HDMI™ Revision 1.4 Compliant 2:1/1:2 Mux/Demux
Recommended Power Supply Decoupling Circuit
Figure 1 is the recommended power supply decoupling circuit configuration. It is recommended to put 0.1µF decoupling capacitor on
each VDD pin of our part. Four 0.1µF decoupling capacitors are put in Figure 1 with an assumption of only four V DD pins on our part.
If there is more or less VDD pins on our part, the number of 0.1µF decoupling capacitors should be adjusted according to the actual
number of VDD pins. On top of 0.1µF decoupling capacitor on each VDD pin, it is recommended to put a 10µF decoupling capacitor
near our part’s VDD, it is for stabilizing the power supply for our part. Ferrite bead is also recommended for isolating the power supply
for our part and other power supplies in other parts of the circuit. But, it is optional and depends on the power supply conditions of
other circuits.
10µF
Ferrite Bead
From main
power supply
0.1µF
V DD
0.1µF
V DD
P e r ic o m P a r t
0.1µF
V DD
0.1µF
V DD
Figure 1: Recommended Power Supply Decoupling Circuit Diagram
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PI3HDMI1421
HDMI™ Revision 1.4 Compliant 2:1/1:2 Mux/Demux
Requirements on the Decoupling Capacitors
i. There is no special requirement on the material of the capacitors. Ceramic capacitors are generally being used with typically
materials of X5R or X7R.
ii. 0.1uF decoupling capacitor in 0402 package is recommended.
Layout and Decoupling Capacitor Placement Consideration
i. Each 0.1µF decoupling capacitor should be placed as close as possible to each VDD pin.
ii. VDD and GND planes should be used to provide a low impedance path for power and ground.
iii. Via holes should be placed to connect to VDD and GND planes directly.
iv. Trace should be as wide as possible.
v. Trace should be as short as possible.
vi. The placement of decoupling capacitor and the way of routing trace should consider the power flowing criteria.
vii. 10µF capacitor should also be placed close to our part and should be placed in the middle location of 0.1µF capacitors.
viii.Avoid the large current circuit placed close to our part; especially when it is shared the same VDD and GND planes, since large
current flowing on our VDD or GND planes will generate a potential variation on the VDD or GND of our part.
Bypass noise
V DD P la ne
Power Flow
G N D P la ne
0 .1 uF
P e r ic o m P a r t
Figure 2: Layout and Decoupling Capacitor Placement Diagram
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PI3HDMI1421
HDMI™ Revision 1.4 Compliant 2:1/1:2 Mux/Demux
BALANCED
PORT1
BALANCED
PORT2
+
+
50
–
–
50
+
+
50
–
–
50
DUT
Fig 3: Crosstalk Setup
BALANCED
PORT1
+
+
50
–
–
50
+
BALANCED
PORT2
–
DUT
Fig 4: Off-isolation setup
BALANCED
PORT1
+
+
–
–
BALANCED
PORT2
DUT
Fig 5: Differential Insertion Loss and -3dB Test Setup
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PI3HDMI1421
HDMI™ Revision 1.4 Compliant 2:1/1:2 Mux/Demux
1
2
3
4
5
PI3HDMI1421ZBE
HDMI Connector
BDy+
Dual-mode DP Source
0.1u
BDy-
Ay+
D
1:2
DEMUX
Ay-
D
CDy+
0.1u
CDy+5V
+5V
500
500
+3V3
2K
2K
2K
SDAB
SCL_A
C
2K
SCLB
20K
20K
1:2
DEMUX
SDA_A
C
SCLC
SDAC
Docking Connector
HPDB
B
(0 - 3V3)
(0 - 5V)
B
100K
1:2
DEMUX
HPD_A
HPDC
(0 - 5V)
100K
120K
120K
A
A
Title
VBIAS = L
PI3HDMI1421ZBE Dual-mode DP 1:2 Source Application
mux_demux_en = H
Size
Rev
A
Document Number
SW = L / H
Date:
5
3
4
Thursday, June 07, 2012
2
Sheet
1
of
3
1
Fig 6: Dual-mode DP 1:2 Source Application Diagram
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PI3HDMI1421
HDMI™ Revision 1.4 Compliant 2:1/1:2 Mux/Demux
5
4
3
2
HDMI Connector 1
1
PI3HDMI1421ZHE
BDy+
HDMI Scalar
BDy-
Ay+
2:1
MUX
D
D
Ay-
CDy+
CDy+5V
+5V
+5V
+5Va
1K
47K
47K
47K
47K
SCLB
10K
SDAB
C
HDMI Connector 2
10K
SCL_A
2:1
MUX
SDA_A
SCLC
C
SDAC
EEPROM 1
EEPROM 2
HPDB
2:1
MUX
+5VB
1K
B
HPD_A
B
HPDC
120K
mux_demux_en = L
SW = L / H
A
A
Title
PI3HDMI1421ZHE HDMI 2:1 Sink Application
Size
Date:
5
4
3
2
Document Number
Thursday, June 07, 2012
Rev
A
Sheet
2
of
3
1
Fig 7: HDMI 2:1 Sink Application Diagram
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PI3HDMI1421
HDMI™ Revision 1.4 Compliant 2:1/1:2 Mux/Demux
Package Mechanical: 48-pin, TQFN (ZB48)
UNIT: mm
1
Notes:
1. All dimensions are in millimeters, angles are in degrees.
2. Coplanarity applies to the exposed thermal pad as well as the terminals.
3. Refer JEDEC MO-220
4. Recommended land pattern is for reference only.
5. Thermal pad soldering area
DATE: 02/11/09
DESCRIPTION: 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZB48
REVISION: A
DOCUMENT CONTROL #: PD-2080
09-0091
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
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PI3HDMI1421
HDMI™ Revision 1.4 Compliant 2:1/1:2 Mux/Demux
Package Mechanical: 42-pin, TQFN (ZH42)
1
Notes:
1. All dimensions are in millimeters, angles in degrees.
2. Coplanarity applies to the exposed thermal pad as well as the terminals.
3. Refer JEDEC MO-220
4. Recommended Land Pattern is for reference only.
5. Thermal Pad Soldering Area
DATE: 02/17/09
DESCRIPTION: 42-contact Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZH (ZH42)
REVISION: C
DOCUMENT CONTROL #: PD-2035
09-0116
Ordering Information
Ordering Code
Package Code
Package Description
PI3HDMI1421ZBE
ZB
48-pin, Pb-free & Green TQFN
PI3HDMI1421ZHE
ZH
42-pin, Pb-free & Green TQFN
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• Adding an X Suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
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