PI6PCIEB24 1:4 PCI Express® Clock Driver Features Description ÎÎPhase jitter filter for PCIe® 2.0 application Pericom Semiconductor's PI6PCIEB24 is a PCI Express® (PCIe) 2.0 compliant high-speed, low-noise differential clock buffer. The device distributes the input differential PCIe clock to four differential pairs of clock outputs with zero delay PLL. ÎÎFour pairs of HCSL PCIe 2.0 Differential Clocks ÎÎProp delay <± 250ps (in PLL mode) ÎÎLow skew < 50ps ÎÎLow jitter < 50ps cycle-to-cycle ÎÎ< 1 ps additive RMS phase jitter ÎÎ100 MHz PLL Mode operation ÎÎ3.3V operation ÎÎPackaging (Pb-free and Green): àà 20-Pin 4.0mm x 4.0mm x0.75mm TQFN (ZD20) Block Diagram Pin Configuration IREF VDD_A VDD SRC SRC# OE_0 16 17 18 19 20 OUT0 OUT0# OUT1 OUT1# SRC SRC# VDD OUT0 OUT0# OE_0 OUT1 OUT2 OUT2# OUT3 OUT3# PLL OE_3 OUT3 OUT3# OE_3 OUT2 OUT2# VDD PWRDWN# PLL/BYPASS# VDD OUT1# PLL/BYPASS# 10-0210 15 14 13 12 11 10 9 8 7 6 PWRDWN# 1 2 3 4 5 1 www.pericom.com PS9070A 09/01/10 PI6PCIEB24 1:4 PCI Express® Clock Driver Pin Descriptions Pin Name Type Pin No Description SRC & SRC# Input 19, 20 0.7V Differential SRC input from PI6C410 clock synthesizer OUT[0:3] & OUT[0:3]# Output 2, 3, 5, 6, 12, 11, 15, 14 0.7V Differential outputs IREF Input 16 External resistor connection to set the differential output current VDD Power 1, 7, 10, 18 3.3V Power Supply for Outputs PWRDWN# Input 9 3.3V LVTTL active LOW input for power down operation VDD_A Power 17 3.3V Power Supply for PLL PLL/BYPASS# Input 8 When HIGH, PLL is enabled, When LOW, PLL is bypassed. OE_0, OE_3 Input 4, 13 When HIGH, enables corresponding OUT0, OUT3 respectively. Ground connection is through the package metal plate underneath. 10-0210 2 www.pericom.com PS9070A 09/01/10 PI6PCIEB24 1:4 PCI Express® Clock Driver Functionality PWRDWN# OUT OUT# 1 Normal Normal 0 IREF × 2 Low Power Down (PWRDWN# assertion) PWRDWN# OUT OUT# Figure 1. Power down sequence When PWRDWN# is asserted (Low), 2xIREF current flows through OUT pin. Power Down (PWRDWN# De-assertion) Tstable <1ms PWRDWN# OUT OUT# Tdrive_PwrDwn# <300us, >200mV Figure 2. Power down de-assert sequence 10-0210 3 www.pericom.com PS9070A 09/01/10 PI6PCIEB24 1:4 PCI Express® Clock Driver Current-mode output buffer characteristics of OUT[0:3], OUT[0:3]# VDD (3.3V ± 5%) Slope ~ 1/Rs RO IOUT ROS Iout 0V VOUT = 0.85V max 0.85V Figure 2. Simplified diagram of current-mode output buffer Differential Clock Buffer characteristics Symbol Minimum Maximum RO 3000Ω N/A ROS unspecified unspecified VOUT N/A 850mV Current Accuracy Symbol Conditions IOUT VDD = 3.30 ±5% Configuration Load Min. Max. R REF = 475Ω 1% Nominal test load for given configuration -12% INOMINAL +12% INOMINAL IREF = 2.32mA INOMINAL refers to the expected current based on the configuration of the device. Differential Clock Output Current Board Target Trace/Term Z Reference R, Iref = VDD/(3xRr) Output Current 100Ω R REF = 475Ω 1%, (100Ω differential ≈ 15% coupling ratio) IREF = 2.32mA 10-0210 4 IOH = 6 x IREF www.pericom.com VOH @ Z 0.7V @ 50 PS9070A 09/01/10 PI6PCIEB24 1:4 PCI Express® Clock Driver Absolute Maximum Ratings (Over operating free-air temperature range) Symbol Parameters Min. Max. VDD_A 3.3V Core Supply Voltage -0.5 4.6 VDD 3.3V I/O Supply Voltage -0.5 4.6 VIH Input High Voltage VIL Input Low Voltage -0.5 Ts Storage Temperature -65 VESD ESD Protection 2000 Units V 4.6 150 °C V Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. DC Electrical Characteristics (VDD = 3.3±5%, VDD_A = 3.3±5%) Symbol Parameters VDD_A Min. Max. 3.3V Core Supply Voltage 3.135 3.465 VDD 3.3V I/O Supply Voltage 3.135 3.465 VIH 3.3V Input High Voltage 2.0 VDD + 0.3 VIL 3.3V Input Low Voltage VSS – 0.3 0.8 IIK Input Leakage Current 0 < VIN < VDD -5 +5 IOH Output High Current IOH = 6 x IREF, 12.2 CIN Input Pin Capacitance COUT Output Pin Capacitance 6 LPIN Pin Inductance 7 IDD Power Supply Current VDD = 3.465V, FCPU = 100MHz 200 ISS Power Down Current Driven outputs 40 TA Ambient Temperature 10-0210 Condition VDD IREF = 2.32mA -45 5 www.pericom.com V μA 15.6 3 Units 5 mA pF nH 85 mA °C PS9070A 09/01/10 PI6PCIEB24 1:4 PCI Express® Clock Driver AC Switching Characteristics (VDD = 3.3±5%, VDD_A = 3.3±5%) Symbol Parameters Min Max. Units 95 105 MHz 175 700 ps 2 Rise and Fall Time Variation 125 ps 2 Rise/Fall Matching 20 % 2 Tpd PLL Mode (PLL/BYPASS# = 1) ±250 ps Tjitter Cycle – Cycle Jitter 50 ps 3, 4 VHIGH Voltage High including overshoot 660 1150 mV 2 VLOW Voltage Low including undershoot -300 mV 2 Vcross Absolute crossing point voltages 250 550 mV 2 ΔVcross Total Variation of Vcross over all edges 140 mV 2 TDC Duty Cycle 45 55 % 3 Tjadd Additive RMS phase jitter for PCIe GenII <0 1 ps 5 Tpd(bypass) Bypass mode (PLL/BYPASS# = 0) 2.5 6.5 ns FIN Trise / Tfall DTrise / DTfall Rise and Fall Time (measured between 0.175V to 0.525V) Notes 1. Test configuration is R s = 33.2Ω, Rp = 49.9Ω, and 2pF. 2. Measurement taken from Single Ended waveform. 3. Measurement taken from Differential waveform. 4. Measurement taken using M1 data capture analysis tool. 5. Additive jitter is calculated from input and output RMS phase jitter using PCIe 2.0 filter by Tjadd = √(output jitter)2 – (input jitter)2 Configuration Test Load Board Termination Rs 33Ω 5% OUT TLA PI6PCIEB24 Rs 33Ω 5% OUT# TLB 475Ω 1% 10-0210 Rp 49.9Ω 1% Rp 49.9Ω 1% 6 2pF 5% www.pericom.com 2pF 5% PS9070A 09/01/10 PI6PCIEB24 1:4 PCI Express® Clock Driver Packaging Mechanical: 20-Pin TQFN (ZD) 1 DATE: 09/11/08 DESCRIPTION: 20-Lead, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZD20 REVISION: -- DOCUMENT CONTROL #: PD-2084 08-0456 Ordering Information(1-3) Ordering Code Package Code Package Description PI6PCIEB24ZDE ZD 20-pin, 4.0mm x 4.0mm, TQFN, Pb-Free and Green 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green 3. Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 10-0210 PCI Express and PCIe are registered trademarks of PCI-SIG. Please visit pcisig.org for information. 7 www.pericom.com PS9070A 09/01/10