PI2EQX5964

PI2EQX5964
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization, Emphasis, & I2C Control
Features
Description
ÎÎUp to 5.0Gbps PCI Express® 2.0 Serial ReDriver
Pericom Semiconductor’s PI2EQX5964 is a low power, PCIe®
compliant signal redriver. The device provides programmable
equalization, amplification, and de-emphasis by using 8 select
bits, to optimize performance over a variety of physical mediums by reducing Inter-symbol interference.
ÎÎSupporting 8 differential channels or 4 lanes of PCIe
Interface
ÎÎI2C configuration controls (3.3V tolerant)
ÎÎAdjustable receiver equalization and transmitter de-
PI2EQX5964 supports eight 100-Ohm Differential CML data
I/O’s between the Protocol ASIC to a switch fabric, across a
backplane, or extends the signals across other distant data pathways on the user’s platform.
emphasis and output levels
ÎÎVariable input an output termination
ÎÎ1:2 channel broadcast
ÎÎChannel loop-back/Mux and Demux Mode
The integrated equalization circuitry provides flexibility with
signal integrity of the PCI Express signal before the ReDriver™,
whereas the integrated de-emphasis circuitry provides flexibility
with signal integrity of the signal after the redriver.
ÎÎElectrical Idle fully supported
ÎÎReceiver detect and individual output control
ÎÎFine adjustment of electrical idle threshold via I2C
In addition to providing signal re-conditioning, Pericom’s
PI2EQX5964 also provides power management Stand-by mode
operated by a Bus Enable pin.
ÎÎSingle supply voltage, 1.2V ± 0.05V
ÎÎPower down modes
ÎÎIndustrial Temp support, -40°C ~ +85°C
ÎÎPackaging: 56-contact TQFN, Pb-free & Green
Block Diagram
Figure1
+
−
xyRx+
+
xyRx-
−
Output
Controls
Inputleveldetect
tocontrollogic
Equalizer
xyTx+
+
A
xyTx-
−
B
Output
Controls
Equalizer
Inputleveldetect
tocontrollogic
+
xyTx+
−
xyTx-
+
xyRx+
−
xyRx-
PCIe 2.0
ReDriver
7111
X6
X770
PI3EQ
Blade Server
Blade Server
PCIe 2.0 Cable
+
−
DataLaneRepeats4Times
SELy_x
Sy_x
Dy_x
Mode
ControlRegisters
&Logic
SDA
SCL
RXD_x
RES_x
DE_x
PD#
LB#
Power
Management
I2CControl
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Ax
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PI2EQX5964
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
RXD_A
PD#
SDA
SCL
NC
VDD
A0TXB0RX+
B0RXVDD
A1TX+
42
A1TX-
41
B1RX-
40
B1RX+
39
VDD
38
A2TX+
16
17
18
37
A2TX-
36
B2RX-
35
B2RX+
34
VDD
33
A3TX+
32
31
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A3TXB3RX+
B3RXVDD
LB#
A1
A0
A4
RESET#
19
30
20
29
21 22 23 24 25 26 27 28
VDD
A2RXB2TXB2TX+
VDD
A3RX+
A3RXB3TX+
B3TX-
A0TX+
7
8
9
10
11
12
13
14
15
MODE
VDD
A2RX+
56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
RXD_B
VDD
A0RX+
A0RXB0TX+
B0TXVDD
A1RX+
A1RXB1TXB1TX+
GND
GND
Pin Configuration
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PI2EQX5964
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
Pin Description
Pin #
Pin Name
Type
Description
2
A0RX+,
I
3
A0RX-
I
CML inputs for Channel A0, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
48
A0TX+,
O
47
A0TX-
O
7
A1RX+,
I
8
A1RX-
I
43
A1TX+,
O
42
A1TX-
O
12
A2RX+,
I
13
A2RX-
I
38
A2TX+,
O
37
A2TX-
O
17
A3RX+,
I
18
A3RX-
I
33
A3TX+,
O
32
A3TX-
O
46
B0RX+,
I
45
B0RX-
I
4
B0TX+,
O
5
B0TX-
O
41
B1RX-,
I
40
B1RX+
I
9
B1TX-,
O
10
B1TX+
O
36
B2RX-,
I
35
B2RX+
I
14
B2TX-,
O
15
B2TX+
O
31
B3RX+,
I
30
B3RX-
I
19
B3TX+,
O
20
B3TX-
O
CML outputs for Channel B3, with internal 50-Ohm pull up during normal
operation and 2K-Ohm pull up otherwise.
26, 27, 25
A0, A1, A4
I
I2C programmable address bit A0, A1 and A4.
28
LB#
I
Loopback control input. Input with internal 100K-Ohm pull-up resistor. LB#
= High or open for normal operation. LB# = Low for loopback connection of
A_RX to A_TX and B_TX.
Data Signals
CML outputs for Channel A0, with internal 50-Ohm pull up during normal
operation and 2K-Ohm pull up otherwise.
CML inputs for Channel A1, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A1, with internal 50-Ohm pull up during normal
operation and 2K-Ohm pull up otherwise.
CML inputs for Channel A2, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A2, with internal 50-Ohm pull up during normal
operation and 2K-Ohm pull up otherwise.
CML inputs for Channel A3 with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A3, with internal 50-Ohm pull up during normal
operation and 2K-Ohm pull up otherwise.
CML inputs for Channel B0, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B0, with internal 50-Ohm pull up during normal
operation and 2K-Ohm pull up otherwise.
CML inputs for Channel B1, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B1, with internal 50-Ohm pull up during normal
operation and 2K-Ohm pull up otherwise.
CML inputs for Channel B2, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B2, with internal 50-Ohm pull up during normal
operation and 2K-Ohm pull up otherwise.
CML inputs for Channel B3, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
Control Signals
(Continued on Next Page)
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PI2EQX5964
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
Pin #
Pin Name
Type
Description
23
Mode
I
Enables I2C control when LOW. Has internal 100K-Ohm pull-up resistor. A
LVCMOS high level selects input pins control, and disables I2C operation. Note,
during startup, input status of the control pin (LB#, RES_A/B#, RXD_A/B,
RESET#) will be latched to set the initial register state.
51
PD#
I
Input with 100K-Ohm pull-up resistor, PD# = High or open is normal operation,
PD# = Low disables the IC and sets the IC into Power Down mode. Both inputs
and outputs go to Hi-Z.
54
NC
No Connect
24
RESET#
I
RESET# is an active low channel reset input for Channel A0, B0, A1, B1, A2, B2,
A3 and B3 with internal 100K-Ohm pull-up resistor. When low, receiver detection cycle is reset, and normal detection cycle is carry on after the pin goes high.
50
RXD_A
I
Receiver detect enable input for Channel A0, A1, A2 and A3 with internal 100KOhm pull-up resistor.
22
RXD_B
I
Receiver detect enable input for Channel B0, B1, B2 and B3 with internal 100KOhm pull-up resistor.
53
SCL
I/O
I2C SCL clock input.
52
SDA
I/O
I2C SDA data input.
55, 56, Center Pad
GND
PWR
Supply Ground
1, 6, 11, 16, 21, 29,
34, 39, 44, 49
VDD
PWR
1.2V Supply Voltage
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PI2EQX5964
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
Description of Operation:
Configuration Modes
Device configuration can be performed in two ways depending on the state of the MODE input. MODE determines whether
IC configuration status is from the input pins or via I2C control. When MODE is set high, the configuration input pins set the
configuration operating state as stored in configuration registers. While MODE is set high, changes to these control registers are
disabled and the initial condition is protected from any changes to insuring a known operating state. When the MODE pin is low,
reprogramming of these control registers via I2C is allowed. Note that the MODE pin is not latched, and is always active to enable
or disable I2C access.
During initial power-on, the value at the configuration input pins: LB#, RESET#,RXD_A and RXD_B, will be latched to the configuration registers as initial startup states.
Equalizer Configuration
The PI2EQX5964 input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) resulting from long signal
traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high-frequency signal components. Because either
too little, or too much, signal compensation may be non-optimal eight levels are provided to adjust for any application.
Equalizer configuration can be programmed via I2C when the mode pin is low. Each group of four channels, A and B, has separate
equalization control, and all four channels within the group are assigned the same configuration state. The Equalizer Selection table
below describes the register state and associated operation of the equalizer.
Equalizer Selection
SEL2_[A:B]
SEL1_[A:B]
SEL0_[A:B]
@1.25GHz
@2.5GHz
0
0
0
0.5dB
1.2dB
0
0
1
0.6dB
1.5dB
0
1
0
1.0dB
2.6dB
0
1
1
1.9dB
4.3dB
1
0
0
2.8dB
5.8dB
1
0
1
3.6dB
7.1dB
1
1
0
5.0dB
9.0dB
1
1
1
7.7dB
12.3dB
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PI2EQX5964
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
Output Configuration
The PI2EQX5964 provides flexible output strength and emphasis controls to provide the optimum signal to pre-compensate for
losses across long trace or noisy environments so that the receiver gets a clean with good eye opening. Control of output configuration is grouped for the A and B channels, so that each channel within the group has the same setting.
Output configuration can be set via I2C when the mode pin is LOW. The Output Swing Control table shows available configuration
settings for output level control, as specified by the SELx_y registers.
Output Swing Control
S1_[A:B]
S0_[A:B]
Swing (Diff. VPP)
0
0
1.1V
0
1
0.5V
1
0
0.8V
1
1
1.0V
Output De-Emphasis Adjustment
De-emphasis settings are determined by the state of the DEx_y input pins and configuration registers, as shown in the Output
De-emphasis table below. Half-bit-de-emphasis is selected as the default power-on mode, but can be changed to full-bit-de-emphasis
via reprogramming the Loopback and De-emphasis Control register using the I2C interface. Output de-emphasis settings are independant of the data rate.
Half-bit with De-emphasis
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Full-bit with De-emphasis
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PI2EQX5964
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
D2_[A:B]
D1_[A:B]
D0_[A:B]
De-emphasis
0
0
0
0dB
0
0
1
-2.5dB
0
1
0
-3.5dB
0
1
1
-4.5dB
1
0
0
-5.5dB
1
0
1
-6.5dB
1
1
0
-7.5dB
1
1
1
-8.5dB
Input Level Detect
An input level detect and output squelch function is provided on each channel to eliminate re-transmission of input noise. A continuous signal level below the Vth- threshold causes the output driver to go to a high-impredance state, so that both the positive and
negative output signal are pulled to VDD by the internal pull-up resistors. This feature supports L0S PCI Express Electrical Idle state.
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PI2EQX5964
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
Receiver Detect
Automatic Receiver Detection is a feature that can set the number of active channels. By sensing the presence of a load device on
the output, the channel can be automatically enabled for operation. This allows the PI2EQX5964 to configure itself properly depending on the devices it is communicating with, whether it is a 4-lane, 3-lane, 2-lane or just 1-lane device or adapter card.
Receiver Detect is enabled by the RXD_A, or RXD_B pins, or alternatively via I2C programming. When RXD_A or RXD_B is set to
low, the Receiver Detect operation for that group of channels is disabled, and those channels go directly to 50-Ohm input termination to ground and 50-Ohm output termination to VDD (for a valid differential channel input level) or to 2K-Ohm (if the signal
level is less than the threshold level).
The RESET# input is used to reset the receiver detect state machine to its initial state. The start of the receiver detect cycle starts
when RESET# transitions from low to high.
When a Receiver Detect cycle begins the differential channel pins are enabled with a 2K-Ohm pull-up to VDD. A 50-Ohm Receiver
termination will change the pin level. This pin level is evaluated after a fixed time-out, and the channel is then set into the proper
operating state. The register bits RX50_Ax and RX50_Bx represent the receiver detect result for their specific channels.
The I/O operation table summarizes the relationships and operation of receiver detect and other signals involved with I/O control.
I/O Operation Control
Detection
States
Control Inputs
Data Channel I/O
PD#
RXD_x RESET# RX50
SIG_x
Input Termination
Output Termination
Mode
0
X
X
X
X
Hi-Z
Hi-Z
Full IC power down, all channels
disabled
1
0
0
X
X
Hi-Z
2K-Ohm pull-up
Channel disabled, output pulls to
VDD. Receiver detect reset
1
0
1
X
0
50-Ohm pull-down
2K-Ohm pull-up
Channel enabled, no input signal,
output pulls to VDD. Receiver detect
disabled
1
0
1
X
1
50-Ohm pull-down
50-Ohm pull-up
Channel enabled, valid input signal
detected, output driving. Receiver
detect disabled.
1
1
0
X
X
Hi-Z
2K-Ohm pull-up
Channel disabled. Receiver detect
reset.
1
1
1
0
X
Hi-Z
2K-Ohm pull-up
Channel disabled, output pulls to
VDD. Receiver detect enabled, no
receiver detected.
1
1
1
1
0
50-Ohm pull-down
2K-Ohm pull-up
Channel inactive, output pulls to
VDD. Receiver detect enabled, receiver
detected. No input signal
1
1
1
1
1
50-Ohm pull-down
50-Ohm pull-up
Channel active, valid input signal detected, output driving. Receiver detect
enabled, load detected.
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0 and
0 0= and
1
0=1
0# = 0
0# = 0
Normal Operation
LB_A0B0# = 1
Loopback Mode
LB_A0B0# = 0 and
OUT_DIS_A0 = 1
PI2EQX5964
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
A0
A0
A0
B0
Loopback
Operation
B0
B0
Loopback Modes
A0
B0
CONDITIONS
Mux Function
Demux Function LB_A0B0# = 1
Solid: PD_B0# =INDIS_A0
0
Solid:
PD_A0#A0= 0
NORMAL MODE
=0
A0
A0
A0
Dashed: LB_A0B0# = 0 and
Dashed: LB_A0B0# = 0 and
A0Rx to A0Tx, B0Rx to B0Tx
OUTDIS_A0 = 0
B0 OUT_DIS_A0 = 1
B0 OUT_DIS_A0 = 1
B0
B0INDIS_B0 = 0
OUTDIS_B0 = 0
Normal Operation
LB_A0B0#
= 1 A0
A0
B0
B0
Loopback Mode
LB_A0B0# = 0 and
LB_A0B0# = 0
OUT_DIS_A0
=
1
BROADCAST MODE
INDIS_A0 =0
A0Rx to A0Tx and B0Tx
INDIS_B0 = 1
OUTDIS_B0 = 0
A0
A0
A0
B0
B0
A0
B0
Broadcast mode
A0
A0
Conditions:
LB_A0B0#
=0
B0
B0
B0
A0
B0
LOOPBACK MODE
A0Rx to B0Tx
A0
Each lane of provides a loopback mode
for test purposes which is controlled by a
strapping pin and I2C register bit. The LB#
pin controls all lanes together. When this
pin is high normal data mode is enabled.
When LB# is low the loopfeature mode is
enabled. The adjacent figure diagrams this
operation. Loopback is not intended to
be dynamically switched, and the normal
system application is to initialize to one
configuration or the other.
The Loopback mode can also support mux/
demux operation. Using I2C configuration, unused inputs and outputs can be
disabled to minimize power and noise.
LB_A0B0# = 0
B0
INDIS_A0 = 0
OUT_DIS_A0 = 1
Mux Function
Demux Function INDIS_B0 = 1
Loopback
Mode = 0
Solid: PD_B0# OUTDIS_B0
=0
Solid: PD_A0#
=0
Dashed:
LB_A0B0#
= 0 and
Dashed:
LB_A0B0#
=
0
and
LB_A0B0#
=
0
and
Loopback Mode
LB_A0B0#
OUT_DIS_A0
= 1= 1
OUT_DIS_A0
=1
OUT_DIS_A0
1
LB_A0B0# = 0= and
DEMUX MODE
INDIS_A0 = 0
OUT_DIS_A0 = 1
A0
A0
A0
A0
B0
B0
B0
B0
A0
A0
A0
A0
B0
B0
B0
B0
Solid Line
OUTDIS_A0 = 0
A0Rx to A0Tx
INDIS_B0 = 1
OUTDIS_B0 = 0
A0
DEMUX MODEB0
Dashed Line
A0
LB_A0B0# = 0
INDIS_A0 = 0
B0
OUTDIS_A0 = 0
Demux Function
A0Rx to B0Tx
INDIS_B0 = 1
Broadcast
mode = 0
Solid:
PD_B0#
Demux
Function
Normal
Operation
Loopback
Mode
Conditions:
LB_A0B0#
=0
OUTDIS_B0 = 0
Dashed:
LB_A0B0#
Solid: PD_B0#
= 0= 0 and
LB_A0B0#
=
1
LB_A0B0#
=
0
and
1
LB_A0B0# = 1
Dashed: OUT_DIS_A0
LB_A0B0# = 0= and
OUT_DIS_A0 = 1
INDIS_A0 = 0
OUT_DIS_A0 = 1MUX MODE
Solid Line
A0
B0
A0
B0
B0Rx to B0Tx
OUTDIS_A0 = 1
A0
B0
MUX MODE
Dasked Line
INDIS_B0 = 0
A0
OUTDIS_B0 = 0
LB_A0B0# = 0
B0
INDIS_A0 = 0
OUTDIS_A0 = 1
Mux Function
Demux Function
A0Rx to B0Tx
INDIS_B0 = 0
Solid: PD_B0# = 0
Solid: PD_A0# = 0
OUTDIS_B0 = 0
Dashed: LB_A0B0#
= 0 and
Dashed: LB_A0B0# = 0 and
OUT_DIS_A0 = 1
OUT_DIS_A0 = 1
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A0
A0
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PS-0.5 10/06/11
PI2EQX5964
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
I2C Operation
The PI2EQX5964 I2C controller operates as a slave device, supporting standard rate operation of 100Kbps, with 7-bit addressing
mode. The data byte format is 8 bit bytes. The bytes must be accessed in sequential order from the lowest to the highest byte with
the ability to stop after any complete byte has been transferred. Address bits A4, A1 and A0 are programmable to support multiple
chips environment. The data is loaded until a Stop sequence is issued.
Configuration Register Summary
Byte Mnemonic
Function
0
SIG
Signal Detect, indicates valid input signal level
1
RX50
Receiver Detect Output, indicates whether a receiver load was detected
2
LBEC
Loopback and Emphasis Control, provides for control of the loopback function and emphasis mode (preemphasis or de-emphasis)
3
INDIS
Channel Input Disable, controls whether a channels input buffer is enabled or disabled
4
OUTDIS
Channel Output Disable: Controls whether a channels output buffer is enabled or disabled
5
RESET
Channel Reset
6
PWR
Power Down Control, enables power down for each channel individually
7
RXDE
Receiver Detect Enable, controls the receiver detect operation
8
AEOC
A-Channels Equalizer and Output Control
9
BEOC
B-Channels Equalizer and Output Control
10
RSVD
Reserved
11
VTH
Idle detect threshold control
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PI2EQX5964
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
Transferring Data
Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge bit. Data is transferred with the
most significant bit (MSB) first (see the I2C Data Transfer diagram). The PI2EQX5964 will never hold the clock line SCL LOW to
force the master into a wait state.
Note: Byte-write and byte-read transfers have a fixed offset of 0x00, because of the very small number of configuration bytes. An
offset byte presented by a host to the PI2EQX5964 is not used.
Addressing
Up to eight PI2EQX5964 devices can be connected to a single I2C bus. The PI2EQX5964 supports 7-bit addressing, with the LSB
indicating either a read or write operation. The address for a specific device is determined by the A0, A1 and A4 input pins.
Address Assignment
A6
A5
A4
A3
A2
A1
1
1
Program
0
0
Programmable
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R/W
1=R, 0=W
PS-0.5 10/06/11
PI2EQX5964
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
Acknowledge
Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH) during the acknowledge clock pulse, the PI2EQX5964 will pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW
during the HIGH period of this clock pulse as indicated in the I2C Data Transfer diagram. The PI2EQX5964 will generate an
acknowledge after each byte has been received.
Data Transfer
A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, the PI2EQX5964 will watch the next
byte of information for a match with its address setting. When a match is found it will respond with a read or write of data on the
following clocks. Each byte must be followed by an acknowledge bit, except for the last byte of a read cycle which ends with a stop
bit. For a write cycle, the first data byte following the address byte is a dummy or fill byte that is not used by the PI2EQX5964. This
byte is provided to provided compatibility with systems implementing 10-bit addressing. Data is transferred with the most significant bit (MSB) first. After each block write, address pointer will reset to byte 0.
Register Description
BYTE 0 - Signal Detect (SIG)
SIG_xy=0=low input signal, SIG_xy=1=valid input signal
Bit
7
6
5
4
3
2
1
0
Name
SIG_A0
SIG_B0
SIG_A1
SIG_B1
SIG_A2
SIG_B2
SIG_A3
SIG_B3
Type
R
R
R
R
R
R
R
R
Power-on
State
X
X
X
X
X
X
X
X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Signal Detect register provides information on the instantaneous status of the channel input from the Input Level Threshold
Detect circuit. If the input level falls below the Vth- level the relevant SIG_xy bit will be 0, indicating a low-level noise or electrical idle input, resulting in the outputs going to the high-impedance off state or squelch mode. If the input level is above Vth-, then
SIG_xy is 1, indicating a valid input signal, and active signal recovery operation.
BYTE 1 - Receiver Detect Output Register (RX50)
Bit
7
6
5
4
3
2
1
0
Name
RX50_A0
RX50_B0
RX50_A1
RX50_B1
RX50_A2
RX50_B2
RX50_A3
RX50_B3
Type
R
R
R
R
R
R
R
R
Power-on
State
X
X
X
X
X
X
X
X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The RX50_xy bits report the result of a receiver detection cycle. One bit is assigned for each channel of the device. RX50_xy is
at a logic 1 level indicating a load and receiver was detected. When RX50_xy is 0 then a load device was not detected. The RX50
register is read-only, and is undefined after power-up until a Receiver Detection cycle completes.
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BYTE 2 - Loopback and Emphasis Control Register (LBEC)
LB_xyxy#=0=loopback mode, LB_xyxy#=1=normal mode, DE_x=0=Full-bit de-emphasis, DE_x=1=Half-bit de-emphasis
Bit
7
Name
2
1
0
LB_A0B0# LB_A1B1# LB_A2B2# LB_A3B3# DE_A
DE_B
rsvd
rsvd
Type
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Power-on
State
LB#
LB#
LB#
LB#
1
1
X
X
1
0
Note: 6
5
4
3
R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
Individual control for each lane is provided for the loopback function via this register.
BYTE 3 - Channel Input Disable (INDIS)
INDIS_xy=0=enable input, INDIS_xy=1=disable input
Bit
7
Name
INDIS_A0 INDIS_B0 INDIS_A1 INDIS_B1
INDIS_A2 INDIS_B2 INDIS_A3 INDIS_B3
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
0
0
0
0
0
0
0
0
Note: 6
5
4
3
2
R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Input Disable register, provides control over the input buffer of each channel independently. When and INDIS_xy bit is
logic 1, then the input buffer is switched off and the input termination is high impedance. This feature can be used for PCB testing,
and when only one input is used during Loopback as a demux function. When INDIS_xy is at a logic 0 state then the input buffer is
enabled (normal operating mode).
BYTE 4 - Channel Output Disable (OUTDIS)
ODIS_xy=0=enable output, ODIS_xy=1=disable output
Bit
7
6
5
4
3
2
1
0
Name
ODIS_A0
ODIS_B0
ODIS_A1
ODIS_B1
ODIS_A2
ODIS_B2
ODIS_A3
ODIS_B3
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
0
0
0
0
0
0
0
0
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Output Disable register, allows control over the output buffer of each channel independently. When and OUTDIS_xy
bit is logic 1, then the output buffer is switched off and the termination is high impedance. This feature can be used for PCB testing,
and when only one output is used during Loopback as a mux function. When INDIS_xy is at a logic 0 state then the input buffer is
enabled (normal operating mode).
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BYTE 5 - Channel Reset (RESET)
RESET# =0=reset, RESET# =1=normal operation. Latch from RESET# input at startup
Bit
7
6
5
4
3
2
1
0
Name
RESET_
A0#
RESET_
B0#
RESET_
A1#
RESET_
B1#
RESET_
A2#
RESET_
B2#
RESET_
A3#
RESET_
B3#
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
Latch from RESET# inputs at startup
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Reset register allows for restart of an individual channels Receiver Detect function. A transition from 0 to 1 initiates
a new Receiver Detect cycle (if the channel is enabled and receiver detect is enabled). While static at 0 or 1, the RESET# bit will have
no effect on operation. The Channel Reset bits are read/write allowing the current state to be checked.
BYTE 6 - Power Down Control (PWR)
PD_xy# =0=channel off/power down, PD_xy# =1=normal operation, Latch from PD# input at startup
Bit
7
6
5
4
3
2
1
0
Name
PD_A0#
PD_B0#
PD_A1#
PD_B1#
PD_A2#
PD_B2#
PD_A3#
PD_B3#
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
Latch from PD# input at startup
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Power Down Control register allows for individual control over each channel for power savings. When PD_xy# is logic 0 the
channel is turned off. When PD_xy# is 1 then the channel is enabled for normal operation.
BYTE 7 - Receiver Detect Enable (RXDETEN)
RXD_xy =0=channel off/power down, RXD_xy =1=normal operation, Latch from PD# input at startup
Bit
7
6
5
4
3
2
1
0
Name
RXDETEN_A0
RXDETEN_B0
RXDETEN_A1
RXDETEN_B1
RXDETEN_A2
RXDETEN_B2
RXDETEN_A3
RXDETEN_B3
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
Latch from RXD_A & RXD_B inputs at startup
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Receiver Detect Enable register allows for control of the receiver detect state machine for each individual channel. When
RXD_xy is set to 0, then the receiver detect function is disabled. When RXD_xy is logic 1, then the receiver detect state machine is
enabled for operation. The initial state of the register bits are determined by the RXD_A and RXD_B input pins during power-up.
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BYTE 8 - A-Channels Equalizer and Output Control (AEOC)
SELx_A: Equalizer configuration, Dx_A: Emphasis control, Sx_A: Output level control (see Configuration Table)
Bit
7
6
5
4
3
2
1
0
Name
SEL0_A
SEL1_A
SEL2_A
D0_A
D1_A
D2_A
S0_A
S1_A
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
1
1
1
1
1
1
1
1
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The A-Channels Equalizer and Output Control register is used to control the configuration of the input equalizer and output
emphasis and levels of the four A channels. These register bits are loaded from the input configuration pins of the same name at
power-on. These bits may be changed if the MODE# input is set to allow I2C configuration. Please refer to the tables (1) Equalizer
Configuration, (2) Output Swing Configuration and (3) Output Emphasis Configuration earlier in this document for setting information. All four A channels get the same configuration settings.
BYTE 9 - B-Channels Equalizer and Output Control (BEOC)
SELx_B: Equalizer configuration, Dx_B: Emphasis control, Sx_B: Output level control (see Configuration Table)
Bit
7
6
5
4
3
2
1
0
Name
SEL0_B
SEL1_B
SEL2_B
D0_B
D1_B
D2_B
S0_B
S1_B
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
1
1
1
1
1
1
1
1
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The B-Channels Equalizer and Output Control register is used to control the configuration of the input equalizer and output
emphasis and levels of the four B channels. These register bits are loaded from the input configuration pins of the same name at
power-on. These bits may be changed if the MODE# input is set to allow I2C configuration. Please refer to the tables (1) Equalizer
Configuration, (2) Output Swing Configuration and (3) Output Emphasis Configuration earlier in this document for setting information. All four B channels get the same configuration settings.
BYTE 10 - Reserved
Reserved Byte 10 is also visible via the I2C interface. This byte is R/W, is initialized to 0 at power up, is used for IC manufacturing
test purposes and should not be changed for normal operation.
BYTE 11 - Idle Detect Threshold Control
Bit
7
6
5
4
3
2
1
0
Name
VTH7
VTH6
VTH5
VTH4
VTH3
VTH2
VTH1
VTH0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
1
1
1
0
1
1
1
1
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
0 = enable
Only 1 bit can be enabled at a time
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Start & Stop Conditions
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. A LOW to HIGH transition on the
SDA line while SCL is HIGH defines a STOP condition, as shown in the figure below.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
I2C START and STOP conditions.
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I2C Data Transfer
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Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Supply Voltage to Ground Potential . . . . . . . . . . . . . –0.5V to +2.5V
DC SIG Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to VDD +0.5V
I2C DC SIG Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5V to +3.6V
Current Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25mA to +25mA
Power Dissipation Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ESD, HBM: I2C pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1kV to +1kV
ESD, HBM: All other pins . . . . . . . . . . . . . . . . . . . . . . . –2kV to +2kV
AC/DC Electrical Characteristics
Power Supply Characteristics (VDD = 1.2 ±0.05V, TA = -40°C ~ +85°C)
Symbol
Parameters
Conditions
Min.
IDDactive
Power supply current - active
All channels switching
IDDstandby
Power supply current - standby
PD_xy# all 0
IDD-channel
Power supply current - per
channel, Active
Typ.
Max.
Units
800
1
5
mA
Max.
Units
50
AC Performance Characteristics (VDD = 1.2 ±0.05V, TA = -40°C ~ +85°C)
Symbol
Parameters
Tpd
Channel latency from input to
output
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Conditions
Min.
Typ.
750
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5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
CML Receiver Input (VDD = 1.2 ±0.05V, TA = -40°C ~ +85°C)
Symbol
Parameters
Conditions
ZRX-DIFF-DC
DC Differential Input Impedance
Min.
Typ.
Max.
80
100
120
Units
Ohms
ZRX-DC
DC Input Impedance
40
50
VRX-DIFFP-P
Differential Input Peak-to-peak Voltage
0.175
VRX-CM-ACP
AC Peak Common Mode Input Voltage
Vth-DIFF p-p
Signal detect threshold voltage
60
1.200
V
150
65
175
mV
Equalizer
Symbol
Parameters
Conditions
JRS-T
Residual jitter
JRS-D
JRM
Min.
Typ.
Max.
Units
Total
0.3
Ulp-p
Residual jitter
Deterministic
0.2
Ulp-p
Random jitter
Note 2
1.5
psrms
Notes
1. K28.7 pattern is applied differentially at point A as shown in AC test circuit (see figure).
2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter.
Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must
be from media-induced loss, and not from clock source modulation. Jitter is measured at 0V at point C of the AC test circuit (see figure).
CML Transmitter Output (VDD = 1.2 ±0.05V, TA = -40°C ~ +85°C)
Symbol
Parameters
Conditions
Min.
Typ.
Max.
ZOUT
Output resistance
Single ended
40
50
60
ZTX-DIFF-DC
DC Differential TX Impedance
VDIFFP
Output Voltage Swing, Differential
|VTX-D+ - VTX-D-|
200
800
VTX-DIFFP-P
Differential Peak-to-peak
Ouput Voltage
VTX-DIFFP-P = 2 * | VTX-D+ VTX-D- |
0.4
1.6
VTX-C
Common-Mode Voltage
| VTX-D+ + VTX-D- | / 2
tF, tR
Transition Time
20% to 80%
CTX(1)
Units
Ohms
80
AC Coupling Capacitor
100
120
mVp-p
V
VDD- 0.3
75
150
ps
200
nF
Notes:
1. Recommended external coupling capacitor.
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Digital I/O DC Specifications (VDD = 1.2 ±0.05V, TA = -40°C ~ +85°C)
Symbol
Parameters
Conditions
Min.
Typ.
Max.
Units
VIH
DC input logic high
VDD/2 +0.2
VDD+0.3
VIL
DC input logic low
-0.3
VDD/2 -0.2
VOH
DC output logic high
IOH = 4mA
VOL
DC output logic low
IOL = 4mA
Vhys
Hysteresis of Schmitt trigger input
IIH(1)
Input high current
IIL1(2)
Input low current
-20
IIL2(3)
Input low current
-20
V
VDD-0.4
0.4
0.2
100
µA
Notes:
1. Includes input signals A1, A2, A4, LB#, MODE#, RESET#, RXD_[A:B], SCL, SDA
2. For control inputs without pullups: SCL, SDA
3. Control inputs with pull-ups include: LB#, MODE#, RESET#, RXD_[A:B], A1, A2, A4
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SDA and SCL I/O for I2C-bus (VDD = 1.2 ±0.05V, TA = -40°C ~ +85°C)
Symbol
Parameters
Conditions
Min.
Typ.
VIH
DC input logic high
0.85VDD
3.6
VIL
DC input logic low
-0.3
0.3VDD
VOL
DC output logic low
Vhys
Hysteresis of Schmitt trigger input
IOL = 3mA
Max.
0.4
Units
V
0.2
Characteristics of the SDA and SCL bus lines for Standard Mode I2C-bus devices(1)
Symbol
Parameter
fSCL
SCL clock frequency
tHD;STA
Conditions
Min.
Typ.
Max.
Unit
0
100
kHz
Hold time (repeated) START condition. After
this period, the first clock pulse is generated
4.0
–
tLOW
LOW period of the SCL clock
4.7
–
tHIGH
HIGH period of the SCL clock
4.0
–
tSU;STA
Set-up time for a repeated START condition
4.7
–
tHD;DAT
Data hold time
10
–
tSU;DAT
Data set-up time
250
–
tr
Rise time of both SDA and SCL signals
–
1000
tf
Fall time of both SDA and SCL signals
tSU;STO
Set-up time for STOP condition
4.0
–
tBUF
Buss free time between a STOP and STOP
condition
4.7
–
Cb
Capacitive load for each bus line
–
400
µs
ns
ns
300
µs
pF
Notes:
1. All values referred to VIHmin and VILmax levels.
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I2C Timing
STOP
START
START
SDA
tSU;DAT
tLOW
tf
tf
tr
t HD;STA
tBUF
SCL
S
tHD;STA
tHD;DAT
HIGH
t SU;STA
Sr
t SU;STO
P
S
Eye Diagrams 5.0Gbps (input left, output right)
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Data Waveforms, 2.5Gbps (left) & 5.0Gbps (right)
AC Test Circuit Referenced in the Electrical Characteristic Table
FR4
Signal
Source
A
B
C
D.U.T.
SmA
Connector
SmA
Connector
In
Out
≤30IN
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Packaging Information
1
DATE: 05/15/08
DESCRIPTION: 56-contact, Thin Fine Pitch Quad Flat No-lead (TQFN)
PACKAGE CODE: ZF56
DOCUMENT CONTROL #: PD-2024
REVISION: C
08-0208
Note:
For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information
Ordering Number
Package Code
Package Description
PI2EQX5964ZFE
ZF
Pb-free & Green 56-Contact TQFN
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• X suffix = Tape/Reel
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