PI3PCIE2415 3.3V PCI Express® 2.0, 2-Lane, 2:1 Mux/DeMux Switch Features Description ÎÎ4 Differential Channel, 2:1 Mux/DeMux Pericom Semiconductor’s PI3PCIE2415 is an 8 to 4 differential channel multiplexer/demultiplexer switch. This solution can switch 2 full PCI Express® 2.0, lanes to one of two locations. Using a unique design technique, Pericom has been able to minimize the impedance of the switch such that the attenuation observed through the switch is negligible. The unique design technique also offers a layout targeted for PCI Express signals, which minimizes the channel to channel skew as well as channel to channel crosstalk as required by the PCI Express specification. ÎÎPCI Express® 2.0 Performance, 5.0Gbps ÎÎPinout optimized for placement between two PCIe slots ÎÎBi-directional operation ÎÎLow Bit-to-Bit Skew, 5ps max ÎÎLow Crosstalk: -26dB@5 GHz ÎÎLow Off Isolation: -20dB@5 GHz ÎÎVDD Operating Range: +3.3V ÎÎESD Tolerance: 2kV HBM ÎÎLow channel-to-channel skew, 35ps max Application ÎÎPackaging (Pb-free & Green): Routing of PCIe® 2.0, signals with low signal attenuation. àà 42-contact, TQFN (ZH42) Block Diagram CI CI DI DI + – + – + – + – AOa AOa BOa BOa AOb AOb BOb BOb + – + – + – + – COa COa DOa DOa + – + – AOb+ AObBI+ BIBOb+ BOb- COb + VDD CI+ GND VDD GND VDD AI AI BI BI Pin Description (Top-Side View) AI+ AI- COb – CI- DOb + COb+ CObDI+ DI- DOb – SEL DOb+ DOb- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 42 41 40 39 GND 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 GND AOa+ AOaGND VDD BOa+ BOaVDD SEL GND COa+ COaVDD GND DOa+ DOaGND 18 19 20 21 Function SEL xIy to xOay L xIy to xOby H All trademarks are property of their respective owners. GND VDD GND VDD Truth Table 13-0009 1 www.pericom.comPS8945B.103/20/13 PI3PCIE2415 3.3V PCI Express® 2.0, 2-Lane, 2:1 Mux/DeMux Switch Signal Descriptions Pin Number Pin Name Type Description 1, 2 AI+, AI- Differential input Differential input pair from PCIE signal source. Signal is passed through to the AOa+, AOa- pin respectively when SEL=0. Signal is passed through to the AOb+, AOb- pin respectively when SEL = 1. 37, 36 AOa+, AOa- Differential pass-through input Differential analog pass-through output. Signal from AI+ and AIis passed through AOa+ and AOa- respectively when SEL=0. 3, 4 AOb+, AOb- Differential pass-through input Differential analog pass-through output. Signal from AI+ and AIis passed through AOa+ and AOa- respectively when SEL=1. 5, 6 BI+, BI- Differential input Differential input pair from PCIE signal source. Signal is passed through to the BOa+, BOa- pin respectively when SEL=0. Signal is passed through to the BOb+, BOb- pin respectively when SEL = 1. 33, 32 BOa+, BOa- Differential pass-through input Differential analog pass-through output. Signal from BI+ and BIis passed through BOa+ and BOa- respectively when SEL=0. 7, 8 BOb+, BOb- Differential pass-through input Differential analog pass-through output. Signal from BI+ and BIis passed through BOb+ and BOb- respectively when SEL=1. 10, 11 CI+, CI- Differential input Differential input pair from PCIE signal source. Signal is passed through the COa+, COa- pin respectively When SEL=0. Signal is passed through to the COb+, COb- pin respectively when SEL = 1. 28, 27 COa+, COa- Differential pass-through input Differential analog pass-through output. Signal from CI+ and CIis passed through COa+, COa- pin respectively when SEL = 0. 12, 13 COb+, COb- Differential pass-through input Differential analog pass-through output. Signal from CI+ and CIis passed through COb+, COb- pin respectively when SEL = 1. 14, 15 DI+, DI- Differential input Differential input pair from PCIE signal source. Signal is passed through the DOa+, DOa- pin respectively When SEL=0. Signal is passed through to the DOb+, DOb- pin respectively when SEL = 1. 24, 23 DOa+, DOa- Differential pass-through input Differential analog pass-through output. Signal from DI+ and DIis passed through DOa+, DOa- pin respectively when SEL = 0. 16, 17 DOb+, DOb- Differential pass-through input Differential analog pass-through output. Signal from DI+ and DIis passed through DOb+, DOb- pin respectively when SEL = 1. 18, 20, 22, 25, 29, GND 35, 38, 40, 42 Ground input Ground 30 SEL 3.6V tolerant low-voltage single-ended input SEL controls the mux through a flow-through latch. 9, 19, 21, 26, 31, 34, 39, 41 VDD Power supply Power, 3.3V ±10% All trademarks are property of their respective owners. 13-0009 2 www.pericom.comPS8945B.103/20/13 PI3PCIE2415 3.3V PCI Express® 2.0, 2-Lane, 2:1 Mux/DeMux Switch Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Supply Voltage to Ground Potential . . . . . . . . . . . . . –0.5V to +4.6V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to VDD DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Symbol Parameter VDD Conditions Min Typ Max Units 3.3V Power Supply 3.0 3.3 3.6 V IDD Total current from VDD 3.3V supply 0 2.5 mA TCASE Case temperature range for operation within spec. -40 85 Celsius Max Units DC Electrical Characteristics (TA = –40°C to +85°C, VDD = 3.3V ± 10%) Description VIH-SEL(2) Input high level, SEL input 2.0 3.6 V VIL-SEL(2) Input Low Level, SEL input 0 0.8 V IIN_SEL(2) Input Leakage Current, SEL input Measured with input at VIH-SEL max and VIL-SEL min –10 10 uA RON On Resistance VDD = Min., VIN = 1.3V, IIN = 40mA 12 Ohm On Channel Capacitance VIN = 0, VDD = 3.3V CON Test Conditions Min Typ(1) Parameter 2.0 pF Note: 1. Typical values are at VDD = 3.3V, Ta = 25°C ambient and maximum loading. All trademarks are property of their respective owners. 13-0009 3 www.pericom.comPS8945B.103/20/13 PI3PCIE2415 3.3V PCI Express® 2.0, 2-Lane, 2:1 Mux/DeMux Switch Dynamic Electrical Characteristics for xI±, xOy± Parameter DDIL DDILOFF DDRL DDNEXT Description Differential Insertion Loss Differential Off Isolation Test Conditions Min. f=1.2GHz -1.5 f=2.5GHz -2.0 f=5.0GHz -5.0 f=7.5GHz -9.0 Typ.(1) f= 0 to 3.0GHz Differential Return Loss Near End Crosstalk Max. Units -20.0 f= 0 to 2.8GHz -14.0 f= 2.8 to 5.0GHz -8.0 f= 5.0 to 7.5GHz -4.0 dB f= 0 to 2.5GHz -32.0 f= 2.5 to 5.0GHz -26.0 f= 5.0 to 7.5GHz -20.0 Switching Characteristics (TA= -40º to +85ºC, VDD = 3.3V±10%) Parameter Description Test Conditions tPZH, tPZL Line Enable Time - SEL to xI±, xOy± tPHZ , tPLZ Line Disable Time - SEL to xI±, xOy± tb-b Bit-to-bit skew within the same differential See "Test Circuit for pair Electrical Characteristics" tch-ch Channel-to-channel skew See "Test Circuit for Electrical Characteristics" See "Test Circuit for Electrical Characteristics" Min. Max. Units 0.5 12.0 ns 0.5 12.0 ns 7 ps 35 ps See "Test Circuit for Electrical Characteristics" Typ. 5.0 Gbps Receive Eye Mask -3.5dB WITH the Switch All trademarks are property of their respective owners. 13-0009 4 www.pericom.comPS8945B.103/20/13 PI3PCIE2415 3.3V PCI Express® 2.0, 2-Lane, 2:1 Mux/DeMux Switch Differential Insertion Loss Differential Return Loss All trademarks are property of their respective owners. 13-0009 5 www.pericom.comPS8945B.103/20/13 PI3PCIE2415 3.3V PCI Express® 2.0, 2-Lane, 2:1 Mux/DeMux Switch Differential Off Isolation Differential Crosstalk All trademarks are property of their respective owners. 13-0009 6 www.pericom.comPS8945B.103/20/13 PI3PCIE2415 3.3V PCI Express® 2.0, 2-Lane, 2:1 Mux/DeMux Switch R Notes: 1.CL = Load capacitance: includes jig and probe capacitance. 2. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator 3. Output 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Output 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, tR ≤ 2.5ns, tF ≤ 2.5ns. 5. The outputs are measured one at a time with one transition per measurement. Switching Waveforms SEL VDD/2 VDD VDD/2 0V Output 1 tPZL tPLZ VDD/2 VOH VOL + 0.15V tPHZ tPZH VOH – 0.15V VDD/2 VOL VOH VOL Output 2 Voltage Waveforms Enable and Disable Times + + + + + + + + + Diff. Insertion Loss and Return Test Circuit All trademarks are property of their respective owners. Diff. Off Isolation Test Circuit 13-0009 7 Diff. Near End Xtalk Test Circuit www.pericom.comPS8945B.103/20/13 PI3PCIE2415 3.3V PCI Express® 2.0, 2-Lane, 2:1 Mux/DeMux Switch Application Information Differential Inputs/Output Characteristics for PCIe® 2.0 speeds Symbol Parameter Min Nom Max Units Comments Tbit Unit Interval 199.94 200.00 200.06 ps Defined by PCIe 2.0 spec. VRX-Diffp-p Differential Input Peak-toPeak Voltage TBD 1.200 V VRX-DIFFp-p = 2*|VRX-D+ - VRX-D-|. Applies to IN_S and RX_IN signals. TRX-EYE Minimum Eye Width at IN_D input pair. TBD Tbit VCM-AC-pp = |VRX-D+ + VRX-D-|/2 - VRX-CM-DC. VCM-AC-pp AC Peak Common-Mode Input Voltage 100 mV VRX-CM-DC = DC(avg) of |VRX-D++VRX-D-|/2 VCM-AC-pp includes all frequencies above 30kHz. ZRX-DIFF-DC Dc Differential Input Impedance 80 ZRX-DC DC Input Impedance 40 VRX-Bias Rx input termination voltage 0 All trademarks are property of their respective owners. 13-0009 100 50 8 W Rx DC Differential Mode impedance 60 W Required IN_D+ as well as IN_D- DC impedance (50 W ± 20% tolerance). Includes mux resistance. 2.0 V Intended to limit power-up stress on PCIe output buffers. 120 www.pericom.comPS8945B.103/20/13 PI3PCIE2415 3.3V PCI Express® 2.0, 2-Lane, 2:1 Mux/DeMux Switch Packaging Mechanical: 42-Contact TQFN (ZH) Notes: 1. All dimensions are in millimeters. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. 3. Refer JEDEC MO-220. 4. Recommended land pattern is for reference only. 5. Thermal pad soldering area DATE: 11/14/12 DESCRIPTION: 42-contact Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZH42 DOCUMENT CONTROL #: PD-2035 REVISION:D 12-0529 Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information Ordering Code Package Code Package Description PI3PCIE2415ZHE ZH Pb-free & Green, 42-contact TQFN Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • "E" denotes Pb-free and Green • Adding an "X" at the end of the ordering code denotes tape and reel packaging All trademarks are property of their respective owners. 13-0009 9 www.pericom.comPS8945B.103/20/13