PI6C2510-133E Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs Features Description • Operating Frequency up to 150 MHz • Low-Noise Phase-Locked Loop Clock Distribution that meets 133 MHz Registered DIMM Synchronous DRAM modules for server/workstation/PC applications • Allows Clock Input to have Spread Spectrum modulation for EMI reduction • Low jitter: Cycle-to-Cycle jitter ±75ps max. • On-chip series damping resistor at clock output drivers for low noise and EMI reduction • Operates at 3.3V VCC, 0–85°C • Packages (Pb-free & Green available): – Plastic 24-pin TSSOP (L) The PI6C2510-133E is a “enhanced,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. This zero-delay feature allows the CLK_IN input clock to be distributed, providing one clock input to one bank of ten outputs, with an output enable. Block Diagram Pin Configuration This clock driver is designed to meet the PC133 SDRAM Registered DIMM specification. For test purposes, the PLL can be bypassed by strapping AVCC to ground. AGND VCC Y0 Y1 Y2 GND GND Y3 Y4 VCC G FB_OUT G 10 Y[0:9] CLK_IN FB_OUT PLL FB_IN AVcc Functional Table Inputs G L H 09-0006 24 1 2 23 3 22 21 4 20 5 6 24-Pin 19 L 18 7 17 8 9 16 15 10 14 11 12 13 CLK_IN AVCC VCC Y9 Y8 GND GND Y7 Y6 Y5 VCC FB_IN Outputs Y[0:9] L CLK_IN FB_OUT CLK_IN CLK_IN 1 PS8505B 11/18/09 PI6C2510-133E Low–noise, Phase –Locked Loop Clock Driver with 10 Clock Outputs Pin Functions Pin Pin Type Name Number CLK_IN 24 I FB_IN 13 I G 11 I FB_OUT 12 O Y[0:9] 3, 4, 5, 8, 9, 15, 16, O 17, 20, 21 AVCC 23 Power AGND 1 Ground 2, 10, 14, Power 22 6, 7, 18, Ground 19 VCC GND Description Reference Clock input. CLK_IN allows spread spectrum. Feedback input. FB_IN provides the feedback signal to the internal PLL. Output bank enable. When G is LOW, outputs Y[0:9] are disabled to a logic low state. When G is HIGH, all outputs Y[0:9] are enabled. Feedback output. FB_OUT is dedicated for external feedback. FB_OUT has an embedded series-damping resistor of same value as clock outputs Y[0:9]. Clock outputs. These outputs provide low-skew copies of CLK_IN. Each output has an embedded series-damping resistor. Analog power supply. AVcc can be also used to bupass the PLL for test purposes. When AVcc is strapped to ground, PLL is bypassed and CLK_IN bufferef directly to the device outputs. Analog ground. AGND provides thr ground referencefor the analog circuitry/ Power Supply Ground DC Specifications - Absolute maximum ratings over operating free-air temperature range. Symbol Parameter Min. Max. VI Input voltage range VCC + 0.5 VO Output voltage range –0.5 VI_DC DC input voltage +5.0 DC output current 100 IO_DC Maximum power dissipation at TA = 59˚C in Power 1.0 still airr TSTG Storage temperature –65 160 Units V mA W °C Note: Stress beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. Parameter ICC CI CO 09-0006 Test Conditions VI = VCC or GND; IO = 0 VI = VCC or GND VO = VCC or GND VCC 3.6V 3.3V 2 Min Typ Max 10 4 6 Units uA pF PS8505B 11/18/09 PI6C2510-133E Low–noise, Phase –Locked Loop Clock Driver with 10 Clock Outputs Recommended Operating Conditions Symbol Parameter VCC Supply voltage VIH High level input voltage VIL Low level input voltage VI Input Voltage TA Operating free-air temperature Min. 3.0 2.0 0.0 0 Max. 3.6 Units 0.8 VCC 85 V Electrical Characteristics (Over recommended operating free-air temperature range.) Pull Up/Down Currents of PI6C2510-133E, VCC = 3.0V Symbol Parameter Condition Min Pull-up current VOUT = 2.4V ICH Pull-up current VOUT = 2.0V Pull-down current VOUT = 0.8V 19 ICIL Pull-down current VOUT = 0.55V 13 °C Max –13.6 –22 Units mA AC Specifications - Timing requirements over recommended ranges of supply voltage and operating free-air temperature. Symbol FCLK Parameter Input Clock Frequency Input Clock Duty Cycle Stabilization Time after power up Min 25 40 Max 150 60 1 Units MHz % ms Switching Characteristics (Over recommended ranges of supply voltage and operating free-air temperature, CL=30pF.) VCC = 3.3V ± 0.3V, 0–85˚C Parameter From To Units Min. Typ. Max. tphase error, with and without CLK_IN↑ at 133MHz FB_IN↑ –150 +150 spread spectrum Any Output or FB_ Jitter, cycle-to-cycle, with and ps Output or FB_OUT OUT in CLKn at 133 –75 +75 without spread spectrum in CLKn+1 MHz Skew, at 133 MHz Any Y or FB_OUT 150 Duty Cycle 45 50 55 % Any Y or FB_OUT tr, rise-time, 0.4V to 2.0V 1.0 ns tf, fall-time, 2.0V to 0.4V 1.1 Note: These switching parameters are guaranteed, but not production tested. 09-0006 3 PS8505B 11/18/09 PI6C2510-133E Low–noise, Phase –Locked Loop Clock Driver with 10 Clock Outputs DOCUMENT CONTROL NO. PD - 1312 24 REVISION: E DATE: 03/09/05 .169 .177 4.3 4.5 .004 .008 1 .303 .311 7.7 7.9 .0256 BSC 0.65 0.45 0.75 .047 1.20 Max .007 .012 0.19 0.30 .002 .006 SEATING PLANE 0.09 0.20 .018 .030 .252 BSC 6.4 0.05 0.15 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com Note: 1. Package Outline Exclusive of Mold Flash and Metal Burr 2. Controlling dimentions in millimeters 3. Ref: JEDEC MO-153F/AD DESCRIPTION: 24-Pin, 173-Mil Wide, TSSOP PACKAGE CODE: L Note: • For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Order Information Ordering Code PI6C2510-133EL PI6C2510-133ELEX Packaging Code L L Packaging Description 24-pin plastic TSSOP Pb-Free & Green 24-pin plastic TSSOP Frequency Range 25MHz - 150MHz 25MHz - 150MHz Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • E = Pb-free and Green • Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 09-0006 4 PS8505B 11/18/09