PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Features Description • • • • • The PI6C48533-01 is a high-performance low-skew LVPECL fanout buffer. PI6C48533-01 features two selectable differential inputs and translates to four LVPECL ultra-low jitter outputs. The inputs can also be configured to single-ended with external resistor bias circuit. The CLK input accepts LPECL or LVDS or LVHSTL or SSTL or HCSL signals, and PCLK input accepts LVPECL or SSTL or CML signals. The outputs are synchronized with input clock during asynchronous assertion/deassertion of CLK_EN pin. PI6C48533-01 is ideal for differential to LVPECL translations and/or LVPECL clock distribution. Typical clock translation and distribution applications are data-communications and telecommunications. Pin-to-pin compatible to ICS8533-01 Maximum operation frequency: 800MHz 4 pair of differential LVPECL outputs Selectable differential CLK and PCLK inputs CLK, nCLK pair accepts LVDS, LVPECL, LVHSTL, SSTL and HCSL input level • PCLK, nPCLK pair supports LVPECL, CML and SSTL input level • • • • • • Output Skew: 100ps (maximum) Part-to-part skew: 150ps (maximum) Propagation delay: 2ns (maximum) 3.3V power supply Operating Temperature: -40oC to 85oC Packaging (Pb-free & Green avaliable): -20-pin TSSOP (L) Block Diagram Pin Diagram CLK_EN D Q LE CLK nCLK PCLK nPCLK CLK_SEL 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 15-0084 1 VEE 1 20 Q0 CLK_EN 2 19 nQ0 CLK_SEL 3 18 VCC CLK 4 17 Q1 nCLK 5 16 nQ1 PCLK 6 15 Q2 nPCLK 7 14 nQ2 NC 8 13 VCC NC 9 12 Q3 VCC 10 11 nQ3 Rev B 6/23/2015 PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Pin Description Name Pin # Type Description VEE 1 P Connect to Negative power supply CLK_EN 2 I_PU Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL level with 50KΩ pull-up. CLK_ SEL 3 I_PD Clock select input. When high, selects PCLK input. When low, selects CLK input. LVCMOS/ LVTTL level with 50KΩ pull-down. CLK 4 I_PD Non-inverting differential clock input nCLK 5 I_PU Inverting differential clock input PCLK 6 I_PD Non-inverting differential clock input nPCLK 7 I_PU Inverting differential clock input NC 8, 9 VCC 10, 13, 18 nQ3, 11, Q3 12 nQ2, 14, Q2 15 nQ1, 16, Q1 17 nQ0, 19, Q0 20 Not connected P Connect to 3.3V. O Differential output pair, LVPECL interface level. O Differential output pair, LVPECL interface level. O Differential output pair, LVPECL interface level. O Differential output pair, LVPECL interface level. Note: 1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up Pin Characteristics Symbol Parameter Conditions Min. Typ. CIN Input Capacitance R_pullup Input Pullup Resistance 50 R_pulldown Input Pulldown Resistance 50 Max. Units 4 pF KΩ Control Input Function Table(1) Inputs Outputs CLK_EN CLK_SEL Selected Source Q0:Q3 nQ0:nQ3 0 0 CLK, nCLK Diasbled: Low Diasbled: High 0 1 PCLK, nPCLK Disabled: Low Disabled: High 1 0 CLK, nCLK Enabled Enabled 1 1 PCLK, nPCLK Enabled Enabled Note: 1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below. 15-0084 2 Rev B 6/23/2015 PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Figure 1. CLK_EN Timing Diagram Disabled Enabled nCLK, nPCLK CLK, PCLK CLK_EN nQ0:nQ3 Q0:Q3 Clock Input Function Table Inputs CLK or PCLK nCLK 0 Outputs or nPCLK Input to Output Mode Polarity Q0:Q3 nQ0:nQ3 1 LOW HIGH Differential to Differential None Inverting 1 0 HIGH LOW Differential to Differential None Inverting 0 Biased; VIN = VCC/2 LOW HIGH Single Ended to Differential None Inverting 1 Biased; VIN = VCC/2 HIGH LOW Single Ended to Differential None Inverting Vcc/2 0 HIGH LOW Single Ended to Differential Inverting VCC/2 1 LOW HIGH Single Ended to Differential Inverting Absolute Maximum Ratings(1) Symbol Parameter Conditions Min. Typ. Max. VCC Supply voltage Referenced to GND VIN Input voltage Referenced to GND -0.5 VCC+0.5V VOUT Output voltage Referenced to GND -0.5 VCC+0.5V TSTG Storage temperature -65 150 Units 4.6 V oC Note: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress speci fications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 15-0084 3 Rev B 6/23/2015 PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Operating Conditions Symbol Parameter VCC Conditions Min. Typ. Max. Units Power Supply Voltage 3.0 3.3 3.6 V TA Ambient Temperature -40 85 oC IEE Power Supply Current 60 mA 500 MHz LVCMOS/LVTTL DC Characteristics (TA = -40oC to 85oC, VCC = 3.0V to 3.6V unless otherwise stated.) Symbol Parameter Conditions Min. Typ. Max. Units VIH Input High Voltage 2 VCC+0.3 VIL Input Low Voltage -0.3 0.8 IIH Input High Current IIL Input Low Current CLK, CLK_SEL VIN = VCC = 3.6V 150 CLK_EN VIN = VCC = 3.6V 5 CLK, CLK_SEL VIN = 0V, VCC = 3.6V -5 CLK_EN VIN = 0V, VCC = 3.6V -150 V µA Differential DC Input Characteristics (TA = -40oC to 85oC, VCC = 3.0V to 3.6V unless otherwise stated.) Symbol Parameter Conditions Min. Typ. Max. IIH Input High Current nCLK, nPCLK VIN = VCC = 3.6V 5 CLK, PCLK VIN = VCC = 3.6V 150 IIL Input Low Current nCLK, nPCLK VCC = 3.6V, VIN = 0V -150 CLK, PCLK VCC = 3.6V, VIN = 0V -5 VPP Peak-to-peak Voltage 0.15 1.3 VCMR Common Mode Input Voltage(1, 2) VEE+0.5 VCC0.85V Units µA V Notes: 1. For single ended applications, the maximum input voltage for CLK and nCLK is VCC+0.3V 2. Common mode voltage is defined as VIH. 15-0084 4 Rev B 6/23/2015 PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer LVPECL DC Characteristics (TA = -40oC to 85oC, VCC = 3.0V to 3.6V, RL= 50Ω to VCC - 2V, unless otherwise stated below.) Symbol Parameter Conditions Min. Typ. Max. Units IIH Input High Current nCLK, nPCLK VIN = VCC = 3.6V 5 CLK, PCLK VIN = VCC = 3.6V 150 IIL Input Low Current nCLK, nPCLK VCC = 3.6V, VIN = 0V -150 CLK, PCLK VCC = 3.6V, VIN = 0V -5 VPP Peak-to-peak Voltage 0.3 1 VCMR Common Mode Input Voltage; Note(1,2) VEE+1.5 VCC VOH Output High Voltage VCC-1.4 VCC-0.9 VOL Output Low Voltage VCC-2.0 VCC-1.6 VSWING Peak-to-peak Output Voltage Swing 0.6 1.0 µA V Notes: 1. For single ended applications, the maximum input voltage for PCLK and nPCLK is VCC+0.3V. 2. Common mode voltage is defined as VIH. AC Characteristics(1) (TA = -40oC to 85oC, VCC = 3.0V to 3.6V, RL= 50Ω to VCC - 2V, unless otherwise stated below.) Symbol Parameter Conditions fmax Output Frequency tPd Propagation Tsk(o) Output-to-output Min. Delay(2) Typ. Max. Units 500 800 MHz 2.0 ns 1.0 Skew(3) 100 Skew(4) Tsk(pp) Part-to-part tr/tf Output Rise/Fall time odc Output duty cycle Jadd Additive Jitter 150 20% - 80% 75 300 40 60 50 ps % fs Notes: 1. All parameters are measured at 500MHz unless noted otherwise 2. Measured from the VCC/2 of the input to the differential output crossing point 3 Defined as skew between outputs at the same supply voltage and with equal load condition. Measured at the outputs differential crossing point. 4. Defined as skew between outputs on different parts operating at the same supply voltage and with equal load condition. Measured at the outputs differential crossing point. 15-0084 5 Rev B 6/23/2015 PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Applications Information Wiring the differenctial input to accept single ended levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609. VCC Single Ended Clock Input R1 1K CLK nCLK C1 0.1µ R2 1K Figure 2: Single-ended Signal Driving Differential Input 15-0084 6 Rev B 6/23/2015 PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Note: • For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information(1,2) Ordering Code Package Code Package Description PI6C48533-01LE L Pb-free & Green 20-pin 173-mil wide TSSOP PI6C48533-01LEX L Pb-free & Green 20-pin 173-mil wide TSSOP, Tape & Reel Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 15-0084 7 Rev B 6/23/2015