PI6CVF857

PI6CVF857
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1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Product Features
Product Description
• Operating Frequency up to 220 MHz for PC3200 Registered
DIMM applications
PI6CVF857 PLL clock device is developed for registered DDR DIMM
applications. The device is a zero-delay buffer that distributes a
differential clock input pair (CLK, CLK) to ten differential pairs of
clock outputs (Y[0:9], Y[0:9]), and one differential pair feedback clock
outputs (FBOUT,FBOUT) . The clock outputs are controlled by the
input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V
LVCMOS input (PWRDWN), and the Analog Power input (AVDD).
When input PWRDWN is low while power is applied, the input
receivers are disabled, the PLL is turned off, and the differential clock
outputs are 3-stated. When the AVDD is strapped low, the PLL is
turned off and bypassed for test purposes.
• Distributes one differential clock input pair to ten differential
clock output pairs
• Inputs (CLK,CLK) and (FBIN,FBIN)
• Input PWRDWN: LVCMOS
• Outputs (Yx, Yx), (FBOUT, FBOUT)
• External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the clock input
• Operates at 2.5V for PC1600, PC2100, PC2700,
and 2.6V for PC3200
• Packaging (Pb-free & Green available):
– 48-pin TSSOP
When the input frequency falls below a suggested detection frequency that is below the operating frequency of the PLL, the device
will enter a low power mode. An input frequency detection circuit will
detect the low frequency condition and perform the same low power
features as when the PWRDWN input is low.
Block Diagram
The PLL in the PI6CVF857 clock driver uses the input clocks (CLK,
CLK) and the feedback clocks (FBIN,FBIN) to provide high-performance, low-skew, low-jitter output differential clocks (Y[0:9], Y[0:9]).
The PI6CVF857 is also able to track Spread Spectrum Clocking for
reduced EMI.
Y0
Y0
Y1
CLK
CLK
FBIN
PLL
Y1
Y2
Y2
Y3
FBIN
Y3
Y4
Y4
Y5
Y5
Y6
PWRDWN
AVDD
Powerdown
and Test
Logic
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
08-0298
1
PS8683D
11/12/08
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
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08-0298
Y6
Y6
Y5
VDDQ
Y0
Y5
Y0
Y1
1
30
Y7
Y2
2
29
Y7
Y2
3
28
VDDQ
VDDQ
4
27
PWRDWN
CLK
5
26
FBIN
CLK
6
25
FBIN
VDDQ
7
24
VDDQ
AVDD
8
23
VDDQ
AGND
9
22
FBOUT
10
21
11 12 13 14 15 16 17 18 19 20
FBOUT
Y8
Y8
Y9
VDDQ
Y4
Y9
GND
Y4
GND
2
VDDQ
40 39 38 37 36 35 34 33 32 31
GND
VDDQ
GND
Y5
Y5
VD D Q
Y6
Y6
GND
GND
Y7
Y7
VD D Q
PWRDWN
FBIN
FBIN
VD D Q
FBOUT
FBOUT
GND
Y8
Y8
VD D Q
Y9
Y9
GND
Y1
48
1
2
47
46
3
45
4
44
5
43
6
7
42
41
8
40
9
10 48-Pin 39
38
11
A
37
12
36
13
35
14
34
15
16
33
32
17
31
18
30
19
29
20
28
21
27
22
23
26
24
25
Y3
GND
Y0
Y0
VD D Q
Y1
Y1
GND
GND
Y2
Y2
VD D Q
VD D Q
CLK
CLK
VD D Q
AV D D
AGND
GND
Y3
Y3
VD D Q
Y4
Y4
GND
Pin Configuration TQFN (ZD)
Y3
Pin Configuration TSSOP ( A)
PS8683D
10/06/08
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
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Pinout Table
Pin Name
De s cription
CLK
CLK
Reference Clock input
Yx
Clock outputs.
Yx
Complement Clock outputs.
FBOUT
FBOUT
Feedback output, and Complement Feedback Output
FBIN
FBIN
Feedback Input, and Complement Feedback Input
Power down and output disable for all Yx and Yx outputs. When PWRDWN = 0, the part is powered down and
the differential clock outputs are disabled to a - state. When PWRDWN = 1, all differential clock outputs are
enabled and run at the same frequency as CLK.
PWRDWN
VDDQ
Power Supply for I/O.
AVDD
Analog /core power supply. AVDD can be used to bypass the PLL for testing purposes. When AVDD is strapped to
ground, PLL is bypassed and CLK is buffered directly to the device outputs.
AGND
Analog/core ground. Provides the ground reference for the analog/core circuitry
GND
Ground
Function Table
Inputs
Outputs
PLL
AVDD
PWRDWN
CLK
CLK
Y
Y
FBOUT
FBOUT
GND
H
L
H
L
H
L
H
Bypassed/off
GND
H
H
L
H
L
H
L
Bypassed/off
X
L
L
H
Z
Z
Z
Z
off
X
L
H
L
Z
Z
Z
Z
off
Nominal(2)
H
L
H
L
H
L
H
on
Nominal(2)
H
H
L
H
L
H
L
on
Z
Z
Z
Z
off
Nominal(2)
X
< 20
MHz (1)
Notes:
1. For testing and power saving purposes, PI6CVF857 will power down if the frequency of the reference inputs CLK, CLK is well below the
operating frequency range. The maximum power down clock frequency is below 20 MHz. For example, PI6CVF857 will be powered down when
the CLK,CLK stop running.
2. AVDD Nominal is 2.5V for PC1600, PC2100, and PC2700. AVDD Nominal is 2.6V for PC3200.
Z = High impedance
X = Don’t care
08-0298
3
PS8683D
10/06/08
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
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Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol
M in.
M a x.
I/O supply voltage range and analog/core supply voltage range
– 0.5
3.6
VI
Input voltage range
– 0.5
VO
Output voltage range
– 0.5
IIK
Input Clamp Current
– 50
50
IOK
Output Clamp Current
– 50
50
IO
Continuous output Current
– 50
50
Continuous current through each AVDD, VDDQ, or GND
– 100
100
Tstg
Storage temperature
– 65
150
∅JA
Junction to ambient thermal (package A)
104
o
C/w
∅JC
Junction to case thermal (package A)
38
o
C/w
VDDQ, AVDD
IO(PWR)
Parame te r
Units
V
VDDQ +0.5
mA
oC
Note: Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
DC Specifications
Recommended Operating Conditions
Symbol
Parame te r
AVDD
Analog/core supply voltage
VDDQ
Output supply voltage
M in.
Nom.
M a x.
VDDQ – 0.12
VDDQ
2.7
P C 16 0 0 - P C 2 7 0 0
2 .3
2.5
2. 7
P C 3200
2 .5
2.6
2. 7
VIL
Low- level input voltage for PWRDWN pin
–0.3
0.7
VIH
High- level input voltage for PWRDWN pin
1.7
VDDQ +0.3
IOH
High- level output current
–
12
IOL
Low- level output current
–
–12
VIX
Input differential- pair crossing voltage
(VDDQ/2)
–0 . 2
(VDDQ/2) +0.2
VIN
Input voltage level
–0 . 3
VDDQ +0.3
DC
0.36
VDDQ +0.6
AC
0 .7
VDDQ +0.6
–4 0
85
VID
Input differential voltage between CLK and
CLK
TA
O perating free air temperature
08-0298
4
PS8683D
Units
V
mA
V
°C
10/06/08
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
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Timing Requirements for PC1600 ~ PC2700 (Over recommended operating free-air temperature)
Symbol
fCK
tDC
AVDD, VDDQ = 2.5V ±0.2V
De s cription
M in.
M a x.
Operating clock frequency(1,2)
60
17 0
Application clock frequency(3)
95
17 0
Input clock duty cycle
tSTAB
40
PLL stabilization time after powerup
Units
MHz
60
%
100
μs
Notes:
1. The PLL is able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the other timing
parameters. (Used for low-speed debug).
3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.
Electrical Characteristics for PC1600 ~ PC2700 (Over recommended operating free-air temperature)
Parame te r
VIK
All inputs
VOH
High output voltage
VOL
Low output voltage
II
Te s t Conditions
II = –18mA
AVDD, VDDQ
M in.
2.3V
Typ.
M ax.
Units
–1.2
IOH = –100μA
2.3 to 2.7V
VDDQ– 0.1
IOH = –12mA
2.3V
1.7
IOL = 100μA
2.3 to 2.7V
0. 1
IOL = 12mA
2.3V
0.6
CLK, FBIN
VI = VDDQ or GND
2.7V
PWRDWN
VI = VDDQ or GND
2.7V
V
±10
μA
IDDPD
CLK & CLK = 0 MHz,
Static supply current IDDQ + IADD
PWRDWN = Low
IDDQ
Dynamic supply current of VDDQ
CLK & CLK = 170 MHz
All outputs are open
2.7V
300
mA
IADD
Dynamic supply current of AVDD
CLK & CLK = 170 MHz
2 . 7V
12
mA
VI = VDDQ or GND
2.5V
CI
CI(Δ)
CLK and CLK
FBIN and FBIN
CLK and CLK(5)
FBIN and FBIN(5)
200
2.0
3 .5
pF
VI = VDDQ or GND
2.5V
–0.25
0.25
Note:
4. The maximum power-down clock frequency is below 20 MHz.
5. Guaranteed by design, but not production tested.
08-0298
5
PS8683D
10/06/08
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
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Timing Requirements for PC3200 (Over recommended operating free-air temperature)
Symbol
fCK
tDC
tSTAB
AVDD, VDDQ = 2.6V ±0.1V
De s cription
Units
M in.
M a x.
Operating clock frequency(1,2)
60
22 0
Application clock frequency(3)
95
220
Input clock duty cycle
40
60
%
100
μs
PLL stabilization time after powerup
MHz
Notes:
1. The PLL is able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the other timing
parameters. (Used for low-speed debug).
3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.
Electrical Characteristics for PC3200 (Over recommended operating free-air temperature)
Parame te r
VIK
All inputs
VOH
High output voltage
VOL
Low output voltage
II
Te s t Conditions
II = –18mA
AVDD, VDDQ
M in.
2.5V
Typ.
M ax.
Units
–1.2
IOH = –100μA
2.5 to 2.7V
VDDQ– 0.1
IOH = –12mA
2.5V
1.7
IOL = 100μA
2.5 to 2.7V
0. 1
IOL = 12mA
2.5V
0.6
CLK, FBIN
VI = VDDQ or GND
2.7V
PWRDWN
VI = VDDQ or GND
2.7V
V
±10
μA
IDDPD
CLK & CLK = 0 MHz,
Static supply current IDDQ + IADD
PWRDWN = Low
IDDQ
Dynamic supply current of VDDQ
CLK & CLK = 200 MHz
All outputs are open
2.7V
300
mA
IADD
Dynamic supply current of AVDD
CLK & CLK = 200 MHz
2 . 7V
12
mA
VI = VDDQ or GND
2.6V
CI
CI(Δ)
CLK and CLK
FBIN and FBIN
CLK and CLK(5)
FBIN and FBIN(5)
200
2.0
3 .5
pF
VI = VDDQ or GND
2.6V
–0.25
0.25
Note:
4. The maximum power-down clock frequency is below 20 MHz.
5. Guaranteed by design, but not production tested.
08-0298
6
PS8683D
10/06/08
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
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AC Specifications for PC1600 ~ PC2700
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)( See Figure 1 & 2 )
Parame te r
De s cription
AVDD, VDDQ = 2.5V ±0.2V
Diagram
M in.
Nom.
Units
M ax
tjit(cc)
Cycle- to- cycle jitter
Figure 4
–5 0
50
t(θ)
Static phase offset(1)
Figure 5
–50
tsk(o)
Output clock skew
Figure 6
tjit(per)
Period jitter
Figure 7
–75
75
tjit(hper)
Half- period jitter
Figure 8
–100
100
tsl(i)
Input clock slew rate
Figure 9
1.0
4.0
tsl(o)
Output clock slew rate(2)
Figure 9
1.0
2 .0
VOX
Output differential- pair cross- voltage
(VDDQ/2) –0.1
(VDDQ/2) +0.1
0
50
ps
75
V/ns
V
The PLL is capable of meeting all the above parameters while supporting SSC synthesizers with the following parameters
SSC modulation frequency
3 0 . 00
50.00
kHz
SSC clock input frequency deviation
0.00
–0.50
%
PLL loop bandwidth(4)
2
Phase angle
MHz
–0 . 0 3 1
degrees
Notes:
1. Static Phase offset does not include Jitter.
2. The Output Skew Rate is calculated by using the load shown in Figure 3.
3. VOX specified at the DRAM clock input or the test load in Figure 2.
4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
08-0298
7
PS8683D
10/06/08
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
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AC Specifications for PC3200
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)( See Figure 1 & 2 )
Parame te r
De s cription
AVDD, VDDQ = 2.6V ±0.1V
Diagram
M in.
Nom.
Units
M ax
tjit(cc)
Cycle- to- cycle jitter
Figure 4
–50
50
t(θ)
Static phase offset(1)
Figure 5
–50
tsk(o)
Output clock skew
Figure 6
tjit(per)
Period jitter
Figure 7
–50
50
tjit(hper)
Half- period jitter
Figure 8
–75
75
tsl(i)
Input clock slew rate
Figure 9
1.0
4.0
tsl(o)
Output clock slew rate(2)
Figure 9
1.0
2 .0
VOX
Output differential- pair cross- voltage
(VDDQ/2) –0.1
(VDDQ/2) +0.1
0
50
ps
75
V/ns
V
The PLL is capable of meeting all the above parameters while supporting SSC synthesizers with the following parameters
SSC modulation frequency
3 0 . 00
50.00
kHz
SSC clock input frequency deviation
0.00
–0.50
%
PLL loop bandwidth(4)
2
Phase angle
MHz
–0.031
degrees
Notes:
1. Static Phase offset does not include Jitter.
2. The Output Skew Rate is calculated by using the load shown in Figure 3.
3. VOX specified at the DRAM clock input or the test load in Figure 2.
4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
08-0298
8
PS8683D
10/06/08
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
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VDD
VCLK
R=60-Ohms
R=60-Ohms
VDD/2
VCLK
Figure 1. IBIS Model Output Load
VDDQ
C=14pF
Z=60-Ohms
R=120-Ohms
Z=60-Ohms
R=1M-Ohms
C=1pF
GND
C=14pF
R=1M-Ohms
C=1pF
GND
PROBE
GND
Figure 2. Output Load Test Circuit 1
08-0298
9
PS8683D
10/06/08
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
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VDD/2
C=14pF
–VDD/2
Z=60-Ohms
Z=50-Ohms
R=10-Ohms
Z=60-Ohms
R=50-Ohms
Z=50-Ohms
VTT
R=10-Ohms
R=50-Ohms
C=14pF
VTT
–VDD/2
Scope
VTT = GND
–VDD/2
Figure 3. Output Load Test Circuit 2
08-0298
10
PS8683D
10/06/08
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
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Yx,FBOUT
Yx,FBOUT
t cycle n
t cycle n+1
t jit(cc) = t cycle n - t cycle n+1
Figure 4. Cycle-to-Cycle Jitter
CLK
CLK
FBIN
FBIN
t(
t(
)n
) n+1
n=N
t
=
∑ 1 t(
)n
N
(N > 1000 samples)
Figure 5. Static Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
t sk(o)
Figure 6. Output Skew
08-0298
11
PS8683D
10/06/08
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
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Yx, FBOUT
Yx, FBOUT
t cycle n
Yx, FBOUT
Yx, FBOUT
1
fO
t jit(per) = t cycle n
1
fO
(f O = input frequency measured at CLK, CLK)
Figure 7. Period Jitter
Yx, FBOUT
Yx, FBOUT
t n+1
half period
t half period n
1
fO
t jit(hper) = t half period n
1
2*f O
Figure 8. Half-Period Jitter
80%
80%
Clock Inputs
and Outputs
V ID , V OD
20%
20%
t r(i), t r(o)
t slr(i/o) =
t f(i), t f(o)
t slf(i/o) =
t r(i/o)
t f(i/o)
Figure 9. Input and Output Slew Rates
08-0298
12
PS8683D
10/06/08
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
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Packaging Mechanical: 48-Pin TSSOP (A)
DOCUMENT CONTROL NO.
PD - 1501
48
REVISION: G
DATE: 03/09/05
.236
.244
6.0
6.2
See Note 4
1
.488 12.4
.496 12.6
See Note 3
.047
1.20 Max
SEATING PLANE
1
.004 0.09
.008 0.20
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
.002
.006
0.05
0.15
.007
.010
.0197
BSC
0.50
0.17
0.27
Note:
1. Controlling dimensions in millimeters.
2. Ref: JEDEC MO-153F/ED
3. Dimension does not include mold Àash, protrusions or gate burrs. Mold Àash, protrusions and gate burrs shall not exceed 0.15mm per side.
4. Dimension does not include interlead Àash or protrusion. Interlead Àash or protrusion
shall not exceed 0.25mm per side.
0.45 .018
0.75 .030
.319
BSC
8.1
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
DESCRIPTION: 48-Pin 240-Mil Wide TSSOP
PACKAGE CODE: A
Ordering Information
Orde ring Code
Package Code
Pin Count - Package Type
PI6CVF857A
A
48- pin TSSOP
PI6CVF857AE
A
Pb- free & Green, 48- pin TSSOP
Notes:
1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/
Pericom Semiconductor Corporation • 1-800-435-2336 • http://www.pericom.com
08-0298
13
PS8683D
10/06/08