PI6C49S1506 High Performance Differential Fanout Buffer Features Description ÎÎ6 differential outputs with 2 banks The PI6C49S1506 is a high performance fanout buffer devicewhich supports up to 1.5GHz frequency. It also integrates a unique feature with user configurable output signaling standards on per bank basis which provide great flexibilities to users. The device also uses Pericom's proprietary input detection technique to make sure illegal input conditions will be detected and reflected by output states. This device is ideal for systems that need to distribute low jitter clock signals to multiple destinations. ÎÎUser configurable output signaling standard for each bank: LVDS or LVPECL or HCSL ÎÎUp to 1.5GHz output frequency for differential outputs ÎÎUltra low additive phase jitter: < 0.03 ps (typ) (differential 156.25MHz, 12KHz to 20MHz integration range) ÎÎSelectable reference inputs support either single-ended or differential or Xtal ÎÎLow skew between outputs within banks (<40ps) ÎÎLow delay from input to output (Tpd typ. 1.5ns) Applications ÎÎSeparate Input output supply voltage for level shifting ÎÎNetworking systems including switches and Routers ÎÎ2.5V / 3.3V power supply ÎÎHigh frequency backplane based computing and telecom platforms ÎÎIndustrial temperature support ÎÎTQFP-32 package Pin Configuration (32-Pin TQFP) Block Diagram QB0 nQB0 OPMODEB1 OPMODEB0 28 27 26 25 24 VDDO 2 23 QB1 QA1 3 22 nQB1 VEE 4 21 VDDO nQA0 5 20 QB2 14 15 16 nCLK1 VDD VEE IREF CLK1 17 nCLK0 8 13 CLK_SEL1 VEE 12 nQB2 18 CLK0 19 7 XTN 6 11 QA0 CLK_SEL0 10 1 1 nQA1 XT 14-0121 VDDO 9 Iref 29 CLK_SEL[1:0] nQA2 3 CLK1 nCLK1 30 QB[0:2] QA2 OPMODEB[1:0] 31 OSC CLK0 nCLK0 OPMODEA1 XT XTN 32 QA[0:2] 3 OPMODEA0 OPMODEA[1:0] PI6C49S1506 Rev C 08/11/14 PI6C49S1506 High Performance Differential Fanout Buffer Pinout Table Pin # Pin Name 1, 21, 24 VDDO nQA1 2,3 QA1 4, 16 VEE nQA0 5, 6 QA0 Type Description Power Power supply pins for outputs Output Bank A differential output pair 1. Pin selectable LVPECL/LVDS/HCSL interface levels. Power Connect to Negative power supply Output Bank A differential output pair 0. Pin selectable LVPECL/LVDS/HCSL interface levels. 7 CLK_SEL0 Input Input clock source selection 8 VEE Power Negative power supply 9 XT Input XTAL input 10 XTN Output XTAL output CLK0 Input Differential clock input nCLK0 Input Differential clock input CLK1 Input Differential clock input nCLK1 Input Differential clock input 15 VDD Power Power supply pins for device core 17 IREF Output Reference current 18 CLK_SEL1 Input Input clock source selection Output Bank B differential output pair 5. Pin selectable LVPECL/LVDS/HCSL interface levels. Output Bank B differential output pair 4. Pin selectable LVPECL/LVDS/HCSL interface levels. 11, 12 13, 14 QB2 19, 20 nQB2 nQB1 22, 23 QB1 25 OPMODEB0 Input Bank B output selection pin 26 OPMODEB1 Input Bank B output selection pin Output Bank B differential output pair 3. Pin selectable LVPECL/LVDS/HCSL interface levels. Output Bank A differential output pair 2. Pin selectable LVPECL/LVDS/HCSL interface levels. nQB0 27, 28 QB0 nQA2 29, 30 QA2 31 OPMODEA1 Input Bank A output selection pin 32 OPMODEA0 Input Bank A output selection pin 14-0121 2 PI6C49S1506 Rev C 08/11/14 PI6C49S1506 High Performance Differential Fanout Buffer Function Table Table 1: Input select function CLK_SEL [1] CLK_SEL [0] Function 0 0 XTAL is the selected input 0 1 CLK0 is the selected reference input 1 X CLK1 is the selected reference input Table 2: Output Mode select function OPMODEA/B [1] OPMODEA/B [0] Output Bank A / Bank B Mode 0 0 LVPECL 0 1 LVDS 1 0 HCSL 1 1 Hi-Z 14-0121 3 PI6C49S1506 Rev C 08/11/14 PI6C49S1506 High Performance Differential Fanout Buffer Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested) Storage temperature....................................................-55 to +150ºC Supply Voltage to Ground Potential (VDD)........... -0.5 to +4.6V Inputs (Referenced to GND)............................-0.5 to VDD+0.5V Clock Output (Referenced to GND)...............-0.5 to VDD+0.5V Soldering Temperature (Max of 10 seconds).....................+260ºC Latch up...................................................................................200mA ESD Protection (Input)................................... 2000 V min (HBM) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Power Supply Characteristics and Operating Conditions Symbol Parameter VDD Core Supply Voltage VDDO Output Supply Voltage IDD Core Power Supply Current Output Power Supply Current IDDO Test Condition Typ. Max. Units 3.135 3.465 V 2.375 2.625 V 3.135 3.465 V 2.375 2.625 V 70 All LVPECL outputs unloaded 75 All LVDS outputs loaded 85 All HCSL outputs unloaded 55 Ambient Operating Temperature TA Min. -40 mA 85 °C Max. Units 150 uA DC Electrical Specifications - Differential Inputs Symbol Parameter IIH Input High current Input = VDD IIL Input Low current Input = GND CIN Input capacitance VIH Input high voltage VIL Input low voltage -0.3 VPk-Pk Input Differential Amplitude PK-PK 0.15 1.3 V VCM Common model input voltage GND + 0.5 VDD -0.85 V 14-0121 Min. Typ. -150 uA 3 PF VDD+0.3 4 V V PI6C49S1506 Rev C 08/11/14 PI6C49S1506 High Performance Differential Fanout Buffer DC Electrical Specifications - LVCMOS Inputs Symbol Parameter Conditions Min. Typ. Max. Units IIH Input High current Input = VDD 150 uA IIL Input Low current Input = GND -150 VIH Input high voltage VDD =3.3V 2.0 VDD+0.3 V VIL Input low voltage VDD =3.3V -0.3 0.8 V VIH Input high voltage VDD =2.5V 1.7 VDD+0.3 V VIL Input low voltage VDD =2.5V -0.3 0.7 V uA DC Electrical Specifications- LVPECL Outputs Parameter Description VOH Output High voltage VOL Output Low voltage Conditions Min. Typ. Max. VDD =3.3V 2.1 2.6 VDD =2.5V 1.3 1.6 VDD =3.3V 1.3 1.8 VDD =2.5V 0.5 0.8 Units V V DC Electrical Specifications- LVDS Outputs Parameter Description VOH Output High voltage 1.433 V VOL Output Low voltage 1.064 V Vocm Output common mode voltage 1.25 V DVocm Change in Vocm between output states Ro Output impedance 14-0121 Conditions Min. Typ. 85 5 PI6C49S1506 Max. Units 55 mV 140 W Rev C 08/11/14 PI6C49S1506 High Performance Differential Fanout Buffer DC Electrical Specifications- HCSL Outputs Parameter Description VOH Output High voltage VOL Output Low voltage Conditions Min. Typ. 520 800 0 Max. Units mV 150 mV AC Electrical Specifications – Differential Outputs Parameter Description FOUT Clock output frequency Tr Output rise time From 20% to 80% 150 ps Tf Output fall time From 80% to 20% 150 ps TODC Output duty cycle Frequency<650MHz, LVPECL input 48 LVPECL outputs 400 LVDS outputs, <650MHz 250 HCSL outputs 520 Output swing Single-ended VPP Buffer additive jitter RMS Tj Conditions Min. Typ. Max. LVPECL, LVDS 1500 HCSL 250 52 Units MHz % mV LVPECL and LVDS outputs 0.03 0.06 ps HCSL outputs 0.06 0.09 ps 460 mV 140 mV VCROSS Absolute crossing voltage HCSL 160 DVCROSS Total variation of crossing voltage HCSL TSK Output Skew 6 outputs devices, outputs in same bank, with same load, at DUT. TPD 40 ps Propagation Delay 1500 ps TOD Valid to HiZ 3 200 ns TOE HiZ to valid 22 200 ns 14-0121 6 PI6C49S1506 Rev C 08/11/14 PI6C49S1506 High Performance Differential Fanout Buffer Phase Noise Plot fOUT = 156.25MHz Additive jitter = √(Output jitter2 - Input jitter2) = 30fs 14-0121 7 PI6C49S1506 Rev C 08/11/14 PI6C49S1506 High Performance Differential Fanout Buffer Output Skew Propagation Delay Output Skew TSK Propagation Delay TPD VOH CLK/nCLK CLK/ nCLK TPLH TPHL QA/QB VOH TPLHx TPHLx QAn/QBn QAn+1/QBn+1 VOH VOL TPLHy TSK = TPLH2 - TPLH1 or TSK = TPHL2 - TPHL1 14-0121 TSK TSK TF VOH VOL VOL TR VOL TPHLy TSK = TPLHy - TPLHx or TSK = TPHLy - TPHLx 8 PI6C49S1506 Rev C 08/11/14 PI6C49S1506 High Performance Differential Fanout Buffer Configuration Test Load Board Termination for HCSL outputs Rs 33 Ω 5% PI6C49S1506 475Ω 1% Clock TLA Rs 33Ω 5% Rp 49.9Ω 1% Clock# TLB Rp 49.9Ω 1% 2pF 5% 2pF 5% Configuration Test Load Board Termination for LVPECL/ LVDS 14-0121 9 PI6C49S1506 Rev C 08/11/14 PI6C49S1506 High Performance Differential Fanout Buffer Application Information Wiring the differential input (Use CLK0) to accept single ended levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609. VDD R1 Single Ended Clock Input 1K CLK /CLK C1 0.1µ R2 1K Figure 1. Single-ended input to Differential input device Power Supply Filtering Techniques As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. All power pins should be individually connected to the power supply plane through vias, and 0.1μF an 1μF bypass capacitors should be used for each pin. VDD VDD 0.1µF 1µF VDDO VDDO 0.1µF 14-0121 10 1µF PI6C49S1506 Rev C 08/11/14 PI6C49S1506 High Performance Differential Fanout Buffer Driving X1 with a Single Ended Input Rs CMOS Clock 0.1µF Single Ended Input, AC couple Osc Input 50Ω Rs CMOS Clock X1 50Ω 0.1µF 0.1µF 50Ω X2 0.1µF Single Ended Input, DC couple Clock IC crystal input guide Clock IC Rs CMOS Clock Differential Clock Input 50Ω Rf 0.1µF 50Ω VDD Differential Clock Input 50Ω C_in C_out XTL_IN XTL_OUT Cb 0.1µF Crystal (CL) C1 Cb C2 LVPECL, DC Couple, Thevenin Equivalent LVPECL, AC Couple, Thevenin Equivalent VDDO VDDO QAn+/ QBn+ LVPECL Driver QAn-/ QBn- RPU 0.1µF RT 100Ω Differential VDDO RPD 0.1µF LVPECL Driver LVPECL Receiver 100Ω Differential VDDO RPD LVPECL Receiver RPU RPU QAn-/ QBn- RT RPD VDDO RT VDDO RPU RPD RPU RPD 2.5V 91Ω RPD 3.3V 120Ω 82Ω 3.3V 160Ω 120Ω 82Ω 14-0121 RPU QAn+/ QBn+ 2.5V 250Ω 62.5Ω 250Ω 62.5Ω 11 PI6C49S1506 Rev C 08/11/14 PI6C49S1506 High Performance Differential Fanout Buffer LVDS DC Couple LVDS AC Couple at Load 0.1µF QAn+/ QBn+ QAn+/ QBn+ LVDS Driver 100Ω Differential 100Ω LVDS Receiver kΩ LVDS Driver QAn-/ QBn- 100Ω Differential kΩ QAn-/ QBn- LVDS AC Couple with Internal Termination Vbias 100Ω 0.1µF Single Ended LVPECL, DC Couple VDDO - 2V QAn+/ QBn+ 0.1µF 50Ω QAn+/ QBn+ 50Ω LVDS Driver 100Ω 100Ω Differential LVPECL Driver Vbias 50Ω QAn-/ QBn- 50Ω 0.1µF QAn-/ QBn- Single Ended LVPECL, DC Couple, Thevenin Equivalent VDDO - 2V 50Ω Single Ended LVPECL, AC Couple, Thevenin Equivalent VDDO - 2V RPU QAn+/ QBn+ LVPECL Driver QAn+/ QBn+ VDDO LVPECL Driver RPD VDDO RPU RPD RPU 3.3V 120Ω 82Ω 14-0121 QAn-/ QBn- RPD 12 Load 50Ω 50Ω 2.5V 250Ω 62.5Ω QAn-/ QBn- 0.1µF RT 50Ω 0.1µF VDDO RT 3.3V 160Ω RT 50Ω 2.5V PI6C49S1506 91Ω Rev C 08/11/14 PI6C49S1506 High Performance Differential Fanout Buffer Clock IC Crystal loading cap. design guide Clock IC Rf CL =crystal spec. loading cap. C_in C_in/out = (3~5pF) of IC pin cap. C_out XTL_IN XTL_OUT Cb Cb = PCB trace (2~4pF) C1,C2 = load cap. of design Crystal (CL) C1 Cb Rd = 50 to 100ohm drive level limit C2 Design guide: C1=C2=2 *CL - (Cb +C_in/out) to meet target +/-ppm < 20 ppm Example1: Select CL=18 pF crystal, C1=C2=2*(18pF) – (4pF+5pF)=27pF, check datasheet too Example2: For higher frequency crystal (=>20MHz), can use formula C1=C2=2*(CL-6), can do fine tune of C1, C2 for more accurate ppm if necessary 14-0121 13 PI6C49S1506 Rev C 08/11/14 PI6C49S1506 High Performance Differential Fanout Buffer Packaging Mechanical: DOCUMENT CONTROL NO. PD - 1814 9.00 BSC .354 Square REVISION: C DATE: 03/09/05 Square 7.00 BSC 0.09 0.20 .004 .008 GAUGE PLANE 0.25 mm .276 1 1.20 Max. .047 0° 7° 0.45 .018 0.75 .030 1.00 REF .039 .004 0.10 Seating Plane 0.30 .012 0.45 .018 0.80 BSC .032 0.05 0.15 .002 .006 0.95 1.05 .037 .041 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Notes: 1. Controlling dimensions in millimeters 2. Ref.: JEDEC MS-026D/ABA 3. Package Outline Exclusive of Mold Flash and Metal Burr DESCRIPTION: 32-Pin, Thin Quad Flat Package, TQFP PACKAGE CODE: FA Ordering Code Package Code Package Type Operating Temperature PI6C49S1506FAIE FA Pb-free & Green, 32-pin TQFP -40 °C to 85 °C Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. “E” denotes Pb-free and Green 3. Adding an “X” at the end of the ordering code denotes tape and Reel packaging 14-0121 14 PI6C49S1506 Rev C 08/11/14