PI6ULS5V9515A ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| I2C Bus/SMBus Repeater drivers on and off. This can be used to isolate a badly behaved slave on power-up until after the system powerup reset. It should never change state during an I2C-bus operation because disabling during a bus operation will hang the bus and enabling part way through a bus cycle could confuse the I2C-bus parts being enabled. The enable pin should only change state when the global bus and the repeater port are in an idle state to prevent system failures. The output low levels for sides are approximately 0.5 V, but the input voltage of each internal buffer must be 70 mV lower (0.43V) or even more lower. When the output internally is driven low the low is not recognized as a low by the input.. This prevents a lockup condition from occurring when the input low condition is released. Two or more PI6ULS5V9515A devices can’t be used in series. The PI6ULS5V9515A design does not allow this configuration. Since there is no direction pin, slightly different valid low-voltage levels are used to avoid lockup conditions between the input and the output of each repeater. A valid low applied at the input of a PI6ULS5V9515A will be propagated as a buffered low with a slightly higher value on the output. When this buffered low is applied to another PI6ULS5V9515Atype device in series, the second device does not recognize it as a valid low and will not propagate it as a buffered low again. The device contains a power-up control circuit that sets an internal latch to prevent the output circuits from becoming active until Vcc is at a valid level (Vcc = 2.3 V). As with the standard I2C system, pull-up resistors are required to provide the logic-high levels on the buffered bus. The PI6ULS5V9515A has standard open-collector configuration of the I2C bus. The size of these pull-up resistors depends on the system, but each side of the repeater must have a pull-up resistor. The device is designed to work with Standard mode and Fast mode I2C devices in addition to SMBus devices. Standard mode I2C devices only specify 3mA in a generic I2C system, where Standard mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used. Features 2 channel, bidirectional buffer I2C-bus and SMBus compatible Operating supply voltage range of 2.3 V to 3.6 V Active HIGH repeater enable input Open-drain input/outputs Lock-up free operation Supports arbitration and clock stretching across the repeater Accommodates Standard-mode and Fast-mode I2Cbus devices and multiple masters Powered-off high-impedance I2C-bus pins 5.5 V tolerant I2C-bus and enable pins 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater) ESD protection exceeds 4KV HBM per JESD22A114 Package: MSOP-8, SOIC-8 and DFN2x3-8L Description The PI6ULS5V9515A is a CMOS integrated circuit intended for I2C bus and SMBus systems applications. The device contains two identical bidirectional opendrain buffer circuits that enable I2C and similar bus systems to be extended without degradation of system performance. The PI6ULS5V9515A enables the system designer to isolate two halves of a bus for both voltage and capacitance, accommodating more I2C devices or longer trace length. It also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus allowing two buses of 400 pF to be connected in an I2C application. The PI6ULS5V9515A has an EN pin to turn the 12-12-0001 PT0455-2 1 12/18/12 PI6ULS5V9515A I C-Bus/SMBus Repeater 2 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Pin Configuration MSOP-8 and SOIC-8 TDFN2x3-8L(Top View) Pin Description Pin No 1 2 3 4 5 6 7 8 Name n.c. SCL0 SDA0 GND EN SDA1 SCL1 VCC Description Not connected serial clock port 0 bus serial data port 0 bus supply ground (0 V) active HIGH repeater enable input serial data port 1 bus serial clock port 1 bus supply voltage (2.3 V to 3.6 V) Block Diagram EN H L Function SCL0 = SCL1; SDA0 = SDA1; disabled Figure 1:Block Diagram 12-12-0001 PT0455-2 2 12/18/12 PI6ULS5V9515A I C-Bus/SMBus Repeater 2 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Maximum Ratings Storage Temperature ................................................................................... -55oC to +125oC DC Input Voltage .............................................................................................-0.5V to +6.0V Control Input Votage(EN) ...............................................................................-0.5V to+6.0V Total Power Dissipation................................................................... 100mA Input/Output Current (portA&B) ......................................................... 50mA Input Current (EN, VCC(A), VCC(B), GND)............................................ 50mA ESD: HBM Mode...........................................................................................................4000V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended operation conditions VCC = 2.3 V to 3.6 V; GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified Symbol Parameter Vcc supply voltage port ICCH HIGH-level supply current ICCL ICCLC LOW-level supply current contention port A supply current Test Conditions - Min. Typ. Max. Unit 2.3 - 3.6 V - 0.5 5 mA - 0.5 5 mA - 1.6 5 mA - 1.7 5 mA - 1.6 5 mA both channels HIGH;; SDAn = SCLn = VCC VCC = 2.7 V both channels HIGH;; SDAn = SCLn = VCC VCC = 3.6 V both channels LOW; VCC = 2.7 V; one SDA and one SCL = GND; other SDA and SCL open both channels LOW; VCC = 3.6 V; one SDA and one SCL = GND; other SDA and SCL open VCC = 2.7V or 3.6V; SDAn = SCLn = GND DC Electrical Characteristics VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified Parameter Test Conditions(1) Description Input and output SDAn and SCLn VIH HIGH-level input voltage VIL (1) LOW-level input voltage VILc Contention LOW-level input voltage - Min. Typ.(2) Max. Unit 0.7VCC -0.5 -0.5 0.4 5.5 +0.3Vcc - V VIK Input clamping voltage II = -18 mA - - -1.2 V ILI Input leakage current VI = 3.6 V - - ±1 μA - - 10 μA - - 5 μA 0.47 0.52 0.6 V guaranteed by design - 70 - mV VI = 3 V or 0 V - 6 - pF 2.0 -0.5 -1 - -10 6 5.5 +0.8 -30 +1 - V V μA μA pF IIL VOL VOL-VILc Cio Vcc=2.3-2.7V ; SDA, SCL; VI = 0.2 V Vcc=3.0-3.6V ; SDA, SCL; VI = 0.2 V IOL = 20 μA or 6 mA LOW-level input current LOW-level output voltage Difference between LOW-level output and LOWlevel input voltage contention input/output capacitance Enable VIH VIL IIL ILI Ci HIGH-level input voltage LOW-level input voltage LOW-level input current Input leakage current Input capacitance VI = 0.2 V VI=Vcc VI = 3.0 V or 0 V Notes: 1 VIL specification is for the first LOW level seen by the SDAB/SCLB lines. V ILc is for the second and subsequent LOW levels seen by the SDAn/SCLn lines. 12-12-0001 PT0455-2 3 12/18/12 PI6ULS5V9515A I C-Bus/SMBus Repeater 2 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Dynamic characteristics GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol (1)(2) Parameter Vcc=2.3-2.7V tPLH LOW-to-HIGH propagation delay tPHL HIGH-to-LOW propagation delay tTLH LOW-to-HIGH transition time tTHL HIGH-to-LOW transition time tSU Set-up time tH Hold time Vcc=3.0-3.6V tPLH LOW-to-HIGH propagation delay tPHL HIGH-to-LOW propagation delay tTLH LOW-to-HIGH transition time tTHL HIGH-to-LOW transition time tSU Set-up time tH Hold time Test Conditions Min. Typ. Max. Unit - 33 45 100 130 113 82 148 57 - 190 130 - ns ns ns ns ns ns - 33 45 100 100 102 68 147 58 - 180 120 - ns ns ns ns ns ns Notes: (1) Typical values taken at VCC = 3.3 V and Tamb = 25C. (2) Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times. Figure 2: Propagation Delay and Transition Times Figure 3: Test Circuit 12-12-0001 PT0455-2 4 12/18/12 PI6ULS5V9515A I C-Bus/SMBus Repeater 2 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Functional Description The PI6ULS5V9515A is a CMOS integrated circuit intended for I2C bus and SMBus systems applications. The device contains two identical bidirectional open-drain buffer circuits that enable I2C and similar bus systems to be extended without degradation of system performance. The PI6ULS5V9515A enables the system designer to isolate two halves of a bus for both voltage and capacitance., accommodating more I2C devices or longer trace length. It also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus allowing two buses of 400 pF to be connected in an I2C application. The PI6ULS5V9515A has an EN pin to turn the drivers on and off. This can be used to isolate a badly behaved slave on power-up until after the system power-up reset. It should never change state during an I2C-bus operation because disabling during a bus operation will hang the bus and enabling part way through a bus cycle could confuse the I 2C-bus parts being enabled. The enable pin should only change state when the global bus and the repeater port are in an idle state to prevent system failures. The output low levels for sides are approximately 0.5 V, but the input voltage of each internal buffer must be 70 mV lower (0.43V) or even more lower. When the output internally is driven low he low is not recognized as a low by the input.. This prevents a lockup condition from occurring when the input low condition is released. Two or more PI6ULS5V9515A devices can’t be used in series. The PI6ULS5V9515A design does not allow this configuration. Since there is no direction pin, slightly different valid low-voltage levels are used to avoid lockup conditions between the input and the output of each repeater. A valid low applied at the input of a PI6ULS5V9515A will be propagated as a buffered low with a slightly higher value on the output. When this buffered low is applied to another PI6ULS5V9515A-type device in series, the second device does not recognize it as a valid low and will not propagate it as a buffered low again. The device contains a power-up control circuit that sets an internal latch to prevent the output circuits from becoming active until Vcc is at a valid level (Vcc = 2.3 V). As with the standard I2C system, pull-up resistors are required to provide the logic-high levels on the buffered bus. The PI6ULS5V9515A has standard open-collector configuration of the I2C bus. The size of these pull-up resistors depends on the system, but each side of the repeater must have a pull-up resistor. The device is designed to work with Standard mode and Fast mode I2C devices in addition to SMBus devices. Standard mode I 2C devices only specify 3 mA in a generic I2C system, where Standard mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used. Application Information A typical application is shown in Figure 4. In this example, the system master is running on a 3.3 V I2C-bus while the slave is connected to a 5V bus. Both buses run at 400 kHz. Master devices can be placed on either bus. The PI6ULS5V9515A is 5V tolerant, so it does not require any additional circuitry to translate between different bus voltages. When one side of the PI6ULS5V9515A is pulled LOW by a device on the I2C-bus, a CMOS hysteresis type input detects the falling edge and causes the internal driver on the other side to turn on, thus causing the other side to also go LOW. The side driven LOW by the PI6ULS5V9515A will typically be at VOL = 0.5 V. Figure 5 and Figure 6 show the waveforms that are seen in a typical application. If the bus master in Figure4 writes to the slave through the PI6ULS5V9515A, Bus 0 has the waveform shown in Figure 5. This looks like a normal I2C transmission until the falling edge of the eighth clock pulse. At that point, the master releases the data line (SDA) while the slave pulls it low through the PI6ULS5V9515A. Because the VOL of the PI6ULS5V9515A typically is around 0.5V, a step in the SDA is seen. After the master has transmitted the ninth clock pulse, the slave releases the data line. On the Bus 1 side of the PI6ULS5V9515A, the clock and data lines have a positive offset from ground equal to the VOL of the PI6ULS5V9515A. After the eighth clock pulse, the data line is pulled to the VOL of the slave device, which is very close to ground in the example. It is important to note that any arbitration or clock-stretching events on Bus 1 require that the VOL of the devices on Bus 1 be 70 mV below the VOL of the PI6ULS5V9515A (see VOL - VILC in Electrical Characteristics) to be recognized by the PI6ULS5V9515A and transmitted to Bus 0. 12-12-0001 PT0455-2 5 12/18/12 PI6ULS5V9515A I C-Bus/SMBus Repeater 2 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| PI6ULS5V9515A Figure 4: Typical Application VOL of PI6ULS5V9515A Figure 5: Bus 0 Waveforms VOL of PI6ULS5V9515A Figure 6: Bus 1 Waveforms 12-12-0001 PT0455-2 6 12/18/12 PI6ULS5V9515A I C-Bus/SMBus Repeater 2 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Mechanical Information MSOP-8 Symbol A A1 A2 b c D E E1 e L θ Note: 1) Controlling dimensions in millimeters. 2) Ref : JEDEC MO-187E/BA 12-12-0001 Dimensions In Millimeters Min Max 0.82 1.10 0.02 0.15 0.75 0.95 0.25 0.38 0.09 0.23 2.90 3.10 2.90 3.10 4.75 5.05 0.65 BSC 0.40 0.80 0° 6° PT0455-2 7 12/18/12 PI6ULS5V9515A I C-Bus/SMBus Repeater 2 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| SOIC-8 Symbol A A1 A2 b c D E E1 e L θ Note: 1) Controlling dimensions in millimeters. 2) Ref : JEDEC MS-012E/AA 12-12-0001 Dimensions In Millimeters Min Max 1.350 1.750 0.100 0.250 1.350 1.550 0.330 0.510 0.170 0.250 4.700 5.100 3.800 4.000 5.800 6.200 1.27 BSC 0.400 1.270 0° 8° PT0455-2 8 12/18/12 PI6ULS5V9515A I C-Bus/SMBus Repeater 2 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| TDFN2x3-8L PKG. DIMENSIONS(MM) SYMBOL MIN. MAX A 0.70 0.80 A1 0.00 0.50 0.20REF A3 D 1.92 2.08 E 2.92 3.07 D1 1.40 1.60 E1 1.40 1.60 0.20MIN k b 0.20 0.30 e 0.50TYP L 0.22 0.38 Note: Ref: JEDEC MO-229 Ordering Information Part No. Package Code Package PI6ULS5V9515AUE U Lead free and Green 8-pin MSOP PI6ULS5V9515AWE W Lead free and Green 8-pin SOIC PI6ULS5V9515AZEE ZE Lead free and Green 8 TDFN2x3-8L Note: E = Pb-free Adding X Suffix= Tape/Reel Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom. 12-12-0001 PT0455-2 9 12/18/12