PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Product Features
Product Description
• External quartz oscillator 32.000kHz and 32.768kHz
selectable.
• Supports I2C-Bus's high speed mode (400 kHz)
• Includes time (Hour/Minute/Second) and calendar
(Year/Month/Date/Day) counter functions (BCD
code)
• Select between 12-hr and 24-hr clock display
• Auto calculation of leap years until 2099
• Built-in high-precision clock precision control logic
• Interrupt generation function (cycle time range: 1
month to 0.5 seconds, includes interrupt flags and
interrupt stop function)
• Alarm functions (Alarm_A: Day/Hour/Min)
• 32-kHz clock output (/INTB output)
• Oscillation stop detection function (used to determine
presence of internal data)
PT7C4372A/C are I2C bus interface-compliant real-time
clocks that have been adjusted for high precision. In
addition to providing a function for generating six types
of interrupts, a dual alarm function, an oscillation stop
detection function (used to determine presence of valid
internal data at power-on), they includes a digital clock
precision adjustment function that can be used to set
various levels of precision.
Since the internal oscillation circuit is driven at a
constant voltage, 32-kHz clock output is stable and free
of voltage fluctuation effects.
Table 1 shows the diverse functions of the two RTC
circuits. More details are shown in section Overview of
Functions.
• Wide Time keeping voltage range: 1.3 V to 6 V
• Wide interface voltage range: 1.8 V to 6 V
• Low current consumption: 0.4 µA/3.0 V (Typ.)
Table 1. Diverse functions of RTC circuits
Item
Function
PT7C4372A/4372C
1
Clock
2
Clock adjustment
Unit 3.051ppm for 32.768kHz crystal;
3.125ppm for 32.000kHz crystal
3
Period interrupt
Output from /INTA and /INTB
4
Alarm
/INTA: Alarm_A; /INTB: Alarm_B
5
Oscillation detect
32-kHz clock output
via /INTB enabled by register
7
I C bus interface with CPU
8
Crystal
External, 32.768kHz or 32.000kHz selectable
6
2
12-07-0001
PT0150-8
1
07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Pin Assignment
PT7C4372A/C
1
INTB
Vcc
2
SCL
OSCIN
7
3
SDA
OSCOUT
6
4
GND
INTA
5
8
8 pin TSSOP
8 pin SOIC
Pin Description
Pin No
Pin
Name
Type
1
/INTB
O
Interrupt B (Open Drain). It outputs alarm interrupts and periodic interrupts.
2
SCL
I
Serial Clock Line. It is for I2C communication. Data input and output across SDA pin is
synchronized with this clock. Up to 6V beyond Vcc may be input.
Serial Data Line (Open Drain output). This line is for transferring I2C bus format data.
When input, up to 6V beyond VCC may be used. When output, it is an open drain output
pin.
Description
3
SDA
I/O
4
GND
P
Ground
5
/INTA
O
Interrupt A (Open Drain). It outputs alarm interrupts and periodic interrupts.
6
OSCOUT
O
Oscillator Circuit Output. Together with OSCIN, an crystal oscillator is connected
between them.
7
OSCIN
I
Oscillator Circuit Input. See OSCOUT pin description.
8
Vcc
P
Power
12-07-0001
PT0150-8
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07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Function Block
Comparator_A
Alarm_A Register
(Week,Min,Hour)
Comparator_B
Alarm_B Register
(WEEK,MIN,HOUR)
32kHz Output Control
FOUT
(PT7C4372B only)
OSCIN
CG
OSCOUT
Divider
Correction
OSC
Time Counter
(Sec,Min,Hour,Day,Date,Month,Year)
Div
CD
Address
Decoder
OSC
Detect
/INTA
Address
Register
SCL
I /O
Control
Interrupt Control
Shift Register
SDA
/INTB
(PT7C4372A/C only)
Maximum Ratings
Storage Temperature............................................................................................................... -65oC to +150oC
Ambient Temperature with Power Applied ...................................................................... -40oC to +85oC
Supply Voltage to Ground Potential (Vcc to GND) ......................................................-0.3V to +6.5V
DC Input (All Other Inputs except Vcc & GND) ...........................................................-0.3V to (Vcc+0.3V)
DC Output Voltage (SDA, /INTA, /INTB pins).............................................................. -0.3V to +6.5V
DC Output Current (FOUT) ................................................................................................. -0.3V to (Vcc+0.3V)
Power Dissipation.................................................................................................................... 320mW (depend on package)
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
Symbol
Description
Min
Type
Max
VCC
Power voltage
1.8
-
6
VOSC
Timekeeping voltage
1.3
-
5.5
VPUP
Applied voltage when OFF (SCL, SDA, /INTA, /INTB pins)
-0.3
-
5.5
Operating temperature
-40
-
85
TA
12-07-0001
PT0150-8
3
Unit
V
ºC
07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Frequency Characteristics
Symbol
Description
f / f
Frequency tolerance
Frequency voltage
characteristics
Frequency temperature
characteristics
f/V
Top
tSTA
Oscillation start up time
fa
Aging
Conditions
TA = +25°C
Vcc = 3.0 V
TA = +25°C
Vcc = 2 V to 5 V
TA = -10°C to +70°C,
Vcc = 3.0 V; +25°C reference
TA = +25°C
Vcc = 3 V
TA = +25°C
VCC=3.0 V; first year
Rating
Unit
Stability AC: 0 ±5
10 -6
±2 Max.
10 -6 / V
+10 / -120
10 -6
3 Max.
s
±5 Max.
10 -6 / year
DC Electrical Characteristics
Unless otherwise specified, GND = 0 V, VCC = 3 V, TA = -40 °C to +85 °C
Sym.
Item
Pin
ICC1
ICC2
Current consumption
Vcc
ICC3
VIL
VIH
Low-level input voltage
High-level input voltage
IOL
Low-level output current
IIL
Input leakage current
IOZ
Output current when OFF
SCL, SDA,
FOE
/INTA,/INTB
SDA
SCL
SDA,
/INTA,/INTB
Conditions
Interface is active at 400kHz
Interface is inactive, enable 32768Hz
SQW wave output
Interface is inactive, disable 32768Hz
SQW wave output
VOL = 0.4
VOL = 0.6
VI = 5.5V or GND, VCC = 5.5V
VO = 5.5V or GND, VCC = 5.5V
Min
Typ
Max
Unit
-
-
150
A
-
500
1000
nA
-
400
800
nA
-0.3
0.8VCC
1.0
6.0
-1
-
0.2VCC
6.0
1
V
V
-1
-
1
mA
A
A
AC Electrical Characteristics
Sym
VHM
VHL
Description
Rising and falling threshold voltage high
Rising and falling threshold voltage low
Value
0.8 VCC
0.2 VCC
Unit
V
V
Signal
VHM
VLM
tr
tf
*
12-07-0001
PT0150-8
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Unless otherwise specified: GND = 0 V, VCC = 2 V to 5.5 V, TA = -40 °C to +85 °C, CL = 50 pF
Symbol
fSCL
tSU;STA
SCL clock frequency
START condition set-up time
Item
Min.
0.6
Typ.
-
Max.
400
-
Unit
kHz
tHD;STA
tSU;DAT
tHD;DAT1
tHD;DAT2
START condition hold time
Data set-up time (RTC read/write)
Data hold time (RTC write)
Data hold time (RTC read)
0.6
200
35
0
-
-
s
ns
ns
tSU;STO
STOP condition setup time
0.6
-
-
s
tBUF
Bus idle time between a START and STOP condition
1.3
-
-
s
tLOW
When SCL = "L"
1.3
-
-
s
tHIGH
When SCL = "H"
0.6
-
-
s
tr
Rise time for SCL and SDA
-
-
0.3
s
-
-
0.3
50
0.5
s
ns
s
tf
Fall time for SCL and SDA
tSP*
Allowable spike time on bus
tD
Duration of staring to stopping
* Note: only reference for design
S
SCL
Sr
tLOW
fSCL
tHIGH
P
tHD;STA
tSP
s
s
tSU;STA
tBUF
SDA
tHD;STA
tSU;DAT
tHD;DAT
tSU;STA
tSU;STO
tHD;STA
tD
S
Start condition
Sr
Restart condition
P
Stop condition
12-07-0001
PT0150-8
5
07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Function Description
Alarm function
PT7C4372A/C
This module is has two alarm system (Alarm_A and
Alarm_B) that outputs interrupt signals from /INTA or
/INTB to CPU when the day of the week, hour or minute
corresponds to the setting. Each of them may output
interrupt signal separately at a specified time. The alarm
may be selectable between on and off for each day of the
week, thus allowing outputting alarm everyday or on a
specific day of the week.
Overview of Functions
Clock function
CPU can read or write data including the year (last two
digits), month, date, day, hour, minute, and second. Any
(two-digit) year that is a multiple of 4 is treated as a leap
year and calculated automatically as such until the year 2099.
Clock precision adjustment function
They have two internal oscillation circuit capacitors, so that
an oscillation circuit may be configured simply by
externally connecting a crystal. Either 32.768kHz or
32.000kHz crystal may be selected to setting the internal
register appropriately.
The clock precision can be adjusted forward or back in units
of ±3.051 ppm (32.768kHz crystal) or ±3.125 ppm
(32.000kHz crystal) and oscillation frequency can be
adjusted in ±189 ppm (32.768kHz crystal) or ±194 ppm
(32.000kHz crystal).
The Alarm_A is output from the /INTA pin while the
Alarm_B is output from either the /INTA or the /INTB pins.
Polling is possible separately for each alarm function.
Oscillation stop detection function, power drop detection
function (voltage monitoring function), and power-on
reset detection function
PT7C4372A/ C have only oscillation stop detection function.
The oscillation stop detection function uses registers to
record if clock data is valid or invalid. This function may be
used to determine if the PT7C4372A/C supply power has
been booted from 0V and if it has been backed up.
This function can be used to implement a higher-precision
clock function, such as by:
Enabling higher clock precision throughout the year by
taking seasonal clock precision adjustments into
account in advance, or
Enabling correction of temperature-related clock
precision variation in systems that include a
temperature detecting function.
Interface with CPU
Data is read and written via the I2C bus interface using two
signal lines: SCL (clock) and SDA (data).
Since the output of the I/O pin of SDA is open drain, a pullup resistor should be used on the circuit board if the CPU
output I/O is also open drain.
The SCL's maximum clock frequency is 400 kHz, which
supports the I2C bus's high-speed mode.
Periodic interrupt
PT7C4372A/C
Periodic interrupts can be output via the /INTA and /INTB
pins.
Select among five Periodic frequency settings: 2 Hz (every
0.5 seconds), 1 Hz (every second), 1/60 Hz (every minute),
1/3600Hz (every hour), or monthly.
Select among two output waveforms for periodic interrupts:
ordinary pulse waveform (2 Hz or 1 Hz) or waveforms
(every second, minute, hour, or month) for CPU-level
interrupts that can support CPU interrupts.
A polling function is also provided to enable monitoring of
pin states via registers.
32-kHz clock output
The 32.768 kHz clock (32.768kHz crystal) or 32.000kHz
clock (32.000kHz crystal) can be output via the /INTB by
setting corresponding register.
Note: The precision of this 32.768 kHz clock output via the
FOUT pin can not be adjusted (even when using the clock
precision adjustment function).
12-07-0001
PT0150-8
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07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Registers
Allocation of registers
Addr.
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Second
-*5
S40
S20
S10
S8
S4
S2
S1
1
Minutes
-
M40
M20
M10
M8
M4
M2
M1
2
Hours
-
-
H20 or
P, /A
H10
H8
H4
H2
H1
3
Days of the week
-
-
-
-
-
W4
W2
W1
4
Days
-
-
D20
D10
D8
D4
D2
D1
5
Months
-
-
-
M10
M8
M4
M2
M1
6
Years
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
7
Time Trimming
/XSL
F6
F5
F4
F3
F2
F1
F0
8
Alarm_A: Minute
-
AM40
AM20
AM10
AM8
AM4
AM2
AM1
9
Alarm_A: Hour
-
-
AH20 or
AP, /A
AH10
AH8
AH4
AH2
AH1
A
Alarm_A: Day
-
AW6
AW5
AW4
AW3
AW2
AW1
AW0
B
Alarm_B: Minute
-
BM40
BM20
BM10
BM8
BM4
BM2
BM1
C
Alarm_B: Hour
-
-
BH20 or
BP, /A
BH10
BH8
BH4
BH2
BH1
D
Alarm_B: Day
-
BW6
BW5
BW4
BW3
BW2
BW1
BW0
E
Control 1
AALE
BALE
SL2
SL1
TEST*2
CT2
CT1
CT0
F
Control 2
-
-
/12, 24
ADJ or
XSTP*3
/CLEN
CTFG
AAFG
BAFG
Caution points:
*1. All bits marked with "-" are read-only bits. Their value when read is always "0".
*2. The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit.
*3. ADJ is for write and XTSP is for read operation. The XTSP bit is set to “0” by writing data into the control register 2 for
normal oscillation. When XSTP is set to “1”, the Time Trimming register, Control 1 register, /CLEN and TEST bits are reset
to “0”.
*4. All bits marked with "-" are read-only bits. Their value when read is always "0".
12-07-0001
PT0150-8
7
07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Control register 1
PT7C4372A
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
E
Control 1
(default)
AALE
0
BALE
0
SL2
0
SL1
0
TEST
0
CT2
0
CT1
0
CT0
0
PT7C4372C
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
E
Control 1
(default)
AALE
0
BALE
0
SL2
0
SL1
0
TEST
0
CT2
0
CT1
1
CT0
1
AALE, BALE
Alarm_A, Alarm_B enable bits.
AALE, BALE
Data
Description
0
Alarm_A (Alarm_B) correspondence action invalid
1
Alarm_A (Alarm_B) correspondence action valid
Default
Read / Write
See section “Alarm Function” for more detail.
SL2, SL1
Interrupt output select bits. Two alarm pulses (Alarm_A and alarm_B), periodic interrupt output (INT), 32kHz clock pulses may
be output to the /INTA or /INTB pins selectively by SL1 and SL2.
SL2
SL1
Description
0
0
Output Alarm_A, Alarm_B, INT to the /INTA. Output 32kHz clock pulses to /INTB.
0
1
Output Alarm_A, INT to the /INTA. Output 32kHz clock pulses, Alarm_B to /INTB.
1
0
Output Alarm_A, Alarm_B to the /INTA. Output 32kHz clock pulses, INT to /INTB.
1
1
Output Alarm_A to the /INTA. Output 32kHz clock pulses, Alarm_B, INT to /INTB.
Default
TEST
TEST
Data
Description
0
Ordinary operation mode
1
Test mode
Default
Read / Write
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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CT2, CT1, CT0
Periodic interrupt output select bits.
CT2
CT1
CT0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
See section 6.5 for more detail.
Wave Form Mode
Pulse
Pulse
Level
Level
Level
Level
Description
Cycle / Falling Timing
Off (“H”)
Fixed at “L”
2Hz (duty 50%)
1Hz (duty 50%)
Every second (synchronized with second count up)
Every minute (Occurs when seconds reach ":00")
Every hour (Occurs when minutes and seconds reach "00:00")
Every month (Occurs at 00:00:00 on first day of month)
Default
Control Register 2
PT7C4372A
Addr.
Description
D7
D6
D5
Control 2
/12, 24
(default)
0
0
Undefined
D4 when read is used as ADJ, when write is used as XSTP.
F
D4
D3
D2
D1
D0
ADJ or XSTP
1
/CLEN
0
CTFG
0
AAFG
0
BAFG
0
PT7C4372C
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
F
Control 2
(default)
0
0
/12, 24
1
ADJ or XSTP
1
/CLEN
1
CTFG
0
AAFG
0
BAFG
0
D4 when read is used as ADJ, when write is used as XSTP.
/12, 24
/12, 24 time display selection bit.
/12, 24
Data
Description
Read/
Write
0
12-hour time display
1
24-hour time display
* Default
See section “Alarm Function” for more detail.
PT7C4372C
/12, 24 time display selection bit.
/12, 24
Data
Description
Read/
Write
0
12-hour time display
1
24-hour time display
* Default
See section “Alarm Function” for more detail.
12-07-0001
PT0150-8
9
07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
ADJ or XSTP
ADJ: 30 second adjust bit. Second is adjusted within 122s (within 125s when 32.000kHz crystal is used) from writing
operation to ADJ.
ADJ
Data
Description
0
Ordinary operation.
1
Second adjustment. 1) For second range from “00” to “29”, second is reset to “00”;
2) For second range from “30” to “59”, second is reset to “00” and minute is incremented by 1.
Write
XSTP: oscillator halt sensing bit.
XSTP
Data
Description
0
Ordinary oscillation.
1
Oscillator halts sensing.
Read
Default
See section “Oscillation Stop Detection”.
/CLEN
PT7C4372A FOUT 32-kHz clock output enabled bit.
Data
/CLEN
Description
0
32-kHz clock (frequency same as crystal’s) output enabled.
1
32-kHz clock output disabled.
Default
Read
PT7C4372C FOUT 32-kHz clock output enabled bit.
/CLEN
Data
Description
0
32-kHz clock (frequency same as crystal’s) output enabled.
1
32-kHz clock output disabled.
Read
Default
CTFG
CTFG
Data
Description
Default
0
Periodic interrupt output OFF status; /INTA or /INTB= OFF (Hi-z) Read
1
Periodic interrupt output ON status; /INTA or /INTB= "L"
0
A "0" can be written only when the periodic interrupt is in level mode, at which time the
/INTA or /INTB pin is set to OFF (“H”) status. After a "0" is written, the value still becomes
"1" again at the next cycle.
1
Setting prohibited
Read
Write
Default
See section “Related Registers” for more detail.
12-07-0001
PT0150-8
10
07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
AAFG, BAFG
AAFG,BAFG Data
0
Read
1
Description
Alarm register does not match current time
Default
Alarm register match current time
0
/INTA or /INTB pin = OFF (H)
1
Setting prohibited
See section “Alarm Function” for more detail.
Time Counter
Default
Write
Time digit display (in BCD code):
Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00.
Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00.
Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to
12 a.m. or 23 to 00.
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
0
Seconds
(default)
0
S40
S20
S10
S8
S4
S2
S1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
1
Minutes
(default)
0
M40
M20
M10
M8
M4
M2
M1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Hours
H20 or P,/A
H10
H8
H4
H2
H1
(default)
0
0
Undefined Undefined Undefined Undefined Undefined Undefined
Note: Any registered imaginary time should be replaced with correct time; otherwise it will cause the clock counter malfunction.
2
Days of the week Counter
Addr.
Description
D7
D6
D5
D4
Days of the week
(default)
0
0
0
0
“-“ indicates write-protected bits. A zero is always read from these bits.
3
D3
0
D2
D1
D0
W4
W2
W1
Undefined Undefined Undefined
The day counter is a divide-by-7 counter that counts from 00 to 01 and up 06 before starting again from 01.
The correspondence between days and count values is shown below.
Days
W4
W2
W1
Day
Remark
0
0
0
Sunday
00 h
0
0
1
Monday
01 h
0
1
0
Tuesday
02 h
Write / Read
0
1
1
Wednesday
03 h
1
0
0
Thursday
04 h
1
0
1
Friday
05 h
1
1
0
Saturday
06 h
Write prohibit
1
1
1
Do not enter a setting for this bit.
12-07-0001
PT0150-8
11
07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Calendar Counter
The data format is BCD format.
Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December).
Range from 1 to 30 (for April, June, September and November).
Range from 1 to 29 (for February in leap years).
Range from 1 to 28 (for February in ordinary years).
Carried to month digits when cycled to 1.
Month digits: Range from 1 to 12 and carried to year digits when cycled to 1.
Year digits: Range from 00 to 99 and 00, 04, 08, … , 92 and 96 are counted as leap years.
Addr.
Description
D7
D6
4
Days
(default)
0
0
5
Months
(default)
0
0
D5
D4
D3
D2
D1
D0
D20
D10
D8
D4
D2
D1
Undefined Undefined Undefined Undefined Undefined Undefined
0
M10
M8
M4
M2
M1
Undefined Undefined Undefined Undefined Undefined
Years
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
(default)
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Note: Any registered imaginary time should be replaced with correct time; otherwise it will cause the clock counter malfunction.
6
Time Trimming Register
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
Time trimming
/XSL
F6
F5
F4
F3
F2
F1
(default)
0
0
0
0
0
0
0
Note: Time trimming function only adjusts clock timing. Oscillation frequency and 32-kHz clock output is not adjusted.
7
F0
0
/XSL bit
The /XSL bit is used to select frequency of the crystal.
/XSL
0
1
Frequency of the crystal (kHz)
32.768
32.000
F6 to F0
Implement a higher-precision clock function. See section “Clock Precision Adjustment Function”.
12-07-0001
PT0150-8
12
07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Alarm Register
See section “Alarm Function” for more details.
Alarm_A, Alarm_B Register
Alarm_A, Alarm_B can output alarm pulses at the time set as the day-of-the-week, hour, minute (e.g. Monday 7:00 a.m. every
day of weeks).
Addr.
Description
D7
D6
D5
8
Alarm_A: Minute
(default)
0
AM40
Undefined
AM10
AM8
AM4
AM2
AM1
Undefined Undefined Undefined Undefined Undefined
Alarm_A: Hour
-
-
(default)
0
0
AM20
Undefined
AH20, or
AP,/A
Undefined
A
Alarm_A: Day
(default)
0
AW6
Undefined
AW5
Undefined
AW4
AW3
AW2
AW1
AW0
Undefined Undefined Undefined Undefined Undefined
B
Alarm_B: Minute
(default)
0
BM40
Undefined
BM10
BM8
BM4
BM2
BM1
Undefined Undefined Undefined Undefined Undefined
Alarm_B: Hour
-
-
(default)
0
0
BM20
Undefined
BH20, or
BP,/A
Undefined
Alarm_B: Day
(default)
0
BW6
Undefined
BW5
Undefined
BW4
BW3
BW2
BW1
BW0
Undefined Undefined Undefined Undefined Undefined
9
C
D
D4
12-07-0001
AH10
D3
AH8
D2
AH4
D1
AH2
AH1
Undefined Undefined Undefined Undefined Undefined
BH10
BH8
BH4
BH2
BH1
Undefined Undefined Undefined Undefined Undefined
PT0150-8
13
D0
07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Clock Precision Adjustment Function
Adjustment range
Adjustment range (ppm)
-189.1 to +189.1
*
Adjustment unit (ppm)
3.05
Internal timing of adjustment
Once every 20 seconds at “00”, “20”, “40” seconds
*
note: add or decrement 2 clock pulses every 20s: 2/(32,76820) = 3.051ppm (or 3.125ppm when 32.000kHz crystal is used).
Adjustment amount and adjustment value
Adjustment data
Adjustment amount
(ppm)
Decimal
Hexadecimal
-189.10
+63
3F h
-186.05
+62
3E h
-183.00
+61
3D h
bit 6
F6
0
0
0
bit 5
F5
1
1
1
bit 4
F4
1
1
1
bit 3
F3
1
1
1
bit 2
F2
1
1
1
bit 1
F1
1
1
0
bit 0
F0
1
0
1
-9.15
-6.10
-3.05
OFF
OFF
+3.05
+6.10
+9.15
+4
+3
+2
+1
0
-1
-2
-3
04 h
03 h
02 h
01 h
00 h
7F h
7E h
7D h
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
+183.00
+186.05
+189.10
OFF
OFF
-60
-61
-62
-63
-64
44 h
43 h
42 h
41 h
40 h
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
Examples:
(1) Setting time forward
Adjust (advance) the clock precision when FOUT clock output is 32767.7 Hz
Determine the current amount of variance
(32767.7 -32768) / 32768 = -9.16 × 10 -6
*[ 32768 ] = Reference values
Calculate the optimum adjustment data (decimal value) relative to the current variance.
Adjustment data = variance / adjustment resolution = -9.16 / 3.05 -3
Calculate the setting adjustment data (hexadecimal)
Setting adjustment data = 128 -3 (80 h – 03h) = 125 (7D h)
(2) Setting time backward
Adjust (set back) the clock precision when FOUT clock output is 32768.3 Hz
Determine the current amount of variance
(32768.3 -32768) / 32768 = +9.16 ×10 -6
Calculate the optimum adjustment data (decimal value) relative to the current variance.
Adjustment data = (variance / adjustment resolution) + 1 = (+9.16 / 3.05) + 1 +4
*Add 1 since reference value is 01h
Calculate the setting adjustment data (hexadecimal)
Setting adjustment data = 04 h
12-07-0001
PT0150-8
14
07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Alarm Function
These part no have Alarm A and Alarm B functions which can all output alarm pulses at the preset days of the week, hours and
minutes.
Related register
Addr.
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
Minutes
-
M40
M20
M10
M8
M4
M2
M1
2
Hours
-
-
H20 or
P, /A
H10
H8
H4
H2
H1
3
Days of the week
-
-
-
-
-
W4
W2
W1
8
Alarm_A: Minute
-
AM40
AM20
AM10
AM8
AM4
AM2
AM1
9
Alarm_A: Hour
-
-
AH20 or
AP, /A
AH10
AH8
AH4
AH2
AH1
A
Alarm_A: Day
-
AW6
AW5
AW4
AW3
AW2
AW1
AW0
B
Alarm_B: Minute
-
BM40
BM20
BM10
BM8
BM4
BM2
BM1
C
Alarm_B: Hour
-
-
BH20 or
BP, /A
BH10
BH8
BH4
BH2
BH1
D
Alarm_B: Day
-
BW6
BW5
BW4
BW3
BW2
BW1
BW0
E
Control 1
AALE
BALE
SL2
SL1
TEST
CT2
CT1
CT0
F
Control 2
-
-
/12, 24
ADJ or
XSTP
CLEN
CTFG
AAFG
BAFG
AALE, BALE:
This bit is used to set up the Alarm A/B function (to generate alarms matching day, hour, or minute settings).
AALE, BALE
Data
Description
0
Alarm_A (Alarm_B) correspondence action invalid
Default
Read / Write
1
Alarm_A (Alarm_B) correspondence action valid
* When using the Alarm A (or B) function, first set this AALE (or BALE) bit value as "0" to stop the function. Next, set the day,
hour, minute, and set the AAFG (or BAFG) bit to 0. Finally, set "1" to the AALE (or BALE) bit to set the Alarm A (or B) function
as valid. The reason for first setting the AALE (or BALE) bit value as "0" is to prevent /INTB or /INTA = "L" output in the event
that a match between the current time and alarm setting occurs while the alarm setting is still being made.
12-07-0001
PT0150-8
15
07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
AAFG, BAFG:
These bits are valid only when the AALE, BALE bits value are "1". When a match occurs between the Alarm A or Alarm B
setting and the current time, the AAFG or BAFG bit value becomes "1" approximately 61 µs afterward. (There is no effect when
the AALE or BALE bit becomes "0".) The /INTB or /INTA = "L" status that is set at this time can be set to OFF by writing a "0"
to these bits.
AAFG,BAFG Data
Description
0
Alarm register does not match current time
Default
Read
1
Alarm register match current time
0
1
Write
/INTA or /INTB pin = OFF (H)
Setting prohibited
Default
SL2, SL1:
Interrupt output select bits. Two alarm pulses (Alarm_A and alarm_B), periodic interrupt output (INT), 32kHz clock pulses may
be output to the /INTA or /INTB pins selectively by SL1 and SL2.
SL2
SL1
Description
0
0
Output Alarm_A, Alarm_B, INT to the /INTA. Output 32kHz clock pulses to /INTB.
0
1
Output Alarm_A, INT to the /INTA. Output 32kHz clock pulses, Alarm_B to /INTB.
1
0
Output Alarm_A, Alarm_B to the /INTA. Output 32kHz clock pulses, INT to /INTB.
1
1
Output Alarm_A to the /INTA. Output 32kHz clock pulses, Alarm_B, INT to /INTB.
Default
/12, 24:
This bit is used to select between 12-hour clock operation and 24-hour clock operation.
12/24
Description
Time
0
12-hour time display
1
24-hour time display
24-hour clock
00
01
02
03
04
05
06
07
08
09
10
11
12-hour clock
12 ( AM 12)
01 ( AM 01 )
02 ( AM 02 )
03 ( AM 03 )
04 ( AM 04 )
05 ( AM 05 )
06 ( AM 06 )
07 ( AM 07 )
08 ( AM 08 )
09 ( AM 09 )
10 ( AM 10 )
11 ( AM 11 )
24-hour clock
12
13
14
15
16
17
18
19
20
21
22
23
12-hour clock
32 ( PM 12 )
21 ( PM 01 )
22 ( PM 02 )
23 ( PM 03 )
24 ( PM 04 )
25 ( PM 05 )
26 ( PM 06 )
27 ( PM 07 )
28 ( PM 08 )
29 ( PM 09 )
30 ( PM 10 )
31 ( PM 11 )
* Be sure to select between 12-hour and 24-hour clock operation before writing the time data.
12-07-0001
PT0150-8
16
07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Examples:
Alarm_A/B: Day-of-the-week
Alarm_A/B: Hour
Alarm_A/B: Minute
Alarm time settings
24-hour
12-hour
Minute
Sun. Mon. Tue. Wed. Thu. Fri. Sat.
AW0 AW1 AW2 AW3 AW4 AW5 AW6 (Hexadecimal) (Hexadecimal)
(Hexadecimal)
AM 00:00 every day
1
1
1
1
1
1
1
00
00
00
AM 01:30 every day
1
1
1
1
1
1
1
01
01
30
AM 11:59 on Mon.
0
1
0
0
0
0
0
11
11
59
PM 00:00 on Mon. to Fri.
0
1
1
1
1
1
0
12
32
00
PM 01:30 on Sun.
1
0
0
0
0
0
0
13
21
30
PM 11:59 on Mon, Wed.
0
1
0
1
0
0
0
23
31
59
WAFG, DAFG and /INTA, /INTB output
61us (approx)
61us (approx)
AAFG (BAFG) bit
/INTA or /INTB pins
(/INTB only for PT7C4372A)
Set AAFG (BAFG)
to 0
Matched alarm time
Matched alarm time
12-07-0001
Set AAFG (BAFG)
to 0
Matched alarm time
PT0150-8
17
07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Periodic Interrupt Function
Periodic interrupt output can be obtained via PT7C4372A/C: /INTA or /INTB pin. Select among five periodic-cycle settings: 2 Hz
(once per 0.5 seconds), 1 Hz (once per second), 1/60 Hz (once per minute), 1/3600 Hz (once per hour), or monthly (on the 1 st of
each month).
Select between two output waveforms for periodic interrupts: an ordinary pulse waveform (2 Hz or 1 Hz) or a waveform (every
second, minute, hour, or month) for CPU-level interrupts that can support CPU interrupts.
A polling function is also provided to enable monitoring of pin states via registers.
Related registers
Period interrupts output via PT7C4372A/C: /INTA, /INTB
Addr.
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CT2
CT1
CT0
AAFG
BAFG
E
Control 1
AALE
BALE
SL2
SL1
TEST
F
Control 2
-
-
/12, 24
ADJ or
XSTP
/CLEN
CTFG
SL2, SL1
Interrupt output select bits. Two alarm pulses (Alarm_A and alarm_B), periodic interrupt output (INT), 32kHz clock pulses may
be output to the /INTA or /INTB pins selectively by SL1 and SL2.
SL2
SL1
Description
0
0
Output Alarm_A, Alarm_B, INT to the /INTA. Output 32kHz clock pulses to /INTB.
0
1
Output Alarm_A, INT to the /INTA. Output 32kHz clock pulses, Alarm_B to /INTB.
1
0
Output Alarm_A, Alarm_B to the /INTA. Output 32kHz clock pulses, INT to /INTB.
1
1
Output Alarm_A to the /INTA. Output 32kHz clock pulses, Alarm_B, INT to /INTB.
Default
CTFG:
During a read operation, this bit indicates the /INTA or /INTB pin's periodic interrupt output status. This status can be set as OFF
by writing a "0" to this bit when /INTA or /INTB = "H".
CTFG
Data
Description
Default
0
Periodic interrupt output OFF status; /INTA or /INTB= OFF (Hi-z) Read
1
Periodic interrupt output ON status; /INTA or /INTB= "L"
0
A "0" can be written only when the periodic interrupt is in level mode, at which time the
/INTA or /INTB pin is set to OFF (“H”) status. After a "0" is written, the value still becomes
"1" again at the next cycle.
1
Setting prohibited
Read
Write
12-07-0001
PT0150-8
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Default
07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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CT2, CT1, CT0:
Periodic interrupt output select bits.
CT2
CT1
CT0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Wave Form Mode
Pulse
Pulse
Level
Level
Level
Level
Description
Cycle / Falling Timing
Off (“H”)
Default
Fixed at “L”
2Hz (duty 50%)
1Hz (duty 50%)
Every second (synchronized with second count up)
Every minute (Occurs when seconds reach ":00")
Every hour (Occurs when minutes and seconds reach "00:00")
Every month (Occurs at 00:00:00 on first day of month)
Mode-specific output waveforms
1) Pulse mode:
Output 2Hz, 1Hz clock pulse.
CTFG bit
/INTA or /INTB pins
(/INTB only for PT7C4372A)
Approx. 92us (32.768kHz crystal is used)
94us (32.000kHz crystal is used)
Counting up of seconds
Since counting up of seconds and the falling edge has a time lag of approx. 92us (at 32.768kHz) (Approx.
94us when 32.000kHz is used), time with apparently approx. one second of delay from time of the real-time
clock may be read when time is read in synchronization with the falling edge of output.
12-07-0001
PT0150-8
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07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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2) Level mode:
One second, one minute or one month may be selected for an interrupt cycle. Counting up of seconds is matched with falling edge
of interrupt output.
CTFG bit
/INTA or /INTB pins
(/INTB only for PT7C4372A)
Write 0 to CTFG
Second count-up
Write 0 to CTFG
Second count-up
Second count-up
3) When the time trimming circuit is used, periodic interrupt cycle changes every 20 seconds.
Pulse mode: The period during which the output pulse is low can be adjusted backward or forward up to ±3.784ms (±3.875ms
when 32.000kHz crystal is used).
For example, the duty for the 1-Hz setting can be adjusted ±0.3784% (or ±0.3875% when 32.000kHz crystal is
used) from 50%.
Level mode: a one-second period can be adjusted backward or forward up to ±3.784 ms (±3.875ms when 32.000kHz crystal
is used).
Various Detection Function
PT7C4372A/C detection function includes oscillation stop detection as well as reporting of detection results in corresponding bits
of Control 2 register.
The status of the power supply, oscillation circuit, and clock can be confirmed by checking these results.
*Note with caution that detection functions may not operate correctly when power flickers occur.
Related register
Addr.
Function
F
Control 2
Bit 7
Bit 6
Bit 5
-
-
/12, 24
Bit 4
ADJ or
XSTP
Bit 3
/CLEN
Bit 2
CTFG
Bit 1
Bit 0
AAFG
BAFG
Oscillation stop detection
When read control register is 2 bit 4, this bit is as XSTP bit sensing oscillator halt. This bit is as 30 second adjust bit when write.
XSTP
Read
Data
Description
0
Ordinary oscillation.
1
Oscillator halts sensing.
Default
This bit senses the oscillator halt. When oscillation is halted after initial power on from 0V or drop in supply voltage, the bit is set
to “1” and remains to be “1” after it is restarted. This bit may be used to judge validity of clock and calendar count data after
power on or supply voltage drop. When this bit is set to “1”, the Time Trimming register, Control 1 register, /CLEN and TEST
bits are reset to “0”. /INTA will stop output and the /INTB will output 32-kHz clock pulses. This bit is set to “0” by setting the
control register 2 during ordinary oscillation.
12-07-0001
PT0150-8
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07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Reading / Writing Data via the I2C Bus Interface
Overview of I2C-BUS
The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination
of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on.
Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and
stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data
transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the
data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per
clock pulse. The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a
chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its
slave address matches the slave address in the received data.
System Configuration
All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to
multiple devices.
SCL and SDA are both connected to the Vcc line via a pull-up resistance. Consequently, SCL and SDA are both held at high level
when the bus is released (when communication is not being performed).
Fig 4. System configuration
Vcc
RP
RP
SDA
SCL
Master
MCU
Slave
RTC
Other Peripheral
Device
Note: When the master is one, the MCU is ready for driving SCL to "H" and RP of SCL may not required.
12-07-0001
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Starting and Stopping I2C Bus Communications
Fig 5. Starting and stopping on I2C bus
1) START condition, repeated START condition, and STOP condition
a) START condition
SDA level changes from high to low while SCL is at high level
b) STOP condition
SDA level changes from low to high while SCL is at high level
c) Repeated START condition (RESTART condition)
In some cases, the START condition occurs between a previous START condition and the next STOP condition, in which
case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the
START condition, the SDA level changes from high to low while SCL is at high level.
2) Caution points
a) The master device always controls the START, RESTART, and STOP conditions for communications.
b) The master device does not impose any restrictions on the timing by which STOP conditions affect transmissions, so
communications can be forcibly stopped at any time while in progress. (However, this is only when this RTC module is in
receiver mode (data reception mode = SDA released).
c) When communicating with this RTC module, the series of operations from transmitting the START condition to
transmitting the STOP condition should occur within 0.5 seconds. (A RESTART condition may be sent between a START
condition and STOP condition, but even in such cases the series of operations from transmitting the START condition to
transmitting the STOP condition should still occur within 0.5 seconds.)
If this series of operations requires 0.5 to 1.0 seconds or longer, the I2C bus interface will be automatically cleared and set to
standby mode by this RTC module's bus timeout function. Note with caution that both write and read operations are invalid for
communications that occur during or after this auto clearing operation. (When the read operation is invalid, all data that is read has
a value of "1").
Restarting of communications begins with transfer of the START condition again.
d) When communicating with this RTC module, wait at least 1.3 µs between transferring a STOP condition (to stop
communications) and transferring the next START condition (to start the next round of communications). (If any carries occur in
the time data during this communication period, corrections are made during this period.)
Fig 6. Interval between start and st
1.3
12-07-0001
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07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Data Transfers and Acknowledge Responses during I2C-BUS Communication
1) Data transfers
Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount
(bytes) of data that are transferred between the START condition and STOP condition. (However, the transfer time must be no
longer than 0.5 seconds and access to the Address Dh (Reserved) register is prohibited.)
The address auto increment function operates during both write and read operations. After address Fh, increment goes to address
0h. Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level. The receiver
(receiving side) captures data while the SCL line is at high level.
*Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART,
or STOP condition.
2) Data acknowledge response (ACK signal)
When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment
is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This
does not include instances where the master device intentionally does not generate an ACK signal.)
Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases
the SDA line and the receiver sets the SDA line to low (= acknowledge) level.
SCL from Master
1
8
2
SDA from transmitter
(sending side)
9
Release SDA
Low active
SDA from receiver
(receiving side)
ACK signal
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the
falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the
transmitter.
When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave that
indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a
STOP condition from the Master.
12-07-0001
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07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Slave Address
The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin,
slave addresses are allocated to each device.
All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device
responds to this communication only when the specified slave address it has received matches its own slave address.
Slave addresses have a fixed length of 7 bits. This RTC's slave address is [ 0110 010 ].
An R/W bit ("*" above) is added to each 7-bit slave address during 8-bit transfers.
Table
Slave address
R / W bit
Transfer data
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Read
65 h
1 (= Read)
0
1
1
0
0
1
0
Write
64 h
0 (= Write)
I2C Bus’s Basic Transfer Format
S
Start indication
Sr
Restart indication
P
Stop indication
A
RTC Acknowledge
A
Master Acknowledge
1) Write via I2C bus
Slave address (7 bits)
S
0
Start
1
1
0
0
1
write A
0
Slave address + write specification
0
A
C
K
Addr. setting
0h~Fh
Transfer mode
0
10
0
0
Address + transfer mode specification
1) Specifies the write start address;
2) Specifies the write mode (=0h fixed)
12-07-0001
A
A
C
K
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
Write data
A
P
A
C
K
Stop
PT0150-8
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07/04/12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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2) Read via I2C bus
a) Standard read
Slave address (7 bits)
S
0
Start
0
0
1
0
Slave address (7 bits)
0
b)
1
0
A
C
K
Slave address + write specification
Sr
Restart
1
1
1
0
0
1
Addr. setting
0h~Fh
write A
Read
0
A
1
A
C
K
Slave address + read specification
indicating next byte will be read.
Transfer mode
0
0
0
A
0
Address + transfer mode specification
1) Specifies the write start address;
2) Specifies the write mode (=0h fixed)
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
Data read (1)
Data is read from the specified start
address and address auto increment.
A
C
K
A
A
C
K
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
Data read (2)
Address auto increment to set the
address for the next data to be read.
/A
P
N
O
Stop
A
C
K
Simplified read
Slave address (7 bits)
S
0
Start
1
1
0
0
1
Addr. setting
0h~Fh
write A
0
Slave address + write specification
0
A
C
K
Transfer mode
0
1
0
Address + transfer mode specification
1) Specifies the write start address;
2) Specifies the write mode (=4h fixed)
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
Data read (1)
Data is read from the specified start
address and address auto increment.
12-07-0001
A
0
A
C
K
A
A
C
K
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
Data read (2)
Address auto increment to set the
address for the next data to be read.
/A
P
N
O
Stop
A
C
K
PT0150-8
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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c) Simplified read with no start address indicating
Only when reading from address Fh (Fh 0h 1h 2h, etc.), a read operation can be performed without specifying the
read start address or the transfer mode.
Slave address (7 bits)
S
0
Start
1
1
0
0
1
Read
0
Slave address + read specification
indicating next byte will be read.
A
1
A
C
K
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
Data read (1)
Data is read from the specified start
address and address auto increment.
A
A
C
K
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
Data read (2)
Address auto increment to set the
address for the next data to be read.
/A
P
N
O
Stop
A
C
K
Note: The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred
during actual communications. (However, the transfer time must be no longer than 0.5 seconds.)
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Real-time Clock Module (I2C Bus)
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Configuration of Oscillating Circuit and Timing Trimming
Recommended Layout for Crystal
OSCIN
OSCOUT
Note: The crystal, traces and crystal input pins
should be isolated from RF generating signals.
Considerations in Mounting Components Surrounding Oscillating Circuit
1) Mount the crystal oscillators in the closest possible position to the IC.
2) Avoid laying any signal or power line close to the oscillation circuit (particularly in the area marked with “←A→” in the
above figure).
3) Apply the highest possible insulation resistance between the OSCOUT pin and the PCB.
4) Avoid using any long parallel line to wire the OSCIN and OSCOUT pin.
5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt.
Built-in Capacitors Specifications and Recommended External Capacitors
Parameter
Symbol
Typ
Unit
OSCIN to GND
CG
20
pF
Build-in capacitors
OSCOUT to GND
CD
5
pF
OSCIN to GND
C1
4
pF
Recommended External capacitors
for crystal CL=12.5pF
OSCOUT to GND
C2
18
pF
Note: The frequency of crystal can be optimized by external capacitor C1 and C2, for frequency=32.768kHz, C1 and C2 should
meet the equation as below:
Cpar + [(C1+CG)*(C2+CD)]/ [(C1+CG)+(C2+CD)] =CL
Cpar is all parasitical capacitor between X1 and X2.
CL is crystal’s load capacitance.
Crystal Specifications
Parameter
Nominal Frequency
Series Resistance
Load Capacitance
Symbol
fO
ESR
CL
Min
-
Typ
32.768
12.5
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Max
70
-
Unit
kHz
k
pF
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Measurement of Oscillation Frequency
PT7C4372A
*1. Clock pulse of 32.768kHz or 32.000kHz is
output from the /INTB output pin on powering on
(XSTP is set to 1).
*2. Use a frequency counter having at least 6 digits
(7 digits or more recommended).
*3. Pull-up the /INTB output pin to Vcc for the
4372A.
/INTB
*4. /INTB applies to the 4372A
GND
Oscillation Frequency Adjustment please refers to page 12, Clock Precision Adjustment Function.
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Mechanical Information
LE (8-pin TSSOP)
Note:
1) Controlling dimensions in millimeters.
12-07-0001
PKG. DIMENSIONS(MM)
SYMBOL
MIN
MAX
A
1.20
A1
0.02
0.15
A2
0.80
1.00
b
0.19
0.30
c
0.09
0.20
D
2.90
3.10
E
4.30
4.50
E1
6.25
6.55
e
0.65 BSC
L
0.50
0.70
θ
1°
7°
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Real-time Clock Module (I2C Bus)
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WE (8-pin SOIC)
Symbol
A
A1
A2
b
c
D
E
E1
e
L
θ
Note:
1) Controlling dimensions in millimeters.
2) Ref : JEDEC MS-012E/AA
Dimensions In Millimeters
Min
Max
1.350
1.750
0.100
0.250
1.350
1.550
0.330
0.510
0.170
0.250
4.700
5.100
3.800
4.000
5.800
6.200
1.27 BSC
0.400
1.270
0°
8°
Ordering Information
Part Number
PT7C4372ALE
Package Code
L
Package
Lead free and Green 8-Pin TSSOP
PT7C4372CLE
PT7C4372AWE
PT7C4372CWE
L
W
W
Lead free and Green 8-Pin TSSOP
Lead free and Green 8-Pin SOIC
Lead free and Green 8-Pin SOIC
Note:
E = Pb-free and Green
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
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