PI6C4853111

PI6C4853111
2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL
Fanout Buffer with 2 to 1 Differential Clock Input Mux
Features
Description
•
•
•
•
FMAX = 500MHz
10 pairs of differential LVPECL outputs
Low additive jitter, <100fs 12k-20MHz
Selectable differential input pairs with single ended input
option
• Input CLK accepts: LVPECL, LVDS, CML, SSTL input
level
• Output skew: 35ps (typ)
The PI6C4853111 is a high-performance low-skew 1-to-10 LVPECL
fanout buffer. The PI6C4853111 features two selectable differential
clock inputs and translates to ten LVPECL outputs. The CLK inputs
accept LVPECL, LVDS, CML and SSTL signals.
Block Diagram
Pin Configuration
PI6C4853111 is ideal for clock distribution applications such as
providing fanout for low noise SaRonix-eCera oscillators.
• Operating Temperature: -40oC to 85oC
• Core Power supply: 3.3V ±10%, Output Power supply:
2.5V ±5% & 3.3V ±10%
• Packaging (Pb-free & Green): −32-pin TQFP (FA)
Q3
/Q3
Q4
/Q4
Q5
/Q5
Q6
/Q6
Q0
/Q0
Q1
/Q1
Q8
/Q8
VDDO
Q7
/Q7
Q8
/Q8
Q9
/Q9
VDDO
VEE
VDD
Q7
/Q7
/CLK1
Q6
/Q6
CLK1
Q5
/Q5
NC
CLK_SEL
1
Q4
/Q4
24 23 22 21 20 19 18 17
16
15
14
13
12
11
10
9
1 2 3 4 5 6 7 8
/CLK0
CLK1
/CLK1
0
25
26
27
28
29
30
31
32
CLK0
CLK0
/CLK0
VDDO
/Q2
Q2
/Q1
Q1
/Q0
Q0
VDDO
Q3
/Q3
CLK_SEL
Q2
/Q2
Q9
/Q9
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PI6C4853111
05/06/13
PI6C4853111
2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL
Fanout Buffer w/ 2 to 1 Differential Clock Input Mux
Pin Description(1)
Name
Pin #
Type
Description
VEE
8
P
Connect to negative power supply
CLK_SEL
2
I
Clock select input. When high, selects CLK1 input. When low, selects CLK0 input. LVCMOS/LVTTL level with 50kΩ pull down.
CLK0
3
I
Differential LVPECL clock input with 75kΩ pull-down
/CLK0
4
I
Inverting differential LVPECL clock input. Defaults to VDD/2 if left floating.
CLK1
6
I
Differential LVPECL clock input with 75kΩ pull-down
/CLK1
7
I
Inverting differential LVPECL clock input. Defaults to VDD/2 if left floating.
NC
5
VDDO
9,16, 25,32
P
Output Power pin
VDD
1
P
Core Power Supply
Q3, /Q3
24,23
O
Differential output pair, LVPECL interface level.
Q2, /Q2
27,26
O
Differential output pair, LVPECL interface level.
Q1, /Q1
29,28
O
Differential output pair, LVPECL interface level.
Q0, /Q0
31,30
O
Differential output pair, LVPECL interface level.
Q9, /Q9
11,10
O
Differential output pair, LVPECL interface level.
Q8, /Q8
13,12
O
Differential output pair, LVPECL interface level.
Q7, /Q7
15,14
O
Differential output pair, LVPECL interface level.
Q6, /Q6
18,17
O
Differential output pair, LVPECL interface level.
Q5, /Q5
20,19
O
Differential output pair, LVPECL interface level.
Q4, /Q4
22,21
O
Differential output pair, LVPECL interface level.
No Connect
Note:
1. I = Input, O = Output, P = Power supply connection.
Pin Characteristics
Symbol
Parameter
R
Input Pullup/Pulldown Resistance
Conditions
Min.
Typ.
Max.
50
Units
kΩ
Control Input Function Table
Inputs
Outputs
0
CLK0
1
CLK1
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PI6C4853111
05/06/13
PI6C4853111
2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL
Fanout Buffer w/ 2 to 1 Differential Clock Input Mux
Absolute Maximum Ratings(1)
Symbol
Parameter
Conditions
Min
VDD
Supply voltage
Referenced to GND
VIN
Input voltage
Referenced to GND
Typ
-0.5
Max
Units
4.6
V
VDD+0.5V
V
100
mA
IOUT
Surge Current
TSTG
Storage temperature
-65
150
oC
VBB
Smk/source Current, IBB
-0.5
+0.5
mA
ӨjA
Package Thermal Resistance
86
˚C/Watt
ӨjC
Package Thermal Resistance
12.7
˚C/Watt
Note:
1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These ratings are stress specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Operating Conditions
Symbol
Parameter
Conditions
VDD
Power Supply Voltage
VDDO
Output Power Supply Voltage
TA
Ambient Temperature
Min
Typ
Max
Units
3.0
3.6
V
2.375
3.6
V
85
oC
-40
LVCMOS/LVTTL DC Characteristics (TA = -40oC to +85oC, VDD = 3.3V ±5%, VDDO = 2.5V ±5% to 3.3V ±10%)
Symbol
Parameter
Conditions
Min
Typ
Max
VIH
Input High Voltage
CLK_SEL
2
VDD+0.3
VIL
Input Low Voltage
CLK_SEL
-0.3
0.8
IIH
Input High Current
CLK_SEL
VIN = VDD = 3.6V
IIL
Input Low Current
CLK_SEL
VIN = 0V, VDD = 3.6V
13-0057
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150
-5
Units
V
μA
μA
PI6C4853111
05/06/13
PI6C4853111
2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL
Fanout Buffer w/ 2 to 1 Differential Clock Input Mux
LVPECL DC Characteristics (TA = -40oC to +85oC, VDD = 3.3V ±10%, VDDO = 2.5V ±5% to 3.3V ±10%)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IIH
Input High
Current
CLK0, CLK1
VIN = VDD = 3.6V
150
µA
/CLK0, /CLK1
VIN = VDD = 3.6V
150
µA
IIL
Input Low
Current
CLK0, CLK1
VDD = 3.6V, VIN = 0V
-5
µA
/CLK0, /CLK1
VDD = 3.6V, VIN = 0V
-150
µA
VPP
Peak-to-peak Voltage
VCMR
Common Mode Input Voltage(1)
0.3
1
V
VEE+1.5
VDD
V
VOH
Output High Voltage(2)
VDDO = 2.5V or 3.3V
VDDO-1.4
VDDO-0.9
V
VOL
Output Low Voltage(2)
VDDO = 2.5V or 3.3V
VDDO-2.0
VDDO-1.7
V
0.6
1.0
V
140
mA
VSWING
IEE
Peak-to-peak Output Voltage Swing
Power Supply Current
@ 400 MHz
120
Notes:
1. For single-ended applications, the maximum input voltage for CLK and /CLK is VDD+0.3V
2. Outputs terminated with 50Ω to VDD-2.0V
AC Characteristics (TA = -40oC to +85oC, VDD = 3.3V ±10%, VDDO = 2.5V ±5% to 3.3V ±10%)
Symbol
fmax
Parameter
Conditions
Min
Typ
Output Frequency
Delay(1)
tpd
Propagation
Tsk
Output-to-output
tr/tf
Output Rise/Fall time
odc
Output duty cycle
Jadd
Additive jitter
Skew(2)
35
Max
Units
500
MHz
4
ns
60
ps
20% - 80%
150
700
ps
f ≤ 400 MHz
45
55
%
VDD = VDDO = 2.5V or
3.3V
75
fs
Notes:
1. Measured from the differential input to the differential output crossing point
2 Defined as skew between outputs at the same supply voltage and with equal loads. Measured at the output differential crossing point
Additive Jitter Calculation
The additive jitter is measured at 12KHz to 20MHz standard noise band with the LVPECL differential input clock at 156.25MHz.
additive jitter = √ jitter_out2 - jitter_in2
Summary of Phase Jitter (Diff. Input and Diff. Output)
Input
Output
VDD = 3.3V, 12kHz-20MHz
253.7
259.7
55.5
fs RMS
VDD = 2.5V, 12kHz-20MHz
186.6
201.3
75.5
fs RMS
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Additive Jitter
Unit
PI6C4853111
05/06/13
PI6C4853111
2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL
Fanout Buffer w/ 2 to 1 Differential Clock Input Mux
Packaging Mechanical: 32-pin TQFP (FA)
DOCUMENT CONTROL NO.
PD - 1814
9.00 BSC
.354
Square
REVISION: C
DATE: 03/09/05
Square
7.00
BSC
0.09
0.20
.004
.008
GAUGE PLANE
0.25 mm
.276
1
1.20 Max.
.047
0°
7°
0.45 .018
0.75 .030
1.00 REF
.039
.004
0.10
Seating Plane
0.30 .012
0.45 .018
0.80 BSC
.032
0.05
0.15
.002
.006
0.95
1.05
.037
.041
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Notes:
1. Controlling dimensions in millimeters
2. Ref.: JEDEC MS-026D/ABA
3. Package Outline Exclusive of Mold Flash and Metal Burr
DESCRIPTION: 32-Pin, Thin Quad Flat Package, TQFP
PACKAGE CODE: FA
Ordering Information(1,2,3)
Ordering Code
Package Code
Package Description
PI6C4853111FAE
FA
Pb-free & Green, 32-pin TQFP
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free & Green
3. X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
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PI6C4853111
05/06/13