PI6C2408 Zero-Delay Clock Buffer Features Description • • • • The PI6C2408 is a PLL-based, zero-delay buffer, with the ability to distribute eight outputs of up to 140 MHz at 3.3 V. Two banks of four outputs exist, and, depending on product option ordered, can supply either reference frequency, prescaled half frequency, or multiplied 2x or 4x input clock frequencies. The PI6C2408 family has a power-sparing feature: when input SEL2 is 0, the component will 3-state one or both banks of outputs depending on the state of input SEL1. A PLL bypass test mode also exists. This product line is available in high-drive and industrial environment versions. • • • • • Maximum rated frequency: 140 MHz Low cycle-to-cycle jitter Input to output delay, less than 150ps External feedback pin allows outputs to be synchronized to the clock input 5V tolerant CLKIN input Operates at 3.3V VDD Test mode allows bypass of the PLL for system testing purposes (e.g., IBIS measurements) Clock frequency multipliers ½x to 4x dependent on option Packaging (Pb-free and Green available): -16-pin, 150-mil SOIC (W) -16-pin 173-mil TSSOP (L) An external feedback pin is used to synchronize the outputs to the input; the relationship between loading of this signal and the other outputs determines the input-output delay. The PI6C2408 is characterized for both commercial and industrial operation. Block Diagram FB_IN CLKIN ÷2 Pin Configuration PLL OUTA2 Option (-3, -4) SEL1 SEL2 OUTA3 OUTA4 Decode Logic ÷2 16 1 15 2 14 3 4 16-Pin 13 5 W, L 12 11 6 10 7 9 8 FB_IN OUTA4 OUTA3 VDD GND OUTB4 OUTB3 SEL1 OUTB3 PI6C2408 (-1, -1H, -2, -3, -4) PLL OUTB1 OUTB2 Option (-2, -3) FB_IN CLKIN CLKIN OUTA1 OUTA2 VDD GND OUTB1 OUTB2 SEL2 OUTA1 MUX OUTB4 OUTA1 MUX OUTA2 OUTA3 SEL2 SEL1 OUTA4 Decode Logic ÷2 PI6C2408-6 MUX OUTB1 OUTB2 OUTB3 OUTB4 08-0298 1 PS8589K 11/06/08 PI6C2408 Zero-Delay Clock Buffer Input Select Decoding for PI6C2408 (-1, -1H,-4) SEL2 SEL1 OUTA [1-4] OUTB [1-4] Output Source PLL 0 0 3- State 3- State PLL O FF 0 1 PLL 3- State PLL ON 1 0 CLKIN CLKIN CLKIN O FF 1 1 PLL PLL PLL ON Input Select Decoding for PI6C2408 (-2,-3) SEL2 SEL1 OUTA [1-4] OUTB [1-4] Output Source PLL 0 0 3- State 3- State PLL O FF 0 1 PLL 3- State PLL ON 1 0 CLKIN CLKIN/2 CLKIN O FF 1 1 PLL PLL PLL ON Input Select Decoding for PI6C2408-6 SEL2 SEL1 OUTA [1-4] OUTB [1-4] Output Source PLL 0 0 3- State 3- State PLL O FF 0 1 CLKIN CLKIN/2 CLKIN O FF 1 0 PLL PLL PLL ON 1 1 PLL PLL/2 PLL ON PI6C2408 Configurations De vice Fe e dback From OUTA [1-4] Fre que ncy OUTB [1-4] Fre que ncy PI6C2408- 1 OUTA or OUTB CLKIN CLKIN PI6C2408- 1H OUTA or OUTB CLKIN CLKIN PI6C2408- 2 OUTA CLKIN CLKIN/2 PI6C2408- 2 OUTB 2X CLKIN CLKIN PI6C2408- 3 OUTA 2X CLKIN CLKIN or CLKIN( 1 ) PI6C2408- 3 OUTB 4X CLKIN 2X CLKIN PI6C2408- 4 OUTA or OUTB 2X CLKIN 2XCLKIN PI6C2408- 6 OUTA CLKIN CLKIN or CLKIN/2 PI6C2408- 6 OUTB CLKIN or 2X CLKIN CLKIN Note: 1. Output phase is indeterminant (0° or 180° from CLKIN) 08-0298 2 PS8589K 11/06/08 PI6C2408 Zero-Delay Clock Buffer Pin Description Pin Signal 1 D e s cription C LK IN Input clock reference frequency (weak pull- down) O UTA[1- 4] C lock output, Bank A (weak pull- down) 4, 13 VDD 3.3V supply 5, 12 GN D Ground O UTB[1- 4] C lock output, Bank B (weak pull- down) 8 SEL2 Select input, bit 2 (weak pull- up) 9 SEL1 Select input, bit 1 (weak pull- up) 16 FB_IN PLL feedback input 2, 3, 14, 15 6, 7, 10 ,11 Zero Delay and Skew Control CLKIN - Input to OUTA/OUTB Delay (ps) CLKIN Input to Output Bank Delay vs. Difference in Loading between FB_IN pin and OUTA/OUTB pins 800 600 400 200 0 -200 -25 -20 -15 -10 0 -5 -400 5 10 15 20 25 PI6C2408-1H -600 -800 PI6C2408-1,2,3,4,6 -900 -1000 Output Load Difference: FB_IN Load - OUTA/OUTB Load (pF) The relationship between loading of the FB_IN signal and other outputs determines the input-output delay. Zero delay is achieved when all outputs, including feedback, are loaded equally. Maximum Ratings Supply Voltage to Ground Potential ............................................................................................................................. –0.5V to +7.0V DC Input Voltage (Except CLKIN) ........................................................................................................................ –0.5V to VDD +0.5V DC Input Voltage CLKIN ...................................................................................................................................................... –0.5 to 7V Storage Temperature ................................................................................................................................................... –65ºC to +150ºC Maximum Soldering Temperature (10 seconds) ........................................................................................................................... 260ºC Junction Temperature .................................................................................................................................................................. 150ºC Static Discharge Voltage (per MIL-STD-883, Method 3015) .................................................................................................... >2000V 08-0298 3 PS8589K 11/06/08 PI6C2408 Zero-Delay Clock Buffer Operating Conditions Parame te r VDD TA CL CIN D e s cription M in. M a x. 3.0 3 .6 3.135 3.465 0 70 Industrial O perating Temperature –40 85 Load Capacitance, below 100 MHz ⎯ 30 Load Capacitance, from 100 MHz to 140MHz ⎯ 15 Input Capacitance ⎯ 7 Supply Voltage Commercial Industrial Commerical O perating Temperature Units V ºC pF DC Electrical Characteristics for Industrial Temperature Devices Parame te r De s cription Te s t Conditions M in. M ax. VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current VIN = 0V 5 0 .0 IIH Input HIGH Current VIN = VDD 100.0 VOL Output LOW Voltage IOL = 8mA (–1, –2, –3,–4, –6); IOL = 12mA (–1H) VOH Output HIGH Voltage IOH = –8mA (–1, –2, –3,–4, –6); IOH = –12mA (–1H) IDD (PD mode) Pwr Dwn Supply Current SEL1 = 0 (–1, –2, –3, –4, –1H); SEL2 = 0 (–6) 2 5 .0 IDD Supply Current Unloaded outputs 100 MHz, Select inputs at VDD or GND 54.0 Units 0.8 V 2.0 μA 0. 4 V 2.4 μA 70.0 (–1H) mA 08-0298 Unloaded outputs 66 MHz, CLKIN, except (–1H) 3 9 .0 Unloaded outputs 33MHz, CLKIN, except (–1H) 20.0 4 PS8589K 11/06/08 PI6C2408 Zero-Delay Clock Buffer AC Electrical Characteristics for Industrial Temperature Devices Parame te rs N ame FO O utput Frequency tDC Duty C ycle(1) (–1, –2, –3, –4, –6) Duty tR (–1H) 30pF load M in. Typ. M ax. Units 100 10 15pF load Measured at VDD/2, FOUT <66.67MHz 30pF load Measured at VDD/2, FOUT <140 MHz 15pF load 140 40 Measured at VDD/2, FOUT <45 MHz 30pF load 45 Measured at VDD/2, FOUT <66.67MHz 30pF load 45 Measured at VDD/2, FOUT <140 MHz 15pF load 40 60 Measured at VDD/2, FOUT <45MHz 30pF load 45 55 50 Measured between 0.8V and 2.0V, 15pF load 1.8 Measured between 0.8V and 2.0V, 30pF load 1.6 Measured between 0.8V and 2.0V, 30pF load 2.2 Measured between 0.8V and 2.0V, 15pF load 1.5 Fall Time(1) (–1H) Measured between 0.8V and 2.0V, 30pF load 1.25 O utput to O utput Skew(1) within same Bank All outputs equally loaded Rise Time(1) –2, –4, –6) (–1H) Fall Time(1) (–1, –2, –4, –6) ps Delay, C LK IN Rising Edge to FB_IN Rising Edge(1) Measured at VDD/2 tSK(D) Device- to- Device Skew(1) Measured at VDD/2 on FB_IN pins of devices tJIT O utput Slew C ycle- to- C ycle Jitter(1) (–1, –1H, –4) C ycle- to- C ycle Jitter(1) (–2, –6) tLOCK PLL Lock Time(1) ns 400 t0 Rate(1) % 250 O utput Bank A to O utput Bank B Skew(1) tSLEW 55 2.5 Rise Time(1) (–1, MHz 60 Measured between 0.8V and 2.0V, 30pF load tF tSK(O) C ycle(1) Te s t Conditions Measured between 0.8V & 2.0V on –1H device using Test C rt #2 900 0 500 1 V/ns Measured at 66.67 MHz, loaded 30pF load 250 Measured at 140 MHz, loaded 15pF load 150 Measured at 66.67 MHz, loaded 30pF load 400 Stable power supply, valid clocks presented on C LK IN and FB_IN pins 1.0 ps ms Notes: 1. See Switching Waveforms on page 7. 08-0298 5 PS8589K 11/06/08 PI6C2408 Zero-Delay Clock Buffer DC Electrical Characteristics for Commercial Temperature Devices Parame te r De s cription Te s t Conditions M in. M ax. VIL Input LOW Voltage ⎯ ⎯ 0.8 VIH Input HIGH Voltage ⎯ 2.0 ⎯ IIL Input LOW Current VIN = 0V ⎯ 50 IIH Input HIGH Current VIN = VDD ⎯ 100 VOL Output LOW Voltage IOL = 8mA (–1, –2, –3,–4, –6); IOL = 12mA (–1H) ⎯ 0.4 VOH Output HIGH Voltage IOH = –8mA (–1, –2, –3,–4, –6); IOH = –12mA (–1H) 2 .4 ⎯ IDD (PD mode) Power Down Supply Current SEL1 = 0 (- 1,- 2,- 3,- 4,- 1H); SEL2 = 0 (- 6) ⎯ 12 IDD Supply Current Unloaded outputs, 66.67 MHz, Select inputs at VDD or GND ⎯ 39 IDD Supply Current Unloaded outputs 100 MHz Select Inputs @ VDD or GND ⎯ 54 Units V μA V μA mA AC Electrial Characteristics for Commercial Temperature Device Parame te rs N ame Te s t Conditions 30pF load M in. Typ. 10 M ax. Units 100 FO O utput Frequency tDC Duty C ycle(1) (–1H) Measured at VDD/2, for high drive output 45 50 55 Duty C ycle (–1, –2, –3, –4, –6) Measured at VDD/2, for normal drive output 40 50 60 tR tF t0 tSK(D) tSLEW tJIT Measured between 0.8V and 2.0V 2.5 Rise Time(1) @15pF Measured between 0.8V and 2.0V 1.8 Rise Time(1) @30pF (–1H) Measured between 0.8V and 2.0V 1.5 Fall Time(1) @30pF Measured between 0.8V and 2.0V 2.2 Fall Time(1) @15pF Measured between 0.8V and 2.0V 1.5 Measured between 0.8V and 2.0V 1.25 All outputs equally loaded, VDD/2 250 O utput Bank A to O utput Bank B S k ew All outputs equally loaded, VDD/2 400 Input- to- O utput Delay, C LK IN Rising Edge to FB_IN Rising Edge(1) Measured at VDD/2 Device to Device Skew(1) Measured at VDD/2 on FB_IN pins of devices Time(1) @30pF O utput- to- O utput bank O utput Slew (–1H) Skew(1) within same Rate(1) C ycle- to- C ycle Jitter (1)(–1,–1H,–4) C ycle- to- C ycle tLOCK 140 Rise Time(1) @30pF Fall tSK(O) 15pF load Jitter(1) (–2,–3,–6) PLL Lock Time(1) MHz % ns ps Measured between 0.8V and 2.0V on –1H device using Test C ircuit #2 900 0 500 1 V/ns Measured at 66.67 MHz, loaded 30pF outputs 250 Measured at 140 MHz, loaded 15pF outputs 150 Measured at 66.7 MHz, loaded 30pF outputs 400 Stable power supply, valid clocks presented on C LK IN and FB_IN pins 1.0 ps ms Notes: 1. See Switching Waveforms on page 7. 08-0298 6 PS8589K 11/06/08 PI6C2408 Zero-Delay Clock Buffer Switching Waveforms tHIGH Duty Cycle Timing VDD/2 All Outputs Rise/Fall Time OUTPUT Output-Output Skew OUTPUT VDD/2 2.0V 0.8V tR tLOW tDC = VDD/2 tHIGH tHIGH + tLOW 3.3V 2.0V 0.8V tF 0V VDD/2 VDD/2 OUTPUT tSK(O) Device-Device Skew OUTPUT Device 1 VDD/2 VDD/2 OUTPUT Device 2 tSK(D) Input-Output Propagation Delay INPUT VDD/2 VDD/2 FB_IN t0 Test Circuit 1 0.1μF 0.1μF VDD OUTPUTS 0.1μF CLK out CLOAD VDD GND Test Circuit 2 1kW CLK out OUTPUTS 0.1μF 1kW VDD GND GND 10pF GND Test Circuit for tSLEW ,Output slew rate on –1H device Test Circuit for all parameters except tSLEW 08-0298 VDD 7 PS8589K 11/06/08 PI6C2408 Zero-Delay Clock Buffer 16-Pin SOIC (W) Package DOCUMENT CONTROL NO. PD - 1004 16 REVISION: E DATE: 03/09/05 .149 .157 3.78 3.99 1 .0099 .0196 .386 .393 9.80 10.00 0.25 [Û 0.50 .0075 .0098 Û .053 .068 1 .0155 .0260 0.393 0.660 REF 1.35 1.75 0.41 1.27 SEATING PLANE .050 BSC 1.27 .013 .020 0.330 0.508 .0040 0.10 .0098 0.25 .016 .050 .2284 .2440 5.80 6.20 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Notes: 1) Controlling dimensions in millimeters. 2) Ref: JEDEC MS-012D/AC 08-0298 0.19 0.25 DESCRIPTION: 16-Pin, 150-Mil Wide, SOIC PACKAGE CODE: W 8 PS8589K 11/06/08 PI6C2408 Zero-Delay Clock Buffer 16-Pin TSSOP (L) Package DOCUMENT CONTROL NO. PD - 1310 REVISION: E 16 DATE: 03/09/05 .169 .177 1 1 .0256 BSC 0.65 .193 .201 4.9 5.1 .007 .012 4.3 4.5 .004 .008 .047 max. 1.20 .002 .006 0.09 0.20 0.45 .018 0.75 .030 SEATING PLANE .252 BSC 6.4 0.05 0.15 0.19 0.30 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com Note: 1. Package Outline Exclusive of Mold Flash and Metal Burr 2. Controlling dimentions in millimeters 3. Ref: JEDEC MO-153F/AB DESCRIPTION: 16-Pin, 173-Mil Wide, TSSOP PACKAGE CODE: L 08-0298 9 PS8589K 11/06/08 PI6C2408 Zero-Delay Clock Buffer Ordering Information (Commercial Temperature Device) Ordering Code Package Description Operating Range PI6C2408-1WE W Pb-free & Green, 16-pin 150-mil SOIC Commercial PI6C2408-1HWE W Pb-free & Green, 16-pin 150-mil SOIC Commercial PI6C2408-2WE W Pb-free & Green, 16-pin 150-mil SOIC Commercial PI6C2408-3W W 16-pin 150-mil SOIC Commercial PI6C2408-3WE W Pb-free & Green, 16-pin 150-mil SOIC Commercial PI6C2408-4W W 16-pin 150-mil SOIC Commercial PI6C2408-4WE W Pb-free & Green, 16-pin 150-mil SOIC Commercial PI6C2408-1WE W Pb-free & Green 16-pin 150-mil SOIC Commercial PI6C2408-1HWE W Pb-free & Green 16-pin 150-mil SOIC Commercial PI6C2408-1LE L Pb-free & Green, 16-pin 173-mil TSSOP Commercial PI6C2408-1HLE L Pb-free & Green, 16-pin 173-mil TSSOP Commercial PI6C2408-4LE L Pb-free & Green, 16-pin 173-mil TSSOP Commercial PI6C2408-1LE L Pb-free & Green 16-pin 173-mil TSSOP Commercial PI6C2408-1HLE L Pb-free & Green 16-pin 173-mil TSSOP Commercial PI6C2408-1HLEX L Pb-free & Green, 16-pin 173-mil TSSOP Commercial 08-0298 10 PS8589K 11/06/08 PI6C2408 Zero-Delay Clock Buffer Ordering Information (Industrial Temperature Device) Ordering Code Package Description Operating Range PI6C2408-1WIE W Pb-free & Green, 16-pin 150-mil SOIC Industrial PI6C2408-1HWIE W Pb-free & Green, 16-pin 150-mil SOIC Industrial PI6C2408-2WE W Pb-free & Green, 16-pin 150-mil SOIC Commercial PI6C2408-2WIE W Pb-free & Green, 16-pin 150-mil SOIC Industrial PI6C2408-3WIE W Pb-free & Green, 16-pin 150-mil SOIC Industrial PI6C2408-4WIE W Pb-free & Green, 16-pin 150-mil SOIC Industrial PI6C2408-1LI L 16-pin 173-mil TSSOP Industrial PI6C2408-1LIE L Pb-free & Green, 16-pin 173-mil TSSOP Industrial Notes: 1. 2. 3. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ E = Pb-free and Green Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 08-0298 11 PS8589K 11/06/08