DESCRIPTION APPLICATIONS FEATURES BLOCK DIAGRAM

RS2253
Second‐Side Regulation Current Mode
PWM Power Switcher
DESCRIPTION
RS2253 combines a dedicated current mode PWM
controller with a high voltage power MOSFET. It is
optimized for high performance, low standby power, and
cost effective off‐line flyback converter applications in
sub 10W range.
RS2253 offers complete protection coverage with
automatic
self‐recovery
feature
including
Cycle‐by‐Cycle current limiting (OCP), over load
protection (OLP), VDD over voltage clamp and under
voltage lockout (UVLO). Excellent EMI performance is
achieved with Orister proprietary frequency Jiggling
technique together with soft switching control at the
totem pole gate drive output. The tone energy at below
20KHz is minimized in the design and audio noise is
eliminated during operation. RS2253 is offered in SOP‐8
package.
APPLICATIONS
•
•
•
•
•
•
•
Battery Charger
Digital Cameras and camcorder Adaptor
PDA power supplies
VCR, SVR, STB, DVD & DVCD Player SMPS
Set‐Top Box (STB) Power
Auxiliary Power Supply for PC and Server
Open‐frame SMPS
FEATURES
• Power on Soft Start Reducing MOSFET VDS
Stress
• Frequency Jiggling to reduce EMI
• Burst Mode Control For Improved Efficiency and
Minimum
• Standby power Design
• Audio Noise Free Operation
• Fixed 50KHz Switching Frequency
• Internal Synchronized Slope Compensation
• Low VDD Startup Current and Low Operating
Current
• Leading Edge Blanking on Current Sense Input
• Good
Protection
Coverage
With
Auto
Self‐Recovery
VDD Over Voltage Clamp and Under Voltage
Lockout with Hysteresis (UVLO)
Line Input Compensated Cycle‐by‐Cycle Over‐
current Threshold Setting For Constant Output
Power Limiting Over Universal Input Voltage
Range
Overload Protection (OLP)
Over Voltage Protection (OVP)
• RoHS Compliant and 100% Lead (Pb)‐Free and
Green (Halogen Free with Commercial Standard)
BLOCK DIAGRAM
Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, No. 233-1, Baociao Rd., Sindian Dist., New Taipei City 23145, Taiwan
RS2253
APPLICATION CIRCUIT
ORDER INFORMATION
Device
RS2253 Y Z
V1.0
Device Code
Y is package designator :
S: SOP‐8
Z is Lead Free designator :
P: Commercial Standard, Lead (Pb) Free and Phosphorous (P) Free Package
G: Green (Halogen Free with Commercial Standard)
2
February 2013
RS2253
PIN CONFIGURATION
PIN DESCRIPTION
Symbol
VDDG
VDD
FB
SENSE
DRAIN
GND
V1.0
Description
Internal Gate Driver Power Supply Pin
DC Power Supply Input Pin
Feedback input Pin. The PWM duty cycle is determined by voltage level
into this pin and the current‐sense signal at Pin 4
Current Sense Input Pin
HV MOSFET Drain Pin. The Drain pin is connected to the primary lead of
the transformer
Ground Pin
3
Pin
1
2
3
4
5, 6
7, 8
February 2013
RS2253
DETAIL DESCRIPTION
The RS2253 is a low power off‐line SMPS Switcher optimized for off‐line flyback converter applications in sub 10W
power range. The burst mode control greatly reduces the standby power consumption and helps the design easily to
meet the international power conservation requirements.
STARTUP CURRENT AND START UP CONTROL
Startup current of RS2253 is designed to be very low so that VDD could be charged up above UVLO threshold level and
device starts up quickly. A large value startup resistor can therefore be used to minimize the power loss yet achieve a
reliable startup in application. For AC/DC adaptor with universal input range design, a 2MΩ, 1/8W startup resistor could
be used together with a VDD capacitor to provide a fast startup and yet low power dissipation design solution.
OPERATION CURRENT
The Operation current of RS2253 is low at 2mA. Good efficient is achieved with RS2253 low operating current together
with the ‘Extended burst mode’ control features.
SOFT START
RS2253 features an internal 4 ms soft start to soften the electrical stress occurring in the power supply during startup. It
is activated during the power on sequence. As soon as VDD reaches UVLO(OFF), the peak current is gradually increased
from nearly zero to the maximum level of 0.77V. Every restart up is followed by a soft start.
FREQUENCY JIGGLING MODE FOR EMI IMPROVEMENT
The frequency Jiggling Mode (switching frequency modulation) is implemented in RS2253. The oscillation frequency is
modulated so that the tone energy is spread out. The spread spectrum minimizes the conduction band EMI and therefore
eases the system design.
EXTENDED BURST MODE OPERATION
At light load or zero load condition, most of the power dissipation in a switching mode power supply is from switching loss
on the MOSFET, the core loss of the transformer and the loss on the snubber circuit. The magnitude of power loss is in
proportion to the switching frequency. Lower switching frequency leads to the reduction on the power loss and thus
conserves the energy.
The switching frequency is internally adjusted at no load or light load condition. The switch frequency reduces atlight/no
load condition to improve the conversion efficiency. At light load or no load condition, the FB input drops below burst
mode threshold level and device enters Burst Mode control. The Gate drive output switches only when VDD voltage drops
below a preset level and FB input is active to output an on state to minimize the switching loss and reduce the standby
power consumption to the greatest extend.
The switching frequency control also eliminates the audio noise at any loading conditions.
OSCILLATOR OPERATION
The switching frequency of RS2253 is internally fixed at 50 KHz. No external frequency setting components are required
for PCB design simplification.
V1.0
4
February 2013
RS2253
CURRENT SENSING AND LEADING EDGE BLANKING
Cycle‐by‐Cycle current limiting is offered in RS2253 current mode PWM control. The switch current is detected by sense
resistor into the sense pin. An internal leading edge blank circuit chops off the sensed voltage spike at initial internal
power MOSFET on state due to snubber diode reverse recovery and surge gate current of internal power MOSFET so
that the external RC filtering on sense input is no longer needed. The current limiting comparator is disabled and cannot
turn off the internal power MOSFET during the blanking period. The PWM duty cycle is determined by the current sense
input voltage and the FB input voltage.
INTERNAL SYNCHRONIZED SLOPE COMPENSATION
Built‐in slope compensation circuit adds voltage ramp onto the current sense input voltage for PWM generation. This
greatly improves the close loop stability at CCM and prevents the sub‐harmonic oscillation and thus reduces the output
ripple voltage.
DRIVE
The internal power MOSFET in RS2253 is driven by a dedicated gate driver for power switch control. Too weak the gate
driving strength results in higher conduction and switch loss of MOSFET while too strong gate drive results the
compromise of EMI.
A good tradeoff is achieved through the built‐in totem pole gate design with right output strength and dead time control.
The low idle loss and good EMI system design is easier to achieve with this dedicated control scheme.
In addition to the gate drive control scheme mentioned, the gate drive strength can also be adjusted externally by a
resistor connected between VDD and VDDG, the falling edge of the Drain output can be well controlled. It provides great
flexibility for system EMI design.
PROTECTION CONTROLS
Good power supply system reliability is achieved with its rich protection features including Cycle‐by‐Cycle current
limiting (OCP), Over Load Protection (OLP) and over voltage clamp, Under Voltage Lockout on VDD (UVLO).
With PTC, the OCP is line voltage compensated to achieve constant output power limit over the universal input voltage
range.
At overload condition when FB input voltage exceeds power limit threshold value for more than TD_PL, control circuit
reacts to shut down the switcher. Switcher restarts when VDD voltage drops below UVLO limit.
VDD is supplied by transformer auxiliary winding output. It is clamped when VDD is higher than 30V. The output of RS2253
is shut down when VDD drops below UVLO(ON) limit and Switcher enters power on start‐up sequence thereafter.
V1.0
5
February 2013
RS2253
ABSOLUTE MAXIMUM RATINGS
Parameter
Drain Voltage (off state)
VDD Voltage
VDDG Input Voltage
VDD Clamp Continuous Current
FB Input Voltage
Sense Input Voltage
Operating Ambient Temperature
Storage Temperature
Lead Temperature (soldering, 10sec)
ESD Voltage Protection, Human Body Model
ESD Voltage Protection, Machine Model
Symbol
VDRAIN
VDD
VDDG IN
IVDD CLAM
VFB IN
VSENSE IN
TOPR
TSTG
-
Ratings
‐0.3 to 650
‐0.3 to 30
‐0.3 to 30
10
‐0.3 to 7
‐0.3 to 7
‐40 to +85
‐40 to +150
+260
2
200
Unit
V
V
V
mA
V
V
o
C
o
C
o
C
KV
V
Notes:
1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
function operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute‐maximum–rated conditions for extended periods may affect device reliability.
2. Caution: Stress above the listed absolute maximum rating may cause permanent damage to the device. * HBM B: 2000V to 3999V
OUTPUT POWER TABLE
SOP‐8 Package
230VAC ±15%
Open Frame*
10W
85 to 265VAC
Open Frame*
8W
°
Note: * = Maximum practical continuous power in an open frame design with sufficient drain pattern as a heat sink, at 50 C ambient.
V1.0
6
February 2013
RS2253
ELECTRICAL CHARACTERISTICS
TA=25°C, VDD=16V, unless otherwise specified
Parameter
Supply Voltage (VDD)
Symbol
Feedback Bias Current
Istartup
Operation Current
VDD Under Voltage Lockout Enter
VDD Under Voltage Lockout
Exit(Recovery)
IVDD
UVLO(ON)
UVLO(OFF)
Over voltage protection voltage
OVP(ON)
VDD Zener clamp Voltage
Feedback Input Section(FB pin)
VFB Open Loop Voltage
VDD
FB pin short circuit current
IFB_SHORT
Zero Duty Cycle FB Threshold
Voltage
Power Limiting FB Threshold
Voltage
Power Limiting Debounce Time
Input Impedance
Current Sense Input(Sense Pin)
Soft start time
Leading edge blanking time
Input Impedance
Over Current Detection and
Control Delay
Internal Current Limiting Threshold
Voltage
Oscillator
Normal Oscillation Frequency
Frequency Temperature Stability
Frequency Voltage Stability
Maximum Duty Cycle
Burst Mode Base Frequency
Power MOSFET Section
MOSFET Drain Source
Breakdown Voltage
Static Drain to Source On
Resistance
Frequency
Frequency Modulation Range
/Base Frequency
V1.0
VFB
CLAMP
OPEN
Test Conditions
Min
Typ.
Max
Unit
‐
3.0
20.0
μA
-
14.2
2.0
14.8
16.0
mA
V
-
8.5
9.0
9.5
V
27.0
28.5
30.0
V
-
30.0
-
V
5.4
5.6
6.0
V
-
1.55
-
mA
VDD=14.5V, Measure
Leakage current into VDD
VFB=3V
CS=0V, FB=3V Ramp up VDD
until gate clock is off
IDD=10mA
Short FB pin to GND and
measure current
VTH_0D
-
-
0.8
-
V
VTH_PL
-
-
3.7
-
V
TD PL
ZFB IN
-
-
50.0
4.0
-
mS
KΩ
-
4.0
300.0
40.0
-
mS
nS
KΩ
TD_OC
From Over Current Occurs till the
Gate drive output start to turn off
-
120.0
-
nS
VTH_OC
FB=3.3V
0.76
0.80
0.82
V
FB=3.3V, CS=0V
-
45.0
70.0
-
50.0
5.0
5.0
80.0
22.0
55.0
90.0
-
KHz
%
%
%
KHz
TSOFTSTART
TBLANKING
ZSENSE IN
FOSC
ΔFTEMP
ΔF_VDD
DMAX
FBURST
B_VDSS
-
-
650.0
-
V
RDS(ON)
VGS=10V, IDS=1A
-
5.0
5.8
Ω
ΔF_VDD
-
-4.0
-
4.0
%
7
February 2013
RS2253
PACKAGE INFORMATION
8-PIN, SOP
Notes:
1. All units are in millimeter
2. Refer to JEDEC MS‐012 variation AA.
V1.0
8
February 2013
RS2253
IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and to discontinue any product without notice at any time.
PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No
circuit patent licenses are implied.
Princeton Technology Corp.
2F, 233-1, Baociao Road,
Sindian, Taipei 23145, Taiwan
Tel: 886-2-66296288
Fax: 886-2-29174598
http://www.princeton.com.tw
V1.0
9
February 2013