PT2257 Electronic Volume Controller IC DESCRIPTION The PT2257 is an electronic volume controller IC utilizing CMOS technology specially designed for the new generation of AV entertainment products. It has two (2) built-in channels making it ideally suitable for mono and stereo sound applications. The PT2257 provides an I2C control interface, an attenuation range of 0 to -79dB, low noise, and high channel separation. It is housed in an 8-pin, DIP or SOP package. The PT2257’s pin assignments and application circuit are optimized for easy PCB layout and cost saving advantages. FEATURES • • • • • • • • CMOS technology Low power consumption Least external components Attenuation range: 0 to -79dB at 1dB/step Operating voltage: 3 to 9V Low Noise, S/N Ratio>100dB (A-weighting) Two channel output Available in 8-pin, DIP or SOP APPLICATIONS • • • • • AV surround audio equipment Car audio Mini compo Computer multi-media speaker Other audio equipment BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, No. 233-1, Baociao Rd., Sindian Dist., New Taipei City 23145, Taiwan PT2257 APPLICATION CIRCUIT ORDER INFORMATION Part Number PT2257-D PT2257-S Package Type 8-Pin, DIP, 300mil 8-Pin, SOP, 150mil Top Code PT2257-D PT2257-S PIN CONFIGURATION PIN DESCRIPTION V1.5 Pin Name I/O LIN I LOUT O VSS SDA SCL VDD I I - ROUT O RIN I Description Left input channel Connect a capacitor to audio source Left output channel Connect a capacitor to audio output Ground I2C data input I2C clock input Power supply Right output channel Connect a capacitor to audio output Right input channel Connect a capacitor to audio source 2 Pin No. 1 2 3 4 5 6 7 8 March 2013 PT2257 FUNCTION DESCRIPTION BUS INTERFACE Data are transmitted to and from the microprocessor to the PT2257 via the SDA and SCL. The SDA and SCL make up the BUS Interface. It should be noted that the pull-up resistors must be connected to the positive supply voltage. DATA VALIDITY A data on the SDA Line is considered valid and stable only when the SCL Signal is in HIGH State. The HIGH and LOW States of the SDA Line can only change when the SCL signal is LOW. Please refer to the figure below. START AND STOP CONDITIONS A Start Condition is activated when 1. The SCL is set to HIGH and 2. SDA shifts from HIGH to LOW state. The Stop Condition is activated when 1. SCL is set to HIGH and 2. SDA shifts from LOW to HIGH state. Please refer to the timing diagram below. BYTE FORMAT Every byte transmitted to the SDA Line consists of 8-bit. Each byte must be followed by an Acknowledge Bit. The MSB is transmitted first. V1.5 3 March 2013 PT2257 ACKNOWLEDGE During the Acknowledge Clock Pulse, the master (µP) puts a resistive HIGH level on the SDA Line. The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge Clock Pulse so that the SDA Line is in a Stable Low State during this Clock Pulse. Please refer to the diagram below. The audio processor that has been addressed has to generate an Acknowledge after receiving each byte; otherwise, the SDA Line will remain at the High Level during the ninth (9th) Clock Pulse. In this case, the master transmitter can generate the STOP Information in order to abort the transfer. TRANSMISSION WITHOUT ACKNOWLEDGE If you want to avoid the acknowledge detection of the audio processor, a simpler µP transmission may be used. Wait one clock and does not check the slave acknowledge of this same clock then send the new data. If you use this approach, there are greater chances of faulty operation as well as decrease in noise immunity. INTERFACE PROTOCOL The interface protocol consists of the following: • • • • • A Start bit A Chip Address byte=88H ACK=Acknowledge bit A Data byte A Stop bit Please refer to the diagram below: PT2257 Address MSB START 1 First Byte 0 0 0 1 LSB 0 0 0 ACK MSB LSB DATA ACK MSB LSB DATA ACK STOP DATA TRANSMITTED (N-BYTES+ACKNOWLEDGE) Notes: 1. ACK=Acknowledge 2. Max. clock speed=100K bits/s V1.5 4 March 2013 PT2257 SOFTWARE SPECIFICATION PT2257 ADDRESS PT2257 Address is shown below: 1 MSB 0 0 0 1 0 0 0 LSB I2C BUS INTERFACE START TIME After Power is turned ON, PT2257 needs to wait for a short time in order to insure stability. The waiting time period for PT2257 to send I2C Bus Signal is at least 200ms. If the waiting time period is less than 200ms, I2C Control may fail. Please refer to the diagram below. V1.5 5 March 2013 PT2257 DATA BYTES DESCRIPTION FUNCTION BITS MSB 1 1 1 1 1 0 0 2 1 1 1 0 0 0 0 3 1 0 1 1 1 1 1 4 1 1 0 0 1 0 1 5 1 A3 0 A3 0 A3 0 6 1 A2 B2 A2 B2 A2 B2 7 1 A1 B1 A1 B1 A1 B1 LSB 1 A0 B0 A0 B0 A0 B0 0 1 1 1 1 0 0 M Function Function OFF (-79dB) 2-Channel, -1dB/step 2-Channel, -10dB/step Left Channel, -1dB/step Left Channel, -10dB/step Right Channel, -1dB/step Right Channel, -10dB/step 2-Channel, MUTE When M=1, MUTE=ON When M=0, MUTE=OFF ATTENUATION UNIT BIT A3 0 0 0 0 0 0 0 0 1 1 A2/B2 0 0 0 0 1 1 1 1 0 0 A1/B1 0 0 1 1 0 0 1 1 0 0 A0/B0 0 1 0 1 0 1 0 1 0 1 Attenuation Value (dB) 0/0 -1/-10 -2/-20 -3/-30 -4/-40 -5/-50 -6/-60 -7/-70 -8/ -9/ Where: Ax=-dB/step, Bx=-10dB/step For example, for a Left Channel Attenuation at -33dB, the data byte is as follows: START 1 0 1 1 0 0 1 1 ACK 1 0 1 0 Left Channel -30dB V1.5 0 0 1 1 ACK STOP Left Channel -3dB 6 March 2013 PT2257 ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage Operating temperature Storage temperature Input voltage Symbol VDD Topr Tstg VI Rating 12 0 to +70 -40 to +150 -0.3 to VCC+0.3 Unit V ℃ ℃ V AUDIO SECTION ELECTRICAL CHARACTERISTICS Parameter Operating voltage Operating current Attenuation step Joint step gain error Inter-channel attenuation gain error ASTEP GERR Min. 3 -0.5 -72 - CERR - 0.5 - dB Maximum output level Vomax 2.0 2.3 2.5 Vrms - 0.07 0.09 - 0.003 0.005 - 2 3 μVrms 90 110 100 120 103 123 dB Volume attenuation range Total harmonic distortion Noise output Symbol VDD IDD ARANGE THD No Conditions VDD=9V, VI=0V Minimum Attenuation Maximum Attenuation VDD=9V, F=1KHz Volume Att=0dB Rload=50K, THD<1% F =1KHz, Vout=2Vrms Volume Att=0dB, A-weighted Vout=200m Vrms Rload=50K Vin=GND, MUTE=OFF Volume Att=0dB, A-weighted 22~22KHz A-weighted 0dB=Vomax, ATT=0dB Typ. 9 9 0 -79 1 0.5 Max. 10 15 - Unit V mA dB dB dB % Signal-to-Noise ratio SNR Channel separation CS Vin=2.5Vrms, F=1KHz,Volume=0dB 100 120 125 dB MUTE Vin=2.5Vrms, F=1KHz Volume Att=0dB, A-weighted 90 95 97 dB Frequency response FR Vin=1Vrms, Volume Att=-10dB - 1 1.3 MHz Input impedance Rin F=1KHz 15 20 26 KΩ Output impedance Rout F=1KHz, Vout=100m Vrms - 100 - Ω Minimum load resistance Rload VDD=9V, Vo=2Vrms,THD<1% 2 - - KΩ Mute attenuation V1.5 7 March 2013 PT2257 I2C BUS SECTION ELECTRICAL CHARACTERISTICS Parameter Bus high input level Bus low input level Symbol VIH VIL Condition VDD=9V VDD=9V Min. 0.4 0 Typ. - Max. VDD 0.2 Unit VDD VDD BUS LINE TIMING CHARACTERISTICS Parameter Low level input voltage High level input voltage SCL clock frequency Time the bus must be free before a new transmission can start Hold time start condition(Note1) Clock low period Clock high period Setup time for start condition(Note2) Data hold time Data setup time Rise time (SDA & SCL Lines) Fall time (SDA & SCL Lines) Stop condition setup time Symbol VIL VIH fSCL Condition VDD=4.0V VDD=4.0V - Min. -0.5 1.6 0 Max. 1.1 4.0 100 Unit V V KHz tBUF - 5.0 - μs tHD-STA tLOW tHIGH tSU-STA tHD-DAT tSU-DAT tR tF tSU-STO - 4.0 5.0 4.0 5.0 0 250 4.0 1000 300 - μs μs μs μs μs ns ns ns μs Notes: 1. The first clock pulse is generated after this period. 2. This is only relevant for a repeated start condition. V1.5 8 March 2013 PT2257 d B V +0 20 -20 5 -40 1 -60 -80 No Weighted VCC=5V % A-Weighted 0.1 VCC=9V 0.01 -100 -120 20 VCC=3V 50 100 200 500 1k 2k 5k 20k 0.001 1m Hz 10m 100m 1 2 4 Vrms Residual Noise Floor THD vs. Output Level, RL=50KΩ 20 10 1 0.5 Vo=2.5Vrms 0.2 1 0.1 0.05 % Vo=1Vrms % 0.02 0.01 0.005 Vo=0.2Vrms 0.1 0.01 0.002 0.001 20 50 100 200 500 1k 2k 5k 0.001 1m 2m 20k 10m Hz THD vs. Frequency 500m 1 2 4 THD vs. Output Level, RL=5KΩ 20 10 5 +0 2 1 -20 -40 -60 d B 100m Vrms % -80 -100 0.1 0.02 0.01 -120 -140 20 50 100 200 500 1k 2k 5k 0.001 1m 2m 20k Hz 100m 500m 1 2 4 Vrms Crosstalk V1.5 10m THD vs. Output Level, RL=2KΩ 9 March 2013 PT2257 PACKAGE INFORMATION 8-PIN, DIP, 300MIL Symbol A A1 A2 b c e D E E1 L Min. 0.50 3.10 0.38 0.21 Nom. 3.30 2.54 BSC. 9.20 7.87 6.35 3.30 9.10 7.62 6.25 2.92 Max. 4.80 3.50 0.55 0.35 9.30 8.25 6.45 3.81 Notes: 1. Refer to JEDEC MS-001 BA. 2. All dimensions are in millimeter. V1.5 10 March 2013 PT2257 8-PIN, SOP, 150MIL Symbol A A1 A2 b c e D E E1 L θ Min. 1.35 0.08 1.20 0.33 0.17 Nom. 1.60 0.15 1.40 1.27 BSC 4.90 6.00 3.90 0.60 - 4.70 5.80 3.70 0.38 0° Max. 1.77 0.28 1.65 0.51 0.26 5.10 6.20 4.10 1.27 8° Notes: 1. Refer to JEDEC MS-012 AA. 2. All dimensions are in millimeter. V1.5 11 March 2013 PT2257 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian Dist., New Taipei City 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.5 12 March 2013