DESCRIPTION FEATURES

PT6301
5 x 7 Dot Character x 20-Digit x 2-Line
Display Controller/Driver with Character RAM
DESCRIPTION
The PT6301 is a 5 × 7 dot matrix type vacuum
fluorescent display tube controller driver IC which
displays characters, numerics and symbols of a
maximum of 20 digits × 2 lines. Dot matrix vacuum
fluorescent display tube drive signals are generated by
serial data sent from a micro-controller.
A display system is easily realized by internal ROM
and RAM for character display. PT6301 has low power
consumption since it is made by CMOS process
technology. Custom codes are provided on customer’s
request.
FEATURES
•
Logic power supply (VDD): 3.3V±10% or
5.0V±10%
• VFD tube drive power supply (VDISP ): 30 to 60V
• VFD driver output current(VFD driver output can
be connected directly to the VFD tube. No
pull-down resistor is required.)
- Segment driver (SEGA1 to A35, SEGB1 to
B35)
Only one driver output is high: -5mA @
VDISP-4V (VDISP=50V, Tj=25℃)
All the driver outputs are high: -350mA @
VDISP-4V (VDISP=50V, Tj=25℃)
- Segment driver (ADA, ADB): -15mA @
VDISP-4V (VDISP=50V, Tj=25℃)
- Grid driver (COM1 to 20): -40mA @ VDISP-4V
(VDISP=50V, Tj=25℃)
• Content of display
SEGA1 to SEGA35 and ADA
- CGROM_A 5 × 7 dots: 240 types (character data)
- CGRAM_A 5 × 7 dots: 16 types (character data)
- ADRAM_A 20 (display digit) × 1 bit (symbol data;
can be used for a cursor.)
- DCRAM_A 20 (display digit) × 8 bits (register for
character data display)
SEGB1 to SEGB35 and ADB
- CGROM_B 5 × 7 dots: 240 types (character data)
- CGRAM_B 5 × 7 dots: 16 types (character data)
- ADRAM_B 20 (display digit) × 1 bit (symbol data;
can be used for a cursor.)
- DCRAM_B 20 (display digit) × 8 bits (register for
character data display)
• Display control function
- Display digit: 1 to 20 digits
- Display duty (brightness adjustment): 0/1024 to
960/1024 stages
- All lights ON/OFF
• 4 interfaces with microcontroller : DA, CS, CP, and
RESET
• Built-in oscillation circuit (external R & C)
• Standby function
Inhibiting the oscillator circuit provides low power
consumption.
• Built-in CIG testing circuit
• Available in CIG package type
Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT6301
BLOCK DIAGRAM
V1.2
2
March 2012
PT6301
APPLICATION CIRCUIT
Notes:
*1. The VDISP voltage depends on the fluorescent display tube used. Adjust the value of the constants R2 and ZD to the VDISP voltage used.
*2. The value of R1 & C1 depend on PT6301 IC chip Supply voltage of VDD (R1=8.2KΩ, C1=39pF, when VDD=5V; R1=6.2KΩ, C1=39pF, when
VDD=3.3V).
V1.2
3
March 2012
PT6301
ORDER INFORMATION
Valid Part Number
PT6301
Package Type
CIG
Top Code
-
PIN CONFIGURATION
V1.2
4
March 2012
PT6301
PIN DESCRIPTION
Pin Name
SEGA1 ~ SEGA35
SEGB1 ~ SEGB35
I/O
Description
Pin No.
O
VFD tube anode electrode drive output.
Directly connected to fluorescent display tube and a pulldown resistor
is not necessary. IOH > -5mA
48 ~ 82
COM1 ~ COM20
O
ADA, ADB
O
V1.2
VDD
L-GND
VDISP
D-GND
-
TEST
I
DO
O
DA
I
CP
I
CS
I
RESET
I
OSC
I/O
VFD tube grid electrode drive output.
Directly connected to fluorescent display tube and a pulldown resistor
is not necessary. IOH > -40mA
VFD tube anode electrode drive output.
Directly connected to fluorescent display tube and a pulldown resistor
is not necessary. IOH > -15mA
VDD, L-GND are power supplies for internal logic.
VDISP, D-GND are power supplies for driving fluorescent tubes. Apply
VDISP after VDD is applied.
Use the same power supply for L-GND and D-GND.
Test mode control pin
“High” → Test mode enable
“Low” → Test mode disable
Data output pin for testing purpose only
Serial data input (positive logic).
Input from LSB.
Shift clock input.
Serial data is shifted on the rising edge of CP.
Chip select input.
Serial data transfer is disabled when CS pin is “H” level.
Reset input.
“Low” initializes all the functions.
Initial status is as follows.
• Address of each RAM ...address “00”H
• Data of each RAM......... Content is undefined
• Display digit....................20 digits
• Brightness adjustment....0/1024
• All lights ON or OFF ......OFF mode
Oscillation connection
An oscillator circuit is formed by connecting an external resistor and
capacitor at this pin. See Application circuit
5
13 ~ 47
11 ~ 2,
84 ~ 93
83, 12
97, 105
96, 106
1, 94
95, 107
98
99
100
101
102
103
104
March 2012
PT6301
FUNCTION DESCRIPTION
COMMAND LIST
NO.
COMMAND
1
DCRAM_A Data Write
MSB
B
B6
7
0
0
B
5
0
1ST BYTE
B
B3
4
1
*
LSB
MSB
2ND BYTE
LSB
B2
B1
B0
B7
B6
B5
B4
B3
B2
*
*
*
C7
*
*
*
*
*
*
D9
C6
C30
C31
C32
C33
C34
*
D8
C5
C25
C26
C27
C28
C29
*
D7
C4
C20
C21
C22
C23
C24
*
D6
C3
C15
C16
C17
C18
C19
*
D5
C2
C10
C11
C12
C13
C14
*
D4
C1
C5
C6
C7
C8
C9
*
D3
C0
C0
C1
C2
C3
C4
C0
D2
C7
*
*
*
*
*
*
C6
C30
C31
C32
C33
C34
*
C5
C25
C26
C27
C28
C29
*
C4
C20
C21
C22
C23
C24
*
C3
C15
C16
C17
C18
C19
*
C2
C10
C11
C12
C13
C14
*
C1
C5
C6
C7
C8
C9
*
C0
C0
C1
C2
C3
C4
C0
2
CGRAM_A Data Write
0
0
1
0
X3
X2
X1
X0
3
5
6
7
8
9
ADRAM_A Data Write
Display Duty Set
Number of digits set
All lights on/off
Test Mode
DCRAM_B Data Write
0
0
0
0
1
1
0
1
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
*
*
K3
*
T3
*
*
*
K2
*
T2
*
*
D1
K1
H
T1
*
*
D0
K0
L
T0
*
A
CGRAM_B Data Write
1
0
1
0
X3
X2
X1
X0
B
F
ADRAM_B Data Write
Standby Mode
1
1
0
1
1
1
1
1
*
*
*
*
*
*
*
*
B1
B0
2nd byte
3rd byte
4th byte
5th byte
6th byte
2nd byte
3rd byte
4th byte
5th byte
6th byte
*: Don’t care
Xn: Address specification for each RAM
Cn: Character code specification for each RAM
Dn: Display duty specification
Kn: Number of digits specification
Tn: Test mode specification
H: All lights ON instruction
L: All lights OFF instruction
When data is written to RAM (DCRAM, CGRAM, ADRAM) continuously, addresses are internally incremented
automatically.
Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later bytes.
Note:
The test mode is used for inspection before shipment. It is not a user function. The user cannot use this command. Enter commands 1 to 3, 5 to 7, 9 to
B, and F alone in the way described on the next page and the following pages. (The operation of this device cannot be guaranteed if other commands
are used.)
V1.2
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March 2012
PT6301
POSITIONAL RELATIONSHIP BETWEEN SEGn AND ADn (one digit)
C0
Co rr es pon ds to the 2 nd by te of the A DR AM _A data w rite c om m and.
AD A
C0
C1
C2
C3
C4
SE GA1
SE GA2
SE GA3
SE GA4
SE GA5
C5
C6
C7
C8
C9
SE GA6
SE GA7
SE GA8
SE GA9
SEGA 10
C 10
C11
C 12
C 13
C 14
S EGA11
SEGA 12
SEGA 13
SEGA 14
SEGA 15
C 15
C 16
C 17
C 18
C 19
SEGA 16
SEGA 17
SEGA 18
SEGA 19
SEGA 20
C 20
C 21
C 22
C 23
C 24
SEGA 21
SEGA 22
SEGA 23
SEGA 24
SEGA 25
C 25
C 26
C 27
C 28
C 29
SEGA 26
SEGA 27
SEGA 28
SEGA 29
SEGA 30
C 30
C 31
C 32
C 33
C 34
SEGA 31
SEGA 32
SEGA 33
SEGA 34
SEGA 35
Co rr es pon ds
Co rr es pon ds
Co rr es pon ds
Co rr es pon ds
Co rr es pon ds
C0
to
to
to
to
to
the
the
the
the
the
6 th by te of th e CG RA M_ A d ata wr ite c om ma nd.
5 th by te of th e CG RA M_ A d ata wr ite c om ma nd.
4 th by te of th e CG RA M_ A d ata wr ite c om ma nd.
3 rd b yte of the C G RAM _A da ta wri te co mm and .
2 nd by te of the CG R AM _A data w rite c om m and.
Co rr es pon ds to the 2 nd by te of the A DR AM _B d ata wr ite c om ma nd.
AD B
C0
C1
C2
C3
C4
SE GB1
SE GB2
SE GB3
SE GB4
SE GB5
C5
C6
C7
C8
C9
SE GB6
SE GB7
SE GB8
SE GB9
SEGB 10
C 10
C11
C 12
C 13
C 14
S EGB11
SEGB 12
SEGB 13
SEGB 14
SEGB 15
C 15
C 16
C 17
C 18
C 19
SEGB 16
SEGB 17
SEGB 18
SEGB 19
SEGB 20
C 20
C 21
C 22
C 23
C 24
SEGB 21
SEGB 22
SEGB 23
SEGB 24
SEGB 25
C 25
C 26
C 27
C 28
C 29
SEGB 26
SEGB 27
SEGB 28
SEGB 29
SEGB 30
C 30
C 31
C 32
C 33
C 34
SEGB 31
SEGB 32
SEGB 33
SEGB 34
SEGB 35
Co rr es pon ds
Co rr es pon ds
Co rr es pon ds
Co rr es pon ds
Co rr es pon ds
to
to
to
to
to
the
the
the
the
the
6 th by te of th e CG RA M_ B da ta wri te co mm and .
5 th by te of th e CG RA M_ B da ta wri te co mm and .
4 th by te of th e CG RA M_ B da ta wri te co mm and .
3 rd b yte of the C G RAM _B data wr ite c om m and.
2 nd by te of the CG R AM _B d ata wr ite c om man d.
CO M n
V1.2
7
March 2012
PT6301
DATA TRANSFER METHOD AND COMMAND WRITE METHOD
Display control command and data are written by an 8-bit serial transfer.
Write timing is shown in the figure below.
Setting the CS pin to “Low” level enables a data transfer.
Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first).
As shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input into the
CP pin. If 8-bit data is input, internal load signals are automatically generated and data is written to each register and
RAM.
Therefore it is not necessary to input load signals from the outside.
Setting the CS pin to “High” disables data transfer. Data input from the point when the CS pin changes from “High” to
“Low” is recognized in 8-bit units.
t DOF F
t CS H
CS
CP
DA
W he n data is wr itten
to DC RAM *
B0 B1 B2 B3 B4 B5 B6 B7
B0 B1 B2 B3 B4 B5 B6 B7
B0 B1 B2 B3 B4 B5 B6 B7
LS B
LS B
LS B
1s t by te
M SB
Co mm and a nd ad dr es s data
2n d by te
M SB
Ch ar ac te r c ode d ata
3r d by te
M SB
Cha rac ter co de da ta o f th e
nex t add re ss
Note:
When data is written to RAM (DCRAM, ADRAM, CGRAM) continuously, addresses are internally incremented automatically. Therefore it is not
necessary to specify the 1st byte to write RAM data for the 2nd and later bytes.
RESET FUNCTION
Reset is executed when the RESET pin is set to “L”, (when turning power on, for example) and initializes all functions.
Initial status is as follows.
Address of each RAM.......................address “00”H
Data of each RAM.............................All contents are undefined
Display digit ......................................20 digits
Brightness adjustment ......................0/1024
All display lights ON or OFF..............OFF mode
Segment output.................................All segment outputs go “Low”
AD output..........................................All AD outputs go “Low”
Be sure to execute the reset operation when turning power on and set again according to “Setting Flowchart” after reset.
V1.2
8
March 2012
PT6301
DESCRIPTION OF COMMANDS AND FUNCTIONS
1 AND 9. DCRAM DATA WRITE
(Write the character code of CGROM and CGRAM to DCRAM)
DCRAM (Data Control RAM) has 20 address x 8-bit RAM to store character code of CGROM and CGRAM. Address
00H(0) to 13H(19) corresponds to COM1 to 20. The character code stored in DCRAM is CONVERTED TO A 5 x 7 dot
matrix character pattern via CGROM or CGRAM.
The DCRAM can store 20 characters. This command writes data from DCRAM address 00H.
COMMAND FORMAT
MSB
B7
B6
B5
B4
B3
B2
0/1
0
0
1
*
*
Note: 0: Select DCRAM_A, 1: Select DCRAM_B
1st Byte
(1st)
2nd Byte
(2nd)
MSB
B7
B6
C7
C6
B5
C5
B4
C4
B3
C3
B2
C2
B1
*
LSB
B0
*
Select DCRAM data write mode
(RAM address is set to 00H automatically)
B1
C1
LSB
B0
C0
Specifies character code of CGRAM and CGROM
(written into DCRAM address 00H)
To specify the character code of CGROM and CGRAM continuously to the next address, specify only character code as
follows. The address of DCRAM is automatically incremented.
2nd Byte
(3rd)
MSB
B7
B6
C7
C6
2nd Byte
(4th)
MSB
B7
B6
C7
C6
B5
C5
B4
C4
B5
C5
B4
C4
B3
C3
B3
C3
B2
C2
B2
C2
B1
C1
LSB
B0
C0
Specifies character code of CGRAM and CGROM
(written into DCRAM address 01H)
B1
C1
LSB
B0
C0
Specifies character code of CGRAM and CGROM
(written into DCRAM address 02H)
:
:
2nd Byte
(21th)
MSB
B7
B6
C7
C6
B5
C5
B4
C4
B3
C3
B2
C2
B1
C1
LSB
B0
C0
Specifies character code of CGRAM and CGROM
(written into DCRAM address 13H)
MSB
LSB
B7
B6
B5
B4
B3
B2
B1
B0 Specifies character code of CGRAM and CGROM
C7
C6
C5
C4
C3
C2 C1 C0 (written into DCRAM address 00H)
C0 (LSB) to C7 (MSB): Character code of CGROM and CGRAM (8 bits 256 characters)
*: Don’t care.
2nd Byte
(22th)
COM POSITIONS AND DCRAM ADDRESSES
DCRAM address
(HEX)
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
V1.2
DCRAM address
(HEX)
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
COM position
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
9
COM position
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
March 2012
PT6301
2 AND A. CGRAM DATA WRITE
(Specifies the addresses of CGRAM and write character pattern data)
CGRAM (Character Generator RAM) has 16 address x 35-bit RAM to store 5 x 7 dot matrix character patterns. A
character pattern stored in CGRAM can be displayed by specifying the character code in a DCRAM. The address of
CGRAM is assigned to 00H to 0FH. (All other addresses are CGROM addresses.) CGRAM can store 16 types of
character patterns.
COMMAND FORMAT
1st Byte
(1st)
MSB
B7
B6
0/1
0
B5
B4
B3
B2
B1
LSB
B0
1
0
X3
X2
X1
X0
Select CGRAM data write mode and specifies
CGRAM address (Ex. Specifies CGRAM address
00H)
Note: 0: Select CGRAM_A, 1: Select CGRAM_B
MSB
2nd Byte
(2nd)
3rd Byte
(3rd)
th
4 Byte
(4th)
B7
*
LSB
B6
C30
MSB
B7
B6
*
C31
MSB
B7
B6
*
C32
B5
C25
B5
C26
B5
C27
B4
C20
B4
C21
B4
C22
B3
C15
B3
C16
B3
C17
B2
C10
B2
C11
B2
C12
B0
C0
B1
C6
LSB
B0
C1
Specifies 2nd column data
(written into CGRAM address 00H)
B1
C7
LSB
B0
C2
Specifies 3rd column data
(written into CGRAM address 00H)
Specifies 4th column data
(written into CGRAM address 00H)
Specifies 5th column data
(written into CGRAM address 00H)
5 Byte
(5th)
MSB
B7
B6
*
C33
B5
C28
B4
C23
B3
C18
B2
C13
B1
C8
LSB
B0
C3
6th Byte
(6th)
MSB
B7
B6
*
C34
B5
C29
B4
C24
B3
C19
B2
C14
B1
C9
LSB
B0
C4
th
Specifies 1st column data
(written into CGRAM address 00H)
B1
C5
To specify the character pattern data continuously to the next address, specify only character pattern data as follows.
The address of CGRAM is automatically incremented. Specification of an address is unnecessary.
The 2nd to 6th byte (character pattern data) are regarded as one data item, so 200ns is sufficient for tDOFF time between
bytes.
V1.2
10
March 2012
PT6301
nd
2 Byte
(7th)
MSB
B7
B6
*
C30
B5
B4
B3
B2
B1
LSB
B0
C25
C20
C15
C10
C5
C0
Specifies 1st column data
(written into CGRAM address 01H)
B1
C9
LSB
B0
C4
Specifies 5th column data
(written into CGRAM address 01H)
：
：
th
6 Byte
(11th)
MSB
B7
B6
*
C34
B5
C29
B4
C24
B3
C19
B2
C14
X0 (LSB) to X3 (MSB): CGRAM address (4 bits 16 characters)
C0 (LSB) to C34 (MSB): Character pattern data (35 bits: 35 outputs per character)
*: Don’t care.
CGRAM ADDRESSES AND CORRESPONDING CGROM ADDRESS
HEX
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
X3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CGROM address
RAM00 (00000000B)
RAM01 (00000001B)
RAM02 (00000010B)
RAM03 (00000011B)
RAM04 (00000100B)
RAM05 (00000101B)
RAM06 (00000110B)
RAM07 (00000111B)
RAM08 (00001000B)
RAM09 (00001001B)
RAM0A (00001010B)
RAM0B (00001011B)
RAM0C (00001100B)
RAM0D (00001101B)
RAM0E (00001110B)
RAM0F (00001111B)
Note: Refer to ROM code tables
V1.2
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March 2012
PT6301
3 AND B. ADRAM DATA WRITE
(Writes symbol data)
ADRAM (Additional Data RAM) has 20 address x 1-bit RAM to store symbol data. Address 00H(0) to 13H(19)
corresponds to COM1 to 20. Symbol data stored in ADRAM is directly output without translation of CGROM and CGRAM.
The ADRAM can store 1 type of symbol patterns per each digit.
The terminal to which the contents of ADRAM are output can be used as a cursor. This command writes data from
ADRAM address 00H.
COMMAND FORMAT
1st Byte
(1st)
MSB
B7
B6
0/1
0
B5
B4
B3
B2
B1
LSB
B0
1
1
*
*
*
*
Select ADRAM data write mode
(RAM address is set to 00H automatically)
Note: 0: Select ADRAM_A, 1: Select ADRAM_B
MSB
2nd Byte
(2nd)
LSB
B7
B6
B5
B4
B3
B2
B1
B0
*
*
*
*
*
*
*
C0
Sets symbol data
(written into ADRAM address 00H)
To specify symbol data continuously to the next address, specify only symbol data as follows. The address of ADRAM is
automatically incremented.
2nd Byte
(3rd)
2nd Byte
(4th)
MSB
B7
B6
*
*
MSB
B7
B6
*
*
B5
B4
B3
B2
B1
*
*
*
*
*
B5
B4
B3
B2
B1
*
*
*
*
*
LSB
B0
C0
LSB
B0
C0
Sets symbol data
(written into ADRAM address 01H)
Sets symbol data
(written into ADRAM address 02H)
：
：
2nd Byte
(21th)
2nd Byte
(22th)
MSB
B7
B6
*
*
MSB
B7
B6
B5
B4
B3
B2
B1
*
*
*
*
*
B5
B4
B3
B2
*
*
*
*
*
*
C0: Symbol data (1 bit: 1-symbol data per digit)
LSB
B0
C0
LSB
B0
B1
*
C0
Sets symbol data
(written into ADRAM address 13H)
Sets symbol data
(re-written into ADRAM address 00H)
*: Don’t care.
COM POSITIONS AND ADRAM ADDRESSES
ADRAM address
(HEX)
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
V1.2
ADRAM address
(HEX)
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
COM position
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
12
COM position
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
March 2012
PT6301
DISPLAY DUTY SET
(Writes display duty value to duty cycle register)
Display duty adjusts brightness in 1024 stages using 10-bit data.
When power is turned on or when the RESET signal is input, the duty cycle register value is “0”. Always execute this
instruction before turning the display on, then set a desired duty value.
COMMAND FORMAT
MSB
1st Byte
(1st)
LSB
B7
B6
B5
B4
B3
B2
B1
B0
0
1
0
1
*
*
D1
D0
MSB
2nd Byte
(2nd)
Select display duty set mode and set duty value
(lower 2 bits)
LSB
B7
B6
B5
B4
B3
B2
B1
B0
D9
D8
D7
D6
D5
D4
D3
D2
Sets duty value
(upper 8 bits)
D0 (LSB) to D9 (MSB): Display duty data (10 bits: 1024 stages)
*: Don’t care
RELATION BETWEEN SETUP DATA AND CONTROLLED COM DUTY
HEX
D9
D8
D7
D6
D5
D4
D3
D2
000
0
0
0
0
0
0
0
0
001
0
0
0
0
0
0
0
0
002
0
0
0
0
0
0
0
0
：
3BE
1
1
1
0
1
1
1
1
3BF
1
1
1
0
1
1
1
1
3C0
1
1
1
1
0
0
0
0
3C1
1
1
1
1
0
0
0
0
：
3FF
1
1
1
1
1
1
1
1
*The state when power is turned on or when RESET signal is input.
D1
0
0
1
D0
0
1
0
1
1
0
0
0
1
0
1
1
1
COM duty
0/1024
1/1024
2/1024
：
958/1024
959/1024
960/1024
960/1024
：
960/1024
DISPLAY DUTY OUTPUT TIMING
Example: COM1
Solid line: For display duty is 960/1024
Doted line: For display duty is 64/1024
96 0/10 24
CO M 1
64 /102 4
SE G A (B ) 1 to 35
A DA (B )
V1.2
13
March 2012
PT6301
NUMBER OF DIGIT SET
(Writes the number of display digit to the display digit register)
This command can set the number of display digit between 5 to 20 digits using 4-bit data. When power is tuned on or
when a RESET signal is input, the number of digit register value is “0”. Always execute this instruction to change the
number of digit before turning the display on.
COMMAND FORMAT
MSB
1st Byte
(1st)
LSB
B7
B6
B5
B4
B3
B2
B1
B0
0
1
1
0
K3
K2
K1
K0
Select the number of digit set mode and specifies the
number of digit value
K0 (LSB) to K3 (MSB): the Number of digit data (4 bits: 5 to 20 digits)
*: Don’t care.
RELATION BETWEEN SETUP DATA AND CONTROLLED COM
The number of digit
HEX K0
of COM
0
0
0
0
0
COM1 to 20
8
0
1
1
0
0
0
COM1 to 5
9
1
2
0
1
0
0
COM1 to 6
A
0
3
1
1
0
0
COM1 to 7
B
1
4
0
0
1
0
COM1 to 8
C
0
5
1
0
1
0
COM1 to 9
D
1
6
0
1
1
0
COM1 to 10
E
0
7
1
1
1
0
COM1 to 11
F
1
*The state when power is turned on or when RESET signal is input.
HEX
K0
K1
K2
K3
K1
K2
K3
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
The number of digit
of COM
COM1 to 12
COM1 to 13
COM1 to 14
COM1 to 15
COM1 to 16
COM1 to 17
COM1 to 18
COM1 to 19
ALL DISPLAY LIGHTS ON/OFF SET
(Turns all display lights ON or OFF)
All display lights ON mode is used primarily for display resting.
(The display duty during ON mode is the value of the duty cycle register.)
All display lights OFF mode is primarily used for display blink and to prevent malfunction when power is turned on.
(All the segment output are “Low”, but COM outputs are still driving.)
COMMAND FORMAT
MSB
1st Byte
(1st)
LSB
B7
B6
B5
B4
B3
B2
B1
B0
0
1
1
1
*
*
H
L
Selects all display lights ON or OFF mode
H, L: Display operation data
*: Don’t care.
SET DATA AND DISPLAY STATE OF SEG AND AD
L
0
1
0
1
V1.2
H
0
0
1
1
Display state of SEG and AD
Normal display
Sets all outputs to Low
Sets all outputs to High
Sets all outputs to High
(The state when power is turned on or when RESET is input)
14
March 2012
PT6301
F. STAND-BY MODE
(Turning off all display-lights and stopped oscillation function)
This mode turns off all display-lights (fixing COM at “Low”) and stops oscillation function.
This completely stops the internal operation of the PT6301 and attains low power consumption of VDD and VDISP.
Note: If the RESET signal is input while the stand-by mode in progress, the stand-by mode is released and all states are
initialized.
COMMAND FORMAT
MSB
1st Byte
(1st)
LSB
B7
B6
B5
B4
B3
B2
B1
B0
1
1
1
1
*
*
*
*
Selects the stand-by mode
*: Don’t care.
RELEASING THE STAND-BY MODE
The timing to release the stand-by mode is shown below.
The stand-by mode is released at the falling edge of CS. (The internal oscillation starts)
When the oscillation becomes stable, the data input is enabled. (Return CS to “High” before entering data)
After the stand-by mode is released, all display-lights are turned off. Release the all display-lights OFF mode to turn on
the display-lights.
Da ta inpu t
CS
m or e th an 20 0ns
CP
m or e th an 20 0ns
B0 B1 B2 B3 B4 B5 B6 B7
LS B
Sta nd- by sta te
(O s ci lla tion s top)
OSC
F ir s t by te
M SB
N o rm all y op er atio n ( A ll ou tput ar e "Low ")
O s ci llati on s tate
O s ci llati on s tar ts
V1.2
15
March 2012
PT6301
SETTING FLOWCHART
(Power applying included)
POWER-OFF FLOWCHART
Display operation mode
Turn off VDISP
Turn off VDD
V1.2
16
March 2012
PT6301
COMMAND WRITE METHOD AND DATA TRANSFER METHOD FOR
TEST MODE
BASIC FLOW FOR TEST MODE
Test flow is shown as the following chart.
Detailed data format for each test are explained in the following pages.
TEST MODE LIST
TEST Mode 1
TEST Mode 2
TEST Mode 3
TEST Mode 4
TEST Mode 5
MSB
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
LSB
1
0
1
0
1
0
1
1
0
0
Oscillation stop with all output “Low”
Oscillation stop with all output “High”
Driver circuit check mode
DCRAM/ADRAM/DIGIT data output mode
CGRAM/CGROM data output mode
TEST MODE 1. OSCILLATION STOP WITH ALL OUTPUT “LOW”
In this test, you can confirm that all the driver output signals are changed to “L”. Also, you can measure the static IDO and
static IDISP without oscillation.
COMMAND FORMAT
MSB
1st Byte
(1st)
LSB
B7
B6
B5
B4
B3
B2
B1
B0
1
0
0
0
0
0
0
1
Selects TEST Mode 1
STATUS OF OUTPUT SIGNALS
COM1 to 20: All “L”
ADA, ADB: All “L”
SEGA1 to 35, SEGB1 to 35: All “L”
DO: “L”
TEST FLOW
V1.2
17
March 2012
PT6301
TEST MODE 2. OSCILLATION STOP WITH ALL OUTPUT “HIGH”
In this test, you can confirm that all the driver output signals are changed to “H”. Also, you can measure the static IDO
and static IDISP without oscillation.
COMMAND FORMAT
MSB
1st Byte
(1st)
LSB
B7
B6
B5
B4
B3
B2
B1
B0
1
0
0
0
0
0
1
0
Selects TEST Mode 2
STATUS OF OUTPUT SIGNALS
COM1 to 20: All “H”
ADA, ADB: All “H”
SEGA1 to 35, SEGB1 to 35: All “H”
DO: “H”
TEST FLOW
TEST MODE 3. DRIVER CIRCUIT CHECK MODE
In this mode, all driver outputs can be directly controlled by input data. Driver control data are input by serial transfer from
DA pin after TEST mode 3 is selected. Data input method is same as normal operation.
COMMAND FORMAT
1st Byte
(1st)
MSB
B7
B6
1
0
B5
B4
B3
B2
B1
LSB
B0
0
0
0
0
1
1
Selects TEST Mode 3
STATUS OF OUTPUT SIGNALS
COM1 to 20: Changed by input data
ADA, ADB: Changed by input data
SEGA1 to 35, SEGB1 to 35: Changed by input data
DO: Undefined
TEST FLOW
INPUT DATA FORMAT
92-bit data are written to DA pin.
First bit
COM <20:11>
10-bit
V1.2
ADA
1bit
SEGA <35:1>
35-bit
18
SEGB <35:1>
35-bit
ADB
1bit
Last bit
COM <1:10>
10-bit
March 2012
PT6301
TEST MODE 4. DCRAM/ADRAM/DIGIT DATA OUTPUT MODE
In this mode, contents of DCRAM and ADRAM for each digit can be confirmed. DCRAM and ADRAM for each digit must
be set before entering TEST mode 4.
COMMAND FORMAT
1st Byte
(1st)
MSB
B7
B6
1
0
B5
0
B4
0
B3
0
B2
1
B1
0
LSB
B0
0
Selects TEST Mode 4
STATUS OF OUTPUT SIGNALS
COM1 to 20: All “L”
ADA, ADB: All “L”
SEGA1 to 35, SEGB1 to 35: All “L”
DO: Data Out
TEST FLOW
OUTPUT DATA FORMAT
92-bit data digits are read from DO pin.
First bit
Digit
COM <20:11>
10-bit
V1.2
ADRAM_A
DCRAM_A <1:8>
Null
DCRAM_B <8:1>
ADRAM_B
1bit
8-bit
54-bit
8-bit
1bit
19
Last bit
Digit
COM <1:10>
10-bit
March 2012
PT6301
TEST MODE 5. CGRAM/CGROM DATA OUTPUT MODE
In this mode, content of CGRAM and CGROM can be confirmed. CGRAM must be set before entering TEST mode 5.
COMMAND FORMAT
1st Byte
(1st)
MSB
B7
B6
1
0
B5
B4
B3
B2
B1
LSB
B0
0
0
0
1
0
1
Selects TEST Mode 5
STATUS OF OUTPUT SIGNALS
COM1 to 20: All “L”
ADA, ADB: All “L”
SEGA1 to 35, SEGB1 to 35: All “L”
DO: Data Out
TEST FLOW
OUTPUT DATA FORMAT
92-bit data per character are read from DO pin.
First bit
Null
11-bit
V1.2
Last bit
CGRAM_A <35:1>
or
CGROM_A <35:1>
35-bit
CGRAM_B <35:1>
or
CGROM_B <35:1>
35-bit
20
Null
11-bit
March 2012
PT6301
ABSOLUTE MAXIMUN RATINGS
Parameter
Supply voltage (1)
Supply voltage (2)
Input voltage
Operating temperature
Storage temperature
Symbol
VDD
VDISP
VIN
Topr
Tstg
IO1
IO2
Output current
IO3
IO4
Condition
COM1 to COM16
ADA, ADB
SEGA1 to SEGA35,
SEGB1 to SEGB35
DO
Rating
-0.3 to +6.5
-0.3 to +70
-0.3 to VDD+0.3
-40 to +85
-65 to +150
-50 to 2.0
-25 to 2.0
Unit
V
V
V
℃
℃
mA
mA
-15 to 2.0
mA
-2 to 2.0
mA
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply voltage (1)
Symbol
VDD
Supply voltage (2)
VDISP
Operating frequency
fosc
Frame frequency
Junction temperature
fFR
Tj
V1.2
Condition
When the power supply voltage
is 5V (typ.)
When the power supply voltage
is 3.3V (typ.)
VDD=5.0V, C=39pF, R=8.2KΩ, Tj=25℃
VDD=3.3V, C=39pF, R=6.2KΩ, Tj=25℃
DIGIT=1 to 20, oscillation, Tj=25℃
-
21
Min.
Typ.
Max.
4.5
5.0
5.5
3.0
3.3
3.6
30
3.0
3.0
146
-40
4.0
4.0
195
-
60
5.0
5.0
215
+125
Unit
V
V
MHz
Hz
℃
March 2012
PT6301
DC CHARACTERISTICS
(Unless otherwise specified, VDD=5.0V±10%, VDISP=30 to 60V, Tj=-40 to +125℃)
Parameter
High level input
voltage
Low level input
voltage
High level input
current
Low level input
current
High level output
voltage
Low level output
voltage
Current
consumption (1)
Current
consumption (2)
Symbol
Applied Pin
Condition
Min.
Typ.
Max.
Unit
VIH
*1
-
0.8VDD
-
-
V
VIL
*1
-
-
-
0.2VDD
V
IIH
*1
VDO=VIN=5.0V
-1.0
-
+1.0
μA
IIL
*1
VDO=5.0V, VIN=0.0V
-1.0
-
+1.0
μA
VOH1
VOH2
COM1 to 20
ADA, ADB
SEGA1 to 35,
SEGB1 to 35
DO
*2
DO
VDD
VDISP=50V, IOH1=-40mA, Tj=25℃
VDISP=50V, IOH2=-15mA, Tj=25℃
VDISP-4
VDISP-4
-
-
V
V
VDISP=50V, IOH3=-5mA, Tj=25℃
VDISP-4
-
-
V
VDD=5.0V, IOH4=-400μA
VDISP=50V, IOL1=+1mA,Tj=25℃
VDD=5.0V, IOL2=+400μA
VDD=5.0V, fosc=4.0MHz
All output lights on
All output lights off
fosc=4.0MHz,
(Typ: Tj=25℃)
no load
(Max. Tj=85℃)
Stand-by mode
(Typ.: Tj=25℃)
(Max. Tj=85℃)
VDD-0.3
-
-
2.0
0.3
6
1
V
V
V
mA
mA
-
1.0
15.0
μA
-
1.0
1.0
μA
-
1.0
10.0
μA
VOH3
VOH4
VOL1
VOL2
IDO1
IDISP1
IDISP2
VDISP
IDD
VDD
IDISP
VDISP
(Unless otherwise specified, VDD=3.3V±10%, VDISP=30 to 60V, Tj=-40 to +125℃)
Parameter
High level input
voltage
Low level input
voltage
High level input
current
Low level input
current
High level output
voltage
Low level output
voltage
Current
consumption (1)
Current
consumption (2)
Symbol
Applied Pin
Condition
Min.
Typ.
Max.
Unit
VIH
*1
-
0.8VDD
-
-
V
VIL
*1
-
-
-
0.2VDD
V
IIH
*1
VDO=VIN=3.3V
-1.0
-
+1.0
μA
IIL
*1
VDO=3.3V, VIN=0.0V
-1.0
-
+1.0
μA
VOH1
VOH2
COM1 to 20
ADA, ADB
SEGA1 to 35,
SEGB1 to 35
DO
*2
DO
VDD
VDISP=50V, IOH1=-40mA, Tj=25℃
VDISP=50V, IOH2=-15mA, Tj=25℃
VDISP-4
VDISP-4
-
-
V
V
VDISP=50V, IOH3=-5mA, Tj=25℃
VDISP-4
-
-
V
VDD=3.3V, IOH4=-400μA
VDISP=50V, IOL1=+1mA,Tj=25℃
VDD=3.3V, IOL2=+400μA
VDD=3.3V, fosc=4.0MHz
VDD-0.3
-
-
2.0
0.3
4
V
V
V
mA
-
-
1
mA
-
1.0
15.0
μA
-
1.0
1.0
μA
-
1.0
10.0
μA
VOH3
VOH4
VOL1
VOL2
IDO1
IDISP1
IDISP2
VDISP
IDD
VDD
IDISP
VDISP
All output lights on
All output lights off
(Typ: Tj=25℃)
(Max. Tj=85℃)
Stand-by mode
(Typ.: Tj=25℃)
(Max. Tj=85℃)
fosc=4.0MHz
no load
Notes:
1. *1=CS, CP, DA, RESET
2. *2=SEGA1 to 35, SEGB1 to 35, ADA, ADB, COM1 to 20
V1.2
22
March 2012
PT6301
AC CHARACTERISTICS
(Unless otherwise specified, VDD=5.0V/3.3V±10%, VDISP=30 to 60V, Tj=-40 to +125℃)
Parameter
Symbol
Condition
CP frequency
fc
CP pulse width
tCW
DA setup time
tDS
DA hold time
tDH
CS setup time
tCSS
CS hold time
tCSH
Oscillation state
CS wait time
tCSW
Data processing time
tDOFF
Oscillation state
When RESET signal is input from
RESET pulse width
tWRES
microcontroller etc. externally
DA wait time
tRSOFF
tR
tR=20 to 80%
CI=100pF
All output slew rate
tF
tF=80 to 20%
V1.2
23
Min.
200
200
200
200
8
200
4
Max.
2.0
-
Unit
MHz
ns
ns
ns
ns
μs
ns
μs
200
-
ns
200
-
2.0
2.0
μs
μs
March 2012
PT6301
TIMING DIAGRAM
Symbol
VIH
VIL
VDD=3.3V±10%
0.8VDD
0.2VDD
VDD=5.0V±10%
0.8VDD
0.2VDD
DATA TIMING
RESET TIMING
HIGH VOLTAGE OUTPUT TIMING
DIGIT OUTPUT TIMING
(for 20-digit display, at a duty of 960/1024)
V1.2
24
March 2012
PT6301
ROM CODE
PT6301-001 (EUROPEAN)
V1.2
25
March 2012
PT6301
PT6301-002 (KATAKANA)
V1.2
26
March 2012
PT6301
PAD CONFIGURATION
Chip size: X=2.50mm, Y=10.14mm
Chip thickness: 280μm
PAD size
- Driver output: X=90μm, Y=60μm
(SEGA1 to 35, SEGB1 to 35, ADA, ADB,
COM1 to 20)
- Logic input/output: X=90μm, Y=65μm
(DA, CS, CP, RESET, OSC0, DO, TEST)
- Power: X=90μm, Y=80μm
(VDD, L-GND, VDISP, D-GND)
Alignment Mark;
V1.2
27
March 2012
PT6301
PAD LOCATION
(unit: μm)
V1.2
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Pad Name
VDISP
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
ADB
SEGB1
SEGB2
SEGB3
SEGB4
SEGB5
SEGB6
SEGB7
SEGB8
SEGB9
SEGB10
SEGB11
SEGB12
SEGB13
SEGB14
SEGB15
SEGB16
SEGB17
SEGB18
SEGB19
SEGB20
SEGB21
SEGB22
SEGB23
SEGB24
SEGB25
SEGB26
SEGB27
SEGB28
SEGB29
SEGB30
SEGB31
SEGB32
SEGB33
SEGB34
SEGB35
SEGA1
SEGA2
SEGA3
SEGA4
SEGA5
SEGA6
SEGA7
28
X
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
Y
4900
4615
4495
4375
4255
4135
4015
3895
3775
3655
3535
3415
3105
3015
2925
2835
2745
2655
2565
2475
2385
2295
2205
2115
2025
1935
1845
1755
1665
1575
1485
1395
1305
1215
1125
1035
945
855
765
675
585
495
405
315
225
135
45
-45
-135
-225
-315
-405
-495
-585
March 2012
PT6301
Pad No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
Alignment
Alignment
V1.2
Pad Name
SEGA8
SEGA9
SEGA10
SEGA11
SEGA12
SEGA13
SEGA14
SEGA15
SEGA16
SEGA17
SEGA18
SEGA19
SEGA20
SEGA21
SEGA22
SEGA23
SEGA24
SEGA25
SEGA26
SEGA27
SEGA28
SEGA29
SEGA30
SEGA31
SEGA32
SEGA33
SEGA35
SEGA35
ADA
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
VDISP
D-GND
L-GND
VDD
TEST
DO
DA
CP
CS
RESET
OSC
VDD
L-GND
D-GND
29
X
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
-1110
-1110
-1110
-1110
-1110
-1110
-1110
-1110
-1110
-1110
-1110
-1110
-1110
-1115
-1115
Y
-675
-765
-855
-945
-1035
-1125
-1215
-1305
-1395
-1485
-1575
-1665
-1755
-1845
-1935
-2025
-2115
-2205
-2295
-2385
-2475
-2565
-2655
-2745
-2835
-2925
-3015
-3105
-3415
-3535
-3655
-3775
-3895
-4015
-4135
-4255
-4375
-4495
-4615
-4900
-4860
-4655
-3015
-2385
-1575
-765
45
855
1665
2475
3015
4655
4860
4955
-4955
March 2012
PT6301
IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and to discontinue any product without notice at any time.
PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No
circuit patent licenses are implied.
Princeton Technology Corp.
2F, 233-1, Baociao Road,
Sindian, Taipei 23145, Taiwan
Tel: 886-2-66296288
Fax: 886-2-29174598
http://www.princeton.com.tw
V1.2
30
March 2012