BU2374FV
Multimedia ICs
VCO + phase comparator IC for PLL system
BU2374FV
BU2374FV is a VCO+phase comparator IC used to construct PLL system. PLL system is constructed and low
jitter clocks can be generated by adopting external LPF and divider. Through a mechanism incorporated in this
IC the output could be switched into quarter. Another function can set in the center point of frequency by
adjusting external resistance.
!Applications
TV
!External dimensions (Unit : mm)
5.0 ± 0.2
14
8
1
7
0.3Min.
1.15 ± 0.1 6.4 ± 0.3
4.4 ± 0.2
0.1
!Features
1) VDD=3.3V±5% operating guaranteed
2) Oscillating range of VCO is 37MHz~60MHz
3) High-speed edge trigger type phase comparator
4) VCO can be fine-adjusted by external resistor.
5) VCO and phase comparator can be controlled
independently.
6) Small SSOP-B14 package
0.15 ± 0.1
0.1
0.22 ± 0.1
0.65
SSOP-B14
!Absolute maximum ratings (Ta=25°C)
Symbol
Limits
Unit
Applied voltalge
VDD
−0.5 to +7.0
V
Inpuit voltage
VIN
−0.5 to VDD+0.5
V
Power dissipation
Pd
400∗
mW
Tstg
−30 to +125
°C
Parameter
Storage temperature
∗An operation is not guaranteed.
∗In case it is used at Ta=25°C or more, 4.0mW is reduceed at every 1°C.
∗Radiation resistance design is not used.
∗Power dissipation is measured when BU2374FV is placed on the board.
!Recommended operating conditions(Ta=25°C)
Symbol
Min.
Typ.
Max.
Unit
Supply voltage
Parameter
VDD
3.15
−
3.45
V
Input H voltage range
VIH
0.8VDD
−
VDD
V
Input L voltage range
VIL
0
−
0.2VDD
V
Topr
−20
−
+75
°C
CL
−
−
15
pF
Operating temperature
Output load
1/7
Phase Detect
Output
Frequency
Input 2
Frequency
Input 1
VCO Output
VCO
divide select
Logic
GND
Logic
VDD
Nmos Gate
Pmos Gate
Detector
Phase
Through
or 1/4
Level
Shifter
VCO
VCO
GND
VCO
VDD
Test Pin
(Normally L or Open)
Phase Detector Output-Enable
(H : disable L : enable)
VCO Powerdown and Output
disable
(H : disable L : enable)
VCO frequency Control input
(Force DC Voltage)
Bias resistor Terminal
(Connect a resistor between
vco VDD)
BU2374FV
Multimedia ICs
!Block diagram
2/7
BU2374FV
Multimedia ICs
!Pin descriptions
Pin No.
Functions
Pin name
1
LOGIC VDD
Digital VDD
2
SELECT
VCO output frequency select (H:1/4 output, L:1/1 output)
3
VCO OUT
VCO output
4
FIN-A
Input reference frequency is applied to Fin A
5
FIN-B
Input for VCO external counter output frequency
6
PFD_OUT
PD output
7
LOGIC_GND
Digital GND
8
TEST
TEST input with Pull-down resistor (Normaly OPEN or 'L')
9
PFD_INHIBIT
Contorol Pin for PD (H:PD disable (Hi impedance state), L:PD enable)
10
VCO_INHIBIT
VCO mode select (H:VCO OUT disable (L Fix), L:VCOOUT enable)
11
VCO_GND
GND for VCO (Analog GND)
12
VCO_IN
VCO control voltage input
13
BIAS
For adjusting VCO output frequency range
(An external resistor connect between VCO_VDD and BIAS)
14
VCO_VDD
VDD for VCO (Analog VDD)
3/7
BU2374FV
Multimedia ICs
!Input / output circuits
Pin No.
Equivalent circuit
Output Pin
(Pin3)
From inside IC
Output Pin
(Pin6)
From inside IC
From inside IC
Input Pin (Schmitt triger)
( Pin2, 4, 5, 8, 9, 10)
Pin8 : with pull-down
resistance
To inside IC
From inside IC
Input Pin
(Pin12)
Input Pin
(Pin13)
From inside IC
From inside IC
4/7
BU2374FV
Multimedia ICs
!Electrical characteristics (Unless otherwise noted,Ta=25°C, VCC=3.3V)
Symbol
Min.
Typ.
VCO_OUT Output H voltage
VOH
3.0
VCO_OUT Output L voltage
VOL
−
IIH, IIL
−
Zi
−
VCO current consumption (inhibit)
IDD(INH)
VCO current consumption (normal operation)
IDD(vco)
VI(vco_in)
Parameter
Max.
Unit
−
−
V
IOH=−2.0mA
−
V
IOL=2.0mA
−
0.3
+1
−
µA
10
−
MΩ
−
−
1
µA
at VCO_INHIBIT=VDD
PFD_INHIBIT=VDD
−
12.5
−
mA
Output 50MHz
0.5
−
VDD−0.5
V
MHz
Conditions
VCO section
input current (VCO_INHIBIT, SELECT)
input impedance (VCO_IN)
VCO control voltage
VCO frequency range
frange
37
−
60
Bias Resistor range
Rbias
2.0
−
3.0
KΩ
∗1
Frequency sersibility
β1
−
23
−
MHz/V
∗2
Duty
45
50
55
%
Output Rise-time
tr
−
2.5
−
nsec
Time is from VDD ∗ 0.2 to vdd ∗ 0.8
Output Fall-time
tf
−
2.5
−
nsec
Time is from VDD ∗ 0.8 to vdd ∗ 0.2
Output duty
at 1/2 VDD point
∗ 1 Value of design
guarantee
(all guarantee range)
Bias R=2.0kΩ 37MHz to 54MHz
Bias R=2.4kΩ 45MHz to 58MHz
Bias R=3.0kΩ 53MHz to 60MHz
∗ 2 Frequency sersibility
{ f1(VCOIN=2.0V)−f2(VCOIN=1.0V)} / 1.0V
∗ 3 When FSEL is H and output frequency is 1/4, culculate
5/7
BU2374FV
Multimedia ICs
(Unless otherwise noted,Ta=25°C, VCC=3.3V)
Symbol
Min.
Typ.
Max.
Unit
VOH
VOL
3.0
−
−
−
−
0.3
V
V
IIH, IIL
−
−
+1
−
µA
PFD current consumption (inhibit)
IDD(INH)
−
−
1
µA
at VCO_INHIBIT=VDD
PFD_INHIBIT=VDD
FIN_A and B=GND
PFD current consumption
(normal operation)
IDD(vco)
−
0.5
−
mA
FIN_A and FIN_B=1MHz
−
−
−
−
−
Parameter
PFD section
PFD_OUT Output H voltage
PFD_OUT Output L voltage
input current
(PFD_INHIBIT, FIN A, FIN B)
PFD Function
∗4
Conditions
IOH=−2.0mA
IOL=2.0mA
∗4
FIN-A
FIN-B
PD OUT
Even if Fin-A and Fin-B are same phase,
PD out is off about 2.5nsec. (VDD=3.0V)
PD OUT
Output time [nsec]
2.5nsec
H output (P-MOS Tr)
Phase error [nsec]
(between Fin-A positive edge
and Fin-B positive edge)
2.5nsec
L output (N-MOS Tr)
Output (V)
Input pin (FIN_A, FIN_B, VCO_INHIBIT, PFD_INHIBIT, SELECT)
Vhys
0.2VDD
VthL
1/2VDD
0.8VDD
VthH
Input (V)
6/7
BU2374FV
Multimedia ICs
!Application example
LOGIC VDD
1 LOGIC VDD
VCO VDD
VCO VDD
14
R
H:VCO_OUT 1/4 divide
L :VCO_OUT normal
2 SELECT
BIAS
13
Bypass
capacitor
Ref input
4 FIN-A
1/N
5 FIN-B
6 PFD OUT
LOGIC GND
7 LOGIC GND
BU2374FV
3 VCO OUT
Bypass
capacitor
VCO IN
12
R
R
VCO GND
VCO GND
11
VCO INHIBIT
10
H:VCO out Disable
L:VCO out Enable
PFD INHIBIT
9
H:PFD out Disable
L:PFD out Enable
TEST
8
VCO_VDD,VCO_GND
Please take care this Power line. Because this line is most weak in digital noise.
So this line must be separated from LOGIC_VDD, GND.
And place bypass capacitor (0.1µF) for power pin as close to BU2374FV as possible.
LOGIC_VDD, LOGIC_GND
This line is noise source. So it should be separated from AVDD (AGND).
And place bypass capacitor (0.1µF) for power pin as close to BU2374FV as possible.
And this line should be connected VDD of external voc-out divide.
Bias
Please take care because the bias is weak in digital noise.
And place capacitor (0.1µF) close to BU2374FV.
∗Recommend to use capacitor that is better to reduce high frequency noise.
∗Recommend to control (SELECT, PFD_INHIBIT, VCO_INHIBIT) by power line (LOGIC_VDD, LOGIC_GND).
7/7
Appendix
Notes
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The contents described herein are subject to change without notice. The specifications for the
product described in this document are for reference only. Upon actual use, therefore, please request
that specifications to be separately delivered.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard
use and operation. Please pay careful attention to the peripheral conditions when designing circuits
and deciding upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams information, described herein
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM
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Appendix1-Rev1.0