ROHM BD35222EFV

TECHNICAL NOTE
High-performance Regulator IC Series for PCs
Ultra Low Dropout
Linear Regulators(4A) for Desktop PC
BD3522EFV, BD35221EFV, BD35222EFV
● Description
BD3522EFV / BD35221EFV / BD35222EFV ultra low-dropout linear chipset regulator operates from a very low input supply,
and offers ideal performance in low input voltage to low output voltage applications. It incorporates a built-in N-MOSFET
power transistor to minimize the input-to-output voltage differential to the ON resistance (RON=50mΩ) level. By lowering the
dropout voltage in this way, the regulator realizes high current output (Iomax=4.0A) with reduced conversion loss, and
thereby obviates the switching regulator and its power transistor, choke coil, and rectifier diode. Thus, BD3522EFV /
BD35221EFV / BD35222EFV designed to enable significant package profile downsizing and cost reduction. In BD3522EFV,
an external resistor allows the entire range of output voltage configurations between 0.65 and 2.7V, while the NRCS (soft
start) function enables a controlled output voltage ramp-up, which can be programmed to whatever power supply sequence
is required.
● Features
1) Internal high-precision reference voltage circuit(0.65V±1%)
2) Internal high-precision output voltage circuit <BD35221EFV/BD35222EFV>
3) Built-in VCC undervoltage lockout circuit (VCC=3.80V)
4) NRCS (soft start) function reduces the magnitude of in-rush current
5) Internal Nch MOSFET driver offers low ON resistance (28mΩ typ)
6) Built-in short circuit protection (SCP)
7) Built-in current limit circuit (4.0A min)
8) Built-in thermal shutdown (TSD) circuit
9) Variable output (0.65~2.7V) <BD3522EFV>
10) High-power package HTSSOP-B20 : 6.5mm x 6.4mm x 1.0mm
11) Tracking function
● Applications
Notebook computers, Desktop computers, LCD-TV, DVD, Digital appliances
● Line-up
Maximum Output Voltage
Adjustable (0.65~2.7V)
1.2V (fixed)
1.5V (fixed)
Package
HTSSOP-B20
Product name
BD3522EFV
BD35221EFV
BD35222EFV
Oct. 2008
●Absolute maximum ratings
Parameter
Symbol
Input Voltage 1
Input Voltage 2
Maximum Output Current
Enable Input Voltage
Power Dissipation 1
Power Dissipation 2
Power Dissipation 3
Power Dissipation 4
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
BD3522EFV
VCC
VIN
IO
Ven
Pd1
Pd2
Pd3
Pd4
Topr
Tstg
Tjmax
Limit
BD35221EFV
6.0 *1
6.0 *1
4*1
6.0
1.00 *2
1.45 *3
2.31 *4
3.20 *5
-10~+100
-55~+125
+150
BD35222EFV
Unit
V
V
A
V
W
W
W
W
℃
℃
℃
*1 Should not exceed Pd.
*2 Reduced by 8mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, no copper foil area)
*3 Reduced by 11.6mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 2-layer,
copper foil area : 15mm×15mm)
*4 Reduced by 18.5mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 2-layer,
copper foil area : 70mm×70mm)
*5 Reduced by 25.6mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 4-layer,
copper foil area : 70mm×70mm)
●Operating Voltage(Ta=25℃)
Parameter
Symbol
Input Voltage 1
Input Voltage 2
Output Voltage Setting Range
Enable Input Voltage
NRCS Capacity
VCC
VIN
Vo
Ven
CNRCS
BD3522EFV
Min.
Max.
4.3
5.5
0.7
VCC-1 *6
VFB
2.7
-0.3
5.5
0.001
1
*6 VCC and VIN do not have to be implemented in the order listed.
★This product is not designed for use in radioactive environments.
2/20
BD35221EFV
Min.
Max.
4.3
5.5
1.25
VCC-1 *6
1.2 (fixed)
-0.3
5.5
0.001
1
BD35222EFV
Min.
Max.
4.3
5.5
1.55
VCC-1 *6
1.5 (fixed)
-0.3
5.5
0.001
1
Unit
V
V
V
V
μF
●Electrical Characteristics (Unless otherwise specified, Ta=25℃, VCC=5V, VEN=3V, VIN=1.7V, R1=3.9kΩ, R2=3.3kΩ)
BD3522EFV
Limit
Parameter
Symbol
Unit
Condition
Min.
Typ.
Max.
ICC
1.4
2.2
mA
Bias Current
IST
0
10
μA
VEN=0V
VCC Shutdown Mode Current
IO
4.0
A
Output Voltage
VFB1
0.643
0.650
0.657
V
Feedback Voltage 1
VFB2
0.637
0.650
0.663
V
Tj=-10 to 100℃
Feedback Voltage 2
REG.l1
0.1
0.5
%/V
VCC=4.3V to 5.5V
Line Regulation 1
REG.l2
0.1
0.5
%/V
VIN=1.2V to 3.3V
Line Regulation 2
REG.L
0.5
10
mV
IO=0 to 4A
Load Regulation
IO=4A,VIN=1.2V
Ron
28
50
mΩ
Output ON Resistance
Tj=-10 to 100℃
IDEN
1
mA
VEN=0V, VO=1V
Standby Discharge Current
[ENABLE]
Enable Pin
Input Voltage High
Enable Pin
Input Voltage Low
Enable Input Bias Current
[FEEDBACK]
Feedback Pin Bias Current
[NRCS]
NRCS Charge Current
NRCS Standby Voltage
[UVLO]
VCC Undervoltage Lockout
Threshold Voltage
VCC Undervoltage Lockout
Hysteresis Voltage
VD Undervoltage Lockout
Threshold Voltage
[SCP]
SCP Start up Voltage
SCP Threshold Voltage
Charge Current
Standby Voltage
ENHIGH
2
-
-
V
ENLOW
-0.2
-
0.8
V
IEN
-
6
10
μA
IFB
-100
0
100
nA
INRCS
VSTB
12
-
20
0
28
50
μA
mV
VCCUVLO
3.5
3.8
4.1
V
VCCHYS
100
160
220
mV
VDUVLO VREF×0.6 VREF×0.7 VREF×0.8
VOSCP
VSCPTH
ISCP
VSCPSTBY
VO×0.3
1.05
2
-
VO×0.4
1.15
4
-
3/20
VO×0.5
1.25
6
50
V
V
V
μA
mV
VEN=3V
VEN=0V
VCC:Sweep-up
VCC:Sweep-down
VD:Sweep-up
VFB=0, VGATE=2.5V
VFB=VCC, VGATE=2.5V
●Electrical Characteristics (Unless otherwise specified, Ta=25℃, VCC=5V, VEN=3V, VIN=1.7V)
BD35221EFV
Limit
Parameter
Symbol
Unit
Condition
Min.
Typ.
Max.
ICC
1.4
2.2
mA
Bias Current
IST
0
10
μA
VEN=0V
VCC Shutdown Mode Current
IO
4.0
A
Output Voltage
VOS1
1.188
1.200
1.212
V
Feedback Voltage 1
VOS2
1.176
1.200
1.224
V
Tj=-10 to 100℃
Feedback Voltage 2
REG.l1
0.1
0.5
%/V
VCC=4.3V to 5.5V
Line Regulation 1
REG.l2
0.1
0.5
%/V
VIN=1.25V to 3.3V
Line Regulation 2
REG.L
0.5
10
mV
IO=0 to 4A
Load Regulation
IO=4A,VIN=1.2V
Ron
28
50
mΩ
Output ON Resistance
Tj=-10 to 100℃
IDEN
1
mA
VEN=0V, VO=1V
Standby Discharge Current
[ENABLE]
Enable Pin
Input Voltage High
Enable Pin
Input Voltage Low
Enable Input Bias Current
[NRCS]
NRCS Charge Current
NRCS Standby Voltage
[UVLO]
VCC Undervoltage Lockout
Threshold Voltage
VCC Undervoltage Lockout
Hysteresis Voltage
VD Undervoltage Lockout
Threshold Voltage
[SCP]
SCP Start up Voltage
SCP Threshold Voltage
Charge Current
Standby Voltage
ENHIGH
2
-
-
V
ENLOW
-0.2
-
0.8
V
IEN
-
6
10
μA
VEN=3V
INRCS
VSTB
12
-
20
0
28
50
μA
mV
VEN=0V
VCCUVLO
3.5
3.8
4.1
V
VCCHYS
100
160
220
mV
VDUVLO
VO×0.6
VO×0.7
VO×0.8
V
VOSCP
VSCPTH
ISCP
VSCPSTBY
VO×0.3
1.05
2
-
VO×0.4
1.15
4
-
VO×0.5
1.25
6
50
V
V
μA
mV
4/20
VCC:Sweep-up
VCC:Sweep-down
VD:Sweep-up
VFB=0, VGATE=2.5V
VFB=VCC, VGATE=2.5V
●Electrical Characteristics (Unless otherwise specified, Ta=25℃, VCC=5V, VEN=3V, VIN=1.7V)
BD35222EFV
Limit
Parameter
Symbol
Unit
Condition
Min.
Typ.
Max.
ICC
1.4
2.2
mA
Bias Current
IST
0
10
μA
VEN=0V
VCC Shutdown Mode Current
IO
4.0
A
Output Voltage
VOS1
1.485
1.500
1.515
V
Feedback Voltage 1
VOS2
1.470
1.500
1.530
V
Tj=-10 to 100℃
Feedback Voltage 2
REG.l1
0.1
0.5
%/V
VCC=4.3V to 5.5V
Line Regulation 1
REG.l2
0.1
0.5
%/V
VIN=1.55V to 3.3V
Line Regulation 2
REG.L
0.5
10
mV
IO=0 to 4A
Load Regulation
IO=4A,VIN=1.5V
Ron
28
50
mΩ
Output ON Resistance
Tj=-10 to 100℃
IDEN
1
mA
VEN=0V, VO=1V
Standby Discharge Current
[ENABLE]
Enable Pin
Input Voltage High
Enable Pin
Input Voltage Low
Enable Input Bias Current
[NRCS]
NRCS Charge Current
NRCS Standby Voltage
[UVLO]
VCC Undervoltage Lockout
Threshold Voltage
VCC Undervoltage Lockout
Hysteresis Voltage
VD Undervoltage Lockout
Threshold Voltage
[SCP]
SCP Start up Voltage
SCP Threshold Voltage
Charge Current
Standby Voltage
ENHIGH
2
-
-
V
ENLOW
-0.2
-
0.8
V
IEN
-
6
10
μA
VEN=3V
INRCS
VSTB
12
-
20
0
28
50
μA
mV
VEN=0V
VCCUVLO
3.5
3.8
4.1
V
VCCHYS
100
160
220
mV
VDUVLO
VO×0.6
VO×0.7
VO×0.8
V
VOSCP
VSCPTH
ISCP
VSCPSTBY
VO×0.3
1.05
2
-
VO×0.4
1.15
4
-
VO×0.5
1.25
6
50
V
V
μA
mV
5/20
VCC:Sweep-up
VCC:Sweep-down
VD:Sweep-up
VFB=0, VGATE=2.5V
VFB=VCC, VGATE=2.5V
●Reference Data
BD3522EFV
Vo
50mV/div
Io
2A/div
Fig.1 Transient Response
(0→4A)
Co=22μF, Cfb=1000pF
T(10μsec/div)
Io
2A/div
4.0A
Io=4A→0A/4μsec
T(100μsec/div)
Io
2A/div
4.0A
T(100μsec/div)
Fig.6 Transient Response
(4→0A)
Co=100μF, Cfb=1000pF
VCC
5V/div
Ven
2V/div
VNRCS
2V/div
VNRCS
2V/div
4.0A
Io=4A→0A/4μsec
T(100μsec/div)
Fig.5 Transient Response
(4→0A)
Co=100μF
Ven
2V/div
Ven
2V/div
41mV
50mV/div
Io=4A→0A/4μsec
Fig.4 Transient Response
(4→0A)
Co=22μF, Cfb=1000pF
T(10μsec/div)
Fig.3 Transient Response
(0→4A)
Co=100μF, Cfb=1000pF
Vo
50mV/div
4.0A
Io=0A→4A/4μsec
Fig.2 Transient Response
(0→4A)
Co=100μF
Vo 41mV
50mV/div
46mV
Io
2A/div
4.0A
Io=0A→4A/4μsec
T(10μsec/div)
Vo 42mV
50mV/div
59mV
Io
2A/div
4.0A
Io=0A→4A/4μsec
Io
2A/div
Vo
Vo
50mV/div
49mV
VIN
2V/div
Vo
1V/div
Vo
1V/div
Vo
1V/div
T(2msec/div)
T(20μsec/div)
VCC→VIN→Ven
Fig.8 Waveform at output OFF
Fig.7 Waveform at output start
Fig.9 Input sequence
VCC
5V/div
VCC
5V/div
VCC
5V/div
Ven
2V/div
Ven
2V/div
Ven
2V/div
VIN
2V/div
VIN
2V/div
VIN
2V/div
Vo
1V/div
Vo
1V/div
Vo
1V/div
VIN→VCC→Ven
Fig.10 Input sequence
Ven→VCC→VIN
Fig.11 Input sequence
6/20
VCC→Ven→VIN
Fig.12 Input sequence
●Reference Data
BD3522EFV
1.23
VCC
VCC
Ven
Ven
1.22
VIN
VIN
Vo
Vo
Vo [V]
1.21
1.20
1.19
1.18
VIN→Ven→VCC
1.17
Ven→VIN→VCC
-50
-25
0
25
50
75
100
125
150
100
125
150
125
150
Tj [℃]
Fig.14 Input sequence
Fig.15 Tj-Vo
5.0
50
1.9
4.5
45
1.8
4.0
40
1.7
3.5
35
1.6
3.0
30
1.5
1.4
IINSTB [μA]
2.0
ISTB [μA]
Icc [mA]
Fig.13 Input sequence
2.5
2.0
25
20
1.3
1.5
15
1.2
1.0
10
1.1
0.5
5
1.0
0
0.0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
Tj [℃]
Fig.16 Tj-ICC
75
100
125
-50
150
25
50
75
Fig.17 Tj-ISTB
Fig.18 Tj-IINSTB
40
9
22
0
Tj [℃]
10
24
-25
Tj [℃]
35
8
30
7
25
18
RON[mΩ]
6
IEN[μA]
INRCS [μA]
20
5
4
16
20
15
3
10
2
14
5
1
12
0
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
0
25
50
75
100
Tj [℃]
Fig.19 Tj-INRCS
Fig.20 Tj-IEN
Fig.21 Tj-RON
(VCC=5V/VO=1.2V)
Vo=2.5V
35
28
30
RON[mΩ]
25
RON[mΩ]
-25
Tj [℃]
30
20
15
26
Vo=1.8V
24
Vo=1.5V
10
22
Vo=1.2V
5
0
20
-25
-50
Tj [℃]
40
-50
150
0
25
50
75
100
125
150
3
5
7
Tj [℃]
Vcc [V]
Fig.22 Tj-RON
(VCC=5V/VO=1.5V)
Fig.23 VCC-RON
7/20
●Block Diagram
BD3522EFV
VCC
C1
VCC
14
11
UVLO2
VIN
UVLOLATCH
15
VCC
VCC
EN
EN
UVLO1
Reference
Block
12
VD
Current
Limit
CL
UVLO1
VREF
×0.7
VIN
16
VIN
17
18
R2
C2
19
VCC
VREF
20
R1
NRCS
VO
SCP/TSD
LATCH
NRCS×0.3
VREF×0.4
FB
LATCH
EN
UVLO1
TSD
1
CL
UVLO1
UVLO2
TSD
SCP
2
VO
3
4
R2
EN
CFB
C3
5
SCP
13
6
CSCP
7
FB
R1
NRCS
8
NRCS
EN/UVLO
CNRCS
9
10
GND
BD35221EFV/BD35222EFV
VCC
C1
VCC
11
14
UVLO2
VIN
UVLO LATCH
VCC
VCC
EN
EN
UVLO1
Reference
Block
12
VIN
R2
15
R1
16
VIN
17
Current
Limit
CL
UVLO1
VREF
×0.7
VD
18
C2
19
VCC
VREF
20
NRCS
VO
NRCS×0.3
VREF×0.4
FB
TSD
SCP/TSD
LATCH
LATCH
EN
UVLO1
1
CL
UVLO1
UVLO2
TSD
SCP
2
4
CFB
EN
C3
5
SCP
13
6
CSCP
VOS
R2
FB
7
NRCS
8
CNRCS
VO
3
NRCS
R1
EN/UVLO
9
8/20
10
GND
●Pin Layout
BD3522EFV
VIN
20
VIN
19
BD35221EFV/BD35222EFV
VIN
18
VIN
17
VIN
16
VIN
15
VD
14
SCP
13
EN
12
VCC
11
VIN
19
VIN
20
VIN
18
VIN
17
FIN
VIN
16
VIN
15
VD
14
SCP
13
EN
12
8
9
VCC
11
FIN
1
2
3
4
5
6
7
VO
VO
VO
VO
VO
VO
FB
8
9
NRCS GND
10
1
2
3
4
5
6
7
GND
VO
VO
VO
VO
VO
VOS
FB
NRCS GND
10
GND
●Pin Function Table
BD3522EFV
PIN
No.
1
2
3
4
5
6
7
BD35221EFV/BD35222EFV
PIN name
PIN Function
VO
VO
VO
VO
VO
VO
FB
Output Voltage Pin
Output Voltage Pin
Output Voltage Pin
Output Voltage Pin
Output Voltage Pin
Output Voltage Pin
Reference Voltage Feedback Pin
In-rush Current Protection (NRCS)
Capacitor Connection Pin
Ground Pin
Ground Pin
Power supply pin
Enable input pin
SCP Delay Time Setting Capacitor
Connection Pin
8
NRCS
9
10
11
12
GND
GND
VCC
EN
13
SCP
14
15
16
17
18
19
20
-
VD
VIN
VIN
VIN
VIN
VIN
VIN
FIN
VIN Input Voltage Detect Pin
Input Voltage Pin
Input Voltage Pin
Input Voltage Pin
Input Voltage Pin
Input Voltage Pin
Input Voltage Pin
Connected to heatsink and GND
9/20
PIN
No.
1
2
3
4
5
6
7
PIN name
PIN Function
VO
VO
VO
VO
VO
VOS
FB
Output Voltage Pin
Output Voltage Pin
Output Voltage Pin
Output Voltage Pin
Output Voltage Pin
Output Voltage Control Pin
Reference Voltage Feedback Pin
In-rush Current Protection (NRCS)
Capacitor Connection Pin
Ground Pin
Ground Pin
Power supply pin
Enable input pin
SCP Delay Time Setting Capacitor
Connection Pin
8
NRCS
9
10
11
12
GND
GND
VCC
EN
13
SCP
14
15
16
17
18
19
20
-
VD
VIN
VIN
VIN
VIN
VIN
VIN
FIN
VIN Input Voltage Detect Pin
Input Voltage Pin
Input Voltage Pin
Input Voltage Pin
Input Voltage Pin
Input Voltage Pin
Input Voltage Pin
Connected to heatsink and GND
●Operation of Each Block
・AMP
This is an error amp compares the reference voltage (0.65V) with VO to drive the output Nch FET (Ron=50mΩ). Frequency
optimization helps to realize rapid transient response, and to support the use of ceramic capacitors on the output. AMP input
voltage ranges from GND to 2.7V, while the AMP output ranges from GND to VCC. When EN is OFF, or when UVLO is
active, output goes LOW and the output of the NchFET switches OFF.
・EN
The EN block controls the regulator’s ON/OFF state via the EN logic input pin. In the OFF position, circuit voltage is
maintained at 0μA, thus minimizing current consumption at standby. The FET is switched ON to enable discharge of the
NRCS pin VO, thereby draining the excess charge and preventing the IC on the load side from malfunctioning. Since no
electrical connection is required (e.g. between the VCC pin and the ESD prevention diode), module operation is
independent of the input sequence.
・VCCUVLO
To prevent malfunctions that can occur during a momentary decrease in VCC, the UVLO circuit switches the output OFF,
and (like the EN block) discharges NRCS and VO. Once the UVLO threshold voltage (TYP3.80V) is reached, the power-on
reset is triggered and output continues.
・VDUVLO
VD pin is the VIN voltage detect pin. When VD voltage exceeds the threshold voltage, VDUVLO becomes active. Once active,
the status of output voltage remains ON even if VD voltage drops. (When VIN voltage drops, SCP engages and output
switches OFF.) Unlike EN and VCC, it is effective at output startup. VDUVLO can be restored either by reconnecting the EN
pin or VCC pin.
・CURRENT LIMIT
When output is ON, the current limit function monitors the internal IC output current against the parameter value. When
current exceeds this level, the current limit module lowers the output current to protect the load IC. When the overcurrent
state is eliminated, output voltage is restored to the parameter value. However when output voltage falls to or below the
SCP startup voltage, the SCP function becomes active and the output switches OFF.
・NRCS (Non Rush Current on Start-up)
The soft start function enabled by connecting an external capacitor between the NRCS pin and ground. Output ramp-up
can be set for any period up to the time the NRCS pin reaches VFB (0.65V). During startup, the NRCS pin serves as a 20μ
A (TYP) constant current source to charge the external capacitor. Output start time is calculated via the formula below.
TNRCS (typ.) =
CNRCS×VFB
INRCS
・TSD (Thermal Shut down)
The shutdown (TSD) circuit automatically is latched OFF when the chip temperature exceeds the threshold temperature
after the programmed time period elapses, thus serving to protect the IC against “thermal runaway” and heat damage.
Because the TSD circuit is intended to shut down the IC only in the presence of extreme heat, it is crucial that the Tj (max)
parameter not be exceeded in the thermal design, in order to avoid potential problems with the TSD.
TTSD (typ.) =
CSCP×VSCPTH
20uA
・VIN
The VIN line acts as the major current supply line, and is connected to the output NchFET drain. Since no electrical
connection (such as between the VCC pin and the ESD protection diode) is necessary, VIN operates independent of the input
sequence. However, since an output NchFET body diode exists between VIN and VO, a VIN-VO electric (diode) connection is
present. Note, therefore, that when output is switched ON or OFF, reverse current may flow to VIN from VO.
・SCP
When output voltage (Vo) drops, the IC assumes that VO pin is shorted to GND and switched the output voltage OFF. After
the GND short has been detected and the programmed delay time has elapsed, output is latched OFF. It is also effective
during output startup. SCP can be cleared either by reconnecting the EN pin or VCC pin. Delay time is calculated via the
formula below.
TSCP (typ.) =
CSCP×VSCPTH
ISCP
10/20
●Timing Chart
EN ON/OFF
VIN
VCC
EN
0.65V(typ)
NRCS
Startup
Vo
t
VCC ON/OFF
VIN
UVLO
Hysteresis
VCC
EN
0.65V(typ)
NRCS
Startup
Vo
t
11/20
●Timing Chart
VD ON
VIN
VDUVLO
VD
VCC
EN
NRCS
Vo
SCP OFF
VIN
VD
VCC
EN
NRCS
SCP startup voltage
Vo
SCP delay time
SCP threshold voltage
SCP
12/20
●Evaluation Board
■ BD3522EFV Evaluation Board Schematic
U1
BD3522EFV
1
2
3
4
VO
INF
RF1
1
U2
C5
C6
C4
RF2
JP6
6
CFB
FB
VIN
VO
VIN
VO
VIN
VO
VIN
19
18
17
1
5
R4
VO
20
VO
VIN
FB
VD
1
JP15
15
R6
NRCS
14
1
8
1
1
NRCS
SCP
13
SGND
C17
VIN
C18
VD
1
EN
SCP
C13
C8
JPF1
C16
R14
VCC
JPF2
C15
R15
7
1
R7
INV
VIN_S
16
9
1
GND
EN
GND
VCC
R12
12
JP10
U3
SW1
C12
VCC
10
VCC
H
1
RLD
VIN
1
1
VO_S
VO
11
1
L
VCC
GND
1
1
1
C11
GND1 GND2
RF3
CF
■ BD3522EFV Evaluation Board List
Component
Rating
Manufacturer
Product Name
Component
Rating
Manufacturer
Product Name
U1
C6
C8
C11
C13
C15
C18(*1)
-
ROHM
KYOCERA
MURATA
MURATA
MURATA
KYOCERA
SANYO
BD3522EFV
CM316B226M06A
GRM188B11H103KD
GRM188B11A105KD
GRM188B11H331KD
CM21B106M06A
6TPB150M
CFB
R6 (@VOUT=1.2V)
R7
R121
R14
R15(@VOUT=1.2V)
1000pF
3.3kΩ
3.9Ω
0kΩ
3.9kΩ
3.3kΩ
MURATA
ROHM
ROHM
ROHM
ROHM
GRM188B11H102KD
MCR03EZPF3301
MCR03EZPF3901
jumper
MCR03EZPF3901
MCR03EZPF3301
22uF
0.01uF
1uF
330pF
10uF
150uF
*1 provision for supply impedance of instruments
■ BD3522EFV Evaluation Board Layout
Silk Screen (Top)
Silk Screen (Bottom)
TOP Layer
Middle Layer_1
Middle Layer_2
Bottom Layer
13/20
●Recommended Circuit Example (BD3522EFV)
VIN
R15
R14
C20
C12
EN
C13
C11
20
19
18
17
16
15
14
13
12
11
VIN
VIN
VIN
VIN
VIN
VIN
VD
SCP
EN
Vcc
Vo
1
Vo
2
Vo
3
Vo
4
Vo
5
Vo
6
FB
7
NRCS GND
8
9
Vcc
GND
10
C8
R6
C1
R6/R7
Recommended
Value
3.3k /3.9k
C1
22μF
C11/C20
1μF/10μF
C8
0.01μF
C6
1000pF
C13
330pF
Component
R7
C6
Programming Notes and Precautions
IC output voltage can be set with a configuration formula VFB×(R6+R7)/R7 using the
values for the internal reference output voltage (VFB) and the output voltage resistors (R6,
R7). Select resistance values that will avoid the impact of the FB bias current (±100nA).
The recommended total resistance value is 10KΩ.
To assure output voltage stability, please be certain the output capacitors are connected
between Vo pin and GND. Output capacitors play a role in loop gain phase compensation
and in mitigating output fluctuation during rapid changes in load level. Insufficient
capacitance may cause oscillation, while high equivalent series reisistance (ESR) will
exacerbate output voltage fluctuation under rapid load change conditions. While a 22μF
ceramic capacitor is recomended, actual stability is highly dependent on temperature and
load conditions. Also, note that connecting different types of capacitors in series may result
in insufficient total phase compensation, thus causing oscillation. In light of this information,
please confirm operation across a variety of temperature and load conditions.
Input capacitors reduce the output impedance of the voltage supply source connected to
the (VCC, VIN) input pins. If the impedance of this power supply were to increase, input
voltage (VCC, VIN) could become unstable, leading to oscillation or lowered ripple rejection
function. While a low-ESR 1μF/10μF capacitor with minimal susceptibility to temperature
is recommended, stability is highly dependent on the input power supply characteristics
and the substrate wiring pattern. In light of this information, please confirm operation
across a variety of temperature and load conditions.
The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush
current from going through the load (VIN to VO) and impacting output capacitors at power
supply start-up. Constant current comes from the NRCS pin when EN is HIGH or the
UVLO function is deactivated. The temporary reference voltage is proportionate to time,
due to the current charge of the NRCS pin capacitor, and output voltage start-up is
proportionate to this reference voltage. Capacitors with low susceptibility to temperature
are recommended, in order to assure a stable soft-start time.
This component is employed when the C16 capacitor causes, or may cause, oscillation. It
provides more precise internal phase correction.
The Short Circuit Protection (SCP) function and the Thermal Shut Down (TSD) function
are built into the IC. Constant current comes from the SCP pin when SCP function or TSD
function is operated. (SCP:4μA, TSD:20μA TYP.) The voltage occurred in SCP pin by
this current overstep the threshold voltage, the status of voltage becomes OFF. Capacitors
with low susceptibility to temperature (330pF or more) are recommended, in order to
assure a stable TSD delay setting time. In light of this information, please confirm the
capacitor value to prevent startup defective.
14/20
●Recommended Circuit Example (BD35221EFV/BD35222EFV)
R15
VIN
R14
C20
C12
EN
C13
C11
20
19
18
17
16
15
14
13
12
11
VIN
VIN
VIN
VIN
VIN
VIN
VD
SCP
EN
Vcc
Vos
6
FB
7
Vcc
FIN
Vo
1
Vo
2
Vo
3
Vo
4
Vo
5
NRCS GND
8
9
GND
10
C8
C6
C1
C1
Recommended
Value
22μF
C11/C20
1μF/10μF
C8
0.01μF
C6
1000pF
C13
330pF
Component
Programming Notes and Precautions
To assure output voltage stability, please be certain the output capacitors are connected
between Vo pin and GND. Output capacitors play a role in loop gain phase compensation
and in mitigating output fluctuation during rapid changes in load level. Insufficient
capacitance may cause oscillation, while high equivalent series reisistance (ESR) will
exacerbate output voltage fluctuation under rapid load change conditions. While a 22μF
ceramic capacitor is recomended, actual stability is highly dependent on temperature and
load conditions. Also, note that connecting different types of capacitors in series may result
in insufficient total phase compensation, thus causing oscillation. In light of this information,
please confirm operation across a variety of temperature and load conditions.
Input capacitors reduce the output impedance of the voltage supply source connected to
the (VCC, VIN) input pins. If the impedance of this power supply were to increase, input
voltage (VCC, VIN) could become unstable, leading to oscillation or lowered ripple rejection
function. While a low-ESR 1μF/10μF capacitor with minimal susceptibility to temperature
is recommended, stability is highly dependent on the input power supply characteristics
and the substrate wiring pattern. In light of this information, please confirm operation
across a variety of temperature and load conditions.
The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush
current from going through the load (VIN to VO) and impacting output capacitors at power
supply start-up. Constant current comes from the NRCS pin when EN is HIGH or the
UVLO function is deactivated. The temporary reference voltage is proportionate to time,
due to the current charge of the NRCS pin capacitor, and output voltage start-up is
proportionate to this reference voltage. Capacitors with low susceptibility to temperature
are recommended, in order to assure a stable soft-start time.
This component is employed when the C16 capacitor causes, or may cause, oscillation. It
provides more precise internal phase correction.
The Short Circuit Protection (SCP) function and the Thermal Shut Down (TSD) function
are built into the IC. Constant current comes from the SCP pin when SCP function or TSD
function is operated. (SCP:4μA, TSD:20μA TYP.) The voltage occurred in SCP pin by
this current overstep the threshold voltage, the status of voltage becomes OFF. Capacitors
with low susceptibility to temperature (330pF or more) are recommended, in order to
assure a stable TSD delay setting time. In light of this information, please confirm the
capacitor value to prevent startup defective.
15/20
●Heat Loss
Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed
temperature limits, and thermal design should allow sufficient margin from the limits.
1. Ambient temperature Ta can be no higher than 100℃.
2. Chip junction temperature (Tj) can be no higher than 150℃.
Chip junction temperature can be determined as follows:
① Calculation based on ambient temperature (Ta)
Tj=Ta+θj-a×W
<Reference values>
θj-a: HTSSOP-B20 125℃/W 1-layer substrate (no copper foil area)
86.2℃/W 1-layer substrate (copper foil area : 15mm×15mm)
54.1℃/W 2-layer substrate (copper foil area : 70mm×70mm)
39.1℃/W 2-layer substrate (copper foil area : 70mm×70mm)
3
Substrate size: 70×70×1.6mm (substrate with thermal via)
It is recommended to layout the VIA for heat radiation in the GND pattern of reverse (of IC) when there is the GND pattern in
the inner layer (in using multiplayer substrate). This package is so small (size: 6.5mm×6.4mm) that it is not available to
layout the VIA in the bottom of IC. Spreading the pattern and being increased the number of VIA like the figure below enable
to get the superior heat radiation characteristic. (This figure is the image. It is recommended that the VIA size and the
number is designed suitable for the actual situation.).
Most of the heat loss that occurs in the BD3522EFV is generated from the output Nch FET. Power loss is determined by the
total VIN-Vo voltage and output current. Be sure to confirm the system input and output voltage and the output current
conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in mind that heat
dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the
BD3522EFV) make certain to factor conditions such as substrate size into the thermal design.
Power consumption (W) =
Input voltage (VIN)- Output voltage (Vo) ×Io(Ave)
Example) Where VIN=1.7V, VO=1.2V, Io(Ave) = 4A,
Power consumption (W) = 1.7(V)-1.2(V) ×4.0(A)
= 2.0(W)
16/20
●Input-Output Equivalent Circuit Diagram (BD3522EFV)
VCC
VCC
1kΩ
VD
1kΩ
VIN
1kΩ
NRCS
VIN
1kΩ
1kΩ 1kΩ
VIN
210kΩ
1kΩ
1kΩ
VIN
VIN
90kΩ
VIN
VCC
VCC
EN
10kΩ
1kΩ
FB
Vo
400kΩ
1kΩ
50kΩ
Vo
Vo
1kΩ
Vo
Vo
Vo
VCC
SCP
1kΩ
5PF
1kΩ
1kΩ
1kΩ
1kΩ
17/20
●Operation Notes
1.
Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can
break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any
over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as
fuses.
2. Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.
3. Power supply lines
Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line,
separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to
ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the
circuit, not that capacitance characteristic values are reduced at low temperatures.
4. GND voltage
The potential of GND pin must be minimum potential in all operating conditions.
5. Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
6. Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
8. ASO
When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.
9. Thermal shutdown circuit
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed
only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not
continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is
assumed.
TSD on temperature [°C] (typ.)
BD3522EFV/BD35221EFV/BD35222EFV
175
10. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting or storing the IC.
18/20
11. Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate,
such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
Resistor
Transistor (NPN)
Pin A
Pin B
C
Pin B
B
E
Pin A
N
N
N
P+
P+
P
Parasitic
element
N
P+
B
N
P substrate
Parasitic element
P+
P
N
C
E
Parasitic
element
P substrate
GND
Parasitic element
GND
GND
GND
Other adjacent elements
Example of IC structure
12. Ground Wiring Pattern.
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing
a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations
caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND
wiring pattern of any external components, either.
●Heat Dissipation Characteristics
◎HTSSOP-B20
4
70mm×70mm×1.6mm (PCB with Thermal Via)
① 1 layer substrate (substrate surface copper foil area:0mm×0mm)
θj-a=125℃/W
② 2 layer substrate (substrate surface copper foil area:15mm×15mm)
θj-a=86.2℃/W
③ 2 layer substrate (substrate surface copper foil area:15mm×15mm)
θj-a=54.1℃/W
④ 4 layer substrate (substrate surface copper foil area:70mm×70mm)
θj-a=39.1℃/W
Power Dissipation :Pd [W]
④3.2W
3
③2.31W
2
②1.45W
①1W
1
0
25
50
75
100
125
150
Ambient Temperature:Ta [℃]
(HTSSOP-B20)
19/20
●Type Designations (Ordering Information)
B
D
3
5
2
2
E
F
Package Type
Product Name
・BD3522
・BD35221
・BD35222
V
E
―
2
E2:Emboss tape reel opposite draw-out side: 1 pin
・EFV: HTSSOP-B20
HTSSOP-B20
<Dimension>
<Tape and Reel information>
Tape
Embossed carrier tape
2500pcs
Quantity
6.5 ± 0.1
11
6.4 ± 0.2
4.4 ± 0.1
1
10
E2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
of feed
0.17 +0.05
−0.03
S
0.08 S
1234
1234
1234
1pin
1234
(Unit:mm)
1234
Reel
1234
0.2 +0.05
−0.04
1234
0.65
1234
1.0Max.
0.85 ± 0.05
0.08 ± 0.05
0.325
Direction
0.5 ± 0.15
1.0 ± 0.2
20
Direction of feed
※When you order , please order in times the amount of package quantity.
20/20
Catalog No.08T427A '08.10 ROHM ©
Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM
CO.,LTD.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or
exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility
whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
appliances and amusement devices).
The Products are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your
use of any Product outside of the prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system
which requires an extremely high level of reliability the failure or malfunction of which may result in a direct
threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no
responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended
to be used for any such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.
ROHM Customer Support System
www.rohm.com
Copyright © 2008 ROHM CO.,LTD.
THE AMERICAS / EUROPE / ASIA / JAPAN
Contact us : [email protected] rohm.co. jp
21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan
TEL : +81-75-311-2121
FAX : +81-75-315-0172
Appendix1-Rev3.0